Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2012 Red Hat Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | * Authors: Ben Skeggs |
| 23 | */ |
| 24 | |
Ben Skeggs | fdb751e | 2014-08-10 04:10:23 +1000 | [diff] [blame^] | 25 | #include <nvif/os.h> |
| 26 | #include <nvif/class.h> |
| 27 | |
| 28 | /*XXX*/ |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 29 | #include <core/client.h> |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 30 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 31 | #include "nouveau_drm.h" |
| 32 | #include "nouveau_dma.h" |
| 33 | #include "nouveau_bo.h" |
| 34 | #include "nouveau_chan.h" |
| 35 | #include "nouveau_fence.h" |
| 36 | #include "nouveau_abi16.h" |
| 37 | |
| 38 | MODULE_PARM_DESC(vram_pushbuf, "Create DMA push buffers in VRAM"); |
| 39 | static int nouveau_vram_pushbuf; |
| 40 | module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400); |
| 41 | |
| 42 | int |
| 43 | nouveau_channel_idle(struct nouveau_channel *chan) |
| 44 | { |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 45 | struct nouveau_cli *cli = (void *)nvif_client(chan->object); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 46 | struct nouveau_fence *fence = NULL; |
| 47 | int ret; |
| 48 | |
Ben Skeggs | 264ce19 | 2013-02-14 13:43:21 +1000 | [diff] [blame] | 49 | ret = nouveau_fence_new(chan, false, &fence); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 50 | if (!ret) { |
| 51 | ret = nouveau_fence_wait(fence, false, false); |
| 52 | nouveau_fence_unref(&fence); |
| 53 | } |
| 54 | |
| 55 | if (ret) |
Ben Skeggs | fa2bade | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 56 | NV_PRINTK(error, cli, "failed to idle channel 0x%08x [%s]\n", |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 57 | chan->object->handle, nvkm_client(&cli->base)->name); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 58 | return ret; |
| 59 | } |
| 60 | |
| 61 | void |
| 62 | nouveau_channel_del(struct nouveau_channel **pchan) |
| 63 | { |
| 64 | struct nouveau_channel *chan = *pchan; |
| 65 | if (chan) { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 66 | if (chan->fence) { |
| 67 | nouveau_channel_idle(chan); |
| 68 | nouveau_fence(chan->drm)->context_del(chan); |
| 69 | } |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 70 | nvif_object_fini(&chan->nvsw); |
| 71 | nvif_object_fini(&chan->gart); |
| 72 | nvif_object_fini(&chan->vram); |
| 73 | nvif_object_ref(NULL, &chan->object); |
| 74 | nvif_object_fini(&chan->push.ctxdma); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 75 | nouveau_bo_vma_del(chan->push.buffer, &chan->push.vma); |
| 76 | nouveau_bo_unmap(chan->push.buffer); |
Marcin Slusarz | 124ea29 | 2012-11-25 23:02:28 +0100 | [diff] [blame] | 77 | if (chan->push.buffer && chan->push.buffer->pin_refcnt) |
| 78 | nouveau_bo_unpin(chan->push.buffer); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 79 | nouveau_bo_ref(NULL, &chan->push.buffer); |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 80 | nvif_device_ref(NULL, &chan->device); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 81 | kfree(chan); |
| 82 | } |
| 83 | *pchan = NULL; |
| 84 | } |
| 85 | |
| 86 | static int |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 87 | nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device, |
| 88 | u32 handle, u32 size, struct nouveau_channel **pchan) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 89 | { |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 90 | struct nouveau_cli *cli = (void *)nvif_client(&device->base); |
Ben Skeggs | 967e7bd | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 91 | struct nouveau_instmem *imem = nvkm_instmem(device); |
| 92 | struct nouveau_vmmgr *vmm = nvkm_vmmgr(device); |
| 93 | struct nouveau_fb *pfb = nvkm_fb(device); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 94 | struct nv_dma_class args = {}; |
| 95 | struct nouveau_channel *chan; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 96 | u32 target; |
| 97 | int ret; |
| 98 | |
| 99 | chan = *pchan = kzalloc(sizeof(*chan), GFP_KERNEL); |
| 100 | if (!chan) |
| 101 | return -ENOMEM; |
| 102 | |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 103 | nvif_device_ref(device, &chan->device); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 104 | chan->drm = drm; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 105 | |
| 106 | /* allocate memory for dma push buffer */ |
| 107 | target = TTM_PL_FLAG_TT; |
| 108 | if (nouveau_vram_pushbuf) |
| 109 | target = TTM_PL_FLAG_VRAM; |
| 110 | |
| 111 | ret = nouveau_bo_new(drm->dev, size, 0, target, 0, 0, NULL, |
| 112 | &chan->push.buffer); |
| 113 | if (ret == 0) { |
| 114 | ret = nouveau_bo_pin(chan->push.buffer, target); |
| 115 | if (ret == 0) |
| 116 | ret = nouveau_bo_map(chan->push.buffer); |
| 117 | } |
| 118 | |
| 119 | if (ret) { |
| 120 | nouveau_channel_del(pchan); |
| 121 | return ret; |
| 122 | } |
| 123 | |
| 124 | /* create dma object covering the *entire* memory space that the |
| 125 | * pushbuf lives in, this is because the GEM code requires that |
| 126 | * we be able to call out to other (indirect) push buffers |
| 127 | */ |
| 128 | chan->push.vma.offset = chan->push.buffer->bo.offset; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 129 | |
Ben Skeggs | 967e7bd | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 130 | if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) { |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 131 | ret = nouveau_bo_vma_add(chan->push.buffer, cli->vm, |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 132 | &chan->push.vma); |
| 133 | if (ret) { |
| 134 | nouveau_channel_del(pchan); |
| 135 | return ret; |
| 136 | } |
| 137 | |
| 138 | args.flags = NV_DMA_TARGET_VM | NV_DMA_ACCESS_VM; |
| 139 | args.start = 0; |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 140 | args.limit = cli->vm->vmm->limit - 1; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 141 | } else |
| 142 | if (chan->push.buffer->bo.mem.mem_type == TTM_PL_VRAM) { |
Ben Skeggs | dceef5d | 2013-03-04 13:01:21 +1000 | [diff] [blame] | 143 | u64 limit = pfb->ram->size - imem->reserved - 1; |
Ben Skeggs | 967e7bd | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 144 | if (device->info.family == NV_DEVICE_INFO_V0_TNT) { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 145 | /* nv04 vram pushbuf hack, retarget to its location in |
| 146 | * the framebuffer bar rather than direct vram access.. |
| 147 | * nfi why this exists, it came from the -nv ddx. |
| 148 | */ |
| 149 | args.flags = NV_DMA_TARGET_PCI | NV_DMA_ACCESS_RDWR; |
Ben Skeggs | 967e7bd | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 150 | args.start = nv_device_resource_start(nvkm_device(device), 1); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 151 | args.limit = args.start + limit; |
| 152 | } else { |
| 153 | args.flags = NV_DMA_TARGET_VRAM | NV_DMA_ACCESS_RDWR; |
| 154 | args.start = 0; |
| 155 | args.limit = limit; |
| 156 | } |
| 157 | } else { |
| 158 | if (chan->drm->agp.stat == ENABLED) { |
| 159 | args.flags = NV_DMA_TARGET_AGP | NV_DMA_ACCESS_RDWR; |
| 160 | args.start = chan->drm->agp.base; |
| 161 | args.limit = chan->drm->agp.base + |
| 162 | chan->drm->agp.size - 1; |
| 163 | } else { |
| 164 | args.flags = NV_DMA_TARGET_VM | NV_DMA_ACCESS_RDWR; |
| 165 | args.start = 0; |
| 166 | args.limit = vmm->limit - 1; |
| 167 | } |
| 168 | } |
| 169 | |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 170 | ret = nvif_object_init(nvif_object(device), NULL, NVDRM_PUSH | |
| 171 | (handle & 0xffff), NV_DMA_FROM_MEMORY_CLASS, |
| 172 | &args, sizeof(args), &chan->push.ctxdma); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 173 | if (ret) { |
| 174 | nouveau_channel_del(pchan); |
| 175 | return ret; |
| 176 | } |
| 177 | |
| 178 | return 0; |
| 179 | } |
| 180 | |
Marcin Slusarz | 5b8a43a | 2012-08-19 23:00:00 +0200 | [diff] [blame] | 181 | static int |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 182 | nouveau_channel_ind(struct nouveau_drm *drm, struct nvif_device *device, |
| 183 | u32 handle, u32 engine, struct nouveau_channel **pchan) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 184 | { |
Ben Skeggs | c97f8c9 | 2012-08-19 16:03:00 +1000 | [diff] [blame] | 185 | static const u16 oclasses[] = { NVE0_CHANNEL_IND_CLASS, |
| 186 | NVC0_CHANNEL_IND_CLASS, |
| 187 | NV84_CHANNEL_IND_CLASS, |
| 188 | NV50_CHANNEL_IND_CLASS, |
| 189 | 0 }; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 190 | const u16 *oclass = oclasses; |
Ben Skeggs | dbff2de | 2012-08-06 18:16:37 +1000 | [diff] [blame] | 191 | struct nve0_channel_ind_class args; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 192 | struct nouveau_channel *chan; |
| 193 | int ret; |
| 194 | |
| 195 | /* allocate dma push buffer */ |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 196 | ret = nouveau_channel_prep(drm, device, handle, 0x12000, &chan); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 197 | *pchan = chan; |
| 198 | if (ret) |
| 199 | return ret; |
| 200 | |
| 201 | /* create channel object */ |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 202 | args.pushbuf = chan->push.ctxdma.handle; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 203 | args.ioffset = 0x10000 + chan->push.vma.offset; |
| 204 | args.ilength = 0x02000; |
Ben Skeggs | 4998104 | 2012-08-06 19:38:25 +1000 | [diff] [blame] | 205 | args.engine = engine; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 206 | |
| 207 | do { |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 208 | ret = nvif_object_new(nvif_object(device), handle, *oclass++, |
| 209 | &args, sizeof(args), &chan->object); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 210 | if (ret == 0) |
| 211 | return ret; |
| 212 | } while (*oclass); |
| 213 | |
| 214 | nouveau_channel_del(pchan); |
| 215 | return ret; |
| 216 | } |
| 217 | |
| 218 | static int |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 219 | nouveau_channel_dma(struct nouveau_drm *drm, struct nvif_device *device, |
| 220 | u32 handle, struct nouveau_channel **pchan) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 221 | { |
Ben Skeggs | c97f8c9 | 2012-08-19 16:03:00 +1000 | [diff] [blame] | 222 | static const u16 oclasses[] = { NV40_CHANNEL_DMA_CLASS, |
| 223 | NV17_CHANNEL_DMA_CLASS, |
| 224 | NV10_CHANNEL_DMA_CLASS, |
| 225 | NV03_CHANNEL_DMA_CLASS, |
| 226 | 0 }; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 227 | const u16 *oclass = oclasses; |
Ben Skeggs | a7c6e75 | 2012-08-14 15:02:29 +1000 | [diff] [blame] | 228 | struct nv03_channel_dma_class args; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 229 | struct nouveau_channel *chan; |
| 230 | int ret; |
| 231 | |
| 232 | /* allocate dma push buffer */ |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 233 | ret = nouveau_channel_prep(drm, device, handle, 0x10000, &chan); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 234 | *pchan = chan; |
| 235 | if (ret) |
| 236 | return ret; |
| 237 | |
| 238 | /* create channel object */ |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 239 | args.pushbuf = chan->push.ctxdma.handle; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 240 | args.offset = chan->push.vma.offset; |
| 241 | |
| 242 | do { |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 243 | ret = nvif_object_new(nvif_object(device), handle, *oclass++, |
| 244 | &args, sizeof(args), &chan->object); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 245 | if (ret == 0) |
| 246 | return ret; |
| 247 | } while (ret && *oclass); |
| 248 | |
| 249 | nouveau_channel_del(pchan); |
| 250 | return ret; |
| 251 | } |
| 252 | |
| 253 | static int |
| 254 | nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart) |
| 255 | { |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 256 | struct nvif_device *device = chan->device; |
| 257 | struct nouveau_cli *cli = (void *)nvif_client(&device->base); |
Ben Skeggs | 967e7bd | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 258 | struct nouveau_instmem *imem = nvkm_instmem(device); |
| 259 | struct nouveau_vmmgr *vmm = nvkm_vmmgr(device); |
| 260 | struct nouveau_fb *pfb = nvkm_fb(device); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 261 | struct nouveau_software_chan *swch; |
Ben Skeggs | f756944 | 2012-10-08 14:29:16 +1000 | [diff] [blame] | 262 | struct nv_dma_class args = {}; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 263 | int ret, i; |
| 264 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 265 | /* allocate dma objects to cover all allowed vram, and gart */ |
Ben Skeggs | 967e7bd | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 266 | if (device->info.family < NV_DEVICE_INFO_V0_FERMI) { |
| 267 | if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 268 | args.flags = NV_DMA_TARGET_VM | NV_DMA_ACCESS_VM; |
| 269 | args.start = 0; |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 270 | args.limit = cli->vm->vmm->limit - 1; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 271 | } else { |
| 272 | args.flags = NV_DMA_TARGET_VRAM | NV_DMA_ACCESS_RDWR; |
| 273 | args.start = 0; |
Ben Skeggs | dceef5d | 2013-03-04 13:01:21 +1000 | [diff] [blame] | 274 | args.limit = pfb->ram->size - imem->reserved - 1; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 275 | } |
| 276 | |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 277 | ret = nvif_object_init(chan->object, NULL, vram, |
| 278 | NV_DMA_IN_MEMORY_CLASS, &args, |
| 279 | sizeof(args), &chan->vram); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 280 | if (ret) |
| 281 | return ret; |
| 282 | |
Ben Skeggs | 967e7bd | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 283 | if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 284 | args.flags = NV_DMA_TARGET_VM | NV_DMA_ACCESS_VM; |
| 285 | args.start = 0; |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 286 | args.limit = cli->vm->vmm->limit - 1; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 287 | } else |
| 288 | if (chan->drm->agp.stat == ENABLED) { |
| 289 | args.flags = NV_DMA_TARGET_AGP | NV_DMA_ACCESS_RDWR; |
| 290 | args.start = chan->drm->agp.base; |
| 291 | args.limit = chan->drm->agp.base + |
| 292 | chan->drm->agp.size - 1; |
| 293 | } else { |
| 294 | args.flags = NV_DMA_TARGET_VM | NV_DMA_ACCESS_RDWR; |
| 295 | args.start = 0; |
| 296 | args.limit = vmm->limit - 1; |
| 297 | } |
| 298 | |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 299 | ret = nvif_object_init(chan->object, NULL, gart, |
| 300 | NV_DMA_IN_MEMORY_CLASS, &args, |
| 301 | sizeof(args), &chan->gart); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 302 | if (ret) |
| 303 | return ret; |
| 304 | } |
| 305 | |
| 306 | /* initialise dma tracking parameters */ |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 307 | switch (chan->object->oclass & 0x00ff) { |
Ben Skeggs | 503b0f1 | 2012-08-14 14:53:51 +1000 | [diff] [blame] | 308 | case 0x006b: |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 309 | case 0x006e: |
| 310 | chan->user_put = 0x40; |
| 311 | chan->user_get = 0x44; |
| 312 | chan->dma.max = (0x10000 / 4) - 2; |
| 313 | break; |
| 314 | default: |
| 315 | chan->user_put = 0x40; |
| 316 | chan->user_get = 0x44; |
| 317 | chan->user_get_hi = 0x60; |
| 318 | chan->dma.ib_base = 0x10000 / 4; |
| 319 | chan->dma.ib_max = (0x02000 / 8) - 1; |
| 320 | chan->dma.ib_put = 0; |
| 321 | chan->dma.ib_free = chan->dma.ib_max - chan->dma.ib_put; |
| 322 | chan->dma.max = chan->dma.ib_base; |
| 323 | break; |
| 324 | } |
| 325 | |
| 326 | chan->dma.put = 0; |
| 327 | chan->dma.cur = chan->dma.put; |
| 328 | chan->dma.free = chan->dma.max - chan->dma.cur; |
| 329 | |
| 330 | ret = RING_SPACE(chan, NOUVEAU_DMA_SKIPS); |
| 331 | if (ret) |
| 332 | return ret; |
| 333 | |
| 334 | for (i = 0; i < NOUVEAU_DMA_SKIPS; i++) |
| 335 | OUT_RING(chan, 0x00000000); |
| 336 | |
Ben Skeggs | 69a6146 | 2013-11-13 10:58:51 +1000 | [diff] [blame] | 337 | /* allocate software object class (used for fences on <= nv05) */ |
Ben Skeggs | 967e7bd | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 338 | if (device->info.family < NV_DEVICE_INFO_V0_CELSIUS) { |
Ben Skeggs | f45f55c | 2014-08-10 04:10:23 +1000 | [diff] [blame] | 339 | ret = nvif_object_init(chan->object, NULL, 0x006e, 0x006e, |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 340 | NULL, 0, &chan->nvsw); |
Ben Skeggs | 4998104 | 2012-08-06 19:38:25 +1000 | [diff] [blame] | 341 | if (ret) |
| 342 | return ret; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 343 | |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 344 | swch = (void *)nvkm_object(&chan->nvsw)->parent; |
Ben Skeggs | 4998104 | 2012-08-06 19:38:25 +1000 | [diff] [blame] | 345 | swch->flip = nouveau_flip_complete; |
| 346 | swch->flip_data = chan; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 347 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 348 | ret = RING_SPACE(chan, 2); |
| 349 | if (ret) |
| 350 | return ret; |
| 351 | |
| 352 | BEGIN_NV04(chan, NvSubSw, 0x0000, 1); |
Ben Skeggs | f45f55c | 2014-08-10 04:10:23 +1000 | [diff] [blame] | 353 | OUT_RING (chan, chan->nvsw.handle); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 354 | FIRE_RING (chan); |
| 355 | } |
| 356 | |
| 357 | /* initialise synchronisation */ |
| 358 | return nouveau_fence(chan->drm)->context_new(chan); |
| 359 | } |
| 360 | |
| 361 | int |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 362 | nouveau_channel_new(struct nouveau_drm *drm, struct nvif_device *device, |
| 363 | u32 handle, u32 arg0, u32 arg1, |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 364 | struct nouveau_channel **pchan) |
| 365 | { |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 366 | struct nouveau_cli *cli = (void *)nvif_client(&device->base); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 367 | int ret; |
| 368 | |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 369 | ret = nouveau_channel_ind(drm, device, handle, arg0, pchan); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 370 | if (ret) { |
Ben Skeggs | fa2bade | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 371 | NV_PRINTK(debug, cli, "ib channel create, %d\n", ret); |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 372 | ret = nouveau_channel_dma(drm, device, handle, pchan); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 373 | if (ret) { |
Ben Skeggs | fa2bade | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 374 | NV_PRINTK(debug, cli, "dma channel create, %d\n", ret); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 375 | return ret; |
| 376 | } |
| 377 | } |
| 378 | |
Ben Skeggs | 4998104 | 2012-08-06 19:38:25 +1000 | [diff] [blame] | 379 | ret = nouveau_channel_init(*pchan, arg0, arg1); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 380 | if (ret) { |
Ben Skeggs | fa2bade | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 381 | NV_PRINTK(error, cli, "channel failed to initialise, %d\n", ret); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 382 | nouveau_channel_del(pchan); |
| 383 | return ret; |
| 384 | } |
| 385 | |
| 386 | return 0; |
| 387 | } |