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Zhu Yib481de92007-09-25 17:54:57 -07001/******************************************************************************
2 *
3 * Copyright(c) 2003 - 2007 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/version.h>
30#include <linux/init.h>
31#include <linux/pci.h>
32#include <linux/dma-mapping.h>
33#include <linux/delay.h>
34#include <linux/skbuff.h>
35#include <linux/netdevice.h>
36#include <linux/wireless.h>
37#include <net/mac80211.h>
Zhu Yib481de92007-09-25 17:54:57 -070038#include <linux/etherdevice.h>
Zhu Yi12342c42007-12-20 11:27:32 +080039#include <asm/unaligned.h>
Zhu Yib481de92007-09-25 17:54:57 -070040
Zhu Yib481de92007-09-25 17:54:57 -070041#include "iwl-4965.h"
42#include "iwl-helpers.h"
43
Christoph Hellwigbb8c0932008-01-27 16:41:47 -080044static void iwl4965_hw_card_show_info(struct iwl4965_priv *priv);
Christoph Hellwig416e1432007-10-25 17:15:49 +080045
Zhu Yib481de92007-09-25 17:54:57 -070046#define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
47 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
48 IWL_RATE_SISO_##s##M_PLCP, \
49 IWL_RATE_MIMO_##s##M_PLCP, \
50 IWL_RATE_##r##M_IEEE, \
51 IWL_RATE_##ip##M_INDEX, \
52 IWL_RATE_##in##M_INDEX, \
53 IWL_RATE_##rp##M_INDEX, \
54 IWL_RATE_##rn##M_INDEX, \
55 IWL_RATE_##pp##M_INDEX, \
56 IWL_RATE_##np##M_INDEX }
57
58/*
59 * Parameter order:
60 * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
61 *
62 * If there isn't a valid next or previous rate then INV is used which
63 * maps to IWL_RATE_INVALID
64 *
65 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -080066const struct iwl4965_rate_info iwl4965_rates[IWL_RATE_COUNT] = {
Zhu Yib481de92007-09-25 17:54:57 -070067 IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
68 IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
69 IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
70 IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
71 IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
72 IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
73 IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
74 IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
75 IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
76 IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
77 IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
78 IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
79 IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
80};
81
Ron Rindjunskyfe01b472008-01-28 14:07:24 +020082#ifdef CONFIG_IWL4965_HT
83
84static const u16 default_tid_to_tx_fifo[] = {
85 IWL_TX_FIFO_AC1,
86 IWL_TX_FIFO_AC0,
87 IWL_TX_FIFO_AC0,
88 IWL_TX_FIFO_AC1,
89 IWL_TX_FIFO_AC2,
90 IWL_TX_FIFO_AC2,
91 IWL_TX_FIFO_AC3,
92 IWL_TX_FIFO_AC3,
93 IWL_TX_FIFO_NONE,
94 IWL_TX_FIFO_NONE,
95 IWL_TX_FIFO_NONE,
96 IWL_TX_FIFO_NONE,
97 IWL_TX_FIFO_NONE,
98 IWL_TX_FIFO_NONE,
99 IWL_TX_FIFO_NONE,
100 IWL_TX_FIFO_NONE,
101 IWL_TX_FIFO_AC3
102};
103
104#endif /*CONFIG_IWL4965_HT */
105
Zhu Yib481de92007-09-25 17:54:57 -0700106static int is_fat_channel(__le32 rxon_flags)
107{
108 return (rxon_flags & RXON_FLG_CHANNEL_MODE_PURE_40_MSK) ||
109 (rxon_flags & RXON_FLG_CHANNEL_MODE_MIXED_MSK);
110}
111
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800112static u8 is_single_stream(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -0700113{
Christoph Hellwigc8b0e6e2007-10-25 17:15:51 +0800114#ifdef CONFIG_IWL4965_HT
Ron Rindjunskyfd105e72007-11-26 16:14:39 +0200115 if (!priv->current_ht_config.is_ht ||
116 (priv->current_ht_config.supp_mcs_set[1] == 0) ||
Zhu Yib481de92007-09-25 17:54:57 -0700117 (priv->ps_mode == IWL_MIMO_PS_STATIC))
118 return 1;
119#else
120 return 1;
Christoph Hellwigc8b0e6e2007-10-25 17:15:51 +0800121#endif /*CONFIG_IWL4965_HT */
Zhu Yib481de92007-09-25 17:54:57 -0700122 return 0;
123}
124
125/*
126 * Determine how many receiver/antenna chains to use.
127 * More provides better reception via diversity. Fewer saves power.
128 * MIMO (dual stream) requires at least 2, but works better with 3.
129 * This does not determine *which* chains to use, just how many.
130 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800131static int iwl4965_get_rx_chain_counter(struct iwl4965_priv *priv,
Zhu Yib481de92007-09-25 17:54:57 -0700132 u8 *idle_state, u8 *rx_state)
133{
134 u8 is_single = is_single_stream(priv);
135 u8 is_cam = test_bit(STATUS_POWER_PMI, &priv->status) ? 0 : 1;
136
137 /* # of Rx chains to use when expecting MIMO. */
138 if (is_single || (!is_cam && (priv->ps_mode == IWL_MIMO_PS_STATIC)))
139 *rx_state = 2;
140 else
141 *rx_state = 3;
142
143 /* # Rx chains when idling and maybe trying to save power */
144 switch (priv->ps_mode) {
145 case IWL_MIMO_PS_STATIC:
146 case IWL_MIMO_PS_DYNAMIC:
147 *idle_state = (is_cam) ? 2 : 1;
148 break;
149 case IWL_MIMO_PS_NONE:
150 *idle_state = (is_cam) ? *rx_state : 1;
151 break;
152 default:
153 *idle_state = 1;
154 break;
155 }
156
157 return 0;
158}
159
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800160int iwl4965_hw_rxq_stop(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -0700161{
162 int rc;
163 unsigned long flags;
164
165 spin_lock_irqsave(&priv->lock, flags);
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800166 rc = iwl4965_grab_nic_access(priv);
Zhu Yib481de92007-09-25 17:54:57 -0700167 if (rc) {
168 spin_unlock_irqrestore(&priv->lock, flags);
169 return rc;
170 }
171
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +0800172 /* stop Rx DMA */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800173 iwl4965_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
174 rc = iwl4965_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
Zhu Yib481de92007-09-25 17:54:57 -0700175 (1 << 24), 1000);
176 if (rc < 0)
177 IWL_ERROR("Can't stop Rx DMA.\n");
178
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800179 iwl4965_release_nic_access(priv);
Zhu Yib481de92007-09-25 17:54:57 -0700180 spin_unlock_irqrestore(&priv->lock, flags);
181
182 return 0;
183}
184
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800185u8 iwl4965_hw_find_station(struct iwl4965_priv *priv, const u8 *addr)
Zhu Yib481de92007-09-25 17:54:57 -0700186{
187 int i;
188 int start = 0;
189 int ret = IWL_INVALID_STATION;
190 unsigned long flags;
Joe Perches0795af52007-10-03 17:59:30 -0700191 DECLARE_MAC_BUF(mac);
Zhu Yib481de92007-09-25 17:54:57 -0700192
193 if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) ||
194 (priv->iw_mode == IEEE80211_IF_TYPE_AP))
195 start = IWL_STA_ID;
196
197 if (is_broadcast_ether_addr(addr))
198 return IWL4965_BROADCAST_ID;
199
200 spin_lock_irqsave(&priv->sta_lock, flags);
201 for (i = start; i < priv->hw_setting.max_stations; i++)
202 if ((priv->stations[i].used) &&
203 (!compare_ether_addr
204 (priv->stations[i].sta.sta.addr, addr))) {
205 ret = i;
206 goto out;
207 }
208
John W. Linvillea50e2e32007-09-27 17:00:29 -0400209 IWL_DEBUG_ASSOC_LIMIT("can not find STA %s total %d\n",
Joe Perches0795af52007-10-03 17:59:30 -0700210 print_mac(mac, addr), priv->num_stations);
Zhu Yib481de92007-09-25 17:54:57 -0700211
212 out:
213 spin_unlock_irqrestore(&priv->sta_lock, flags);
214 return ret;
215}
216
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800217static int iwl4965_nic_set_pwr_src(struct iwl4965_priv *priv, int pwr_max)
Zhu Yib481de92007-09-25 17:54:57 -0700218{
Tomas Winklerd8609652007-10-25 17:15:35 +0800219 int ret;
Zhu Yib481de92007-09-25 17:54:57 -0700220 unsigned long flags;
221
222 spin_lock_irqsave(&priv->lock, flags);
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800223 ret = iwl4965_grab_nic_access(priv);
Tomas Winklerd8609652007-10-25 17:15:35 +0800224 if (ret) {
Zhu Yib481de92007-09-25 17:54:57 -0700225 spin_unlock_irqrestore(&priv->lock, flags);
Tomas Winklerd8609652007-10-25 17:15:35 +0800226 return ret;
Zhu Yib481de92007-09-25 17:54:57 -0700227 }
228
229 if (!pwr_max) {
230 u32 val;
231
Tomas Winklerd8609652007-10-25 17:15:35 +0800232 ret = pci_read_config_dword(priv->pci_dev, PCI_POWER_SOURCE,
Zhu Yib481de92007-09-25 17:54:57 -0700233 &val);
234
235 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT)
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800236 iwl4965_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
Zhu Yib481de92007-09-25 17:54:57 -0700237 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
238 ~APMG_PS_CTRL_MSK_PWR_SRC);
239 } else
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800240 iwl4965_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
Zhu Yib481de92007-09-25 17:54:57 -0700241 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
242 ~APMG_PS_CTRL_MSK_PWR_SRC);
243
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800244 iwl4965_release_nic_access(priv);
Zhu Yib481de92007-09-25 17:54:57 -0700245 spin_unlock_irqrestore(&priv->lock, flags);
246
Tomas Winklerd8609652007-10-25 17:15:35 +0800247 return ret;
Zhu Yib481de92007-09-25 17:54:57 -0700248}
249
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800250static int iwl4965_rx_init(struct iwl4965_priv *priv, struct iwl4965_rx_queue *rxq)
Zhu Yib481de92007-09-25 17:54:57 -0700251{
252 int rc;
253 unsigned long flags;
Ron Rindjunsky9ee1ba42007-11-26 16:14:42 +0200254 unsigned int rb_size;
Zhu Yib481de92007-09-25 17:54:57 -0700255
256 spin_lock_irqsave(&priv->lock, flags);
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800257 rc = iwl4965_grab_nic_access(priv);
Zhu Yib481de92007-09-25 17:54:57 -0700258 if (rc) {
259 spin_unlock_irqrestore(&priv->lock, flags);
260 return rc;
261 }
262
Ron Rindjunsky9ee1ba42007-11-26 16:14:42 +0200263 if (iwl4965_param_amsdu_size_8K)
264 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
265 else
266 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
267
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +0800268 /* Stop Rx DMA */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800269 iwl4965_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
Zhu Yib481de92007-09-25 17:54:57 -0700270
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +0800271 /* Reset driver's Rx queue write index */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800272 iwl4965_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +0800273
274 /* Tell device where to find RBD circular buffer in DRAM */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800275 iwl4965_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
Zhu Yib481de92007-09-25 17:54:57 -0700276 rxq->dma_addr >> 8);
277
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +0800278 /* Tell device where in DRAM to update its Rx status */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800279 iwl4965_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
Zhu Yib481de92007-09-25 17:54:57 -0700280 (priv->hw_setting.shared_phys +
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800281 offsetof(struct iwl4965_shared, val0)) >> 4);
Zhu Yib481de92007-09-25 17:54:57 -0700282
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +0800283 /* Enable Rx DMA, enable host interrupt, Rx buffer size 4k, 256 RBDs */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800284 iwl4965_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
Zhu Yib481de92007-09-25 17:54:57 -0700285 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
286 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
Ron Rindjunsky9ee1ba42007-11-26 16:14:42 +0200287 rb_size |
Zhu Yib481de92007-09-25 17:54:57 -0700288 /*0x10 << 4 | */
289 (RX_QUEUE_SIZE_LOG <<
290 FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT));
291
292 /*
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800293 * iwl4965_write32(priv,CSR_INT_COAL_REG,0);
Zhu Yib481de92007-09-25 17:54:57 -0700294 */
295
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800296 iwl4965_release_nic_access(priv);
Zhu Yib481de92007-09-25 17:54:57 -0700297 spin_unlock_irqrestore(&priv->lock, flags);
298
299 return 0;
300}
301
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +0800302/* Tell 4965 where to find the "keep warm" buffer */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800303static int iwl4965_kw_init(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -0700304{
305 unsigned long flags;
306 int rc;
307
308 spin_lock_irqsave(&priv->lock, flags);
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800309 rc = iwl4965_grab_nic_access(priv);
Zhu Yib481de92007-09-25 17:54:57 -0700310 if (rc)
311 goto out;
312
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800313 iwl4965_write_direct32(priv, IWL_FH_KW_MEM_ADDR_REG,
Zhu Yib481de92007-09-25 17:54:57 -0700314 priv->kw.dma_addr >> 4);
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800315 iwl4965_release_nic_access(priv);
Zhu Yib481de92007-09-25 17:54:57 -0700316out:
317 spin_unlock_irqrestore(&priv->lock, flags);
318 return rc;
319}
320
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800321static int iwl4965_kw_alloc(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -0700322{
323 struct pci_dev *dev = priv->pci_dev;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800324 struct iwl4965_kw *kw = &priv->kw;
Zhu Yib481de92007-09-25 17:54:57 -0700325
326 kw->size = IWL4965_KW_SIZE; /* TBW need set somewhere else */
327 kw->v_addr = pci_alloc_consistent(dev, kw->size, &kw->dma_addr);
328 if (!kw->v_addr)
329 return -ENOMEM;
330
331 return 0;
332}
333
334#define CHECK_AND_PRINT(x) ((eeprom_ch->flags & EEPROM_CHANNEL_##x) \
335 ? # x " " : "")
336
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +0800337/**
338 * iwl4965_set_fat_chan_info - Copy fat channel info into driver's priv.
339 *
340 * Does not set up a command, or touch hardware.
341 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800342int iwl4965_set_fat_chan_info(struct iwl4965_priv *priv, int phymode, u16 channel,
343 const struct iwl4965_eeprom_channel *eeprom_ch,
Zhu Yib481de92007-09-25 17:54:57 -0700344 u8 fat_extension_channel)
345{
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800346 struct iwl4965_channel_info *ch_info;
Zhu Yib481de92007-09-25 17:54:57 -0700347
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800348 ch_info = (struct iwl4965_channel_info *)
349 iwl4965_get_channel_info(priv, phymode, channel);
Zhu Yib481de92007-09-25 17:54:57 -0700350
351 if (!is_channel_valid(ch_info))
352 return -1;
353
354 IWL_DEBUG_INFO("FAT Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x"
355 " %ddBm): Ad-Hoc %ssupported\n",
356 ch_info->channel,
357 is_channel_a_band(ch_info) ?
358 "5.2" : "2.4",
359 CHECK_AND_PRINT(IBSS),
360 CHECK_AND_PRINT(ACTIVE),
361 CHECK_AND_PRINT(RADAR),
362 CHECK_AND_PRINT(WIDE),
363 CHECK_AND_PRINT(NARROW),
364 CHECK_AND_PRINT(DFS),
365 eeprom_ch->flags,
366 eeprom_ch->max_power_avg,
367 ((eeprom_ch->flags & EEPROM_CHANNEL_IBSS)
368 && !(eeprom_ch->flags & EEPROM_CHANNEL_RADAR)) ?
369 "" : "not ");
370
371 ch_info->fat_eeprom = *eeprom_ch;
372 ch_info->fat_max_power_avg = eeprom_ch->max_power_avg;
373 ch_info->fat_curr_txpow = eeprom_ch->max_power_avg;
374 ch_info->fat_min_power = 0;
375 ch_info->fat_scan_power = eeprom_ch->max_power_avg;
376 ch_info->fat_flags = eeprom_ch->flags;
377 ch_info->fat_extension_channel = fat_extension_channel;
378
379 return 0;
380}
381
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +0800382/**
383 * iwl4965_kw_free - Free the "keep warm" buffer
384 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800385static void iwl4965_kw_free(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -0700386{
387 struct pci_dev *dev = priv->pci_dev;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800388 struct iwl4965_kw *kw = &priv->kw;
Zhu Yib481de92007-09-25 17:54:57 -0700389
390 if (kw->v_addr) {
391 pci_free_consistent(dev, kw->size, kw->v_addr, kw->dma_addr);
392 memset(kw, 0, sizeof(*kw));
393 }
394}
395
396/**
397 * iwl4965_txq_ctx_reset - Reset TX queue context
398 * Destroys all DMA structures and initialise them again
399 *
400 * @param priv
401 * @return error code
402 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800403static int iwl4965_txq_ctx_reset(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -0700404{
405 int rc = 0;
406 int txq_id, slots_num;
407 unsigned long flags;
408
409 iwl4965_kw_free(priv);
410
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +0800411 /* Free all tx/cmd queues and keep-warm buffer */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800412 iwl4965_hw_txq_ctx_free(priv);
Zhu Yib481de92007-09-25 17:54:57 -0700413
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +0800414 /* Alloc keep-warm buffer */
Zhu Yib481de92007-09-25 17:54:57 -0700415 rc = iwl4965_kw_alloc(priv);
416 if (rc) {
417 IWL_ERROR("Keep Warm allocation failed");
418 goto error_kw;
419 }
420
421 spin_lock_irqsave(&priv->lock, flags);
422
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800423 rc = iwl4965_grab_nic_access(priv);
Zhu Yib481de92007-09-25 17:54:57 -0700424 if (unlikely(rc)) {
425 IWL_ERROR("TX reset failed");
426 spin_unlock_irqrestore(&priv->lock, flags);
427 goto error_reset;
428 }
429
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +0800430 /* Turn off all Tx DMA channels */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800431 iwl4965_write_prph(priv, KDR_SCD_TXFACT, 0);
432 iwl4965_release_nic_access(priv);
Zhu Yib481de92007-09-25 17:54:57 -0700433 spin_unlock_irqrestore(&priv->lock, flags);
434
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +0800435 /* Tell 4965 where to find the keep-warm buffer */
Zhu Yib481de92007-09-25 17:54:57 -0700436 rc = iwl4965_kw_init(priv);
437 if (rc) {
438 IWL_ERROR("kw_init failed\n");
439 goto error_reset;
440 }
441
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +0800442 /* Alloc and init all (default 16) Tx queues,
443 * including the command queue (#4) */
Zhu Yib481de92007-09-25 17:54:57 -0700444 for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++) {
445 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
446 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800447 rc = iwl4965_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
Zhu Yib481de92007-09-25 17:54:57 -0700448 txq_id);
449 if (rc) {
450 IWL_ERROR("Tx %d queue init failed\n", txq_id);
451 goto error;
452 }
453 }
454
455 return rc;
456
457 error:
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800458 iwl4965_hw_txq_ctx_free(priv);
Zhu Yib481de92007-09-25 17:54:57 -0700459 error_reset:
460 iwl4965_kw_free(priv);
461 error_kw:
462 return rc;
463}
464
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800465int iwl4965_hw_nic_init(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -0700466{
467 int rc;
468 unsigned long flags;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800469 struct iwl4965_rx_queue *rxq = &priv->rxq;
Zhu Yib481de92007-09-25 17:54:57 -0700470 u8 rev_id;
471 u32 val;
472 u8 val_link;
473
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800474 iwl4965_power_init_handle(priv);
Zhu Yib481de92007-09-25 17:54:57 -0700475
476 /* nic_init */
477 spin_lock_irqsave(&priv->lock, flags);
478
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800479 iwl4965_set_bit(priv, CSR_GIO_CHICKEN_BITS,
Zhu Yib481de92007-09-25 17:54:57 -0700480 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
481
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800482 iwl4965_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
483 rc = iwl4965_poll_bit(priv, CSR_GP_CNTRL,
Zhu Yib481de92007-09-25 17:54:57 -0700484 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
485 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
486 if (rc < 0) {
487 spin_unlock_irqrestore(&priv->lock, flags);
488 IWL_DEBUG_INFO("Failed to init the card\n");
489 return rc;
490 }
491
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800492 rc = iwl4965_grab_nic_access(priv);
Zhu Yib481de92007-09-25 17:54:57 -0700493 if (rc) {
494 spin_unlock_irqrestore(&priv->lock, flags);
495 return rc;
496 }
497
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800498 iwl4965_read_prph(priv, APMG_CLK_CTRL_REG);
Zhu Yib481de92007-09-25 17:54:57 -0700499
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800500 iwl4965_write_prph(priv, APMG_CLK_CTRL_REG,
Zhu Yib481de92007-09-25 17:54:57 -0700501 APMG_CLK_VAL_DMA_CLK_RQT |
502 APMG_CLK_VAL_BSM_CLK_RQT);
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800503 iwl4965_read_prph(priv, APMG_CLK_CTRL_REG);
Zhu Yib481de92007-09-25 17:54:57 -0700504
505 udelay(20);
506
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800507 iwl4965_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
Zhu Yib481de92007-09-25 17:54:57 -0700508 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
509
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800510 iwl4965_release_nic_access(priv);
511 iwl4965_write32(priv, CSR_INT_COALESCING, 512 / 32);
Zhu Yib481de92007-09-25 17:54:57 -0700512 spin_unlock_irqrestore(&priv->lock, flags);
513
514 /* Determine HW type */
515 rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
516 if (rc)
517 return rc;
518
519 IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id);
520
521 iwl4965_nic_set_pwr_src(priv, 1);
522 spin_lock_irqsave(&priv->lock, flags);
523
524 if ((rev_id & 0x80) == 0x80 && (rev_id & 0x7f) < 8) {
525 pci_read_config_dword(priv->pci_dev, PCI_REG_WUM8, &val);
526 /* Enable No Snoop field */
527 pci_write_config_dword(priv->pci_dev, PCI_REG_WUM8,
528 val & ~(1 << 11));
529 }
530
531 spin_unlock_irqrestore(&priv->lock, flags);
532
Zhu Yib481de92007-09-25 17:54:57 -0700533 if (priv->eeprom.calib_version < EEPROM_TX_POWER_VERSION_NEW) {
534 IWL_ERROR("Older EEPROM detected! Aborting.\n");
535 return -EINVAL;
536 }
537
538 pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link);
539
540 /* disable L1 entry -- workaround for pre-B1 */
541 pci_write_config_byte(priv->pci_dev, PCI_LINK_CTRL, val_link & ~0x02);
542
543 spin_lock_irqsave(&priv->lock, flags);
544
545 /* set CSR_HW_CONFIG_REG for uCode use */
546
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800547 iwl4965_set_bit(priv, CSR_SW_VER, CSR_HW_IF_CONFIG_REG_BIT_KEDRON_R |
Zhu Yib481de92007-09-25 17:54:57 -0700548 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
549 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
550
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800551 rc = iwl4965_grab_nic_access(priv);
Zhu Yib481de92007-09-25 17:54:57 -0700552 if (rc < 0) {
553 spin_unlock_irqrestore(&priv->lock, flags);
554 IWL_DEBUG_INFO("Failed to init the card\n");
555 return rc;
556 }
557
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800558 iwl4965_read_prph(priv, APMG_PS_CTRL_REG);
559 iwl4965_set_bits_prph(priv, APMG_PS_CTRL_REG,
Zhu Yib481de92007-09-25 17:54:57 -0700560 APMG_PS_CTRL_VAL_RESET_REQ);
561 udelay(5);
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800562 iwl4965_clear_bits_prph(priv, APMG_PS_CTRL_REG,
Zhu Yib481de92007-09-25 17:54:57 -0700563 APMG_PS_CTRL_VAL_RESET_REQ);
564
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800565 iwl4965_release_nic_access(priv);
Zhu Yib481de92007-09-25 17:54:57 -0700566 spin_unlock_irqrestore(&priv->lock, flags);
567
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800568 iwl4965_hw_card_show_info(priv);
Zhu Yib481de92007-09-25 17:54:57 -0700569
570 /* end nic_init */
571
572 /* Allocate the RX queue, or reset if it is already allocated */
573 if (!rxq->bd) {
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800574 rc = iwl4965_rx_queue_alloc(priv);
Zhu Yib481de92007-09-25 17:54:57 -0700575 if (rc) {
576 IWL_ERROR("Unable to initialize Rx queue\n");
577 return -ENOMEM;
578 }
579 } else
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800580 iwl4965_rx_queue_reset(priv, rxq);
Zhu Yib481de92007-09-25 17:54:57 -0700581
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800582 iwl4965_rx_replenish(priv);
Zhu Yib481de92007-09-25 17:54:57 -0700583
584 iwl4965_rx_init(priv, rxq);
585
586 spin_lock_irqsave(&priv->lock, flags);
587
588 rxq->need_update = 1;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800589 iwl4965_rx_queue_update_write_ptr(priv, rxq);
Zhu Yib481de92007-09-25 17:54:57 -0700590
591 spin_unlock_irqrestore(&priv->lock, flags);
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +0800592
593 /* Allocate and init all Tx and Command queues */
Zhu Yib481de92007-09-25 17:54:57 -0700594 rc = iwl4965_txq_ctx_reset(priv);
595 if (rc)
596 return rc;
597
598 if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
599 IWL_DEBUG_RF_KILL("SW RF KILL supported in EEPROM.\n");
600
601 if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
602 IWL_DEBUG_RF_KILL("HW RF KILL supported in EEPROM.\n");
603
604 set_bit(STATUS_INIT, &priv->status);
605
606 return 0;
607}
608
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800609int iwl4965_hw_nic_stop_master(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -0700610{
611 int rc = 0;
612 u32 reg_val;
613 unsigned long flags;
614
615 spin_lock_irqsave(&priv->lock, flags);
616
617 /* set stop master bit */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800618 iwl4965_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
Zhu Yib481de92007-09-25 17:54:57 -0700619
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800620 reg_val = iwl4965_read32(priv, CSR_GP_CNTRL);
Zhu Yib481de92007-09-25 17:54:57 -0700621
622 if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE ==
623 (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE))
624 IWL_DEBUG_INFO("Card in power save, master is already "
625 "stopped\n");
626 else {
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800627 rc = iwl4965_poll_bit(priv, CSR_RESET,
Zhu Yib481de92007-09-25 17:54:57 -0700628 CSR_RESET_REG_FLAG_MASTER_DISABLED,
629 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
630 if (rc < 0) {
631 spin_unlock_irqrestore(&priv->lock, flags);
632 return rc;
633 }
634 }
635
636 spin_unlock_irqrestore(&priv->lock, flags);
637 IWL_DEBUG_INFO("stop master\n");
638
639 return rc;
640}
641
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +0800642/**
643 * iwl4965_hw_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
644 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800645void iwl4965_hw_txq_ctx_stop(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -0700646{
647
648 int txq_id;
649 unsigned long flags;
650
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +0800651 /* Stop each Tx DMA channel, and wait for it to be idle */
Zhu Yib481de92007-09-25 17:54:57 -0700652 for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++) {
653 spin_lock_irqsave(&priv->lock, flags);
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800654 if (iwl4965_grab_nic_access(priv)) {
Zhu Yib481de92007-09-25 17:54:57 -0700655 spin_unlock_irqrestore(&priv->lock, flags);
656 continue;
657 }
658
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800659 iwl4965_write_direct32(priv,
Zhu Yib481de92007-09-25 17:54:57 -0700660 IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
661 0x0);
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800662 iwl4965_poll_direct_bit(priv, IWL_FH_TSSR_TX_STATUS_REG,
Zhu Yib481de92007-09-25 17:54:57 -0700663 IWL_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE
664 (txq_id), 200);
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800665 iwl4965_release_nic_access(priv);
Zhu Yib481de92007-09-25 17:54:57 -0700666 spin_unlock_irqrestore(&priv->lock, flags);
667 }
668
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +0800669 /* Deallocate memory for all Tx queues */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800670 iwl4965_hw_txq_ctx_free(priv);
Zhu Yib481de92007-09-25 17:54:57 -0700671}
672
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800673int iwl4965_hw_nic_reset(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -0700674{
675 int rc = 0;
676 unsigned long flags;
677
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800678 iwl4965_hw_nic_stop_master(priv);
Zhu Yib481de92007-09-25 17:54:57 -0700679
680 spin_lock_irqsave(&priv->lock, flags);
681
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800682 iwl4965_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
Zhu Yib481de92007-09-25 17:54:57 -0700683
684 udelay(10);
685
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800686 iwl4965_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
687 rc = iwl4965_poll_bit(priv, CSR_RESET,
Zhu Yib481de92007-09-25 17:54:57 -0700688 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
689 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25);
690
691 udelay(10);
692
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800693 rc = iwl4965_grab_nic_access(priv);
Zhu Yib481de92007-09-25 17:54:57 -0700694 if (!rc) {
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800695 iwl4965_write_prph(priv, APMG_CLK_EN_REG,
Zhu Yib481de92007-09-25 17:54:57 -0700696 APMG_CLK_VAL_DMA_CLK_RQT |
697 APMG_CLK_VAL_BSM_CLK_RQT);
698
699 udelay(10);
700
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800701 iwl4965_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
Zhu Yib481de92007-09-25 17:54:57 -0700702 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
703
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800704 iwl4965_release_nic_access(priv);
Zhu Yib481de92007-09-25 17:54:57 -0700705 }
706
707 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
708 wake_up_interruptible(&priv->wait_command_queue);
709
710 spin_unlock_irqrestore(&priv->lock, flags);
711
712 return rc;
713
714}
715
716#define REG_RECALIB_PERIOD (60)
717
718/**
719 * iwl4965_bg_statistics_periodic - Timer callback to queue statistics
720 *
721 * This callback is provided in order to queue the statistics_work
722 * in work_queue context (v. softirq)
723 *
724 * This timer function is continually reset to execute within
725 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
726 * was received. We need to ensure we receive the statistics in order
727 * to update the temperature used for calibrating the TXPOWER. However,
728 * we can't send the statistics command from softirq context (which
729 * is the context which timers run at) so we have to queue off the
730 * statistics_work to actually send the command to the hardware.
731 */
732static void iwl4965_bg_statistics_periodic(unsigned long data)
733{
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800734 struct iwl4965_priv *priv = (struct iwl4965_priv *)data;
Zhu Yib481de92007-09-25 17:54:57 -0700735
736 queue_work(priv->workqueue, &priv->statistics_work);
737}
738
739/**
740 * iwl4965_bg_statistics_work - Send the statistics request to the hardware.
741 *
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800742 * This is queued by iwl4965_bg_statistics_periodic.
Zhu Yib481de92007-09-25 17:54:57 -0700743 */
744static void iwl4965_bg_statistics_work(struct work_struct *work)
745{
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800746 struct iwl4965_priv *priv = container_of(work, struct iwl4965_priv,
Zhu Yib481de92007-09-25 17:54:57 -0700747 statistics_work);
748
749 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
750 return;
751
752 mutex_lock(&priv->mutex);
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800753 iwl4965_send_statistics_request(priv);
Zhu Yib481de92007-09-25 17:54:57 -0700754 mutex_unlock(&priv->mutex);
755}
756
757#define CT_LIMIT_CONST 259
758#define TM_CT_KILL_THRESHOLD 110
759
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800760void iwl4965_rf_kill_ct_config(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -0700761{
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800762 struct iwl4965_ct_kill_config cmd;
Zhu Yib481de92007-09-25 17:54:57 -0700763 u32 R1, R2, R3;
764 u32 temp_th;
765 u32 crit_temperature;
766 unsigned long flags;
767 int rc = 0;
768
769 spin_lock_irqsave(&priv->lock, flags);
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800770 iwl4965_write32(priv, CSR_UCODE_DRV_GP1_CLR,
Zhu Yib481de92007-09-25 17:54:57 -0700771 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
772 spin_unlock_irqrestore(&priv->lock, flags);
773
774 if (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK) {
775 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
776 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
777 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
778 } else {
779 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
780 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
781 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
782 }
783
784 temp_th = CELSIUS_TO_KELVIN(TM_CT_KILL_THRESHOLD);
785
786 crit_temperature = ((temp_th * (R3-R1))/CT_LIMIT_CONST) + R2;
787 cmd.critical_temperature_R = cpu_to_le32(crit_temperature);
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800788 rc = iwl4965_send_cmd_pdu(priv,
Zhu Yib481de92007-09-25 17:54:57 -0700789 REPLY_CT_KILL_CONFIG_CMD, sizeof(cmd), &cmd);
790 if (rc)
791 IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
792 else
793 IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded\n");
794}
795
Christoph Hellwigc8b0e6e2007-10-25 17:15:51 +0800796#ifdef CONFIG_IWL4965_SENSITIVITY
Zhu Yib481de92007-09-25 17:54:57 -0700797
798/* "false alarms" are signals that our DSP tries to lock onto,
799 * but then determines that they are either noise, or transmissions
800 * from a distant wireless network (also "noise", really) that get
801 * "stepped on" by stronger transmissions within our own network.
802 * This algorithm attempts to set a sensitivity level that is high
803 * enough to receive all of our own network traffic, but not so
804 * high that our DSP gets too busy trying to lock onto non-network
805 * activity/noise. */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800806static int iwl4965_sens_energy_cck(struct iwl4965_priv *priv,
Zhu Yib481de92007-09-25 17:54:57 -0700807 u32 norm_fa,
808 u32 rx_enable_time,
809 struct statistics_general_data *rx_info)
810{
811 u32 max_nrg_cck = 0;
812 int i = 0;
813 u8 max_silence_rssi = 0;
814 u32 silence_ref = 0;
815 u8 silence_rssi_a = 0;
816 u8 silence_rssi_b = 0;
817 u8 silence_rssi_c = 0;
818 u32 val;
819
820 /* "false_alarms" values below are cross-multiplications to assess the
821 * numbers of false alarms within the measured period of actual Rx
822 * (Rx is off when we're txing), vs the min/max expected false alarms
823 * (some should be expected if rx is sensitive enough) in a
824 * hypothetical listening period of 200 time units (TU), 204.8 msec:
825 *
826 * MIN_FA/fixed-time < false_alarms/actual-rx-time < MAX_FA/beacon-time
827 *
828 * */
829 u32 false_alarms = norm_fa * 200 * 1024;
830 u32 max_false_alarms = MAX_FA_CCK * rx_enable_time;
831 u32 min_false_alarms = MIN_FA_CCK * rx_enable_time;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800832 struct iwl4965_sensitivity_data *data = NULL;
Zhu Yib481de92007-09-25 17:54:57 -0700833
834 data = &(priv->sensitivity_data);
835
836 data->nrg_auto_corr_silence_diff = 0;
837
838 /* Find max silence rssi among all 3 receivers.
839 * This is background noise, which may include transmissions from other
840 * networks, measured during silence before our network's beacon */
841 silence_rssi_a = (u8)((rx_info->beacon_silence_rssi_a &
Reinette Chatre8a1b0242008-01-14 17:46:25 -0800842 ALL_BAND_FILTER) >> 8);
Zhu Yib481de92007-09-25 17:54:57 -0700843 silence_rssi_b = (u8)((rx_info->beacon_silence_rssi_b &
Reinette Chatre8a1b0242008-01-14 17:46:25 -0800844 ALL_BAND_FILTER) >> 8);
Zhu Yib481de92007-09-25 17:54:57 -0700845 silence_rssi_c = (u8)((rx_info->beacon_silence_rssi_c &
Reinette Chatre8a1b0242008-01-14 17:46:25 -0800846 ALL_BAND_FILTER) >> 8);
Zhu Yib481de92007-09-25 17:54:57 -0700847
848 val = max(silence_rssi_b, silence_rssi_c);
849 max_silence_rssi = max(silence_rssi_a, (u8) val);
850
851 /* Store silence rssi in 20-beacon history table */
852 data->nrg_silence_rssi[data->nrg_silence_idx] = max_silence_rssi;
853 data->nrg_silence_idx++;
854 if (data->nrg_silence_idx >= NRG_NUM_PREV_STAT_L)
855 data->nrg_silence_idx = 0;
856
857 /* Find max silence rssi across 20 beacon history */
858 for (i = 0; i < NRG_NUM_PREV_STAT_L; i++) {
859 val = data->nrg_silence_rssi[i];
860 silence_ref = max(silence_ref, val);
861 }
862 IWL_DEBUG_CALIB("silence a %u, b %u, c %u, 20-bcn max %u\n",
863 silence_rssi_a, silence_rssi_b, silence_rssi_c,
864 silence_ref);
865
866 /* Find max rx energy (min value!) among all 3 receivers,
867 * measured during beacon frame.
868 * Save it in 10-beacon history table. */
869 i = data->nrg_energy_idx;
870 val = min(rx_info->beacon_energy_b, rx_info->beacon_energy_c);
871 data->nrg_value[i] = min(rx_info->beacon_energy_a, val);
872
873 data->nrg_energy_idx++;
874 if (data->nrg_energy_idx >= 10)
875 data->nrg_energy_idx = 0;
876
877 /* Find min rx energy (max value) across 10 beacon history.
878 * This is the minimum signal level that we want to receive well.
879 * Add backoff (margin so we don't miss slightly lower energy frames).
880 * This establishes an upper bound (min value) for energy threshold. */
881 max_nrg_cck = data->nrg_value[0];
882 for (i = 1; i < 10; i++)
883 max_nrg_cck = (u32) max(max_nrg_cck, (data->nrg_value[i]));
884 max_nrg_cck += 6;
885
886 IWL_DEBUG_CALIB("rx energy a %u, b %u, c %u, 10-bcn max/min %u\n",
887 rx_info->beacon_energy_a, rx_info->beacon_energy_b,
888 rx_info->beacon_energy_c, max_nrg_cck - 6);
889
890 /* Count number of consecutive beacons with fewer-than-desired
891 * false alarms. */
892 if (false_alarms < min_false_alarms)
893 data->num_in_cck_no_fa++;
894 else
895 data->num_in_cck_no_fa = 0;
896 IWL_DEBUG_CALIB("consecutive bcns with few false alarms = %u\n",
897 data->num_in_cck_no_fa);
898
899 /* If we got too many false alarms this time, reduce sensitivity */
900 if (false_alarms > max_false_alarms) {
901 IWL_DEBUG_CALIB("norm FA %u > max FA %u\n",
902 false_alarms, max_false_alarms);
903 IWL_DEBUG_CALIB("... reducing sensitivity\n");
904 data->nrg_curr_state = IWL_FA_TOO_MANY;
905
906 if (data->auto_corr_cck > AUTO_CORR_MAX_TH_CCK) {
907 /* Store for "fewer than desired" on later beacon */
908 data->nrg_silence_ref = silence_ref;
909
910 /* increase energy threshold (reduce nrg value)
911 * to decrease sensitivity */
912 if (data->nrg_th_cck > (NRG_MAX_CCK + NRG_STEP_CCK))
913 data->nrg_th_cck = data->nrg_th_cck
914 - NRG_STEP_CCK;
915 }
916
917 /* increase auto_corr values to decrease sensitivity */
918 if (data->auto_corr_cck < AUTO_CORR_MAX_TH_CCK)
919 data->auto_corr_cck = AUTO_CORR_MAX_TH_CCK + 1;
920 else {
921 val = data->auto_corr_cck + AUTO_CORR_STEP_CCK;
922 data->auto_corr_cck = min((u32)AUTO_CORR_MAX_CCK, val);
923 }
924 val = data->auto_corr_cck_mrc + AUTO_CORR_STEP_CCK;
925 data->auto_corr_cck_mrc = min((u32)AUTO_CORR_MAX_CCK_MRC, val);
926
927 /* Else if we got fewer than desired, increase sensitivity */
928 } else if (false_alarms < min_false_alarms) {
929 data->nrg_curr_state = IWL_FA_TOO_FEW;
930
931 /* Compare silence level with silence level for most recent
932 * healthy number or too many false alarms */
933 data->nrg_auto_corr_silence_diff = (s32)data->nrg_silence_ref -
934 (s32)silence_ref;
935
936 IWL_DEBUG_CALIB("norm FA %u < min FA %u, silence diff %d\n",
937 false_alarms, min_false_alarms,
938 data->nrg_auto_corr_silence_diff);
939
940 /* Increase value to increase sensitivity, but only if:
941 * 1a) previous beacon did *not* have *too many* false alarms
942 * 1b) AND there's a significant difference in Rx levels
943 * from a previous beacon with too many, or healthy # FAs
944 * OR 2) We've seen a lot of beacons (100) with too few
945 * false alarms */
946 if ((data->nrg_prev_state != IWL_FA_TOO_MANY) &&
947 ((data->nrg_auto_corr_silence_diff > NRG_DIFF) ||
948 (data->num_in_cck_no_fa > MAX_NUMBER_CCK_NO_FA))) {
949
950 IWL_DEBUG_CALIB("... increasing sensitivity\n");
951 /* Increase nrg value to increase sensitivity */
952 val = data->nrg_th_cck + NRG_STEP_CCK;
953 data->nrg_th_cck = min((u32)NRG_MIN_CCK, val);
954
955 /* Decrease auto_corr values to increase sensitivity */
956 val = data->auto_corr_cck - AUTO_CORR_STEP_CCK;
957 data->auto_corr_cck = max((u32)AUTO_CORR_MIN_CCK, val);
958
959 val = data->auto_corr_cck_mrc - AUTO_CORR_STEP_CCK;
960 data->auto_corr_cck_mrc =
961 max((u32)AUTO_CORR_MIN_CCK_MRC, val);
962
963 } else
964 IWL_DEBUG_CALIB("... but not changing sensitivity\n");
965
966 /* Else we got a healthy number of false alarms, keep status quo */
967 } else {
968 IWL_DEBUG_CALIB(" FA in safe zone\n");
969 data->nrg_curr_state = IWL_FA_GOOD_RANGE;
970
971 /* Store for use in "fewer than desired" with later beacon */
972 data->nrg_silence_ref = silence_ref;
973
974 /* If previous beacon had too many false alarms,
975 * give it some extra margin by reducing sensitivity again
976 * (but don't go below measured energy of desired Rx) */
977 if (IWL_FA_TOO_MANY == data->nrg_prev_state) {
978 IWL_DEBUG_CALIB("... increasing margin\n");
979 data->nrg_th_cck -= NRG_MARGIN;
980 }
981 }
982
983 /* Make sure the energy threshold does not go above the measured
984 * energy of the desired Rx signals (reduced by backoff margin),
985 * or else we might start missing Rx frames.
986 * Lower value is higher energy, so we use max()!
987 */
988 data->nrg_th_cck = max(max_nrg_cck, data->nrg_th_cck);
989 IWL_DEBUG_CALIB("new nrg_th_cck %u\n", data->nrg_th_cck);
990
991 data->nrg_prev_state = data->nrg_curr_state;
992
993 return 0;
994}
995
996
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800997static int iwl4965_sens_auto_corr_ofdm(struct iwl4965_priv *priv,
Zhu Yib481de92007-09-25 17:54:57 -0700998 u32 norm_fa,
999 u32 rx_enable_time)
1000{
1001 u32 val;
1002 u32 false_alarms = norm_fa * 200 * 1024;
1003 u32 max_false_alarms = MAX_FA_OFDM * rx_enable_time;
1004 u32 min_false_alarms = MIN_FA_OFDM * rx_enable_time;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001005 struct iwl4965_sensitivity_data *data = NULL;
Zhu Yib481de92007-09-25 17:54:57 -07001006
1007 data = &(priv->sensitivity_data);
1008
1009 /* If we got too many false alarms this time, reduce sensitivity */
1010 if (false_alarms > max_false_alarms) {
1011
1012 IWL_DEBUG_CALIB("norm FA %u > max FA %u)\n",
1013 false_alarms, max_false_alarms);
1014
1015 val = data->auto_corr_ofdm + AUTO_CORR_STEP_OFDM;
1016 data->auto_corr_ofdm =
1017 min((u32)AUTO_CORR_MAX_OFDM, val);
1018
1019 val = data->auto_corr_ofdm_mrc + AUTO_CORR_STEP_OFDM;
1020 data->auto_corr_ofdm_mrc =
1021 min((u32)AUTO_CORR_MAX_OFDM_MRC, val);
1022
1023 val = data->auto_corr_ofdm_x1 + AUTO_CORR_STEP_OFDM;
1024 data->auto_corr_ofdm_x1 =
1025 min((u32)AUTO_CORR_MAX_OFDM_X1, val);
1026
1027 val = data->auto_corr_ofdm_mrc_x1 + AUTO_CORR_STEP_OFDM;
1028 data->auto_corr_ofdm_mrc_x1 =
1029 min((u32)AUTO_CORR_MAX_OFDM_MRC_X1, val);
1030 }
1031
1032 /* Else if we got fewer than desired, increase sensitivity */
1033 else if (false_alarms < min_false_alarms) {
1034
1035 IWL_DEBUG_CALIB("norm FA %u < min FA %u\n",
1036 false_alarms, min_false_alarms);
1037
1038 val = data->auto_corr_ofdm - AUTO_CORR_STEP_OFDM;
1039 data->auto_corr_ofdm =
1040 max((u32)AUTO_CORR_MIN_OFDM, val);
1041
1042 val = data->auto_corr_ofdm_mrc - AUTO_CORR_STEP_OFDM;
1043 data->auto_corr_ofdm_mrc =
1044 max((u32)AUTO_CORR_MIN_OFDM_MRC, val);
1045
1046 val = data->auto_corr_ofdm_x1 - AUTO_CORR_STEP_OFDM;
1047 data->auto_corr_ofdm_x1 =
1048 max((u32)AUTO_CORR_MIN_OFDM_X1, val);
1049
1050 val = data->auto_corr_ofdm_mrc_x1 - AUTO_CORR_STEP_OFDM;
1051 data->auto_corr_ofdm_mrc_x1 =
1052 max((u32)AUTO_CORR_MIN_OFDM_MRC_X1, val);
1053 }
1054
1055 else
1056 IWL_DEBUG_CALIB("min FA %u < norm FA %u < max FA %u OK\n",
1057 min_false_alarms, false_alarms, max_false_alarms);
1058
1059 return 0;
1060}
1061
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001062static int iwl4965_sensitivity_callback(struct iwl4965_priv *priv,
1063 struct iwl4965_cmd *cmd, struct sk_buff *skb)
Zhu Yib481de92007-09-25 17:54:57 -07001064{
1065 /* We didn't cache the SKB; let the caller free it */
1066 return 1;
1067}
1068
1069/* Prepare a SENSITIVITY_CMD, send to uCode if values have changed */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001070static int iwl4965_sensitivity_write(struct iwl4965_priv *priv, u8 flags)
Zhu Yib481de92007-09-25 17:54:57 -07001071{
1072 int rc = 0;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001073 struct iwl4965_sensitivity_cmd cmd ;
1074 struct iwl4965_sensitivity_data *data = NULL;
1075 struct iwl4965_host_cmd cmd_out = {
Zhu Yib481de92007-09-25 17:54:57 -07001076 .id = SENSITIVITY_CMD,
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001077 .len = sizeof(struct iwl4965_sensitivity_cmd),
Zhu Yib481de92007-09-25 17:54:57 -07001078 .meta.flags = flags,
1079 .data = &cmd,
1080 };
1081
1082 data = &(priv->sensitivity_data);
1083
1084 memset(&cmd, 0, sizeof(cmd));
1085
1086 cmd.table[HD_AUTO_CORR32_X4_TH_ADD_MIN_INDEX] =
1087 cpu_to_le16((u16)data->auto_corr_ofdm);
1088 cmd.table[HD_AUTO_CORR32_X4_TH_ADD_MIN_MRC_INDEX] =
1089 cpu_to_le16((u16)data->auto_corr_ofdm_mrc);
1090 cmd.table[HD_AUTO_CORR32_X1_TH_ADD_MIN_INDEX] =
1091 cpu_to_le16((u16)data->auto_corr_ofdm_x1);
1092 cmd.table[HD_AUTO_CORR32_X1_TH_ADD_MIN_MRC_INDEX] =
1093 cpu_to_le16((u16)data->auto_corr_ofdm_mrc_x1);
1094
1095 cmd.table[HD_AUTO_CORR40_X4_TH_ADD_MIN_INDEX] =
1096 cpu_to_le16((u16)data->auto_corr_cck);
1097 cmd.table[HD_AUTO_CORR40_X4_TH_ADD_MIN_MRC_INDEX] =
1098 cpu_to_le16((u16)data->auto_corr_cck_mrc);
1099
1100 cmd.table[HD_MIN_ENERGY_CCK_DET_INDEX] =
1101 cpu_to_le16((u16)data->nrg_th_cck);
1102 cmd.table[HD_MIN_ENERGY_OFDM_DET_INDEX] =
1103 cpu_to_le16((u16)data->nrg_th_ofdm);
1104
1105 cmd.table[HD_BARKER_CORR_TH_ADD_MIN_INDEX] =
1106 __constant_cpu_to_le16(190);
1107 cmd.table[HD_BARKER_CORR_TH_ADD_MIN_MRC_INDEX] =
1108 __constant_cpu_to_le16(390);
1109 cmd.table[HD_OFDM_ENERGY_TH_IN_INDEX] =
1110 __constant_cpu_to_le16(62);
1111
1112 IWL_DEBUG_CALIB("ofdm: ac %u mrc %u x1 %u mrc_x1 %u thresh %u\n",
1113 data->auto_corr_ofdm, data->auto_corr_ofdm_mrc,
1114 data->auto_corr_ofdm_x1, data->auto_corr_ofdm_mrc_x1,
1115 data->nrg_th_ofdm);
1116
1117 IWL_DEBUG_CALIB("cck: ac %u mrc %u thresh %u\n",
1118 data->auto_corr_cck, data->auto_corr_cck_mrc,
1119 data->nrg_th_cck);
1120
Ben Cahillf7d09d72007-11-29 11:09:51 +08001121 /* Update uCode's "work" table, and copy it to DSP */
Zhu Yib481de92007-09-25 17:54:57 -07001122 cmd.control = SENSITIVITY_CMD_CONTROL_WORK_TABLE;
1123
1124 if (flags & CMD_ASYNC)
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001125 cmd_out.meta.u.callback = iwl4965_sensitivity_callback;
Zhu Yib481de92007-09-25 17:54:57 -07001126
1127 /* Don't send command to uCode if nothing has changed */
1128 if (!memcmp(&cmd.table[0], &(priv->sensitivity_tbl[0]),
1129 sizeof(u16)*HD_TABLE_SIZE)) {
1130 IWL_DEBUG_CALIB("No change in SENSITIVITY_CMD\n");
1131 return 0;
1132 }
1133
1134 /* Copy table for comparison next time */
1135 memcpy(&(priv->sensitivity_tbl[0]), &(cmd.table[0]),
1136 sizeof(u16)*HD_TABLE_SIZE);
1137
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001138 rc = iwl4965_send_cmd(priv, &cmd_out);
Zhu Yib481de92007-09-25 17:54:57 -07001139 if (!rc) {
1140 IWL_DEBUG_CALIB("SENSITIVITY_CMD succeeded\n");
1141 return rc;
1142 }
1143
1144 return 0;
1145}
1146
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001147void iwl4965_init_sensitivity(struct iwl4965_priv *priv, u8 flags, u8 force)
Zhu Yib481de92007-09-25 17:54:57 -07001148{
1149 int rc = 0;
1150 int i;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001151 struct iwl4965_sensitivity_data *data = NULL;
Zhu Yib481de92007-09-25 17:54:57 -07001152
1153 IWL_DEBUG_CALIB("Start iwl4965_init_sensitivity\n");
1154
1155 if (force)
1156 memset(&(priv->sensitivity_tbl[0]), 0,
1157 sizeof(u16)*HD_TABLE_SIZE);
1158
1159 /* Clear driver's sensitivity algo data */
1160 data = &(priv->sensitivity_data);
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001161 memset(data, 0, sizeof(struct iwl4965_sensitivity_data));
Zhu Yib481de92007-09-25 17:54:57 -07001162
1163 data->num_in_cck_no_fa = 0;
1164 data->nrg_curr_state = IWL_FA_TOO_MANY;
1165 data->nrg_prev_state = IWL_FA_TOO_MANY;
1166 data->nrg_silence_ref = 0;
1167 data->nrg_silence_idx = 0;
1168 data->nrg_energy_idx = 0;
1169
1170 for (i = 0; i < 10; i++)
1171 data->nrg_value[i] = 0;
1172
1173 for (i = 0; i < NRG_NUM_PREV_STAT_L; i++)
1174 data->nrg_silence_rssi[i] = 0;
1175
1176 data->auto_corr_ofdm = 90;
1177 data->auto_corr_ofdm_mrc = 170;
1178 data->auto_corr_ofdm_x1 = 105;
1179 data->auto_corr_ofdm_mrc_x1 = 220;
1180 data->auto_corr_cck = AUTO_CORR_CCK_MIN_VAL_DEF;
1181 data->auto_corr_cck_mrc = 200;
1182 data->nrg_th_cck = 100;
1183 data->nrg_th_ofdm = 100;
1184
1185 data->last_bad_plcp_cnt_ofdm = 0;
1186 data->last_fa_cnt_ofdm = 0;
1187 data->last_bad_plcp_cnt_cck = 0;
1188 data->last_fa_cnt_cck = 0;
1189
1190 /* Clear prior Sensitivity command data to force send to uCode */
1191 if (force)
1192 memset(&(priv->sensitivity_tbl[0]), 0,
1193 sizeof(u16)*HD_TABLE_SIZE);
1194
1195 rc |= iwl4965_sensitivity_write(priv, flags);
1196 IWL_DEBUG_CALIB("<<return 0x%X\n", rc);
1197
1198 return;
1199}
1200
1201
1202/* Reset differential Rx gains in NIC to prepare for chain noise calibration.
1203 * Called after every association, but this runs only once!
1204 * ... once chain noise is calibrated the first time, it's good forever. */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001205void iwl4965_chain_noise_reset(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -07001206{
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001207 struct iwl4965_chain_noise_data *data = NULL;
Zhu Yib481de92007-09-25 17:54:57 -07001208 int rc = 0;
1209
1210 data = &(priv->chain_noise_data);
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001211 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl4965_is_associated(priv)) {
1212 struct iwl4965_calibration_cmd cmd;
Zhu Yib481de92007-09-25 17:54:57 -07001213
1214 memset(&cmd, 0, sizeof(cmd));
1215 cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
1216 cmd.diff_gain_a = 0;
1217 cmd.diff_gain_b = 0;
1218 cmd.diff_gain_c = 0;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001219 rc = iwl4965_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
Zhu Yib481de92007-09-25 17:54:57 -07001220 sizeof(cmd), &cmd);
1221 msleep(4);
1222 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
1223 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
1224 }
1225 return;
1226}
1227
1228/*
1229 * Accumulate 20 beacons of signal and noise statistics for each of
1230 * 3 receivers/antennas/rx-chains, then figure out:
1231 * 1) Which antennas are connected.
1232 * 2) Differential rx gain settings to balance the 3 receivers.
1233 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001234static void iwl4965_noise_calibration(struct iwl4965_priv *priv,
1235 struct iwl4965_notif_statistics *stat_resp)
Zhu Yib481de92007-09-25 17:54:57 -07001236{
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001237 struct iwl4965_chain_noise_data *data = NULL;
Zhu Yib481de92007-09-25 17:54:57 -07001238 int rc = 0;
1239
1240 u32 chain_noise_a;
1241 u32 chain_noise_b;
1242 u32 chain_noise_c;
1243 u32 chain_sig_a;
1244 u32 chain_sig_b;
1245 u32 chain_sig_c;
1246 u32 average_sig[NUM_RX_CHAINS] = {INITIALIZATION_VALUE};
1247 u32 average_noise[NUM_RX_CHAINS] = {INITIALIZATION_VALUE};
1248 u32 max_average_sig;
1249 u16 max_average_sig_antenna_i;
1250 u32 min_average_noise = MIN_AVERAGE_NOISE_MAX_VALUE;
1251 u16 min_average_noise_antenna_i = INITIALIZATION_VALUE;
1252 u16 i = 0;
1253 u16 chan_num = INITIALIZATION_VALUE;
1254 u32 band = INITIALIZATION_VALUE;
1255 u32 active_chains = 0;
1256 unsigned long flags;
1257 struct statistics_rx_non_phy *rx_info = &(stat_resp->rx.general);
1258
1259 data = &(priv->chain_noise_data);
1260
1261 /* Accumulate just the first 20 beacons after the first association,
1262 * then we're done forever. */
1263 if (data->state != IWL_CHAIN_NOISE_ACCUMULATE) {
1264 if (data->state == IWL_CHAIN_NOISE_ALIVE)
1265 IWL_DEBUG_CALIB("Wait for noise calib reset\n");
1266 return;
1267 }
1268
1269 spin_lock_irqsave(&priv->lock, flags);
1270 if (rx_info->interference_data_flag != INTERFERENCE_DATA_AVAILABLE) {
1271 IWL_DEBUG_CALIB(" << Interference data unavailable\n");
1272 spin_unlock_irqrestore(&priv->lock, flags);
1273 return;
1274 }
1275
1276 band = (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) ? 0 : 1;
1277 chan_num = le16_to_cpu(priv->staging_rxon.channel);
1278
1279 /* Make sure we accumulate data for just the associated channel
1280 * (even if scanning). */
1281 if ((chan_num != (le32_to_cpu(stat_resp->flag) >> 16)) ||
1282 ((STATISTICS_REPLY_FLG_BAND_24G_MSK ==
1283 (stat_resp->flag & STATISTICS_REPLY_FLG_BAND_24G_MSK)) && band)) {
1284 IWL_DEBUG_CALIB("Stats not from chan=%d, band=%d\n",
1285 chan_num, band);
1286 spin_unlock_irqrestore(&priv->lock, flags);
1287 return;
1288 }
1289
1290 /* Accumulate beacon statistics values across 20 beacons */
1291 chain_noise_a = le32_to_cpu(rx_info->beacon_silence_rssi_a) &
1292 IN_BAND_FILTER;
1293 chain_noise_b = le32_to_cpu(rx_info->beacon_silence_rssi_b) &
1294 IN_BAND_FILTER;
1295 chain_noise_c = le32_to_cpu(rx_info->beacon_silence_rssi_c) &
1296 IN_BAND_FILTER;
1297
1298 chain_sig_a = le32_to_cpu(rx_info->beacon_rssi_a) & IN_BAND_FILTER;
1299 chain_sig_b = le32_to_cpu(rx_info->beacon_rssi_b) & IN_BAND_FILTER;
1300 chain_sig_c = le32_to_cpu(rx_info->beacon_rssi_c) & IN_BAND_FILTER;
1301
1302 spin_unlock_irqrestore(&priv->lock, flags);
1303
1304 data->beacon_count++;
1305
1306 data->chain_noise_a = (chain_noise_a + data->chain_noise_a);
1307 data->chain_noise_b = (chain_noise_b + data->chain_noise_b);
1308 data->chain_noise_c = (chain_noise_c + data->chain_noise_c);
1309
1310 data->chain_signal_a = (chain_sig_a + data->chain_signal_a);
1311 data->chain_signal_b = (chain_sig_b + data->chain_signal_b);
1312 data->chain_signal_c = (chain_sig_c + data->chain_signal_c);
1313
1314 IWL_DEBUG_CALIB("chan=%d, band=%d, beacon=%d\n", chan_num, band,
1315 data->beacon_count);
1316 IWL_DEBUG_CALIB("chain_sig: a %d b %d c %d\n",
1317 chain_sig_a, chain_sig_b, chain_sig_c);
1318 IWL_DEBUG_CALIB("chain_noise: a %d b %d c %d\n",
1319 chain_noise_a, chain_noise_b, chain_noise_c);
1320
1321 /* If this is the 20th beacon, determine:
1322 * 1) Disconnected antennas (using signal strengths)
1323 * 2) Differential gain (using silence noise) to balance receivers */
1324 if (data->beacon_count == CAL_NUM_OF_BEACONS) {
1325
1326 /* Analyze signal for disconnected antenna */
1327 average_sig[0] = (data->chain_signal_a) / CAL_NUM_OF_BEACONS;
1328 average_sig[1] = (data->chain_signal_b) / CAL_NUM_OF_BEACONS;
1329 average_sig[2] = (data->chain_signal_c) / CAL_NUM_OF_BEACONS;
1330
1331 if (average_sig[0] >= average_sig[1]) {
1332 max_average_sig = average_sig[0];
1333 max_average_sig_antenna_i = 0;
1334 active_chains = (1 << max_average_sig_antenna_i);
1335 } else {
1336 max_average_sig = average_sig[1];
1337 max_average_sig_antenna_i = 1;
1338 active_chains = (1 << max_average_sig_antenna_i);
1339 }
1340
1341 if (average_sig[2] >= max_average_sig) {
1342 max_average_sig = average_sig[2];
1343 max_average_sig_antenna_i = 2;
1344 active_chains = (1 << max_average_sig_antenna_i);
1345 }
1346
1347 IWL_DEBUG_CALIB("average_sig: a %d b %d c %d\n",
1348 average_sig[0], average_sig[1], average_sig[2]);
1349 IWL_DEBUG_CALIB("max_average_sig = %d, antenna %d\n",
1350 max_average_sig, max_average_sig_antenna_i);
1351
1352 /* Compare signal strengths for all 3 receivers. */
1353 for (i = 0; i < NUM_RX_CHAINS; i++) {
1354 if (i != max_average_sig_antenna_i) {
1355 s32 rssi_delta = (max_average_sig -
1356 average_sig[i]);
1357
1358 /* If signal is very weak, compared with
1359 * strongest, mark it as disconnected. */
1360 if (rssi_delta > MAXIMUM_ALLOWED_PATHLOSS)
1361 data->disconn_array[i] = 1;
1362 else
1363 active_chains |= (1 << i);
1364 IWL_DEBUG_CALIB("i = %d rssiDelta = %d "
1365 "disconn_array[i] = %d\n",
1366 i, rssi_delta, data->disconn_array[i]);
1367 }
1368 }
1369
1370 /*If both chains A & B are disconnected -
1371 * connect B and leave A as is */
1372 if (data->disconn_array[CHAIN_A] &&
1373 data->disconn_array[CHAIN_B]) {
1374 data->disconn_array[CHAIN_B] = 0;
1375 active_chains |= (1 << CHAIN_B);
1376 IWL_DEBUG_CALIB("both A & B chains are disconnected! "
1377 "W/A - declare B as connected\n");
1378 }
1379
1380 IWL_DEBUG_CALIB("active_chains (bitwise) = 0x%x\n",
1381 active_chains);
1382
1383 /* Save for use within RXON, TX, SCAN commands, etc. */
1384 priv->valid_antenna = active_chains;
1385
1386 /* Analyze noise for rx balance */
1387 average_noise[0] = ((data->chain_noise_a)/CAL_NUM_OF_BEACONS);
1388 average_noise[1] = ((data->chain_noise_b)/CAL_NUM_OF_BEACONS);
1389 average_noise[2] = ((data->chain_noise_c)/CAL_NUM_OF_BEACONS);
1390
1391 for (i = 0; i < NUM_RX_CHAINS; i++) {
1392 if (!(data->disconn_array[i]) &&
1393 (average_noise[i] <= min_average_noise)) {
1394 /* This means that chain i is active and has
1395 * lower noise values so far: */
1396 min_average_noise = average_noise[i];
1397 min_average_noise_antenna_i = i;
1398 }
1399 }
1400
1401 data->delta_gain_code[min_average_noise_antenna_i] = 0;
1402
1403 IWL_DEBUG_CALIB("average_noise: a %d b %d c %d\n",
1404 average_noise[0], average_noise[1],
1405 average_noise[2]);
1406
1407 IWL_DEBUG_CALIB("min_average_noise = %d, antenna %d\n",
1408 min_average_noise, min_average_noise_antenna_i);
1409
1410 for (i = 0; i < NUM_RX_CHAINS; i++) {
1411 s32 delta_g = 0;
1412
1413 if (!(data->disconn_array[i]) &&
1414 (data->delta_gain_code[i] ==
1415 CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) {
1416 delta_g = average_noise[i] - min_average_noise;
1417 data->delta_gain_code[i] = (u8)((delta_g *
1418 10) / 15);
1419 if (CHAIN_NOISE_MAX_DELTA_GAIN_CODE <
1420 data->delta_gain_code[i])
1421 data->delta_gain_code[i] =
1422 CHAIN_NOISE_MAX_DELTA_GAIN_CODE;
1423
1424 data->delta_gain_code[i] =
1425 (data->delta_gain_code[i] | (1 << 2));
1426 } else
1427 data->delta_gain_code[i] = 0;
1428 }
1429 IWL_DEBUG_CALIB("delta_gain_codes: a %d b %d c %d\n",
1430 data->delta_gain_code[0],
1431 data->delta_gain_code[1],
1432 data->delta_gain_code[2]);
1433
1434 /* Differential gain gets sent to uCode only once */
1435 if (!data->radio_write) {
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001436 struct iwl4965_calibration_cmd cmd;
Zhu Yib481de92007-09-25 17:54:57 -07001437 data->radio_write = 1;
1438
1439 memset(&cmd, 0, sizeof(cmd));
1440 cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
1441 cmd.diff_gain_a = data->delta_gain_code[0];
1442 cmd.diff_gain_b = data->delta_gain_code[1];
1443 cmd.diff_gain_c = data->delta_gain_code[2];
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001444 rc = iwl4965_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
Zhu Yib481de92007-09-25 17:54:57 -07001445 sizeof(cmd), &cmd);
1446 if (rc)
1447 IWL_DEBUG_CALIB("fail sending cmd "
1448 "REPLY_PHY_CALIBRATION_CMD \n");
1449
1450 /* TODO we might want recalculate
1451 * rx_chain in rxon cmd */
1452
1453 /* Mark so we run this algo only once! */
1454 data->state = IWL_CHAIN_NOISE_CALIBRATED;
1455 }
1456 data->chain_noise_a = 0;
1457 data->chain_noise_b = 0;
1458 data->chain_noise_c = 0;
1459 data->chain_signal_a = 0;
1460 data->chain_signal_b = 0;
1461 data->chain_signal_c = 0;
1462 data->beacon_count = 0;
1463 }
1464 return;
1465}
1466
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001467static void iwl4965_sensitivity_calibration(struct iwl4965_priv *priv,
1468 struct iwl4965_notif_statistics *resp)
Zhu Yib481de92007-09-25 17:54:57 -07001469{
1470 int rc = 0;
1471 u32 rx_enable_time;
1472 u32 fa_cck;
1473 u32 fa_ofdm;
1474 u32 bad_plcp_cck;
1475 u32 bad_plcp_ofdm;
1476 u32 norm_fa_ofdm;
1477 u32 norm_fa_cck;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001478 struct iwl4965_sensitivity_data *data = NULL;
Zhu Yib481de92007-09-25 17:54:57 -07001479 struct statistics_rx_non_phy *rx_info = &(resp->rx.general);
1480 struct statistics_rx *statistics = &(resp->rx);
1481 unsigned long flags;
1482 struct statistics_general_data statis;
1483
1484 data = &(priv->sensitivity_data);
1485
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001486 if (!iwl4965_is_associated(priv)) {
Zhu Yib481de92007-09-25 17:54:57 -07001487 IWL_DEBUG_CALIB("<< - not associated\n");
1488 return;
1489 }
1490
1491 spin_lock_irqsave(&priv->lock, flags);
1492 if (rx_info->interference_data_flag != INTERFERENCE_DATA_AVAILABLE) {
1493 IWL_DEBUG_CALIB("<< invalid data.\n");
1494 spin_unlock_irqrestore(&priv->lock, flags);
1495 return;
1496 }
1497
1498 /* Extract Statistics: */
1499 rx_enable_time = le32_to_cpu(rx_info->channel_load);
1500 fa_cck = le32_to_cpu(statistics->cck.false_alarm_cnt);
1501 fa_ofdm = le32_to_cpu(statistics->ofdm.false_alarm_cnt);
1502 bad_plcp_cck = le32_to_cpu(statistics->cck.plcp_err);
1503 bad_plcp_ofdm = le32_to_cpu(statistics->ofdm.plcp_err);
1504
1505 statis.beacon_silence_rssi_a =
1506 le32_to_cpu(statistics->general.beacon_silence_rssi_a);
1507 statis.beacon_silence_rssi_b =
1508 le32_to_cpu(statistics->general.beacon_silence_rssi_b);
1509 statis.beacon_silence_rssi_c =
1510 le32_to_cpu(statistics->general.beacon_silence_rssi_c);
1511 statis.beacon_energy_a =
1512 le32_to_cpu(statistics->general.beacon_energy_a);
1513 statis.beacon_energy_b =
1514 le32_to_cpu(statistics->general.beacon_energy_b);
1515 statis.beacon_energy_c =
1516 le32_to_cpu(statistics->general.beacon_energy_c);
1517
1518 spin_unlock_irqrestore(&priv->lock, flags);
1519
1520 IWL_DEBUG_CALIB("rx_enable_time = %u usecs\n", rx_enable_time);
1521
1522 if (!rx_enable_time) {
1523 IWL_DEBUG_CALIB("<< RX Enable Time == 0! \n");
1524 return;
1525 }
1526
1527 /* These statistics increase monotonically, and do not reset
1528 * at each beacon. Calculate difference from last value, or just
1529 * use the new statistics value if it has reset or wrapped around. */
1530 if (data->last_bad_plcp_cnt_cck > bad_plcp_cck)
1531 data->last_bad_plcp_cnt_cck = bad_plcp_cck;
1532 else {
1533 bad_plcp_cck -= data->last_bad_plcp_cnt_cck;
1534 data->last_bad_plcp_cnt_cck += bad_plcp_cck;
1535 }
1536
1537 if (data->last_bad_plcp_cnt_ofdm > bad_plcp_ofdm)
1538 data->last_bad_plcp_cnt_ofdm = bad_plcp_ofdm;
1539 else {
1540 bad_plcp_ofdm -= data->last_bad_plcp_cnt_ofdm;
1541 data->last_bad_plcp_cnt_ofdm += bad_plcp_ofdm;
1542 }
1543
1544 if (data->last_fa_cnt_ofdm > fa_ofdm)
1545 data->last_fa_cnt_ofdm = fa_ofdm;
1546 else {
1547 fa_ofdm -= data->last_fa_cnt_ofdm;
1548 data->last_fa_cnt_ofdm += fa_ofdm;
1549 }
1550
1551 if (data->last_fa_cnt_cck > fa_cck)
1552 data->last_fa_cnt_cck = fa_cck;
1553 else {
1554 fa_cck -= data->last_fa_cnt_cck;
1555 data->last_fa_cnt_cck += fa_cck;
1556 }
1557
1558 /* Total aborted signal locks */
1559 norm_fa_ofdm = fa_ofdm + bad_plcp_ofdm;
1560 norm_fa_cck = fa_cck + bad_plcp_cck;
1561
1562 IWL_DEBUG_CALIB("cck: fa %u badp %u ofdm: fa %u badp %u\n", fa_cck,
1563 bad_plcp_cck, fa_ofdm, bad_plcp_ofdm);
1564
1565 iwl4965_sens_auto_corr_ofdm(priv, norm_fa_ofdm, rx_enable_time);
1566 iwl4965_sens_energy_cck(priv, norm_fa_cck, rx_enable_time, &statis);
1567 rc |= iwl4965_sensitivity_write(priv, CMD_ASYNC);
1568
1569 return;
1570}
1571
1572static void iwl4965_bg_sensitivity_work(struct work_struct *work)
1573{
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001574 struct iwl4965_priv *priv = container_of(work, struct iwl4965_priv,
Zhu Yib481de92007-09-25 17:54:57 -07001575 sensitivity_work);
1576
1577 mutex_lock(&priv->mutex);
1578
1579 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
1580 test_bit(STATUS_SCANNING, &priv->status)) {
1581 mutex_unlock(&priv->mutex);
1582 return;
1583 }
1584
1585 if (priv->start_calib) {
1586 iwl4965_noise_calibration(priv, &priv->statistics);
1587
1588 if (priv->sensitivity_data.state ==
1589 IWL_SENS_CALIB_NEED_REINIT) {
1590 iwl4965_init_sensitivity(priv, CMD_ASYNC, 0);
1591 priv->sensitivity_data.state = IWL_SENS_CALIB_ALLOWED;
1592 } else
1593 iwl4965_sensitivity_calibration(priv,
1594 &priv->statistics);
1595 }
1596
1597 mutex_unlock(&priv->mutex);
1598 return;
1599}
Christoph Hellwigc8b0e6e2007-10-25 17:15:51 +08001600#endif /*CONFIG_IWL4965_SENSITIVITY*/
Zhu Yib481de92007-09-25 17:54:57 -07001601
1602static void iwl4965_bg_txpower_work(struct work_struct *work)
1603{
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001604 struct iwl4965_priv *priv = container_of(work, struct iwl4965_priv,
Zhu Yib481de92007-09-25 17:54:57 -07001605 txpower_work);
1606
1607 /* If a scan happened to start before we got here
1608 * then just return; the statistics notification will
1609 * kick off another scheduled work to compensate for
1610 * any temperature delta we missed here. */
1611 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
1612 test_bit(STATUS_SCANNING, &priv->status))
1613 return;
1614
1615 mutex_lock(&priv->mutex);
1616
1617 /* Regardless of if we are assocaited, we must reconfigure the
1618 * TX power since frames can be sent on non-radar channels while
1619 * not associated */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001620 iwl4965_hw_reg_send_txpower(priv);
Zhu Yib481de92007-09-25 17:54:57 -07001621
1622 /* Update last_temperature to keep is_calib_needed from running
1623 * when it isn't needed... */
1624 priv->last_temperature = priv->temperature;
1625
1626 mutex_unlock(&priv->mutex);
1627}
1628
1629/*
1630 * Acquire priv->lock before calling this function !
1631 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001632static void iwl4965_set_wr_ptrs(struct iwl4965_priv *priv, int txq_id, u32 index)
Zhu Yib481de92007-09-25 17:54:57 -07001633{
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001634 iwl4965_write_direct32(priv, HBUS_TARG_WRPTR,
Zhu Yib481de92007-09-25 17:54:57 -07001635 (index & 0xff) | (txq_id << 8));
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001636 iwl4965_write_prph(priv, KDR_SCD_QUEUE_RDPTR(txq_id), index);
Zhu Yib481de92007-09-25 17:54:57 -07001637}
1638
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08001639/**
1640 * iwl4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
1641 * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
1642 * @scd_retry: (1) Indicates queue will be used in aggregation mode
1643 *
1644 * NOTE: Acquire priv->lock before calling this function !
Zhu Yib481de92007-09-25 17:54:57 -07001645 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001646static void iwl4965_tx_queue_set_status(struct iwl4965_priv *priv,
1647 struct iwl4965_tx_queue *txq,
Zhu Yib481de92007-09-25 17:54:57 -07001648 int tx_fifo_id, int scd_retry)
1649{
1650 int txq_id = txq->q.id;
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08001651
1652 /* Find out whether to activate Tx queue */
Zhu Yib481de92007-09-25 17:54:57 -07001653 int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
1654
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08001655 /* Set up and activate */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001656 iwl4965_write_prph(priv, KDR_SCD_QUEUE_STATUS_BITS(txq_id),
Zhu Yib481de92007-09-25 17:54:57 -07001657 (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
1658 (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) |
1659 (scd_retry << SCD_QUEUE_STTS_REG_POS_WSL) |
1660 (scd_retry << SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
1661 SCD_QUEUE_STTS_REG_MSK);
1662
1663 txq->sched_retry = scd_retry;
1664
1665 IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08001666 active ? "Activate" : "Deactivate",
Zhu Yib481de92007-09-25 17:54:57 -07001667 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
1668}
1669
1670static const u16 default_queue_to_tx_fifo[] = {
1671 IWL_TX_FIFO_AC3,
1672 IWL_TX_FIFO_AC2,
1673 IWL_TX_FIFO_AC1,
1674 IWL_TX_FIFO_AC0,
1675 IWL_CMD_FIFO_NUM,
1676 IWL_TX_FIFO_HCCA_1,
1677 IWL_TX_FIFO_HCCA_2
1678};
1679
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001680static inline void iwl4965_txq_ctx_activate(struct iwl4965_priv *priv, int txq_id)
Zhu Yib481de92007-09-25 17:54:57 -07001681{
1682 set_bit(txq_id, &priv->txq_ctx_active_msk);
1683}
1684
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001685static inline void iwl4965_txq_ctx_deactivate(struct iwl4965_priv *priv, int txq_id)
Zhu Yib481de92007-09-25 17:54:57 -07001686{
1687 clear_bit(txq_id, &priv->txq_ctx_active_msk);
1688}
1689
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001690int iwl4965_alive_notify(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -07001691{
1692 u32 a;
1693 int i = 0;
1694 unsigned long flags;
1695 int rc;
1696
1697 spin_lock_irqsave(&priv->lock, flags);
1698
Christoph Hellwigc8b0e6e2007-10-25 17:15:51 +08001699#ifdef CONFIG_IWL4965_SENSITIVITY
Zhu Yib481de92007-09-25 17:54:57 -07001700 memset(&(priv->sensitivity_data), 0,
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001701 sizeof(struct iwl4965_sensitivity_data));
Zhu Yib481de92007-09-25 17:54:57 -07001702 memset(&(priv->chain_noise_data), 0,
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001703 sizeof(struct iwl4965_chain_noise_data));
Zhu Yib481de92007-09-25 17:54:57 -07001704 for (i = 0; i < NUM_RX_CHAINS; i++)
1705 priv->chain_noise_data.delta_gain_code[i] =
1706 CHAIN_NOISE_DELTA_GAIN_INIT_VAL;
Christoph Hellwigc8b0e6e2007-10-25 17:15:51 +08001707#endif /* CONFIG_IWL4965_SENSITIVITY*/
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001708 rc = iwl4965_grab_nic_access(priv);
Zhu Yib481de92007-09-25 17:54:57 -07001709 if (rc) {
1710 spin_unlock_irqrestore(&priv->lock, flags);
1711 return rc;
1712 }
1713
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08001714 /* Clear 4965's internal Tx Scheduler data base */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001715 priv->scd_base_addr = iwl4965_read_prph(priv, KDR_SCD_SRAM_BASE_ADDR);
Zhu Yib481de92007-09-25 17:54:57 -07001716 a = priv->scd_base_addr + SCD_CONTEXT_DATA_OFFSET;
1717 for (; a < priv->scd_base_addr + SCD_TX_STTS_BITMAP_OFFSET; a += 4)
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001718 iwl4965_write_targ_mem(priv, a, 0);
Zhu Yib481de92007-09-25 17:54:57 -07001719 for (; a < priv->scd_base_addr + SCD_TRANSLATE_TBL_OFFSET; a += 4)
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001720 iwl4965_write_targ_mem(priv, a, 0);
Zhu Yib481de92007-09-25 17:54:57 -07001721 for (; a < sizeof(u16) * priv->hw_setting.max_txq_num; a += 4)
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001722 iwl4965_write_targ_mem(priv, a, 0);
Zhu Yib481de92007-09-25 17:54:57 -07001723
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08001724 /* Tel 4965 where to find Tx byte count tables */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001725 iwl4965_write_prph(priv, KDR_SCD_DRAM_BASE_ADDR,
Zhu Yib481de92007-09-25 17:54:57 -07001726 (priv->hw_setting.shared_phys +
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001727 offsetof(struct iwl4965_shared, queues_byte_cnt_tbls)) >> 10);
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08001728
1729 /* Disable chain mode for all queues */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001730 iwl4965_write_prph(priv, KDR_SCD_QUEUECHAIN_SEL, 0);
Zhu Yib481de92007-09-25 17:54:57 -07001731
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08001732 /* Initialize each Tx queue (including the command queue) */
Zhu Yib481de92007-09-25 17:54:57 -07001733 for (i = 0; i < priv->hw_setting.max_txq_num; i++) {
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08001734
1735 /* TFD circular buffer read/write indexes */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001736 iwl4965_write_prph(priv, KDR_SCD_QUEUE_RDPTR(i), 0);
1737 iwl4965_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08001738
1739 /* Max Tx Window size for Scheduler-ACK mode */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001740 iwl4965_write_targ_mem(priv, priv->scd_base_addr +
Zhu Yib481de92007-09-25 17:54:57 -07001741 SCD_CONTEXT_QUEUE_OFFSET(i),
1742 (SCD_WIN_SIZE <<
1743 SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
1744 SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08001745
1746 /* Frame limit */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001747 iwl4965_write_targ_mem(priv, priv->scd_base_addr +
Zhu Yib481de92007-09-25 17:54:57 -07001748 SCD_CONTEXT_QUEUE_OFFSET(i) +
1749 sizeof(u32),
1750 (SCD_FRAME_LIMIT <<
1751 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1752 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
1753
1754 }
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001755 iwl4965_write_prph(priv, KDR_SCD_INTERRUPT_MASK,
Zhu Yib481de92007-09-25 17:54:57 -07001756 (1 << priv->hw_setting.max_txq_num) - 1);
1757
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08001758 /* Activate all Tx DMA/FIFO channels */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001759 iwl4965_write_prph(priv, KDR_SCD_TXFACT,
Zhu Yib481de92007-09-25 17:54:57 -07001760 SCD_TXFACT_REG_TXFIFO_MASK(0, 7));
1761
1762 iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08001763
1764 /* Map each Tx/cmd queue to its corresponding fifo */
Zhu Yib481de92007-09-25 17:54:57 -07001765 for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
1766 int ac = default_queue_to_tx_fifo[i];
1767 iwl4965_txq_ctx_activate(priv, i);
1768 iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
1769 }
1770
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001771 iwl4965_release_nic_access(priv);
Zhu Yib481de92007-09-25 17:54:57 -07001772 spin_unlock_irqrestore(&priv->lock, flags);
1773
1774 return 0;
1775}
1776
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08001777/**
1778 * iwl4965_hw_set_hw_setting
1779 *
1780 * Called when initializing driver
1781 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001782int iwl4965_hw_set_hw_setting(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -07001783{
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08001784 /* Allocate area for Tx byte count tables and Rx queue status */
Zhu Yib481de92007-09-25 17:54:57 -07001785 priv->hw_setting.shared_virt =
1786 pci_alloc_consistent(priv->pci_dev,
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001787 sizeof(struct iwl4965_shared),
Zhu Yib481de92007-09-25 17:54:57 -07001788 &priv->hw_setting.shared_phys);
1789
1790 if (!priv->hw_setting.shared_virt)
1791 return -1;
1792
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001793 memset(priv->hw_setting.shared_virt, 0, sizeof(struct iwl4965_shared));
Zhu Yib481de92007-09-25 17:54:57 -07001794
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001795 priv->hw_setting.max_txq_num = iwl4965_param_queues_num;
Zhu Yib481de92007-09-25 17:54:57 -07001796 priv->hw_setting.ac_queue_count = AC_NUM;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001797 priv->hw_setting.tx_cmd_len = sizeof(struct iwl4965_tx_cmd);
Zhu Yib481de92007-09-25 17:54:57 -07001798 priv->hw_setting.max_rxq_size = RX_QUEUE_SIZE;
1799 priv->hw_setting.max_rxq_log = RX_QUEUE_SIZE_LOG;
Ron Rindjunsky9ee1ba42007-11-26 16:14:42 +02001800 if (iwl4965_param_amsdu_size_8K)
1801 priv->hw_setting.rx_buf_size = IWL_RX_BUF_SIZE_8K;
1802 else
1803 priv->hw_setting.rx_buf_size = IWL_RX_BUF_SIZE_4K;
1804 priv->hw_setting.max_pkt_size = priv->hw_setting.rx_buf_size - 256;
Zhu Yib481de92007-09-25 17:54:57 -07001805 priv->hw_setting.max_stations = IWL4965_STATION_COUNT;
1806 priv->hw_setting.bcast_sta_id = IWL4965_BROADCAST_ID;
1807 return 0;
1808}
1809
1810/**
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001811 * iwl4965_hw_txq_ctx_free - Free TXQ Context
Zhu Yib481de92007-09-25 17:54:57 -07001812 *
1813 * Destroy all TX DMA queues and structures
1814 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001815void iwl4965_hw_txq_ctx_free(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -07001816{
1817 int txq_id;
1818
1819 /* Tx queues */
1820 for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++)
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001821 iwl4965_tx_queue_free(priv, &priv->txq[txq_id]);
Zhu Yib481de92007-09-25 17:54:57 -07001822
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08001823 /* Keep-warm buffer */
Zhu Yib481de92007-09-25 17:54:57 -07001824 iwl4965_kw_free(priv);
1825}
1826
1827/**
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08001828 * iwl4965_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
Zhu Yib481de92007-09-25 17:54:57 -07001829 *
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08001830 * Does NOT advance any TFD circular buffer read/write indexes
1831 * Does NOT free the TFD itself (which is within circular buffer)
Zhu Yib481de92007-09-25 17:54:57 -07001832 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001833int iwl4965_hw_txq_free_tfd(struct iwl4965_priv *priv, struct iwl4965_tx_queue *txq)
Zhu Yib481de92007-09-25 17:54:57 -07001834{
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001835 struct iwl4965_tfd_frame *bd_tmp = (struct iwl4965_tfd_frame *)&txq->bd[0];
1836 struct iwl4965_tfd_frame *bd = &bd_tmp[txq->q.read_ptr];
Zhu Yib481de92007-09-25 17:54:57 -07001837 struct pci_dev *dev = priv->pci_dev;
1838 int i;
1839 int counter = 0;
1840 int index, is_odd;
1841
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08001842 /* Host command buffers stay mapped in memory, nothing to clean */
Zhu Yib481de92007-09-25 17:54:57 -07001843 if (txq->q.id == IWL_CMD_QUEUE_NUM)
Zhu Yib481de92007-09-25 17:54:57 -07001844 return 0;
1845
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08001846 /* Sanity check on number of chunks */
Zhu Yib481de92007-09-25 17:54:57 -07001847 counter = IWL_GET_BITS(*bd, num_tbs);
1848 if (counter > MAX_NUM_OF_TBS) {
1849 IWL_ERROR("Too many chunks: %i\n", counter);
1850 /* @todo issue fatal error, it is quite serious situation */
1851 return 0;
1852 }
1853
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08001854 /* Unmap chunks, if any.
1855 * TFD info for odd chunks is different format than for even chunks. */
Zhu Yib481de92007-09-25 17:54:57 -07001856 for (i = 0; i < counter; i++) {
1857 index = i / 2;
1858 is_odd = i & 0x1;
1859
1860 if (is_odd)
1861 pci_unmap_single(
1862 dev,
1863 IWL_GET_BITS(bd->pa[index], tb2_addr_lo16) |
1864 (IWL_GET_BITS(bd->pa[index],
1865 tb2_addr_hi20) << 16),
1866 IWL_GET_BITS(bd->pa[index], tb2_len),
1867 PCI_DMA_TODEVICE);
1868
1869 else if (i > 0)
1870 pci_unmap_single(dev,
1871 le32_to_cpu(bd->pa[index].tb1_addr),
1872 IWL_GET_BITS(bd->pa[index], tb1_len),
1873 PCI_DMA_TODEVICE);
1874
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08001875 /* Free SKB, if any, for this chunk */
Tomas Winklerfc4b6852007-10-25 17:15:24 +08001876 if (txq->txb[txq->q.read_ptr].skb[i]) {
1877 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[i];
Zhu Yib481de92007-09-25 17:54:57 -07001878
1879 dev_kfree_skb(skb);
Tomas Winklerfc4b6852007-10-25 17:15:24 +08001880 txq->txb[txq->q.read_ptr].skb[i] = NULL;
Zhu Yib481de92007-09-25 17:54:57 -07001881 }
1882 }
1883 return 0;
1884}
1885
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001886int iwl4965_hw_reg_set_txpower(struct iwl4965_priv *priv, s8 power)
Zhu Yib481de92007-09-25 17:54:57 -07001887{
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001888 IWL_ERROR("TODO: Implement iwl4965_hw_reg_set_txpower!\n");
Zhu Yib481de92007-09-25 17:54:57 -07001889 return -EINVAL;
1890}
1891
1892static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res)
1893{
1894 s32 sign = 1;
1895
1896 if (num < 0) {
1897 sign = -sign;
1898 num = -num;
1899 }
1900 if (denom < 0) {
1901 sign = -sign;
1902 denom = -denom;
1903 }
1904 *res = 1;
1905 *res = ((num * 2 + denom) / (denom * 2)) * sign;
1906
1907 return 1;
1908}
1909
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08001910/**
1911 * iwl4965_get_voltage_compensation - Power supply voltage comp for txpower
1912 *
1913 * Determines power supply voltage compensation for txpower calculations.
1914 * Returns number of 1/2-dB steps to subtract from gain table index,
1915 * to compensate for difference between power supply voltage during
1916 * factory measurements, vs. current power supply voltage.
1917 *
1918 * Voltage indication is higher for lower voltage.
1919 * Lower voltage requires more gain (lower gain table index).
1920 */
Zhu Yib481de92007-09-25 17:54:57 -07001921static s32 iwl4965_get_voltage_compensation(s32 eeprom_voltage,
1922 s32 current_voltage)
1923{
1924 s32 comp = 0;
1925
1926 if ((TX_POWER_IWL_ILLEGAL_VOLTAGE == eeprom_voltage) ||
1927 (TX_POWER_IWL_ILLEGAL_VOLTAGE == current_voltage))
1928 return 0;
1929
1930 iwl4965_math_div_round(current_voltage - eeprom_voltage,
1931 TX_POWER_IWL_VOLTAGE_CODES_PER_03V, &comp);
1932
1933 if (current_voltage > eeprom_voltage)
1934 comp *= 2;
1935 if ((comp < -2) || (comp > 2))
1936 comp = 0;
1937
1938 return comp;
1939}
1940
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001941static const struct iwl4965_channel_info *
1942iwl4965_get_channel_txpower_info(struct iwl4965_priv *priv, u8 phymode, u16 channel)
Zhu Yib481de92007-09-25 17:54:57 -07001943{
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001944 const struct iwl4965_channel_info *ch_info;
Zhu Yib481de92007-09-25 17:54:57 -07001945
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001946 ch_info = iwl4965_get_channel_info(priv, phymode, channel);
Zhu Yib481de92007-09-25 17:54:57 -07001947
1948 if (!is_channel_valid(ch_info))
1949 return NULL;
1950
1951 return ch_info;
1952}
1953
1954static s32 iwl4965_get_tx_atten_grp(u16 channel)
1955{
1956 if (channel >= CALIB_IWL_TX_ATTEN_GR5_FCH &&
1957 channel <= CALIB_IWL_TX_ATTEN_GR5_LCH)
1958 return CALIB_CH_GROUP_5;
1959
1960 if (channel >= CALIB_IWL_TX_ATTEN_GR1_FCH &&
1961 channel <= CALIB_IWL_TX_ATTEN_GR1_LCH)
1962 return CALIB_CH_GROUP_1;
1963
1964 if (channel >= CALIB_IWL_TX_ATTEN_GR2_FCH &&
1965 channel <= CALIB_IWL_TX_ATTEN_GR2_LCH)
1966 return CALIB_CH_GROUP_2;
1967
1968 if (channel >= CALIB_IWL_TX_ATTEN_GR3_FCH &&
1969 channel <= CALIB_IWL_TX_ATTEN_GR3_LCH)
1970 return CALIB_CH_GROUP_3;
1971
1972 if (channel >= CALIB_IWL_TX_ATTEN_GR4_FCH &&
1973 channel <= CALIB_IWL_TX_ATTEN_GR4_LCH)
1974 return CALIB_CH_GROUP_4;
1975
1976 IWL_ERROR("Can't find txatten group for channel %d.\n", channel);
1977 return -1;
1978}
1979
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001980static u32 iwl4965_get_sub_band(const struct iwl4965_priv *priv, u32 channel)
Zhu Yib481de92007-09-25 17:54:57 -07001981{
1982 s32 b = -1;
1983
1984 for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) {
1985 if (priv->eeprom.calib_info.band_info[b].ch_from == 0)
1986 continue;
1987
1988 if ((channel >= priv->eeprom.calib_info.band_info[b].ch_from)
1989 && (channel <= priv->eeprom.calib_info.band_info[b].ch_to))
1990 break;
1991 }
1992
1993 return b;
1994}
1995
1996static s32 iwl4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
1997{
1998 s32 val;
1999
2000 if (x2 == x1)
2001 return y1;
2002 else {
2003 iwl4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val);
2004 return val + y2;
2005 }
2006}
2007
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08002008/**
2009 * iwl4965_interpolate_chan - Interpolate factory measurements for one channel
2010 *
2011 * Interpolates factory measurements from the two sample channels within a
2012 * sub-band, to apply to channel of interest. Interpolation is proportional to
2013 * differences in channel frequencies, which is proportional to differences
2014 * in channel number.
2015 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002016static int iwl4965_interpolate_chan(struct iwl4965_priv *priv, u32 channel,
2017 struct iwl4965_eeprom_calib_ch_info *chan_info)
Zhu Yib481de92007-09-25 17:54:57 -07002018{
2019 s32 s = -1;
2020 u32 c;
2021 u32 m;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002022 const struct iwl4965_eeprom_calib_measure *m1;
2023 const struct iwl4965_eeprom_calib_measure *m2;
2024 struct iwl4965_eeprom_calib_measure *omeas;
Zhu Yib481de92007-09-25 17:54:57 -07002025 u32 ch_i1;
2026 u32 ch_i2;
2027
2028 s = iwl4965_get_sub_band(priv, channel);
2029 if (s >= EEPROM_TX_POWER_BANDS) {
2030 IWL_ERROR("Tx Power can not find channel %d ", channel);
2031 return -1;
2032 }
2033
2034 ch_i1 = priv->eeprom.calib_info.band_info[s].ch1.ch_num;
2035 ch_i2 = priv->eeprom.calib_info.band_info[s].ch2.ch_num;
2036 chan_info->ch_num = (u8) channel;
2037
2038 IWL_DEBUG_TXPOWER("channel %d subband %d factory cal ch %d & %d\n",
2039 channel, s, ch_i1, ch_i2);
2040
2041 for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) {
2042 for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) {
2043 m1 = &(priv->eeprom.calib_info.band_info[s].ch1.
2044 measurements[c][m]);
2045 m2 = &(priv->eeprom.calib_info.band_info[s].ch2.
2046 measurements[c][m]);
2047 omeas = &(chan_info->measurements[c][m]);
2048
2049 omeas->actual_pow =
2050 (u8) iwl4965_interpolate_value(channel, ch_i1,
2051 m1->actual_pow,
2052 ch_i2,
2053 m2->actual_pow);
2054 omeas->gain_idx =
2055 (u8) iwl4965_interpolate_value(channel, ch_i1,
2056 m1->gain_idx, ch_i2,
2057 m2->gain_idx);
2058 omeas->temperature =
2059 (u8) iwl4965_interpolate_value(channel, ch_i1,
2060 m1->temperature,
2061 ch_i2,
2062 m2->temperature);
2063 omeas->pa_det =
2064 (s8) iwl4965_interpolate_value(channel, ch_i1,
2065 m1->pa_det, ch_i2,
2066 m2->pa_det);
2067
2068 IWL_DEBUG_TXPOWER
2069 ("chain %d meas %d AP1=%d AP2=%d AP=%d\n", c, m,
2070 m1->actual_pow, m2->actual_pow, omeas->actual_pow);
2071 IWL_DEBUG_TXPOWER
2072 ("chain %d meas %d NI1=%d NI2=%d NI=%d\n", c, m,
2073 m1->gain_idx, m2->gain_idx, omeas->gain_idx);
2074 IWL_DEBUG_TXPOWER
2075 ("chain %d meas %d PA1=%d PA2=%d PA=%d\n", c, m,
2076 m1->pa_det, m2->pa_det, omeas->pa_det);
2077 IWL_DEBUG_TXPOWER
2078 ("chain %d meas %d T1=%d T2=%d T=%d\n", c, m,
2079 m1->temperature, m2->temperature,
2080 omeas->temperature);
2081 }
2082 }
2083
2084 return 0;
2085}
2086
2087/* bit-rate-dependent table to prevent Tx distortion, in half-dB units,
2088 * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates. */
2089static s32 back_off_table[] = {
2090 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */
2091 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */
2092 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */
2093 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */
2094 10 /* CCK */
2095};
2096
2097/* Thermal compensation values for txpower for various frequency ranges ...
2098 * ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002099static struct iwl4965_txpower_comp_entry {
Zhu Yib481de92007-09-25 17:54:57 -07002100 s32 degrees_per_05db_a;
2101 s32 degrees_per_05db_a_denom;
2102} tx_power_cmp_tble[CALIB_CH_GROUP_MAX] = {
2103 {9, 2}, /* group 0 5.2, ch 34-43 */
2104 {4, 1}, /* group 1 5.2, ch 44-70 */
2105 {4, 1}, /* group 2 5.2, ch 71-124 */
2106 {4, 1}, /* group 3 5.2, ch 125-200 */
2107 {3, 1} /* group 4 2.4, ch all */
2108};
2109
2110static s32 get_min_power_index(s32 rate_power_index, u32 band)
2111{
2112 if (!band) {
2113 if ((rate_power_index & 7) <= 4)
2114 return MIN_TX_GAIN_INDEX_52GHZ_EXT;
2115 }
2116 return MIN_TX_GAIN_INDEX;
2117}
2118
2119struct gain_entry {
2120 u8 dsp;
2121 u8 radio;
2122};
2123
2124static const struct gain_entry gain_table[2][108] = {
2125 /* 5.2GHz power gain index table */
2126 {
2127 {123, 0x3F}, /* highest txpower */
2128 {117, 0x3F},
2129 {110, 0x3F},
2130 {104, 0x3F},
2131 {98, 0x3F},
2132 {110, 0x3E},
2133 {104, 0x3E},
2134 {98, 0x3E},
2135 {110, 0x3D},
2136 {104, 0x3D},
2137 {98, 0x3D},
2138 {110, 0x3C},
2139 {104, 0x3C},
2140 {98, 0x3C},
2141 {110, 0x3B},
2142 {104, 0x3B},
2143 {98, 0x3B},
2144 {110, 0x3A},
2145 {104, 0x3A},
2146 {98, 0x3A},
2147 {110, 0x39},
2148 {104, 0x39},
2149 {98, 0x39},
2150 {110, 0x38},
2151 {104, 0x38},
2152 {98, 0x38},
2153 {110, 0x37},
2154 {104, 0x37},
2155 {98, 0x37},
2156 {110, 0x36},
2157 {104, 0x36},
2158 {98, 0x36},
2159 {110, 0x35},
2160 {104, 0x35},
2161 {98, 0x35},
2162 {110, 0x34},
2163 {104, 0x34},
2164 {98, 0x34},
2165 {110, 0x33},
2166 {104, 0x33},
2167 {98, 0x33},
2168 {110, 0x32},
2169 {104, 0x32},
2170 {98, 0x32},
2171 {110, 0x31},
2172 {104, 0x31},
2173 {98, 0x31},
2174 {110, 0x30},
2175 {104, 0x30},
2176 {98, 0x30},
2177 {110, 0x25},
2178 {104, 0x25},
2179 {98, 0x25},
2180 {110, 0x24},
2181 {104, 0x24},
2182 {98, 0x24},
2183 {110, 0x23},
2184 {104, 0x23},
2185 {98, 0x23},
2186 {110, 0x22},
2187 {104, 0x18},
2188 {98, 0x18},
2189 {110, 0x17},
2190 {104, 0x17},
2191 {98, 0x17},
2192 {110, 0x16},
2193 {104, 0x16},
2194 {98, 0x16},
2195 {110, 0x15},
2196 {104, 0x15},
2197 {98, 0x15},
2198 {110, 0x14},
2199 {104, 0x14},
2200 {98, 0x14},
2201 {110, 0x13},
2202 {104, 0x13},
2203 {98, 0x13},
2204 {110, 0x12},
2205 {104, 0x08},
2206 {98, 0x08},
2207 {110, 0x07},
2208 {104, 0x07},
2209 {98, 0x07},
2210 {110, 0x06},
2211 {104, 0x06},
2212 {98, 0x06},
2213 {110, 0x05},
2214 {104, 0x05},
2215 {98, 0x05},
2216 {110, 0x04},
2217 {104, 0x04},
2218 {98, 0x04},
2219 {110, 0x03},
2220 {104, 0x03},
2221 {98, 0x03},
2222 {110, 0x02},
2223 {104, 0x02},
2224 {98, 0x02},
2225 {110, 0x01},
2226 {104, 0x01},
2227 {98, 0x01},
2228 {110, 0x00},
2229 {104, 0x00},
2230 {98, 0x00},
2231 {93, 0x00},
2232 {88, 0x00},
2233 {83, 0x00},
2234 {78, 0x00},
2235 },
2236 /* 2.4GHz power gain index table */
2237 {
2238 {110, 0x3f}, /* highest txpower */
2239 {104, 0x3f},
2240 {98, 0x3f},
2241 {110, 0x3e},
2242 {104, 0x3e},
2243 {98, 0x3e},
2244 {110, 0x3d},
2245 {104, 0x3d},
2246 {98, 0x3d},
2247 {110, 0x3c},
2248 {104, 0x3c},
2249 {98, 0x3c},
2250 {110, 0x3b},
2251 {104, 0x3b},
2252 {98, 0x3b},
2253 {110, 0x3a},
2254 {104, 0x3a},
2255 {98, 0x3a},
2256 {110, 0x39},
2257 {104, 0x39},
2258 {98, 0x39},
2259 {110, 0x38},
2260 {104, 0x38},
2261 {98, 0x38},
2262 {110, 0x37},
2263 {104, 0x37},
2264 {98, 0x37},
2265 {110, 0x36},
2266 {104, 0x36},
2267 {98, 0x36},
2268 {110, 0x35},
2269 {104, 0x35},
2270 {98, 0x35},
2271 {110, 0x34},
2272 {104, 0x34},
2273 {98, 0x34},
2274 {110, 0x33},
2275 {104, 0x33},
2276 {98, 0x33},
2277 {110, 0x32},
2278 {104, 0x32},
2279 {98, 0x32},
2280 {110, 0x31},
2281 {104, 0x31},
2282 {98, 0x31},
2283 {110, 0x30},
2284 {104, 0x30},
2285 {98, 0x30},
2286 {110, 0x6},
2287 {104, 0x6},
2288 {98, 0x6},
2289 {110, 0x5},
2290 {104, 0x5},
2291 {98, 0x5},
2292 {110, 0x4},
2293 {104, 0x4},
2294 {98, 0x4},
2295 {110, 0x3},
2296 {104, 0x3},
2297 {98, 0x3},
2298 {110, 0x2},
2299 {104, 0x2},
2300 {98, 0x2},
2301 {110, 0x1},
2302 {104, 0x1},
2303 {98, 0x1},
2304 {110, 0x0},
2305 {104, 0x0},
2306 {98, 0x0},
2307 {97, 0},
2308 {96, 0},
2309 {95, 0},
2310 {94, 0},
2311 {93, 0},
2312 {92, 0},
2313 {91, 0},
2314 {90, 0},
2315 {89, 0},
2316 {88, 0},
2317 {87, 0},
2318 {86, 0},
2319 {85, 0},
2320 {84, 0},
2321 {83, 0},
2322 {82, 0},
2323 {81, 0},
2324 {80, 0},
2325 {79, 0},
2326 {78, 0},
2327 {77, 0},
2328 {76, 0},
2329 {75, 0},
2330 {74, 0},
2331 {73, 0},
2332 {72, 0},
2333 {71, 0},
2334 {70, 0},
2335 {69, 0},
2336 {68, 0},
2337 {67, 0},
2338 {66, 0},
2339 {65, 0},
2340 {64, 0},
2341 {63, 0},
2342 {62, 0},
2343 {61, 0},
2344 {60, 0},
2345 {59, 0},
2346 }
2347};
2348
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002349static int iwl4965_fill_txpower_tbl(struct iwl4965_priv *priv, u8 band, u16 channel,
Zhu Yib481de92007-09-25 17:54:57 -07002350 u8 is_fat, u8 ctrl_chan_high,
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002351 struct iwl4965_tx_power_db *tx_power_tbl)
Zhu Yib481de92007-09-25 17:54:57 -07002352{
2353 u8 saturation_power;
2354 s32 target_power;
2355 s32 user_target_power;
2356 s32 power_limit;
2357 s32 current_temp;
2358 s32 reg_limit;
2359 s32 current_regulatory;
2360 s32 txatten_grp = CALIB_CH_GROUP_MAX;
2361 int i;
2362 int c;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002363 const struct iwl4965_channel_info *ch_info = NULL;
2364 struct iwl4965_eeprom_calib_ch_info ch_eeprom_info;
2365 const struct iwl4965_eeprom_calib_measure *measurement;
Zhu Yib481de92007-09-25 17:54:57 -07002366 s16 voltage;
2367 s32 init_voltage;
2368 s32 voltage_compensation;
2369 s32 degrees_per_05db_num;
2370 s32 degrees_per_05db_denom;
2371 s32 factory_temp;
2372 s32 temperature_comp[2];
2373 s32 factory_gain_index[2];
2374 s32 factory_actual_pwr[2];
2375 s32 power_index;
2376
2377 /* Sanity check requested level (dBm) */
2378 if (priv->user_txpower_limit < IWL_TX_POWER_TARGET_POWER_MIN) {
2379 IWL_WARNING("Requested user TXPOWER %d below limit.\n",
2380 priv->user_txpower_limit);
2381 return -EINVAL;
2382 }
2383 if (priv->user_txpower_limit > IWL_TX_POWER_TARGET_POWER_MAX) {
2384 IWL_WARNING("Requested user TXPOWER %d above limit.\n",
2385 priv->user_txpower_limit);
2386 return -EINVAL;
2387 }
2388
2389 /* user_txpower_limit is in dBm, convert to half-dBm (half-dB units
2390 * are used for indexing into txpower table) */
2391 user_target_power = 2 * priv->user_txpower_limit;
2392
2393 /* Get current (RXON) channel, band, width */
2394 ch_info =
2395 iwl4965_get_channel_txpower_info(priv, priv->phymode, channel);
2396
2397 IWL_DEBUG_TXPOWER("chan %d band %d is_fat %d\n", channel, band,
2398 is_fat);
2399
2400 if (!ch_info)
2401 return -EINVAL;
2402
2403 /* get txatten group, used to select 1) thermal txpower adjustment
2404 * and 2) mimo txpower balance between Tx chains. */
2405 txatten_grp = iwl4965_get_tx_atten_grp(channel);
2406 if (txatten_grp < 0)
2407 return -EINVAL;
2408
2409 IWL_DEBUG_TXPOWER("channel %d belongs to txatten group %d\n",
2410 channel, txatten_grp);
2411
2412 if (is_fat) {
2413 if (ctrl_chan_high)
2414 channel -= 2;
2415 else
2416 channel += 2;
2417 }
2418
2419 /* hardware txpower limits ...
2420 * saturation (clipping distortion) txpowers are in half-dBm */
2421 if (band)
2422 saturation_power = priv->eeprom.calib_info.saturation_power24;
2423 else
2424 saturation_power = priv->eeprom.calib_info.saturation_power52;
2425
2426 if (saturation_power < IWL_TX_POWER_SATURATION_MIN ||
2427 saturation_power > IWL_TX_POWER_SATURATION_MAX) {
2428 if (band)
2429 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_24;
2430 else
2431 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_52;
2432 }
2433
2434 /* regulatory txpower limits ... reg_limit values are in half-dBm,
2435 * max_power_avg values are in dBm, convert * 2 */
2436 if (is_fat)
2437 reg_limit = ch_info->fat_max_power_avg * 2;
2438 else
2439 reg_limit = ch_info->max_power_avg * 2;
2440
2441 if ((reg_limit < IWL_TX_POWER_REGULATORY_MIN) ||
2442 (reg_limit > IWL_TX_POWER_REGULATORY_MAX)) {
2443 if (band)
2444 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_24;
2445 else
2446 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_52;
2447 }
2448
2449 /* Interpolate txpower calibration values for this channel,
2450 * based on factory calibration tests on spaced channels. */
2451 iwl4965_interpolate_chan(priv, channel, &ch_eeprom_info);
2452
2453 /* calculate tx gain adjustment based on power supply voltage */
2454 voltage = priv->eeprom.calib_info.voltage;
2455 init_voltage = (s32)le32_to_cpu(priv->card_alive_init.voltage);
2456 voltage_compensation =
2457 iwl4965_get_voltage_compensation(voltage, init_voltage);
2458
2459 IWL_DEBUG_TXPOWER("curr volt %d eeprom volt %d volt comp %d\n",
2460 init_voltage,
2461 voltage, voltage_compensation);
2462
2463 /* get current temperature (Celsius) */
2464 current_temp = max(priv->temperature, IWL_TX_POWER_TEMPERATURE_MIN);
2465 current_temp = min(priv->temperature, IWL_TX_POWER_TEMPERATURE_MAX);
2466 current_temp = KELVIN_TO_CELSIUS(current_temp);
2467
2468 /* select thermal txpower adjustment params, based on channel group
2469 * (same frequency group used for mimo txatten adjustment) */
2470 degrees_per_05db_num =
2471 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a;
2472 degrees_per_05db_denom =
2473 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a_denom;
2474
2475 /* get per-chain txpower values from factory measurements */
2476 for (c = 0; c < 2; c++) {
2477 measurement = &ch_eeprom_info.measurements[c][1];
2478
2479 /* txgain adjustment (in half-dB steps) based on difference
2480 * between factory and current temperature */
2481 factory_temp = measurement->temperature;
2482 iwl4965_math_div_round((current_temp - factory_temp) *
2483 degrees_per_05db_denom,
2484 degrees_per_05db_num,
2485 &temperature_comp[c]);
2486
2487 factory_gain_index[c] = measurement->gain_idx;
2488 factory_actual_pwr[c] = measurement->actual_pow;
2489
2490 IWL_DEBUG_TXPOWER("chain = %d\n", c);
2491 IWL_DEBUG_TXPOWER("fctry tmp %d, "
2492 "curr tmp %d, comp %d steps\n",
2493 factory_temp, current_temp,
2494 temperature_comp[c]);
2495
2496 IWL_DEBUG_TXPOWER("fctry idx %d, fctry pwr %d\n",
2497 factory_gain_index[c],
2498 factory_actual_pwr[c]);
2499 }
2500
2501 /* for each of 33 bit-rates (including 1 for CCK) */
2502 for (i = 0; i < POWER_TABLE_NUM_ENTRIES; i++) {
2503 u8 is_mimo_rate;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002504 union iwl4965_tx_power_dual_stream tx_power;
Zhu Yib481de92007-09-25 17:54:57 -07002505
2506 /* for mimo, reduce each chain's txpower by half
2507 * (3dB, 6 steps), so total output power is regulatory
2508 * compliant. */
2509 if (i & 0x8) {
2510 current_regulatory = reg_limit -
2511 IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION;
2512 is_mimo_rate = 1;
2513 } else {
2514 current_regulatory = reg_limit;
2515 is_mimo_rate = 0;
2516 }
2517
2518 /* find txpower limit, either hardware or regulatory */
2519 power_limit = saturation_power - back_off_table[i];
2520 if (power_limit > current_regulatory)
2521 power_limit = current_regulatory;
2522
2523 /* reduce user's txpower request if necessary
2524 * for this rate on this channel */
2525 target_power = user_target_power;
2526 if (target_power > power_limit)
2527 target_power = power_limit;
2528
2529 IWL_DEBUG_TXPOWER("rate %d sat %d reg %d usr %d tgt %d\n",
2530 i, saturation_power - back_off_table[i],
2531 current_regulatory, user_target_power,
2532 target_power);
2533
2534 /* for each of 2 Tx chains (radio transmitters) */
2535 for (c = 0; c < 2; c++) {
2536 s32 atten_value;
2537
2538 if (is_mimo_rate)
2539 atten_value =
2540 (s32)le32_to_cpu(priv->card_alive_init.
2541 tx_atten[txatten_grp][c]);
2542 else
2543 atten_value = 0;
2544
2545 /* calculate index; higher index means lower txpower */
2546 power_index = (u8) (factory_gain_index[c] -
2547 (target_power -
2548 factory_actual_pwr[c]) -
2549 temperature_comp[c] -
2550 voltage_compensation +
2551 atten_value);
2552
2553/* IWL_DEBUG_TXPOWER("calculated txpower index %d\n",
2554 power_index); */
2555
2556 if (power_index < get_min_power_index(i, band))
2557 power_index = get_min_power_index(i, band);
2558
2559 /* adjust 5 GHz index to support negative indexes */
2560 if (!band)
2561 power_index += 9;
2562
2563 /* CCK, rate 32, reduce txpower for CCK */
2564 if (i == POWER_TABLE_CCK_ENTRY)
2565 power_index +=
2566 IWL_TX_POWER_CCK_COMPENSATION_C_STEP;
2567
2568 /* stay within the table! */
2569 if (power_index > 107) {
2570 IWL_WARNING("txpower index %d > 107\n",
2571 power_index);
2572 power_index = 107;
2573 }
2574 if (power_index < 0) {
2575 IWL_WARNING("txpower index %d < 0\n",
2576 power_index);
2577 power_index = 0;
2578 }
2579
2580 /* fill txpower command for this rate/chain */
2581 tx_power.s.radio_tx_gain[c] =
2582 gain_table[band][power_index].radio;
2583 tx_power.s.dsp_predis_atten[c] =
2584 gain_table[band][power_index].dsp;
2585
2586 IWL_DEBUG_TXPOWER("chain %d mimo %d index %d "
2587 "gain 0x%02x dsp %d\n",
2588 c, atten_value, power_index,
2589 tx_power.s.radio_tx_gain[c],
2590 tx_power.s.dsp_predis_atten[c]);
2591 }/* for each chain */
2592
2593 tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw);
2594
2595 }/* for each rate */
2596
2597 return 0;
2598}
2599
2600/**
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002601 * iwl4965_hw_reg_send_txpower - Configure the TXPOWER level user limit
Zhu Yib481de92007-09-25 17:54:57 -07002602 *
2603 * Uses the active RXON for channel, band, and characteristics (fat, high)
2604 * The power limit is taken from priv->user_txpower_limit.
2605 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002606int iwl4965_hw_reg_send_txpower(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -07002607{
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002608 struct iwl4965_txpowertable_cmd cmd = { 0 };
Zhu Yib481de92007-09-25 17:54:57 -07002609 int rc = 0;
2610 u8 band = 0;
2611 u8 is_fat = 0;
2612 u8 ctrl_chan_high = 0;
2613
2614 if (test_bit(STATUS_SCANNING, &priv->status)) {
2615 /* If this gets hit a lot, switch it to a BUG() and catch
2616 * the stack trace to find out who is calling this during
2617 * a scan. */
2618 IWL_WARNING("TX Power requested while scanning!\n");
2619 return -EAGAIN;
2620 }
2621
2622 band = ((priv->phymode == MODE_IEEE80211B) ||
2623 (priv->phymode == MODE_IEEE80211G));
2624
2625 is_fat = is_fat_channel(priv->active_rxon.flags);
2626
2627 if (is_fat &&
2628 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
2629 ctrl_chan_high = 1;
2630
2631 cmd.band = band;
2632 cmd.channel = priv->active_rxon.channel;
2633
2634 rc = iwl4965_fill_txpower_tbl(priv, band,
2635 le16_to_cpu(priv->active_rxon.channel),
2636 is_fat, ctrl_chan_high, &cmd.tx_power);
2637 if (rc)
2638 return rc;
2639
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002640 rc = iwl4965_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, sizeof(cmd), &cmd);
Zhu Yib481de92007-09-25 17:54:57 -07002641 return rc;
2642}
2643
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002644int iwl4965_hw_channel_switch(struct iwl4965_priv *priv, u16 channel)
Zhu Yib481de92007-09-25 17:54:57 -07002645{
2646 int rc;
2647 u8 band = 0;
2648 u8 is_fat = 0;
2649 u8 ctrl_chan_high = 0;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002650 struct iwl4965_channel_switch_cmd cmd = { 0 };
2651 const struct iwl4965_channel_info *ch_info;
Zhu Yib481de92007-09-25 17:54:57 -07002652
2653 band = ((priv->phymode == MODE_IEEE80211B) ||
2654 (priv->phymode == MODE_IEEE80211G));
2655
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002656 ch_info = iwl4965_get_channel_info(priv, priv->phymode, channel);
Zhu Yib481de92007-09-25 17:54:57 -07002657
2658 is_fat = is_fat_channel(priv->staging_rxon.flags);
2659
2660 if (is_fat &&
2661 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
2662 ctrl_chan_high = 1;
2663
2664 cmd.band = band;
2665 cmd.expect_beacon = 0;
2666 cmd.channel = cpu_to_le16(channel);
2667 cmd.rxon_flags = priv->active_rxon.flags;
2668 cmd.rxon_filter_flags = priv->active_rxon.filter_flags;
2669 cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
2670 if (ch_info)
2671 cmd.expect_beacon = is_channel_radar(ch_info);
2672 else
2673 cmd.expect_beacon = 1;
2674
2675 rc = iwl4965_fill_txpower_tbl(priv, band, channel, is_fat,
2676 ctrl_chan_high, &cmd.tx_power);
2677 if (rc) {
2678 IWL_DEBUG_11H("error:%d fill txpower_tbl\n", rc);
2679 return rc;
2680 }
2681
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002682 rc = iwl4965_send_cmd_pdu(priv, REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd);
Zhu Yib481de92007-09-25 17:54:57 -07002683 return rc;
2684}
2685
2686#define RTS_HCCA_RETRY_LIMIT 3
2687#define RTS_DFAULT_RETRY_LIMIT 60
2688
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002689void iwl4965_hw_build_tx_cmd_rate(struct iwl4965_priv *priv,
2690 struct iwl4965_cmd *cmd,
Zhu Yib481de92007-09-25 17:54:57 -07002691 struct ieee80211_tx_control *ctrl,
2692 struct ieee80211_hdr *hdr, int sta_id,
2693 int is_hcca)
2694{
Tomas Winkler87e4f7d2008-01-14 17:46:16 -08002695 struct iwl4965_tx_cmd *tx = &cmd->cmd.tx;
Zhu Yib481de92007-09-25 17:54:57 -07002696 u8 rts_retry_limit = 0;
2697 u8 data_retry_limit = 0;
Zhu Yib481de92007-09-25 17:54:57 -07002698 u16 fc = le16_to_cpu(hdr->frame_control);
Tomas Winkler87e4f7d2008-01-14 17:46:16 -08002699 u8 rate_plcp;
2700 u16 rate_flags = 0;
2701 int rate_idx = min(ctrl->tx_rate & 0xffff, IWL_RATE_COUNT - 1);
Zhu Yib481de92007-09-25 17:54:57 -07002702
Tomas Winkler87e4f7d2008-01-14 17:46:16 -08002703 rate_plcp = iwl4965_rates[rate_idx].plcp;
Zhu Yib481de92007-09-25 17:54:57 -07002704
2705 rts_retry_limit = (is_hcca) ?
2706 RTS_HCCA_RETRY_LIMIT : RTS_DFAULT_RETRY_LIMIT;
2707
Tomas Winkler87e4f7d2008-01-14 17:46:16 -08002708 if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
2709 rate_flags |= RATE_MCS_CCK_MSK;
2710
2711
Zhu Yib481de92007-09-25 17:54:57 -07002712 if (ieee80211_is_probe_response(fc)) {
2713 data_retry_limit = 3;
2714 if (data_retry_limit < rts_retry_limit)
2715 rts_retry_limit = data_retry_limit;
2716 } else
2717 data_retry_limit = IWL_DEFAULT_TX_RETRY;
2718
2719 if (priv->data_retry_limit != -1)
2720 data_retry_limit = priv->data_retry_limit;
2721
Tomas Winkler87e4f7d2008-01-14 17:46:16 -08002722
2723 if (ieee80211_is_data(fc)) {
2724 tx->initial_rate_index = 0;
2725 tx->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
2726 } else {
Zhu Yib481de92007-09-25 17:54:57 -07002727 switch (fc & IEEE80211_FCTL_STYPE) {
2728 case IEEE80211_STYPE_AUTH:
2729 case IEEE80211_STYPE_DEAUTH:
2730 case IEEE80211_STYPE_ASSOC_REQ:
2731 case IEEE80211_STYPE_REASSOC_REQ:
Tomas Winkler87e4f7d2008-01-14 17:46:16 -08002732 if (tx->tx_flags & TX_CMD_FLG_RTS_MSK) {
2733 tx->tx_flags &= ~TX_CMD_FLG_RTS_MSK;
2734 tx->tx_flags |= TX_CMD_FLG_CTS_MSK;
Zhu Yib481de92007-09-25 17:54:57 -07002735 }
2736 break;
2737 default:
2738 break;
2739 }
Tomas Winkler87e4f7d2008-01-14 17:46:16 -08002740
2741 /* Alternate between antenna A and B for successive frames */
2742 if (priv->use_ant_b_for_management_frame) {
2743 priv->use_ant_b_for_management_frame = 0;
2744 rate_flags |= RATE_MCS_ANT_B_MSK;
2745 } else {
2746 priv->use_ant_b_for_management_frame = 1;
2747 rate_flags |= RATE_MCS_ANT_A_MSK;
2748 }
Zhu Yib481de92007-09-25 17:54:57 -07002749 }
2750
Tomas Winkler87e4f7d2008-01-14 17:46:16 -08002751 tx->rts_retry_limit = rts_retry_limit;
2752 tx->data_retry_limit = data_retry_limit;
2753 tx->rate_n_flags = iwl4965_hw_set_rate_n_flags(rate_plcp, rate_flags);
Zhu Yib481de92007-09-25 17:54:57 -07002754}
2755
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002756int iwl4965_hw_get_rx_read(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -07002757{
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002758 struct iwl4965_shared *shared_data = priv->hw_setting.shared_virt;
Zhu Yib481de92007-09-25 17:54:57 -07002759
2760 return IWL_GET_BITS(*shared_data, rb_closed_stts_rb_num);
2761}
2762
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002763int iwl4965_hw_get_temperature(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -07002764{
2765 return priv->temperature;
2766}
2767
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002768unsigned int iwl4965_hw_get_beacon_cmd(struct iwl4965_priv *priv,
2769 struct iwl4965_frame *frame, u8 rate)
Zhu Yib481de92007-09-25 17:54:57 -07002770{
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002771 struct iwl4965_tx_beacon_cmd *tx_beacon_cmd;
Zhu Yib481de92007-09-25 17:54:57 -07002772 unsigned int frame_size;
2773
2774 tx_beacon_cmd = &frame->u.beacon;
2775 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2776
2777 tx_beacon_cmd->tx.sta_id = IWL4965_BROADCAST_ID;
2778 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2779
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002780 frame_size = iwl4965_fill_beacon_frame(priv,
Zhu Yib481de92007-09-25 17:54:57 -07002781 tx_beacon_cmd->frame,
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002782 iwl4965_broadcast_addr,
Zhu Yib481de92007-09-25 17:54:57 -07002783 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2784
2785 BUG_ON(frame_size > MAX_MPDU_SIZE);
2786 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2787
2788 if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
2789 tx_beacon_cmd->tx.rate_n_flags =
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002790 iwl4965_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
Zhu Yib481de92007-09-25 17:54:57 -07002791 else
2792 tx_beacon_cmd->tx.rate_n_flags =
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002793 iwl4965_hw_set_rate_n_flags(rate, 0);
Zhu Yib481de92007-09-25 17:54:57 -07002794
2795 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2796 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK);
2797 return (sizeof(*tx_beacon_cmd) + frame_size);
2798}
2799
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08002800/*
2801 * Tell 4965 where to find circular buffer of Tx Frame Descriptors for
2802 * given Tx queue, and enable the DMA channel used for that queue.
2803 *
2804 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
2805 * channels supported in hardware.
2806 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002807int iwl4965_hw_tx_queue_init(struct iwl4965_priv *priv, struct iwl4965_tx_queue *txq)
Zhu Yib481de92007-09-25 17:54:57 -07002808{
2809 int rc;
2810 unsigned long flags;
2811 int txq_id = txq->q.id;
2812
2813 spin_lock_irqsave(&priv->lock, flags);
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002814 rc = iwl4965_grab_nic_access(priv);
Zhu Yib481de92007-09-25 17:54:57 -07002815 if (rc) {
2816 spin_unlock_irqrestore(&priv->lock, flags);
2817 return rc;
2818 }
2819
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08002820 /* Circular buffer (TFD queue in DRAM) physical base address */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002821 iwl4965_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
Zhu Yib481de92007-09-25 17:54:57 -07002822 txq->q.dma_addr >> 8);
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08002823
2824 /* Enable DMA channel, using same id as for TFD queue */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002825 iwl4965_write_direct32(
Zhu Yib481de92007-09-25 17:54:57 -07002826 priv, IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
2827 IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
2828 IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL);
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002829 iwl4965_release_nic_access(priv);
Zhu Yib481de92007-09-25 17:54:57 -07002830 spin_unlock_irqrestore(&priv->lock, flags);
2831
2832 return 0;
2833}
2834
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002835int iwl4965_hw_txq_attach_buf_to_tfd(struct iwl4965_priv *priv, void *ptr,
Zhu Yib481de92007-09-25 17:54:57 -07002836 dma_addr_t addr, u16 len)
2837{
2838 int index, is_odd;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002839 struct iwl4965_tfd_frame *tfd = ptr;
Zhu Yib481de92007-09-25 17:54:57 -07002840 u32 num_tbs = IWL_GET_BITS(*tfd, num_tbs);
2841
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08002842 /* Each TFD can point to a maximum 20 Tx buffers */
Zhu Yib481de92007-09-25 17:54:57 -07002843 if ((num_tbs >= MAX_NUM_OF_TBS) || (num_tbs < 0)) {
2844 IWL_ERROR("Error can not send more than %d chunks\n",
2845 MAX_NUM_OF_TBS);
2846 return -EINVAL;
2847 }
2848
2849 index = num_tbs / 2;
2850 is_odd = num_tbs & 0x1;
2851
2852 if (!is_odd) {
2853 tfd->pa[index].tb1_addr = cpu_to_le32(addr);
2854 IWL_SET_BITS(tfd->pa[index], tb1_addr_hi,
Tomas Winkler6a218f62008-01-14 17:46:15 -08002855 iwl_get_dma_hi_address(addr));
Zhu Yib481de92007-09-25 17:54:57 -07002856 IWL_SET_BITS(tfd->pa[index], tb1_len, len);
2857 } else {
2858 IWL_SET_BITS(tfd->pa[index], tb2_addr_lo16,
2859 (u32) (addr & 0xffff));
2860 IWL_SET_BITS(tfd->pa[index], tb2_addr_hi20, addr >> 16);
2861 IWL_SET_BITS(tfd->pa[index], tb2_len, len);
2862 }
2863
2864 IWL_SET_BITS(*tfd, num_tbs, num_tbs + 1);
2865
2866 return 0;
2867}
2868
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002869static void iwl4965_hw_card_show_info(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -07002870{
2871 u16 hw_version = priv->eeprom.board_revision_4965;
2872
2873 IWL_DEBUG_INFO("4965ABGN HW Version %u.%u.%u\n",
2874 ((hw_version >> 8) & 0x0F),
2875 ((hw_version >> 8) >> 4), (hw_version & 0x00FF));
2876
2877 IWL_DEBUG_INFO("4965ABGN PBA Number %.16s\n",
2878 priv->eeprom.board_pba_number_4965);
2879}
2880
2881#define IWL_TX_CRC_SIZE 4
2882#define IWL_TX_DELIMITER_SIZE 4
2883
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08002884/**
2885 * iwl4965_tx_queue_update_wr_ptr - Set up entry in Tx byte-count array
2886 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002887int iwl4965_tx_queue_update_wr_ptr(struct iwl4965_priv *priv,
2888 struct iwl4965_tx_queue *txq, u16 byte_cnt)
Zhu Yib481de92007-09-25 17:54:57 -07002889{
2890 int len;
2891 int txq_id = txq->q.id;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002892 struct iwl4965_shared *shared_data = priv->hw_setting.shared_virt;
Zhu Yib481de92007-09-25 17:54:57 -07002893
2894 if (txq->need_update == 0)
2895 return 0;
2896
2897 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
2898
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08002899 /* Set up byte count within first 256 entries */
Zhu Yib481de92007-09-25 17:54:57 -07002900 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
Tomas Winklerfc4b6852007-10-25 17:15:24 +08002901 tfd_offset[txq->q.write_ptr], byte_cnt, len);
Zhu Yib481de92007-09-25 17:54:57 -07002902
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08002903 /* If within first 64 entries, duplicate at end */
Tomas Winklerfc4b6852007-10-25 17:15:24 +08002904 if (txq->q.write_ptr < IWL4965_MAX_WIN_SIZE)
Zhu Yib481de92007-09-25 17:54:57 -07002905 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
Tomas Winklerfc4b6852007-10-25 17:15:24 +08002906 tfd_offset[IWL4965_QUEUE_SIZE + txq->q.write_ptr],
Zhu Yib481de92007-09-25 17:54:57 -07002907 byte_cnt, len);
2908
2909 return 0;
2910}
2911
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08002912/**
2913 * iwl4965_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
2914 *
2915 * Selects how many and which Rx receivers/antennas/chains to use.
2916 * This should not be used for scan command ... it puts data in wrong place.
2917 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002918void iwl4965_set_rxon_chain(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -07002919{
2920 u8 is_single = is_single_stream(priv);
2921 u8 idle_state, rx_state;
2922
2923 priv->staging_rxon.rx_chain = 0;
2924 rx_state = idle_state = 3;
2925
2926 /* Tell uCode which antennas are actually connected.
2927 * Before first association, we assume all antennas are connected.
2928 * Just after first association, iwl4965_noise_calibration()
2929 * checks which antennas actually *are* connected. */
2930 priv->staging_rxon.rx_chain |=
2931 cpu_to_le16(priv->valid_antenna << RXON_RX_CHAIN_VALID_POS);
2932
2933 /* How many receivers should we use? */
2934 iwl4965_get_rx_chain_counter(priv, &idle_state, &rx_state);
2935 priv->staging_rxon.rx_chain |=
2936 cpu_to_le16(rx_state << RXON_RX_CHAIN_MIMO_CNT_POS);
2937 priv->staging_rxon.rx_chain |=
2938 cpu_to_le16(idle_state << RXON_RX_CHAIN_CNT_POS);
2939
2940 if (!is_single && (rx_state >= 2) &&
2941 !test_bit(STATUS_POWER_PMI, &priv->status))
2942 priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
2943 else
2944 priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
2945
2946 IWL_DEBUG_ASSOC("rx chain %X\n", priv->staging_rxon.rx_chain);
2947}
2948
Christoph Hellwigc8b0e6e2007-10-25 17:15:51 +08002949#ifdef CONFIG_IWL4965_HT
2950#ifdef CONFIG_IWL4965_HT_AGG
Zhu Yib481de92007-09-25 17:54:57 -07002951/*
2952 get the traffic load value for tid
2953*/
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002954static u32 iwl4965_tl_get_load(struct iwl4965_priv *priv, u8 tid)
Zhu Yib481de92007-09-25 17:54:57 -07002955{
2956 u32 load = 0;
2957 u32 current_time = jiffies_to_msecs(jiffies);
2958 u32 time_diff;
2959 s32 index;
2960 unsigned long flags;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002961 struct iwl4965_traffic_load *tid_ptr = NULL;
Zhu Yib481de92007-09-25 17:54:57 -07002962
2963 if (tid >= TID_MAX_LOAD_COUNT)
2964 return 0;
2965
2966 tid_ptr = &(priv->lq_mngr.agg_ctrl.traffic_load[tid]);
2967
2968 current_time -= current_time % TID_ROUND_VALUE;
2969
2970 spin_lock_irqsave(&priv->lq_mngr.lock, flags);
2971 if (!(tid_ptr->queue_count))
2972 goto out;
2973
2974 time_diff = TIME_WRAP_AROUND(tid_ptr->time_stamp, current_time);
2975 index = time_diff / TID_QUEUE_CELL_SPACING;
2976
2977 if (index >= TID_QUEUE_MAX_SIZE) {
2978 u32 oldest_time = current_time - TID_MAX_TIME_DIFF;
2979
2980 while (tid_ptr->queue_count &&
2981 (tid_ptr->time_stamp < oldest_time)) {
2982 tid_ptr->total -= tid_ptr->packet_count[tid_ptr->head];
2983 tid_ptr->packet_count[tid_ptr->head] = 0;
2984 tid_ptr->time_stamp += TID_QUEUE_CELL_SPACING;
2985 tid_ptr->queue_count--;
2986 tid_ptr->head++;
2987 if (tid_ptr->head >= TID_QUEUE_MAX_SIZE)
2988 tid_ptr->head = 0;
2989 }
2990 }
2991 load = tid_ptr->total;
2992
2993 out:
2994 spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
2995 return load;
2996}
2997
2998/*
2999 increment traffic load value for tid and also remove
3000 any old values if passed the certian time period
3001*/
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003002static void iwl4965_tl_add_packet(struct iwl4965_priv *priv, u8 tid)
Zhu Yib481de92007-09-25 17:54:57 -07003003{
3004 u32 current_time = jiffies_to_msecs(jiffies);
3005 u32 time_diff;
3006 s32 index;
3007 unsigned long flags;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003008 struct iwl4965_traffic_load *tid_ptr = NULL;
Zhu Yib481de92007-09-25 17:54:57 -07003009
3010 if (tid >= TID_MAX_LOAD_COUNT)
3011 return;
3012
3013 tid_ptr = &(priv->lq_mngr.agg_ctrl.traffic_load[tid]);
3014
3015 current_time -= current_time % TID_ROUND_VALUE;
3016
3017 spin_lock_irqsave(&priv->lq_mngr.lock, flags);
3018 if (!(tid_ptr->queue_count)) {
3019 tid_ptr->total = 1;
3020 tid_ptr->time_stamp = current_time;
3021 tid_ptr->queue_count = 1;
3022 tid_ptr->head = 0;
3023 tid_ptr->packet_count[0] = 1;
3024 goto out;
3025 }
3026
3027 time_diff = TIME_WRAP_AROUND(tid_ptr->time_stamp, current_time);
3028 index = time_diff / TID_QUEUE_CELL_SPACING;
3029
3030 if (index >= TID_QUEUE_MAX_SIZE) {
3031 u32 oldest_time = current_time - TID_MAX_TIME_DIFF;
3032
3033 while (tid_ptr->queue_count &&
3034 (tid_ptr->time_stamp < oldest_time)) {
3035 tid_ptr->total -= tid_ptr->packet_count[tid_ptr->head];
3036 tid_ptr->packet_count[tid_ptr->head] = 0;
3037 tid_ptr->time_stamp += TID_QUEUE_CELL_SPACING;
3038 tid_ptr->queue_count--;
3039 tid_ptr->head++;
3040 if (tid_ptr->head >= TID_QUEUE_MAX_SIZE)
3041 tid_ptr->head = 0;
3042 }
3043 }
3044
3045 index = (tid_ptr->head + index) % TID_QUEUE_MAX_SIZE;
3046 tid_ptr->packet_count[index] = tid_ptr->packet_count[index] + 1;
3047 tid_ptr->total = tid_ptr->total + 1;
3048
3049 if ((index + 1) > tid_ptr->queue_count)
3050 tid_ptr->queue_count = index + 1;
3051 out:
3052 spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
3053
3054}
3055
3056#define MMAC_SCHED_MAX_NUMBER_OF_HT_BACK_FLOWS 7
3057enum HT_STATUS {
3058 BA_STATUS_FAILURE = 0,
3059 BA_STATUS_INITIATOR_DELBA,
3060 BA_STATUS_RECIPIENT_DELBA,
3061 BA_STATUS_RENEW_ADDBA_REQUEST,
3062 BA_STATUS_ACTIVE,
3063};
3064
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08003065/**
3066 * iwl4964_tl_ba_avail - Find out if an unused aggregation queue is available
3067 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003068static u8 iwl4964_tl_ba_avail(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -07003069{
3070 int i;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003071 struct iwl4965_lq_mngr *lq;
Zhu Yib481de92007-09-25 17:54:57 -07003072 u8 count = 0;
3073 u16 msk;
3074
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003075 lq = (struct iwl4965_lq_mngr *)&(priv->lq_mngr);
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08003076
3077 /* Find out how many agg queues are in use */
Zhu Yib481de92007-09-25 17:54:57 -07003078 for (i = 0; i < TID_MAX_LOAD_COUNT ; i++) {
3079 msk = 1 << i;
3080 if ((lq->agg_ctrl.granted_ba & msk) ||
3081 (lq->agg_ctrl.wait_for_agg_status & msk))
3082 count++;
3083 }
3084
3085 if (count < MMAC_SCHED_MAX_NUMBER_OF_HT_BACK_FLOWS)
3086 return 1;
3087
3088 return 0;
3089}
3090
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003091static void iwl4965_ba_status(struct iwl4965_priv *priv,
Zhu Yib481de92007-09-25 17:54:57 -07003092 u8 tid, enum HT_STATUS status);
3093
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003094static int iwl4965_perform_addba(struct iwl4965_priv *priv, u8 tid, u32 length,
Zhu Yib481de92007-09-25 17:54:57 -07003095 u32 ba_timeout)
3096{
3097 int rc;
3098
3099 rc = ieee80211_start_BA_session(priv->hw, priv->bssid, tid);
3100 if (rc)
3101 iwl4965_ba_status(priv, tid, BA_STATUS_FAILURE);
3102
3103 return rc;
3104}
3105
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003106static int iwl4965_perform_delba(struct iwl4965_priv *priv, u8 tid)
Zhu Yib481de92007-09-25 17:54:57 -07003107{
3108 int rc;
3109
3110 rc = ieee80211_stop_BA_session(priv->hw, priv->bssid, tid);
3111 if (rc)
3112 iwl4965_ba_status(priv, tid, BA_STATUS_FAILURE);
3113
3114 return rc;
3115}
3116
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003117static void iwl4965_turn_on_agg_for_tid(struct iwl4965_priv *priv,
3118 struct iwl4965_lq_mngr *lq,
Zhu Yib481de92007-09-25 17:54:57 -07003119 u8 auto_agg, u8 tid)
3120{
3121 u32 tid_msk = (1 << tid);
3122 unsigned long flags;
3123
3124 spin_lock_irqsave(&priv->lq_mngr.lock, flags);
3125/*
3126 if ((auto_agg) && (!lq->enable_counter)){
3127 lq->agg_ctrl.next_retry = 0;
3128 lq->agg_ctrl.tid_retry = 0;
3129 spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
3130 return;
3131 }
3132*/
3133 if (!(lq->agg_ctrl.granted_ba & tid_msk) &&
3134 (lq->agg_ctrl.requested_ba & tid_msk)) {
3135 u8 available_queues;
3136 u32 load;
3137
3138 spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
3139 available_queues = iwl4964_tl_ba_avail(priv);
3140 load = iwl4965_tl_get_load(priv, tid);
3141
3142 spin_lock_irqsave(&priv->lq_mngr.lock, flags);
3143 if (!available_queues) {
3144 if (auto_agg)
3145 lq->agg_ctrl.tid_retry |= tid_msk;
3146 else {
3147 lq->agg_ctrl.requested_ba &= ~tid_msk;
3148 lq->agg_ctrl.wait_for_agg_status &= ~tid_msk;
3149 }
3150 } else if ((auto_agg) &&
3151 ((load <= lq->agg_ctrl.tid_traffic_load_threshold) ||
3152 ((lq->agg_ctrl.wait_for_agg_status & tid_msk))))
3153 lq->agg_ctrl.tid_retry |= tid_msk;
3154 else {
3155 lq->agg_ctrl.wait_for_agg_status |= tid_msk;
3156 spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
3157 iwl4965_perform_addba(priv, tid, 0x40,
3158 lq->agg_ctrl.ba_timeout);
3159 spin_lock_irqsave(&priv->lq_mngr.lock, flags);
3160 }
3161 }
3162 spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
3163}
3164
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003165static void iwl4965_turn_on_agg(struct iwl4965_priv *priv, u8 tid)
Zhu Yib481de92007-09-25 17:54:57 -07003166{
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003167 struct iwl4965_lq_mngr *lq;
Zhu Yib481de92007-09-25 17:54:57 -07003168 unsigned long flags;
3169
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003170 lq = (struct iwl4965_lq_mngr *)&(priv->lq_mngr);
Zhu Yib481de92007-09-25 17:54:57 -07003171
3172 if ((tid < TID_MAX_LOAD_COUNT))
3173 iwl4965_turn_on_agg_for_tid(priv, lq, lq->agg_ctrl.auto_agg,
3174 tid);
3175 else if (tid == TID_ALL_SPECIFIED) {
3176 if (lq->agg_ctrl.requested_ba) {
3177 for (tid = 0; tid < TID_MAX_LOAD_COUNT; tid++)
3178 iwl4965_turn_on_agg_for_tid(priv, lq,
3179 lq->agg_ctrl.auto_agg, tid);
3180 } else {
3181 spin_lock_irqsave(&priv->lq_mngr.lock, flags);
3182 lq->agg_ctrl.tid_retry = 0;
3183 lq->agg_ctrl.next_retry = 0;
3184 spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
3185 }
3186 }
3187
3188}
3189
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003190void iwl4965_turn_off_agg(struct iwl4965_priv *priv, u8 tid)
Zhu Yib481de92007-09-25 17:54:57 -07003191{
3192 u32 tid_msk;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003193 struct iwl4965_lq_mngr *lq;
Zhu Yib481de92007-09-25 17:54:57 -07003194 unsigned long flags;
3195
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003196 lq = (struct iwl4965_lq_mngr *)&(priv->lq_mngr);
Zhu Yib481de92007-09-25 17:54:57 -07003197
3198 if ((tid < TID_MAX_LOAD_COUNT)) {
3199 tid_msk = 1 << tid;
3200 spin_lock_irqsave(&priv->lq_mngr.lock, flags);
3201 lq->agg_ctrl.wait_for_agg_status |= tid_msk;
3202 lq->agg_ctrl.requested_ba &= ~tid_msk;
3203 spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
3204 iwl4965_perform_delba(priv, tid);
3205 } else if (tid == TID_ALL_SPECIFIED) {
3206 spin_lock_irqsave(&priv->lq_mngr.lock, flags);
3207 for (tid = 0; tid < TID_MAX_LOAD_COUNT; tid++) {
3208 tid_msk = 1 << tid;
3209 lq->agg_ctrl.wait_for_agg_status |= tid_msk;
3210 spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
3211 iwl4965_perform_delba(priv, tid);
3212 spin_lock_irqsave(&priv->lq_mngr.lock, flags);
3213 }
3214 lq->agg_ctrl.requested_ba = 0;
3215 spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
3216 }
3217}
3218
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08003219/**
3220 * iwl4965_ba_status - Update driver's link quality mgr with tid's HT status
3221 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003222static void iwl4965_ba_status(struct iwl4965_priv *priv,
Zhu Yib481de92007-09-25 17:54:57 -07003223 u8 tid, enum HT_STATUS status)
3224{
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003225 struct iwl4965_lq_mngr *lq;
Zhu Yib481de92007-09-25 17:54:57 -07003226 u32 tid_msk = (1 << tid);
3227 unsigned long flags;
3228
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003229 lq = (struct iwl4965_lq_mngr *)&(priv->lq_mngr);
Zhu Yib481de92007-09-25 17:54:57 -07003230
3231 if ((tid >= TID_MAX_LOAD_COUNT))
3232 goto out;
3233
3234 spin_lock_irqsave(&priv->lq_mngr.lock, flags);
3235 switch (status) {
3236 case BA_STATUS_ACTIVE:
3237 if (!(lq->agg_ctrl.granted_ba & tid_msk))
3238 lq->agg_ctrl.granted_ba |= tid_msk;
3239 break;
3240 default:
3241 if ((lq->agg_ctrl.granted_ba & tid_msk))
3242 lq->agg_ctrl.granted_ba &= ~tid_msk;
3243 break;
3244 }
3245
3246 lq->agg_ctrl.wait_for_agg_status &= ~tid_msk;
3247 if (status != BA_STATUS_ACTIVE) {
3248 if (lq->agg_ctrl.auto_agg) {
3249 lq->agg_ctrl.tid_retry |= tid_msk;
3250 lq->agg_ctrl.next_retry =
3251 jiffies + msecs_to_jiffies(500);
3252 } else
3253 lq->agg_ctrl.requested_ba &= ~tid_msk;
3254 }
3255 spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
3256 out:
3257 return;
3258}
3259
3260static void iwl4965_bg_agg_work(struct work_struct *work)
3261{
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003262 struct iwl4965_priv *priv = container_of(work, struct iwl4965_priv,
Zhu Yib481de92007-09-25 17:54:57 -07003263 agg_work);
3264
3265 u32 tid;
3266 u32 retry_tid;
3267 u32 tid_msk;
3268 unsigned long flags;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003269 struct iwl4965_lq_mngr *lq = (struct iwl4965_lq_mngr *)&(priv->lq_mngr);
Zhu Yib481de92007-09-25 17:54:57 -07003270
3271 spin_lock_irqsave(&priv->lq_mngr.lock, flags);
3272 retry_tid = lq->agg_ctrl.tid_retry;
3273 lq->agg_ctrl.tid_retry = 0;
3274 spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
3275
3276 if (retry_tid == TID_ALL_SPECIFIED)
3277 iwl4965_turn_on_agg(priv, TID_ALL_SPECIFIED);
3278 else {
3279 for (tid = 0; tid < TID_MAX_LOAD_COUNT; tid++) {
3280 tid_msk = (1 << tid);
3281 if (retry_tid & tid_msk)
3282 iwl4965_turn_on_agg(priv, tid);
3283 }
3284 }
3285
3286 spin_lock_irqsave(&priv->lq_mngr.lock, flags);
3287 if (lq->agg_ctrl.tid_retry)
3288 lq->agg_ctrl.next_retry = jiffies + msecs_to_jiffies(500);
3289 spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
3290 return;
3291}
Zhu Yib481de92007-09-25 17:54:57 -07003292
Tomas Winkler87e4f7d2008-01-14 17:46:16 -08003293/* TODO: move this functionality to rate scaling */
3294void iwl4965_tl_get_stats(struct iwl4965_priv *priv,
3295 struct ieee80211_hdr *hdr)
Zhu Yib481de92007-09-25 17:54:57 -07003296{
Tomas Winkler87e4f7d2008-01-14 17:46:16 -08003297 __le16 *qc = ieee80211_get_qos_ctrl(hdr);
Zhu Yib481de92007-09-25 17:54:57 -07003298
Zhu Yib481de92007-09-25 17:54:57 -07003299 if (qc &&
3300 (priv->iw_mode != IEEE80211_IF_TYPE_IBSS)) {
3301 u8 tid = 0;
3302 tid = (u8) (le16_to_cpu(*qc) & 0xF);
3303 if (tid < TID_MAX_LOAD_COUNT)
3304 iwl4965_tl_add_packet(priv, tid);
3305 }
3306
3307 if (priv->lq_mngr.agg_ctrl.next_retry &&
3308 (time_after(priv->lq_mngr.agg_ctrl.next_retry, jiffies))) {
3309 unsigned long flags;
3310
3311 spin_lock_irqsave(&priv->lq_mngr.lock, flags);
3312 priv->lq_mngr.agg_ctrl.next_retry = 0;
3313 spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
3314 schedule_work(&priv->agg_work);
3315 }
Zhu Yib481de92007-09-25 17:54:57 -07003316}
3317
Tomas Winkler87e4f7d2008-01-14 17:46:16 -08003318#endif /*CONFIG_IWL4965_HT_AGG */
3319#endif /* CONFIG_IWL4965_HT */
3320
Zhu Yib481de92007-09-25 17:54:57 -07003321/**
3322 * sign_extend - Sign extend a value using specified bit as sign-bit
3323 *
3324 * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1
3325 * and bit0..2 is 001b which when sign extended to 1111111111111001b is -7.
3326 *
3327 * @param oper value to sign extend
3328 * @param index 0 based bit index (0<=index<32) to sign bit
3329 */
3330static s32 sign_extend(u32 oper, int index)
3331{
3332 u8 shift = 31 - index;
3333
3334 return (s32)(oper << shift) >> shift;
3335}
3336
3337/**
3338 * iwl4965_get_temperature - return the calibrated temperature (in Kelvin)
3339 * @statistics: Provides the temperature reading from the uCode
3340 *
3341 * A return of <0 indicates bogus data in the statistics
3342 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003343int iwl4965_get_temperature(const struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -07003344{
3345 s32 temperature;
3346 s32 vt;
3347 s32 R1, R2, R3;
3348 u32 R4;
3349
3350 if (test_bit(STATUS_TEMPERATURE, &priv->status) &&
3351 (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)) {
3352 IWL_DEBUG_TEMP("Running FAT temperature calibration\n");
3353 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
3354 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
3355 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
3356 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[1]);
3357 } else {
3358 IWL_DEBUG_TEMP("Running temperature calibration\n");
3359 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
3360 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
3361 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
3362 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[0]);
3363 }
3364
3365 /*
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08003366 * Temperature is only 23 bits, so sign extend out to 32.
Zhu Yib481de92007-09-25 17:54:57 -07003367 *
3368 * NOTE If we haven't received a statistics notification yet
3369 * with an updated temperature, use R4 provided to us in the
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08003370 * "initialize" ALIVE response.
3371 */
Zhu Yib481de92007-09-25 17:54:57 -07003372 if (!test_bit(STATUS_TEMPERATURE, &priv->status))
3373 vt = sign_extend(R4, 23);
3374 else
3375 vt = sign_extend(
3376 le32_to_cpu(priv->statistics.general.temperature), 23);
3377
3378 IWL_DEBUG_TEMP("Calib values R[1-3]: %d %d %d R4: %d\n",
3379 R1, R2, R3, vt);
3380
3381 if (R3 == R1) {
3382 IWL_ERROR("Calibration conflict R1 == R3\n");
3383 return -1;
3384 }
3385
3386 /* Calculate temperature in degrees Kelvin, adjust by 97%.
3387 * Add offset to center the adjustment around 0 degrees Centigrade. */
3388 temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2);
3389 temperature /= (R3 - R1);
3390 temperature = (temperature * 97) / 100 +
3391 TEMPERATURE_CALIB_KELVIN_OFFSET;
3392
3393 IWL_DEBUG_TEMP("Calibrated temperature: %dK, %dC\n", temperature,
3394 KELVIN_TO_CELSIUS(temperature));
3395
3396 return temperature;
3397}
3398
3399/* Adjust Txpower only if temperature variance is greater than threshold. */
3400#define IWL_TEMPERATURE_THRESHOLD 3
3401
3402/**
3403 * iwl4965_is_temp_calib_needed - determines if new calibration is needed
3404 *
3405 * If the temperature changed has changed sufficiently, then a recalibration
3406 * is needed.
3407 *
3408 * Assumes caller will replace priv->last_temperature once calibration
3409 * executed.
3410 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003411static int iwl4965_is_temp_calib_needed(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -07003412{
3413 int temp_diff;
3414
3415 if (!test_bit(STATUS_STATISTICS, &priv->status)) {
3416 IWL_DEBUG_TEMP("Temperature not updated -- no statistics.\n");
3417 return 0;
3418 }
3419
3420 temp_diff = priv->temperature - priv->last_temperature;
3421
3422 /* get absolute value */
3423 if (temp_diff < 0) {
3424 IWL_DEBUG_POWER("Getting cooler, delta %d, \n", temp_diff);
3425 temp_diff = -temp_diff;
3426 } else if (temp_diff == 0)
3427 IWL_DEBUG_POWER("Same temp, \n");
3428 else
3429 IWL_DEBUG_POWER("Getting warmer, delta %d, \n", temp_diff);
3430
3431 if (temp_diff < IWL_TEMPERATURE_THRESHOLD) {
3432 IWL_DEBUG_POWER("Thermal txpower calib not needed\n");
3433 return 0;
3434 }
3435
3436 IWL_DEBUG_POWER("Thermal txpower calib needed\n");
3437
3438 return 1;
3439}
3440
3441/* Calculate noise level, based on measurements during network silence just
3442 * before arriving beacon. This measurement can be done only if we know
3443 * exactly when to expect beacons, therefore only when we're associated. */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003444static void iwl4965_rx_calc_noise(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -07003445{
3446 struct statistics_rx_non_phy *rx_info
3447 = &(priv->statistics.rx.general);
3448 int num_active_rx = 0;
3449 int total_silence = 0;
3450 int bcn_silence_a =
3451 le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
3452 int bcn_silence_b =
3453 le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
3454 int bcn_silence_c =
3455 le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
3456
3457 if (bcn_silence_a) {
3458 total_silence += bcn_silence_a;
3459 num_active_rx++;
3460 }
3461 if (bcn_silence_b) {
3462 total_silence += bcn_silence_b;
3463 num_active_rx++;
3464 }
3465 if (bcn_silence_c) {
3466 total_silence += bcn_silence_c;
3467 num_active_rx++;
3468 }
3469
3470 /* Average among active antennas */
3471 if (num_active_rx)
3472 priv->last_rx_noise = (total_silence / num_active_rx) - 107;
3473 else
3474 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
3475
3476 IWL_DEBUG_CALIB("inband silence a %u, b %u, c %u, dBm %d\n",
3477 bcn_silence_a, bcn_silence_b, bcn_silence_c,
3478 priv->last_rx_noise);
3479}
3480
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003481void iwl4965_hw_rx_statistics(struct iwl4965_priv *priv, struct iwl4965_rx_mem_buffer *rxb)
Zhu Yib481de92007-09-25 17:54:57 -07003482{
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003483 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
Zhu Yib481de92007-09-25 17:54:57 -07003484 int change;
3485 s32 temp;
3486
3487 IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
3488 (int)sizeof(priv->statistics), pkt->len);
3489
3490 change = ((priv->statistics.general.temperature !=
3491 pkt->u.stats.general.temperature) ||
3492 ((priv->statistics.flag &
3493 STATISTICS_REPLY_FLG_FAT_MODE_MSK) !=
3494 (pkt->u.stats.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)));
3495
3496 memcpy(&priv->statistics, &pkt->u.stats, sizeof(priv->statistics));
3497
3498 set_bit(STATUS_STATISTICS, &priv->status);
3499
3500 /* Reschedule the statistics timer to occur in
3501 * REG_RECALIB_PERIOD seconds to ensure we get a
3502 * thermal update even if the uCode doesn't give
3503 * us one */
3504 mod_timer(&priv->statistics_periodic, jiffies +
3505 msecs_to_jiffies(REG_RECALIB_PERIOD * 1000));
3506
3507 if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
3508 (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) {
3509 iwl4965_rx_calc_noise(priv);
Christoph Hellwigc8b0e6e2007-10-25 17:15:51 +08003510#ifdef CONFIG_IWL4965_SENSITIVITY
Zhu Yib481de92007-09-25 17:54:57 -07003511 queue_work(priv->workqueue, &priv->sensitivity_work);
3512#endif
3513 }
3514
3515 /* If the hardware hasn't reported a change in
3516 * temperature then don't bother computing a
3517 * calibrated temperature value */
3518 if (!change)
3519 return;
3520
3521 temp = iwl4965_get_temperature(priv);
3522 if (temp < 0)
3523 return;
3524
3525 if (priv->temperature != temp) {
3526 if (priv->temperature)
3527 IWL_DEBUG_TEMP("Temperature changed "
3528 "from %dC to %dC\n",
3529 KELVIN_TO_CELSIUS(priv->temperature),
3530 KELVIN_TO_CELSIUS(temp));
3531 else
3532 IWL_DEBUG_TEMP("Temperature "
3533 "initialized to %dC\n",
3534 KELVIN_TO_CELSIUS(temp));
3535 }
3536
3537 priv->temperature = temp;
3538 set_bit(STATUS_TEMPERATURE, &priv->status);
3539
3540 if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
3541 iwl4965_is_temp_calib_needed(priv))
3542 queue_work(priv->workqueue, &priv->txpower_work);
3543}
3544
Zhu Yi12342c42007-12-20 11:27:32 +08003545static void iwl4965_add_radiotap(struct iwl4965_priv *priv,
3546 struct sk_buff *skb,
3547 struct iwl4965_rx_phy_res *rx_start,
3548 struct ieee80211_rx_status *stats,
3549 u32 ampdu_status)
3550{
3551 s8 signal = stats->ssi;
3552 s8 noise = 0;
3553 int rate = stats->rate;
3554 u64 tsf = stats->mactime;
3555 __le16 phy_flags_hw = rx_start->phy_flags;
3556 struct iwl4965_rt_rx_hdr {
3557 struct ieee80211_radiotap_header rt_hdr;
3558 __le64 rt_tsf; /* TSF */
3559 u8 rt_flags; /* radiotap packet flags */
3560 u8 rt_rate; /* rate in 500kb/s */
3561 __le16 rt_channelMHz; /* channel in MHz */
3562 __le16 rt_chbitmask; /* channel bitfield */
3563 s8 rt_dbmsignal; /* signal in dBm, kluged to signed */
3564 s8 rt_dbmnoise;
3565 u8 rt_antenna; /* antenna number */
3566 } __attribute__ ((packed)) *iwl4965_rt;
3567
3568 /* TODO: We won't have enough headroom for HT frames. Fix it later. */
3569 if (skb_headroom(skb) < sizeof(*iwl4965_rt)) {
3570 if (net_ratelimit())
3571 printk(KERN_ERR "not enough headroom [%d] for "
Miguel Botón01c20982008-01-04 23:34:35 +01003572 "radiotap head [%zd]\n",
Zhu Yi12342c42007-12-20 11:27:32 +08003573 skb_headroom(skb), sizeof(*iwl4965_rt));
3574 return;
3575 }
3576
3577 /* put radiotap header in front of 802.11 header and data */
3578 iwl4965_rt = (void *)skb_push(skb, sizeof(*iwl4965_rt));
3579
3580 /* initialise radiotap header */
3581 iwl4965_rt->rt_hdr.it_version = PKTHDR_RADIOTAP_VERSION;
3582 iwl4965_rt->rt_hdr.it_pad = 0;
3583
3584 /* total header + data */
3585 put_unaligned(cpu_to_le16(sizeof(*iwl4965_rt)),
3586 &iwl4965_rt->rt_hdr.it_len);
3587
3588 /* Indicate all the fields we add to the radiotap header */
3589 put_unaligned(cpu_to_le32((1 << IEEE80211_RADIOTAP_TSFT) |
3590 (1 << IEEE80211_RADIOTAP_FLAGS) |
3591 (1 << IEEE80211_RADIOTAP_RATE) |
3592 (1 << IEEE80211_RADIOTAP_CHANNEL) |
3593 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |
3594 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) |
3595 (1 << IEEE80211_RADIOTAP_ANTENNA)),
3596 &iwl4965_rt->rt_hdr.it_present);
3597
3598 /* Zero the flags, we'll add to them as we go */
3599 iwl4965_rt->rt_flags = 0;
3600
3601 put_unaligned(cpu_to_le64(tsf), &iwl4965_rt->rt_tsf);
3602
3603 iwl4965_rt->rt_dbmsignal = signal;
3604 iwl4965_rt->rt_dbmnoise = noise;
3605
3606 /* Convert the channel frequency and set the flags */
3607 put_unaligned(cpu_to_le16(stats->freq), &iwl4965_rt->rt_channelMHz);
3608 if (!(phy_flags_hw & RX_RES_PHY_FLAGS_BAND_24_MSK))
3609 put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
3610 IEEE80211_CHAN_5GHZ),
3611 &iwl4965_rt->rt_chbitmask);
3612 else if (phy_flags_hw & RX_RES_PHY_FLAGS_MOD_CCK_MSK)
3613 put_unaligned(cpu_to_le16(IEEE80211_CHAN_CCK |
3614 IEEE80211_CHAN_2GHZ),
3615 &iwl4965_rt->rt_chbitmask);
3616 else /* 802.11g */
3617 put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
3618 IEEE80211_CHAN_2GHZ),
3619 &iwl4965_rt->rt_chbitmask);
3620
3621 rate = iwl4965_rate_index_from_plcp(rate);
3622 if (rate == -1)
3623 iwl4965_rt->rt_rate = 0;
3624 else
3625 iwl4965_rt->rt_rate = iwl4965_rates[rate].ieee;
3626
3627 /*
3628 * "antenna number"
3629 *
3630 * It seems that the antenna field in the phy flags value
3631 * is actually a bitfield. This is undefined by radiotap,
3632 * it wants an actual antenna number but I always get "7"
3633 * for most legacy frames I receive indicating that the
3634 * same frame was received on all three RX chains.
3635 *
3636 * I think this field should be removed in favour of a
3637 * new 802.11n radiotap field "RX chains" that is defined
3638 * as a bitmask.
3639 */
3640 iwl4965_rt->rt_antenna =
3641 le16_to_cpu(phy_flags_hw & RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
3642
3643 /* set the preamble flag if appropriate */
3644 if (phy_flags_hw & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
3645 iwl4965_rt->rt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
3646
3647 stats->flag |= RX_FLAG_RADIOTAP;
3648}
3649
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003650static void iwl4965_handle_data_packet(struct iwl4965_priv *priv, int is_data,
Zhu Yib481de92007-09-25 17:54:57 -07003651 int include_phy,
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003652 struct iwl4965_rx_mem_buffer *rxb,
Zhu Yib481de92007-09-25 17:54:57 -07003653 struct ieee80211_rx_status *stats)
3654{
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003655 struct iwl4965_rx_packet *pkt = (struct iwl4965_rx_packet *)rxb->skb->data;
Zhu Yib481de92007-09-25 17:54:57 -07003656 struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
3657 (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) : NULL;
3658 struct ieee80211_hdr *hdr;
3659 u16 len;
3660 __le32 *rx_end;
3661 unsigned int skblen;
3662 u32 ampdu_status;
3663
3664 if (!include_phy && priv->last_phy_res[0])
3665 rx_start = (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
3666
3667 if (!rx_start) {
3668 IWL_ERROR("MPDU frame without a PHY data\n");
3669 return;
3670 }
3671 if (include_phy) {
3672 hdr = (struct ieee80211_hdr *)((u8 *) & rx_start[1] +
3673 rx_start->cfg_phy_cnt);
3674
3675 len = le16_to_cpu(rx_start->byte_count);
3676
3677 rx_end = (__le32 *) ((u8 *) & pkt->u.raw[0] +
3678 sizeof(struct iwl4965_rx_phy_res) +
3679 rx_start->cfg_phy_cnt + len);
3680
3681 } else {
3682 struct iwl4965_rx_mpdu_res_start *amsdu =
3683 (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
3684
3685 hdr = (struct ieee80211_hdr *)(pkt->u.raw +
3686 sizeof(struct iwl4965_rx_mpdu_res_start));
3687 len = le16_to_cpu(amsdu->byte_count);
3688 rx_start->byte_count = amsdu->byte_count;
3689 rx_end = (__le32 *) (((u8 *) hdr) + len);
3690 }
Ron Rindjunsky9ee1ba42007-11-26 16:14:42 +02003691 if (len > priv->hw_setting.max_pkt_size || len < 16) {
Zhu Yi12342c42007-12-20 11:27:32 +08003692 IWL_WARNING("byte count out of range [16,4K] : %d\n", len);
Zhu Yib481de92007-09-25 17:54:57 -07003693 return;
3694 }
3695
3696 ampdu_status = le32_to_cpu(*rx_end);
3697 skblen = ((u8 *) rx_end - (u8 *) & pkt->u.raw[0]) + sizeof(u32);
3698
3699 /* start from MAC */
3700 skb_reserve(rxb->skb, (void *)hdr - (void *)pkt);
3701 skb_put(rxb->skb, len); /* end where data ends */
3702
3703 /* We only process data packets if the interface is open */
3704 if (unlikely(!priv->is_open)) {
3705 IWL_DEBUG_DROP_LIMIT
3706 ("Dropping packet while interface is not open.\n");
3707 return;
3708 }
3709
Zhu Yib481de92007-09-25 17:54:57 -07003710 stats->flag = 0;
3711 hdr = (struct ieee80211_hdr *)rxb->skb->data;
3712
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003713 if (iwl4965_param_hwcrypto)
3714 iwl4965_set_decrypted_flag(priv, rxb->skb, ampdu_status, stats);
Zhu Yib481de92007-09-25 17:54:57 -07003715
Zhu Yi12342c42007-12-20 11:27:32 +08003716 if (priv->add_radiotap)
3717 iwl4965_add_radiotap(priv, rxb->skb, rx_start, stats, ampdu_status);
3718
Zhu Yib481de92007-09-25 17:54:57 -07003719 ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
3720 priv->alloc_rxb_skb--;
3721 rxb->skb = NULL;
3722#ifdef LED
3723 priv->led_packets += len;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003724 iwl4965_setup_activity_timer(priv);
Zhu Yib481de92007-09-25 17:54:57 -07003725#endif
3726}
3727
3728/* Calc max signal level (dBm) among 3 possible receivers */
3729static int iwl4965_calc_rssi(struct iwl4965_rx_phy_res *rx_resp)
3730{
3731 /* data from PHY/DSP regarding signal strength, etc.,
3732 * contents are always there, not configurable by host. */
3733 struct iwl4965_rx_non_cfg_phy *ncphy =
3734 (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy;
3735 u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL_AGC_DB_MASK)
3736 >> IWL_AGC_DB_POS;
3737
3738 u32 valid_antennae =
3739 (le16_to_cpu(rx_resp->phy_flags) & RX_PHY_FLAGS_ANTENNAE_MASK)
3740 >> RX_PHY_FLAGS_ANTENNAE_OFFSET;
3741 u8 max_rssi = 0;
3742 u32 i;
3743
3744 /* Find max rssi among 3 possible receivers.
3745 * These values are measured by the digital signal processor (DSP).
3746 * They should stay fairly constant even as the signal strength varies,
3747 * if the radio's automatic gain control (AGC) is working right.
3748 * AGC value (see below) will provide the "interesting" info. */
3749 for (i = 0; i < 3; i++)
3750 if (valid_antennae & (1 << i))
3751 max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
3752
3753 IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
3754 ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
3755 max_rssi, agc);
3756
3757 /* dBm = max_rssi dB - agc dB - constant.
3758 * Higher AGC (higher radio gain) means lower signal. */
3759 return (max_rssi - agc - IWL_RSSI_OFFSET);
3760}
3761
Christoph Hellwigc8b0e6e2007-10-25 17:15:51 +08003762#ifdef CONFIG_IWL4965_HT
Zhu Yib481de92007-09-25 17:54:57 -07003763
3764/* Parsed Information Elements */
3765struct ieee802_11_elems {
3766 u8 *ds_params;
3767 u8 ds_params_len;
3768 u8 *tim;
3769 u8 tim_len;
3770 u8 *ibss_params;
3771 u8 ibss_params_len;
3772 u8 *erp_info;
3773 u8 erp_info_len;
3774 u8 *ht_cap_param;
3775 u8 ht_cap_param_len;
3776 u8 *ht_extra_param;
3777 u8 ht_extra_param_len;
3778};
3779
3780static int parse_elems(u8 *start, size_t len, struct ieee802_11_elems *elems)
3781{
3782 size_t left = len;
3783 u8 *pos = start;
3784 int unknown = 0;
3785
3786 memset(elems, 0, sizeof(*elems));
3787
3788 while (left >= 2) {
3789 u8 id, elen;
3790
3791 id = *pos++;
3792 elen = *pos++;
3793 left -= 2;
3794
3795 if (elen > left)
3796 return -1;
3797
3798 switch (id) {
3799 case WLAN_EID_DS_PARAMS:
3800 elems->ds_params = pos;
3801 elems->ds_params_len = elen;
3802 break;
3803 case WLAN_EID_TIM:
3804 elems->tim = pos;
3805 elems->tim_len = elen;
3806 break;
3807 case WLAN_EID_IBSS_PARAMS:
3808 elems->ibss_params = pos;
3809 elems->ibss_params_len = elen;
3810 break;
3811 case WLAN_EID_ERP_INFO:
3812 elems->erp_info = pos;
3813 elems->erp_info_len = elen;
3814 break;
3815 case WLAN_EID_HT_CAPABILITY:
3816 elems->ht_cap_param = pos;
3817 elems->ht_cap_param_len = elen;
3818 break;
3819 case WLAN_EID_HT_EXTRA_INFO:
3820 elems->ht_extra_param = pos;
3821 elems->ht_extra_param_len = elen;
3822 break;
3823 default:
3824 unknown++;
3825 break;
3826 }
3827
3828 left -= elen;
3829 pos += elen;
3830 }
3831
3832 return 0;
3833}
Ron Rindjunsky326eeee2007-11-26 16:14:37 +02003834
3835void iwl4965_init_ht_hw_capab(struct ieee80211_ht_info *ht_info, int mode)
3836{
3837 ht_info->cap = 0;
3838 memset(ht_info->supp_mcs_set, 0, 16);
3839
3840 ht_info->ht_supported = 1;
3841
3842 if (mode == MODE_IEEE80211A) {
3843 ht_info->cap |= (u16)IEEE80211_HT_CAP_SUP_WIDTH;
3844 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_40;
3845 ht_info->supp_mcs_set[4] = 0x01;
3846 }
3847 ht_info->cap |= (u16)IEEE80211_HT_CAP_GRN_FLD;
3848 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_20;
3849 ht_info->cap |= (u16)(IEEE80211_HT_CAP_MIMO_PS &
3850 (IWL_MIMO_PS_NONE << 2));
Ron Rindjunsky9ee1ba42007-11-26 16:14:42 +02003851 if (iwl4965_param_amsdu_size_8K) {
3852 printk(KERN_DEBUG "iwl4965 in A-MSDU 8K support mode\n");
3853 ht_info->cap |= (u16)IEEE80211_HT_CAP_MAX_AMSDU;
3854 }
Ron Rindjunsky326eeee2007-11-26 16:14:37 +02003855
3856 ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
3857 ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
3858
3859 ht_info->supp_mcs_set[0] = 0xFF;
3860 ht_info->supp_mcs_set[1] = 0xFF;
3861}
Christoph Hellwigc8b0e6e2007-10-25 17:15:51 +08003862#endif /* CONFIG_IWL4965_HT */
Zhu Yib481de92007-09-25 17:54:57 -07003863
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003864static void iwl4965_sta_modify_ps_wake(struct iwl4965_priv *priv, int sta_id)
Zhu Yib481de92007-09-25 17:54:57 -07003865{
3866 unsigned long flags;
3867
3868 spin_lock_irqsave(&priv->sta_lock, flags);
3869 priv->stations[sta_id].sta.station_flags &= ~STA_FLG_PWR_SAVE_MSK;
3870 priv->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK;
3871 priv->stations[sta_id].sta.sta.modify_mask = 0;
3872 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3873 spin_unlock_irqrestore(&priv->sta_lock, flags);
3874
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003875 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
Zhu Yib481de92007-09-25 17:54:57 -07003876}
3877
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003878static void iwl4965_update_ps_mode(struct iwl4965_priv *priv, u16 ps_bit, u8 *addr)
Zhu Yib481de92007-09-25 17:54:57 -07003879{
3880 /* FIXME: need locking over ps_status ??? */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003881 u8 sta_id = iwl4965_hw_find_station(priv, addr);
Zhu Yib481de92007-09-25 17:54:57 -07003882
3883 if (sta_id != IWL_INVALID_STATION) {
3884 u8 sta_awake = priv->stations[sta_id].
3885 ps_status == STA_PS_STATUS_WAKE;
3886
3887 if (sta_awake && ps_bit)
3888 priv->stations[sta_id].ps_status = STA_PS_STATUS_SLEEP;
3889 else if (!sta_awake && !ps_bit) {
3890 iwl4965_sta_modify_ps_wake(priv, sta_id);
3891 priv->stations[sta_id].ps_status = STA_PS_STATUS_WAKE;
3892 }
3893 }
3894}
3895
Mohamed Abbas7878a5a2007-11-29 11:10:13 +08003896#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
3897
Zhu Yib481de92007-09-25 17:54:57 -07003898/* Called for REPLY_4965_RX (legacy ABG frames), or
3899 * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003900static void iwl4965_rx_reply_rx(struct iwl4965_priv *priv,
3901 struct iwl4965_rx_mem_buffer *rxb)
Zhu Yib481de92007-09-25 17:54:57 -07003902{
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003903 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
Zhu Yib481de92007-09-25 17:54:57 -07003904 /* Use phy data (Rx signal strength, etc.) contained within
3905 * this rx packet for legacy frames,
3906 * or phy data cached from REPLY_RX_PHY_CMD for HT frames. */
3907 int include_phy = (pkt->hdr.cmd == REPLY_4965_RX);
3908 struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
3909 (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) :
3910 (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
3911 __le32 *rx_end;
3912 unsigned int len = 0;
3913 struct ieee80211_hdr *header;
3914 u16 fc;
3915 struct ieee80211_rx_status stats = {
3916 .mactime = le64_to_cpu(rx_start->timestamp),
3917 .channel = le16_to_cpu(rx_start->channel),
3918 .phymode =
3919 (rx_start->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
3920 MODE_IEEE80211G : MODE_IEEE80211A,
3921 .antenna = 0,
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003922 .rate = iwl4965_hw_get_rate(rx_start->rate_n_flags),
Zhu Yib481de92007-09-25 17:54:57 -07003923 .flag = 0,
Zhu Yib481de92007-09-25 17:54:57 -07003924 };
3925 u8 network_packet;
3926
3927 if ((unlikely(rx_start->cfg_phy_cnt > 20))) {
3928 IWL_DEBUG_DROP
3929 ("dsp size out of range [0,20]: "
3930 "%d/n", rx_start->cfg_phy_cnt);
3931 return;
3932 }
3933 if (!include_phy) {
3934 if (priv->last_phy_res[0])
3935 rx_start = (struct iwl4965_rx_phy_res *)
3936 &priv->last_phy_res[1];
3937 else
3938 rx_start = NULL;
3939 }
3940
3941 if (!rx_start) {
3942 IWL_ERROR("MPDU frame without a PHY data\n");
3943 return;
3944 }
3945
3946 if (include_phy) {
3947 header = (struct ieee80211_hdr *)((u8 *) & rx_start[1]
3948 + rx_start->cfg_phy_cnt);
3949
3950 len = le16_to_cpu(rx_start->byte_count);
3951 rx_end = (__le32 *) (pkt->u.raw + rx_start->cfg_phy_cnt +
3952 sizeof(struct iwl4965_rx_phy_res) + len);
3953 } else {
3954 struct iwl4965_rx_mpdu_res_start *amsdu =
3955 (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
3956
3957 header = (void *)(pkt->u.raw +
3958 sizeof(struct iwl4965_rx_mpdu_res_start));
3959 len = le16_to_cpu(amsdu->byte_count);
3960 rx_end = (__le32 *) (pkt->u.raw +
3961 sizeof(struct iwl4965_rx_mpdu_res_start) + len);
3962 }
3963
3964 if (!(*rx_end & RX_RES_STATUS_NO_CRC32_ERROR) ||
3965 !(*rx_end & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
3966 IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n",
3967 le32_to_cpu(*rx_end));
3968 return;
3969 }
3970
3971 priv->ucode_beacon_time = le32_to_cpu(rx_start->beacon_time_stamp);
3972
3973 stats.freq = ieee80211chan2mhz(stats.channel);
3974
3975 /* Find max signal strength (dBm) among 3 antenna/receiver chains */
3976 stats.ssi = iwl4965_calc_rssi(rx_start);
3977
3978 /* Meaningful noise values are available only from beacon statistics,
3979 * which are gathered only when associated, and indicate noise
3980 * only for the associated network channel ...
3981 * Ignore these noise values while scanning (other channels) */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003982 if (iwl4965_is_associated(priv) &&
Zhu Yib481de92007-09-25 17:54:57 -07003983 !test_bit(STATUS_SCANNING, &priv->status)) {
3984 stats.noise = priv->last_rx_noise;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003985 stats.signal = iwl4965_calc_sig_qual(stats.ssi, stats.noise);
Zhu Yib481de92007-09-25 17:54:57 -07003986 } else {
3987 stats.noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003988 stats.signal = iwl4965_calc_sig_qual(stats.ssi, 0);
Zhu Yib481de92007-09-25 17:54:57 -07003989 }
3990
3991 /* Reset beacon noise level if not associated. */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003992 if (!iwl4965_is_associated(priv))
Zhu Yib481de92007-09-25 17:54:57 -07003993 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
3994
Christoph Hellwigc8b0e6e2007-10-25 17:15:51 +08003995#ifdef CONFIG_IWL4965_DEBUG
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003996 /* TODO: Parts of iwl4965_report_frame are broken for 4965 */
3997 if (iwl4965_debug_level & (IWL_DL_RX))
Zhu Yib481de92007-09-25 17:54:57 -07003998 /* Set "1" to report good data frames in groups of 100 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003999 iwl4965_report_frame(priv, pkt, header, 1);
Zhu Yib481de92007-09-25 17:54:57 -07004000
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004001 if (iwl4965_debug_level & (IWL_DL_RX | IWL_DL_STATS))
Zhu Yib481de92007-09-25 17:54:57 -07004002 IWL_DEBUG_RX("Rssi %d, noise %d, qual %d, TSF %lu\n",
4003 stats.ssi, stats.noise, stats.signal,
4004 (long unsigned int)le64_to_cpu(rx_start->timestamp));
4005#endif
4006
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004007 network_packet = iwl4965_is_network_packet(priv, header);
Zhu Yib481de92007-09-25 17:54:57 -07004008 if (network_packet) {
4009 priv->last_rx_rssi = stats.ssi;
4010 priv->last_beacon_time = priv->ucode_beacon_time;
4011 priv->last_tsf = le64_to_cpu(rx_start->timestamp);
4012 }
4013
4014 fc = le16_to_cpu(header->frame_control);
4015 switch (fc & IEEE80211_FCTL_FTYPE) {
4016 case IEEE80211_FTYPE_MGMT:
4017
4018 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
4019 iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
4020 header->addr2);
4021 switch (fc & IEEE80211_FCTL_STYPE) {
4022 case IEEE80211_STYPE_PROBE_RESP:
4023 case IEEE80211_STYPE_BEACON:
4024 if ((priv->iw_mode == IEEE80211_IF_TYPE_STA &&
4025 !compare_ether_addr(header->addr2, priv->bssid)) ||
4026 (priv->iw_mode == IEEE80211_IF_TYPE_IBSS &&
4027 !compare_ether_addr(header->addr3, priv->bssid))) {
4028 struct ieee80211_mgmt *mgmt =
4029 (struct ieee80211_mgmt *)header;
4030 u64 timestamp =
4031 le64_to_cpu(mgmt->u.beacon.timestamp);
4032
4033 priv->timestamp0 = timestamp & 0xFFFFFFFF;
4034 priv->timestamp1 =
4035 (timestamp >> 32) & 0xFFFFFFFF;
4036 priv->beacon_int = le16_to_cpu(
4037 mgmt->u.beacon.beacon_int);
4038 if (priv->call_post_assoc_from_beacon &&
4039 (priv->iw_mode == IEEE80211_IF_TYPE_STA)) {
4040 priv->call_post_assoc_from_beacon = 0;
4041 queue_work(priv->workqueue,
4042 &priv->post_associate.work);
4043 }
4044 }
4045 break;
4046
4047 case IEEE80211_STYPE_ACTION:
4048 break;
4049
4050 /*
Johannes Berg471b3ef2007-12-28 14:32:58 +01004051 * TODO: Use the new callback function from
4052 * mac80211 instead of sniffing these packets.
Zhu Yib481de92007-09-25 17:54:57 -07004053 */
4054 case IEEE80211_STYPE_ASSOC_RESP:
4055 case IEEE80211_STYPE_REASSOC_RESP:
mabbas052c4b92007-10-25 17:15:43 +08004056 if (network_packet) {
Christoph Hellwigc8b0e6e2007-10-25 17:15:51 +08004057#ifdef CONFIG_IWL4965_HT
Zhu Yib481de92007-09-25 17:54:57 -07004058 u8 *pos = NULL;
4059 struct ieee802_11_elems elems;
Christoph Hellwigc8b0e6e2007-10-25 17:15:51 +08004060#endif /*CONFIG_IWL4965_HT */
Zhu Yib481de92007-09-25 17:54:57 -07004061 struct ieee80211_mgmt *mgnt =
4062 (struct ieee80211_mgmt *)header;
4063
Mohamed Abbas7878a5a2007-11-29 11:10:13 +08004064 /* We have just associated, give some
4065 * time for the 4-way handshake if
4066 * any. Don't start scan too early. */
4067 priv->next_scan_jiffies = jiffies +
4068 IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
4069
Zhu Yib481de92007-09-25 17:54:57 -07004070 priv->assoc_id = (~((1 << 15) | (1 << 14))
4071 & le16_to_cpu(mgnt->u.assoc_resp.aid));
4072 priv->assoc_capability =
4073 le16_to_cpu(
4074 mgnt->u.assoc_resp.capab_info);
Christoph Hellwigc8b0e6e2007-10-25 17:15:51 +08004075#ifdef CONFIG_IWL4965_HT
Zhu Yib481de92007-09-25 17:54:57 -07004076 pos = mgnt->u.assoc_resp.variable;
4077 if (!parse_elems(pos,
4078 len - (pos - (u8 *) mgnt),
4079 &elems)) {
4080 if (elems.ht_extra_param &&
4081 elems.ht_cap_param)
4082 break;
4083 }
Christoph Hellwigc8b0e6e2007-10-25 17:15:51 +08004084#endif /*CONFIG_IWL4965_HT */
Zhu Yib481de92007-09-25 17:54:57 -07004085 /* assoc_id is 0 no association */
4086 if (!priv->assoc_id)
4087 break;
4088 if (priv->beacon_int)
4089 queue_work(priv->workqueue,
4090 &priv->post_associate.work);
4091 else
4092 priv->call_post_assoc_from_beacon = 1;
4093 }
4094
4095 break;
4096
4097 case IEEE80211_STYPE_PROBE_REQ:
4098 if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) &&
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004099 !iwl4965_is_associated(priv)) {
Joe Perches0795af52007-10-03 17:59:30 -07004100 DECLARE_MAC_BUF(mac1);
4101 DECLARE_MAC_BUF(mac2);
4102 DECLARE_MAC_BUF(mac3);
4103
Zhu Yib481de92007-09-25 17:54:57 -07004104 IWL_DEBUG_DROP("Dropping (non network): "
Joe Perches0795af52007-10-03 17:59:30 -07004105 "%s, %s, %s\n",
4106 print_mac(mac1, header->addr1),
4107 print_mac(mac2, header->addr2),
4108 print_mac(mac3, header->addr3));
Zhu Yib481de92007-09-25 17:54:57 -07004109 return;
4110 }
4111 }
4112 iwl4965_handle_data_packet(priv, 0, include_phy, rxb, &stats);
4113 break;
4114
4115 case IEEE80211_FTYPE_CTL:
Ron Rindjunsky9ab46172007-12-25 17:00:38 +02004116#ifdef CONFIG_IWL4965_HT
Zhu Yib481de92007-09-25 17:54:57 -07004117 switch (fc & IEEE80211_FCTL_STYPE) {
4118 case IEEE80211_STYPE_BACK_REQ:
4119 IWL_DEBUG_HT("IEEE80211_STYPE_BACK_REQ arrived\n");
4120 iwl4965_handle_data_packet(priv, 0, include_phy,
4121 rxb, &stats);
4122 break;
4123 default:
4124 break;
4125 }
4126#endif
Zhu Yib481de92007-09-25 17:54:57 -07004127 break;
4128
Joe Perches0795af52007-10-03 17:59:30 -07004129 case IEEE80211_FTYPE_DATA: {
4130 DECLARE_MAC_BUF(mac1);
4131 DECLARE_MAC_BUF(mac2);
4132 DECLARE_MAC_BUF(mac3);
4133
Zhu Yib481de92007-09-25 17:54:57 -07004134 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
4135 iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
4136 header->addr2);
4137
4138 if (unlikely(!network_packet))
4139 IWL_DEBUG_DROP("Dropping (non network): "
Joe Perches0795af52007-10-03 17:59:30 -07004140 "%s, %s, %s\n",
4141 print_mac(mac1, header->addr1),
4142 print_mac(mac2, header->addr2),
4143 print_mac(mac3, header->addr3));
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004144 else if (unlikely(iwl4965_is_duplicate_packet(priv, header)))
Joe Perches0795af52007-10-03 17:59:30 -07004145 IWL_DEBUG_DROP("Dropping (dup): %s, %s, %s\n",
4146 print_mac(mac1, header->addr1),
4147 print_mac(mac2, header->addr2),
4148 print_mac(mac3, header->addr3));
Zhu Yib481de92007-09-25 17:54:57 -07004149 else
4150 iwl4965_handle_data_packet(priv, 1, include_phy, rxb,
4151 &stats);
4152 break;
Joe Perches0795af52007-10-03 17:59:30 -07004153 }
Zhu Yib481de92007-09-25 17:54:57 -07004154 default:
4155 break;
4156
4157 }
4158}
4159
4160/* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
4161 * This will be used later in iwl4965_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004162static void iwl4965_rx_reply_rx_phy(struct iwl4965_priv *priv,
4163 struct iwl4965_rx_mem_buffer *rxb)
Zhu Yib481de92007-09-25 17:54:57 -07004164{
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004165 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
Zhu Yib481de92007-09-25 17:54:57 -07004166 priv->last_phy_res[0] = 1;
4167 memcpy(&priv->last_phy_res[1], &(pkt->u.raw[0]),
4168 sizeof(struct iwl4965_rx_phy_res));
4169}
4170
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004171static void iwl4965_rx_missed_beacon_notif(struct iwl4965_priv *priv,
4172 struct iwl4965_rx_mem_buffer *rxb)
Zhu Yib481de92007-09-25 17:54:57 -07004173
4174{
Christoph Hellwigc8b0e6e2007-10-25 17:15:51 +08004175#ifdef CONFIG_IWL4965_SENSITIVITY
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004176 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
4177 struct iwl4965_missed_beacon_notif *missed_beacon;
Zhu Yib481de92007-09-25 17:54:57 -07004178
4179 missed_beacon = &pkt->u.missed_beacon;
4180 if (le32_to_cpu(missed_beacon->consequtive_missed_beacons) > 5) {
4181 IWL_DEBUG_CALIB("missed bcn cnsq %d totl %d rcd %d expctd %d\n",
4182 le32_to_cpu(missed_beacon->consequtive_missed_beacons),
4183 le32_to_cpu(missed_beacon->total_missed_becons),
4184 le32_to_cpu(missed_beacon->num_recvd_beacons),
4185 le32_to_cpu(missed_beacon->num_expected_beacons));
4186 priv->sensitivity_data.state = IWL_SENS_CALIB_NEED_REINIT;
4187 if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)))
4188 queue_work(priv->workqueue, &priv->sensitivity_work);
4189 }
Christoph Hellwigc8b0e6e2007-10-25 17:15:51 +08004190#endif /*CONFIG_IWL4965_SENSITIVITY*/
Zhu Yib481de92007-09-25 17:54:57 -07004191}
4192
Christoph Hellwigc8b0e6e2007-10-25 17:15:51 +08004193#ifdef CONFIG_IWL4965_HT
4194#ifdef CONFIG_IWL4965_HT_AGG
Zhu Yib481de92007-09-25 17:54:57 -07004195
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004196/**
4197 * iwl4965_set_tx_status - Update driver's record of one Tx frame's status
4198 *
4199 * This will get sent to mac80211.
4200 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004201static void iwl4965_set_tx_status(struct iwl4965_priv *priv, int txq_id, int idx,
Zhu Yib481de92007-09-25 17:54:57 -07004202 u32 status, u32 retry_count, u32 rate)
4203{
4204 struct ieee80211_tx_status *tx_status =
4205 &(priv->txq[txq_id].txb[idx].status);
4206
4207 tx_status->flags = status ? IEEE80211_TX_STATUS_ACK : 0;
4208 tx_status->retry_count += retry_count;
4209 tx_status->control.tx_rate = rate;
4210}
4211
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004212#endif/* CONFIG_IWL4965_HT_AGG */
Zhu Yib481de92007-09-25 17:54:57 -07004213
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004214/**
4215 * iwl4965_sta_modify_enable_tid_tx - Enable Tx for this TID in station table
4216 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004217static void iwl4965_sta_modify_enable_tid_tx(struct iwl4965_priv *priv,
Zhu Yib481de92007-09-25 17:54:57 -07004218 int sta_id, int tid)
4219{
4220 unsigned long flags;
4221
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004222 /* Remove "disable" flag, to enable Tx for this TID */
Zhu Yib481de92007-09-25 17:54:57 -07004223 spin_lock_irqsave(&priv->sta_lock, flags);
4224 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_TID_DISABLE_TX;
4225 priv->stations[sta_id].sta.tid_disable_tx &= cpu_to_le16(~(1 << tid));
4226 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
4227 spin_unlock_irqrestore(&priv->sta_lock, flags);
4228
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004229 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
Zhu Yib481de92007-09-25 17:54:57 -07004230}
4231
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004232/**
4233 * iwl4965_tx_status_reply_compressed_ba - Update tx status from block-ack
4234 *
4235 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
4236 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
4237 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004238static int iwl4965_tx_status_reply_compressed_ba(struct iwl4965_priv *priv,
4239 struct iwl4965_ht_agg *agg,
4240 struct iwl4965_compressed_ba_resp*
Zhu Yib481de92007-09-25 17:54:57 -07004241 ba_resp)
4242
4243{
4244 int i, sh, ack;
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004245 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
4246 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
4247 u64 bitmap;
4248 int successes = 0;
4249 struct ieee80211_tx_status *tx_status;
Zhu Yib481de92007-09-25 17:54:57 -07004250
4251 if (unlikely(!agg->wait_for_ba)) {
4252 IWL_ERROR("Received BA when not expected\n");
4253 return -EINVAL;
4254 }
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004255
4256 /* Mark that the expected block-ack response arrived */
Zhu Yib481de92007-09-25 17:54:57 -07004257 agg->wait_for_ba = 0;
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004258 IWL_DEBUG_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004259
4260 /* Calculate shift to align block-ack bits with our Tx window bits */
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004261 sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl>>4);
Ian Schram01ebd062007-10-25 17:15:22 +08004262 if (sh < 0) /* tbw something is wrong with indices */
Zhu Yib481de92007-09-25 17:54:57 -07004263 sh += 0x100;
4264
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004265 /* don't use 64-bit values for now */
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004266 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
Zhu Yib481de92007-09-25 17:54:57 -07004267
4268 if (agg->frame_count > (64 - sh)) {
4269 IWL_DEBUG_TX_REPLY("more frames than bitmap size");
4270 return -1;
4271 }
4272
4273 /* check for success or failure according to the
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004274 * transmitted bitmap and block-ack bitmap */
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004275 bitmap &= agg->bitmap;
Zhu Yib481de92007-09-25 17:54:57 -07004276
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004277 /* For each frame attempted in aggregation,
4278 * update driver's record of tx frame's status. */
Zhu Yib481de92007-09-25 17:54:57 -07004279 for (i = 0; i < agg->frame_count ; i++) {
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004280 ack = bitmap & (1 << i);
4281 successes += !!ack;
Zhu Yib481de92007-09-25 17:54:57 -07004282 IWL_DEBUG_TX_REPLY("%s ON i=%d idx=%d raw=%d\n",
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004283 ack? "ACK":"NACK", i, (agg->start_idx + i) & 0xff,
4284 agg->start_idx + i);
Zhu Yib481de92007-09-25 17:54:57 -07004285 }
4286
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004287 tx_status = &priv->txq[scd_flow].txb[agg->start_idx].status;
4288 tx_status->flags = IEEE80211_TX_STATUS_ACK;
4289 tx_status->retry_count++;
4290#ifdef CONFIG_IWL4965_HT_AGG
4291 tx_status->flags |= IEEE80211_TX_STATUS_AGG_STATS;
4292 tx_status->successes = successes;
4293 tx_status->frame_count = agg->frame_count;
4294#endif /* CONFIG_IWL4965_HT_AGG */
4295 tx_status->control.tx_rate = agg->rate_n_flags;
Zhu Yib481de92007-09-25 17:54:57 -07004296
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004297 IWL_DEBUG_TX_REPLY("Bitmap %llx\n", bitmap);
4298
4299 return 0;
4300}
4301
4302/**
4303 * iwl4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
4304 */
4305static void iwl4965_tx_queue_stop_scheduler(struct iwl4965_priv *priv,
4306 u16 txq_id)
4307{
4308 /* Simply stop the queue, but don't change any configuration;
4309 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
4310 iwl4965_write_prph(priv,
4311 KDR_SCD_QUEUE_STATUS_BITS(txq_id),
4312 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
4313 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
4314}
4315
4316/**
4317 * txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID
4318 */
4319static int iwl4965_tx_queue_agg_disable(struct iwl4965_priv *priv, u16 txq_id,
4320 u16 ssn_idx, u8 tx_fifo)
4321{
4322 if (IWL_BACK_QUEUE_FIRST_ID > txq_id) {
4323 IWL_WARNING("queue number too small: %d, must be > %d\n",
4324 txq_id, IWL_BACK_QUEUE_FIRST_ID);
4325 return -EINVAL;
4326 }
4327
4328 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
4329
4330 iwl4965_clear_bits_prph(priv, KDR_SCD_QUEUECHAIN_SEL, (1 << txq_id));
4331
4332 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
4333 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
4334 /* supposes that ssn_idx is valid (!= 0xFFF) */
4335 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
4336
4337 iwl4965_clear_bits_prph(priv, KDR_SCD_INTERRUPT_MASK, (1 << txq_id));
4338 iwl4965_txq_ctx_deactivate(priv, txq_id);
4339 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
4340
4341 return 0;
4342}
4343
4344int iwl4965_check_empty_hw_queue(struct iwl4965_priv *priv, int sta_id,
4345 u8 tid, int txq_id)
4346{
4347 struct iwl4965_queue *q = &priv->txq[txq_id].q;
4348 u8 *addr = priv->stations[sta_id].sta.sta.addr;
4349 struct iwl4965_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
4350
4351 switch (priv->stations[sta_id].tid[tid].agg.state) {
4352 case IWL_EMPTYING_HW_QUEUE_DELBA:
4353 /* We are reclaiming the last packet of the */
4354 /* aggregated HW queue */
4355 if (txq_id == tid_data->agg.txq_id &&
4356 q->read_ptr == q->write_ptr) {
4357 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
4358 int tx_fifo = default_tid_to_tx_fifo[tid];
4359 IWL_DEBUG_HT("HW queue empty: continue DELBA flow\n");
4360 iwl4965_tx_queue_agg_disable(priv, txq_id,
4361 ssn, tx_fifo);
4362 tid_data->agg.state = IWL_AGG_OFF;
4363 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, addr, tid);
4364 }
4365 break;
4366 case IWL_EMPTYING_HW_QUEUE_ADDBA:
4367 /* We are reclaiming the last packet of the queue */
4368 if (tid_data->tfds_in_queue == 0) {
4369 IWL_DEBUG_HT("HW queue empty: continue ADDBA flow\n");
4370 tid_data->agg.state = IWL_AGG_ON;
4371 ieee80211_start_tx_ba_cb_irqsafe(priv->hw, addr, tid);
4372 }
4373 break;
4374 }
Zhu Yib481de92007-09-25 17:54:57 -07004375 return 0;
4376}
4377
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004378/**
4379 * iwl4965_queue_dec_wrap - Decrement queue index, wrap back to end if needed
4380 * @index -- current index
4381 * @n_bd -- total number of entries in queue (s/b power of 2)
4382 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004383static inline int iwl4965_queue_dec_wrap(int index, int n_bd)
Zhu Yib481de92007-09-25 17:54:57 -07004384{
4385 return (index == 0) ? n_bd - 1 : index - 1;
4386}
4387
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004388/**
4389 * iwl4965_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
4390 *
4391 * Handles block-acknowledge notification from device, which reports success
4392 * of frames sent via aggregation.
4393 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004394static void iwl4965_rx_reply_compressed_ba(struct iwl4965_priv *priv,
4395 struct iwl4965_rx_mem_buffer *rxb)
Zhu Yib481de92007-09-25 17:54:57 -07004396{
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004397 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
4398 struct iwl4965_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
Zhu Yib481de92007-09-25 17:54:57 -07004399 int index;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004400 struct iwl4965_tx_queue *txq = NULL;
4401 struct iwl4965_ht_agg *agg;
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004402 DECLARE_MAC_BUF(mac);
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004403
4404 /* "flow" corresponds to Tx queue */
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004405 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004406
4407 /* "ssn" is start of block-ack Tx window, corresponds to index
4408 * (in Tx queue's circular buffer) of first TFD/frame in window */
Zhu Yib481de92007-09-25 17:54:57 -07004409 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
4410
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004411 if (scd_flow >= ARRAY_SIZE(priv->txq)) {
Zhu Yib481de92007-09-25 17:54:57 -07004412 IWL_ERROR("BUG_ON scd_flow is bigger than number of queues");
4413 return;
4414 }
4415
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004416 txq = &priv->txq[scd_flow];
Zhu Yib481de92007-09-25 17:54:57 -07004417 agg = &priv->stations[ba_resp->sta_id].tid[ba_resp->tid].agg;
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004418
4419 /* Find index just before block-ack window */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004420 index = iwl4965_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
Zhu Yib481de92007-09-25 17:54:57 -07004421
Ian Schram01ebd062007-10-25 17:15:22 +08004422 /* TODO: Need to get this copy more safely - now good for debug */
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004423
Joe Perches0795af52007-10-03 17:59:30 -07004424 IWL_DEBUG_TX_REPLY("REPLY_COMPRESSED_BA [%d]Received from %s, "
4425 "sta_id = %d\n",
Zhu Yib481de92007-09-25 17:54:57 -07004426 agg->wait_for_ba,
Joe Perches0795af52007-10-03 17:59:30 -07004427 print_mac(mac, (u8*) &ba_resp->sta_addr_lo32),
Zhu Yib481de92007-09-25 17:54:57 -07004428 ba_resp->sta_id);
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004429 IWL_DEBUG_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
Zhu Yib481de92007-09-25 17:54:57 -07004430 "%d, scd_ssn = %d\n",
4431 ba_resp->tid,
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004432 ba_resp->seq_ctl,
4433 ba_resp->bitmap,
Zhu Yib481de92007-09-25 17:54:57 -07004434 ba_resp->scd_flow,
4435 ba_resp->scd_ssn);
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004436 IWL_DEBUG_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx \n",
Zhu Yib481de92007-09-25 17:54:57 -07004437 agg->start_idx,
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004438 agg->bitmap);
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004439
4440 /* Update driver's record of ACK vs. not for each frame in window */
Zhu Yib481de92007-09-25 17:54:57 -07004441 iwl4965_tx_status_reply_compressed_ba(priv, agg, ba_resp);
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004442
4443 /* Release all TFDs before the SSN, i.e. all TFDs in front of
4444 * block-ack window (we assume that they've been successfully
4445 * transmitted ... if not, it's too late anyway). */
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004446 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
4447 int freed = iwl4965_tx_queue_reclaim(priv, scd_flow, index);
4448 priv->stations[ba_resp->sta_id].
4449 tid[ba_resp->tid].tfds_in_queue -= freed;
4450 if (iwl4965_queue_space(&txq->q) > txq->q.low_mark &&
4451 priv->mac80211_registered &&
4452 agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)
4453 ieee80211_wake_queue(priv->hw, scd_flow);
4454 iwl4965_check_empty_hw_queue(priv, ba_resp->sta_id,
4455 ba_resp->tid, scd_flow);
4456 }
Zhu Yib481de92007-09-25 17:54:57 -07004457}
4458
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004459/**
4460 * iwl4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
4461 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004462static int iwl4965_tx_queue_set_q2ratid(struct iwl4965_priv *priv, u16 ra_tid,
Zhu Yib481de92007-09-25 17:54:57 -07004463 u16 txq_id)
4464{
4465 u32 tbl_dw_addr;
4466 u32 tbl_dw;
4467 u16 scd_q2ratid;
4468
4469 scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
4470
4471 tbl_dw_addr = priv->scd_base_addr +
4472 SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
4473
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004474 tbl_dw = iwl4965_read_targ_mem(priv, tbl_dw_addr);
Zhu Yib481de92007-09-25 17:54:57 -07004475
4476 if (txq_id & 0x1)
4477 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
4478 else
4479 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
4480
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004481 iwl4965_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
Zhu Yib481de92007-09-25 17:54:57 -07004482
4483 return 0;
4484}
4485
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004486
Zhu Yib481de92007-09-25 17:54:57 -07004487/**
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004488 * iwl4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
4489 *
4490 * NOTE: txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID,
4491 * i.e. it must be one of the higher queues used for aggregation
Zhu Yib481de92007-09-25 17:54:57 -07004492 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004493static int iwl4965_tx_queue_agg_enable(struct iwl4965_priv *priv, int txq_id,
Zhu Yib481de92007-09-25 17:54:57 -07004494 int tx_fifo, int sta_id, int tid,
4495 u16 ssn_idx)
4496{
4497 unsigned long flags;
4498 int rc;
4499 u16 ra_tid;
4500
4501 if (IWL_BACK_QUEUE_FIRST_ID > txq_id)
4502 IWL_WARNING("queue number too small: %d, must be > %d\n",
4503 txq_id, IWL_BACK_QUEUE_FIRST_ID);
4504
4505 ra_tid = BUILD_RAxTID(sta_id, tid);
4506
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004507 /* Modify device's station table to Tx this TID */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004508 iwl4965_sta_modify_enable_tid_tx(priv, sta_id, tid);
Zhu Yib481de92007-09-25 17:54:57 -07004509
4510 spin_lock_irqsave(&priv->lock, flags);
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004511 rc = iwl4965_grab_nic_access(priv);
Zhu Yib481de92007-09-25 17:54:57 -07004512 if (rc) {
4513 spin_unlock_irqrestore(&priv->lock, flags);
4514 return rc;
4515 }
4516
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004517 /* Stop this Tx queue before configuring it */
Zhu Yib481de92007-09-25 17:54:57 -07004518 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
4519
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004520 /* Map receiver-address / traffic-ID to this queue */
Zhu Yib481de92007-09-25 17:54:57 -07004521 iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
4522
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004523 /* Set this queue as a chain-building queue */
Reinette Chatre8a1b0242008-01-14 17:46:25 -08004524 iwl4965_set_bits_prph(priv, KDR_SCD_QUEUECHAIN_SEL, (1 << txq_id));
Zhu Yib481de92007-09-25 17:54:57 -07004525
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004526 /* Place first TFD at index corresponding to start sequence number.
4527 * Assumes that ssn_idx is valid (!= 0xFFF) */
Tomas Winklerfc4b6852007-10-25 17:15:24 +08004528 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
4529 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
Zhu Yib481de92007-09-25 17:54:57 -07004530 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
4531
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004532 /* Set up Tx window size and frame limit for this queue */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004533 iwl4965_write_targ_mem(priv,
Zhu Yib481de92007-09-25 17:54:57 -07004534 priv->scd_base_addr + SCD_CONTEXT_QUEUE_OFFSET(txq_id),
4535 (SCD_WIN_SIZE << SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
4536 SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
4537
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004538 iwl4965_write_targ_mem(priv, priv->scd_base_addr +
Zhu Yib481de92007-09-25 17:54:57 -07004539 SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
4540 (SCD_FRAME_LIMIT << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
4541 & SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
4542
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004543 iwl4965_set_bits_prph(priv, KDR_SCD_INTERRUPT_MASK, (1 << txq_id));
Zhu Yib481de92007-09-25 17:54:57 -07004544
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004545 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
Zhu Yib481de92007-09-25 17:54:57 -07004546 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
4547
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004548 iwl4965_release_nic_access(priv);
Zhu Yib481de92007-09-25 17:54:57 -07004549 spin_unlock_irqrestore(&priv->lock, flags);
4550
4551 return 0;
4552}
4553
Christoph Hellwigc8b0e6e2007-10-25 17:15:51 +08004554#endif /* CONFIG_IWL4965_HT */
Zhu Yib481de92007-09-25 17:54:57 -07004555
4556/**
4557 * iwl4965_add_station - Initialize a station's hardware rate table
4558 *
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004559 * The uCode's station table contains a table of fallback rates
Zhu Yib481de92007-09-25 17:54:57 -07004560 * for automatic fallback during transmission.
4561 *
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004562 * NOTE: This sets up a default set of values. These will be replaced later
4563 * if the driver's iwl-4965-rs rate scaling algorithm is used, instead of
4564 * rc80211_simple.
Zhu Yib481de92007-09-25 17:54:57 -07004565 *
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004566 * NOTE: Run REPLY_ADD_STA command to set up station table entry, before
4567 * calling this function (which runs REPLY_TX_LINK_QUALITY_CMD,
4568 * which requires station table entry to exist).
Zhu Yib481de92007-09-25 17:54:57 -07004569 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004570void iwl4965_add_station(struct iwl4965_priv *priv, const u8 *addr, int is_ap)
Zhu Yib481de92007-09-25 17:54:57 -07004571{
4572 int i, r;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004573 struct iwl4965_link_quality_cmd link_cmd = {
Zhu Yib481de92007-09-25 17:54:57 -07004574 .reserved1 = 0,
4575 };
4576 u16 rate_flags;
4577
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004578 /* Set up the rate scaling to start at selected rate, fall back
4579 * all the way down to 1M in IEEE order, and then spin on 1M */
Zhu Yib481de92007-09-25 17:54:57 -07004580 if (is_ap)
4581 r = IWL_RATE_54M_INDEX;
4582 else if (priv->phymode == MODE_IEEE80211A)
4583 r = IWL_RATE_6M_INDEX;
4584 else
4585 r = IWL_RATE_1M_INDEX;
4586
4587 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
4588 rate_flags = 0;
4589 if (r >= IWL_FIRST_CCK_RATE && r <= IWL_LAST_CCK_RATE)
4590 rate_flags |= RATE_MCS_CCK_MSK;
4591
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004592 /* Use Tx antenna B only */
Zhu Yib481de92007-09-25 17:54:57 -07004593 rate_flags |= RATE_MCS_ANT_B_MSK;
4594 rate_flags &= ~RATE_MCS_ANT_A_MSK;
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004595
Zhu Yib481de92007-09-25 17:54:57 -07004596 link_cmd.rs_table[i].rate_n_flags =
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004597 iwl4965_hw_set_rate_n_flags(iwl4965_rates[r].plcp, rate_flags);
4598 r = iwl4965_get_prev_ieee_rate(r);
Zhu Yib481de92007-09-25 17:54:57 -07004599 }
4600
4601 link_cmd.general_params.single_stream_ant_msk = 2;
4602 link_cmd.general_params.dual_stream_ant_msk = 3;
4603 link_cmd.agg_params.agg_dis_start_th = 3;
4604 link_cmd.agg_params.agg_time_limit = cpu_to_le16(4000);
4605
4606 /* Update the rate scaling for control frame Tx to AP */
4607 link_cmd.sta_id = is_ap ? IWL_AP_ID : IWL4965_BROADCAST_ID;
4608
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004609 iwl4965_send_cmd_pdu(priv, REPLY_TX_LINK_QUALITY_CMD, sizeof(link_cmd),
Zhu Yib481de92007-09-25 17:54:57 -07004610 &link_cmd);
4611}
4612
Christoph Hellwigc8b0e6e2007-10-25 17:15:51 +08004613#ifdef CONFIG_IWL4965_HT
Zhu Yib481de92007-09-25 17:54:57 -07004614
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004615static u8 iwl4965_is_channel_extension(struct iwl4965_priv *priv, int phymode,
Zhu Yib481de92007-09-25 17:54:57 -07004616 u16 channel, u8 extension_chan_offset)
4617{
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004618 const struct iwl4965_channel_info *ch_info;
Zhu Yib481de92007-09-25 17:54:57 -07004619
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004620 ch_info = iwl4965_get_channel_info(priv, phymode, channel);
Zhu Yib481de92007-09-25 17:54:57 -07004621 if (!is_channel_valid(ch_info))
4622 return 0;
4623
4624 if (extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_AUTO)
4625 return 0;
4626
4627 if ((ch_info->fat_extension_channel == extension_chan_offset) ||
4628 (ch_info->fat_extension_channel == HT_IE_EXT_CHANNEL_MAX))
4629 return 1;
4630
4631 return 0;
4632}
4633
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004634static u8 iwl4965_is_fat_tx_allowed(struct iwl4965_priv *priv,
Ron Rindjunskyfd105e72007-11-26 16:14:39 +02004635 struct ieee80211_ht_info *sta_ht_inf)
Zhu Yib481de92007-09-25 17:54:57 -07004636{
Ron Rindjunskyfd105e72007-11-26 16:14:39 +02004637 struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
Zhu Yib481de92007-09-25 17:54:57 -07004638
Ron Rindjunskyfd105e72007-11-26 16:14:39 +02004639 if ((!iwl_ht_conf->is_ht) ||
4640 (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ) ||
4641 (iwl_ht_conf->extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_AUTO))
Zhu Yib481de92007-09-25 17:54:57 -07004642 return 0;
4643
Ron Rindjunskyfd105e72007-11-26 16:14:39 +02004644 if (sta_ht_inf) {
4645 if ((!sta_ht_inf->ht_supported) ||
4646 (!sta_ht_inf->cap & IEEE80211_HT_CAP_SUP_WIDTH))
4647 return 0;
4648 }
Zhu Yib481de92007-09-25 17:54:57 -07004649
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004650 return (iwl4965_is_channel_extension(priv, priv->phymode,
Ron Rindjunskyfd105e72007-11-26 16:14:39 +02004651 iwl_ht_conf->control_channel,
4652 iwl_ht_conf->extension_chan_offset));
Zhu Yib481de92007-09-25 17:54:57 -07004653}
4654
Ron Rindjunskyfd105e72007-11-26 16:14:39 +02004655void iwl4965_set_rxon_ht(struct iwl4965_priv *priv, struct iwl_ht_info *ht_info)
Zhu Yib481de92007-09-25 17:54:57 -07004656{
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004657 struct iwl4965_rxon_cmd *rxon = &priv->staging_rxon;
Zhu Yib481de92007-09-25 17:54:57 -07004658 u32 val;
4659
4660 if (!ht_info->is_ht)
4661 return;
4662
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004663 /* Set up channel bandwidth: 20 MHz only, or 20/40 mixed if fat ok */
Ron Rindjunskyfd105e72007-11-26 16:14:39 +02004664 if (iwl4965_is_fat_tx_allowed(priv, NULL))
Zhu Yib481de92007-09-25 17:54:57 -07004665 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK;
4666 else
4667 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
4668 RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
4669
4670 if (le16_to_cpu(rxon->channel) != ht_info->control_channel) {
4671 IWL_DEBUG_ASSOC("control diff than current %d %d\n",
4672 le16_to_cpu(rxon->channel),
4673 ht_info->control_channel);
4674 rxon->channel = cpu_to_le16(ht_info->control_channel);
4675 return;
4676 }
4677
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004678 /* Note: control channel is opposite of extension channel */
Zhu Yib481de92007-09-25 17:54:57 -07004679 switch (ht_info->extension_chan_offset) {
4680 case IWL_EXT_CHANNEL_OFFSET_ABOVE:
4681 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
4682 break;
4683 case IWL_EXT_CHANNEL_OFFSET_BELOW:
4684 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
4685 break;
4686 case IWL_EXT_CHANNEL_OFFSET_AUTO:
4687 rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
4688 break;
4689 default:
4690 rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
4691 break;
4692 }
4693
Ron Rindjunskyfd105e72007-11-26 16:14:39 +02004694 val = ht_info->ht_protection;
Zhu Yib481de92007-09-25 17:54:57 -07004695
4696 rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS);
4697
Zhu Yib481de92007-09-25 17:54:57 -07004698 iwl4965_set_rxon_chain(priv);
4699
4700 IWL_DEBUG_ASSOC("supported HT rate 0x%X %X "
4701 "rxon flags 0x%X operation mode :0x%X "
4702 "extension channel offset 0x%x "
4703 "control chan %d\n",
Ron Rindjunskyfd105e72007-11-26 16:14:39 +02004704 ht_info->supp_mcs_set[0], ht_info->supp_mcs_set[1],
4705 le32_to_cpu(rxon->flags), ht_info->ht_protection,
Zhu Yib481de92007-09-25 17:54:57 -07004706 ht_info->extension_chan_offset,
4707 ht_info->control_channel);
4708 return;
4709}
4710
Ron Rindjunsky67d62032007-11-26 16:14:40 +02004711void iwl4965_set_ht_add_station(struct iwl4965_priv *priv, u8 index,
4712 struct ieee80211_ht_info *sta_ht_inf)
Zhu Yib481de92007-09-25 17:54:57 -07004713{
4714 __le32 sta_flags;
Tomas Winklere53cfe02008-01-30 22:05:13 -08004715 u8 mimo_ps_mode;
Zhu Yib481de92007-09-25 17:54:57 -07004716
Ron Rindjunsky67d62032007-11-26 16:14:40 +02004717 if (!sta_ht_inf || !sta_ht_inf->ht_supported)
Zhu Yib481de92007-09-25 17:54:57 -07004718 goto done;
4719
Tomas Winklere53cfe02008-01-30 22:05:13 -08004720 mimo_ps_mode = (sta_ht_inf->cap & IEEE80211_HT_CAP_MIMO_PS) >> 2;
4721
Zhu Yib481de92007-09-25 17:54:57 -07004722 sta_flags = priv->stations[index].sta.station_flags;
4723
Tomas Winklere53cfe02008-01-30 22:05:13 -08004724 sta_flags &= ~(STA_FLG_RTS_MIMO_PROT_MSK | STA_FLG_MIMO_DIS_MSK);
4725
4726 switch (mimo_ps_mode) {
4727 case WLAN_HT_CAP_MIMO_PS_STATIC:
4728 sta_flags |= STA_FLG_MIMO_DIS_MSK;
4729 break;
4730 case WLAN_HT_CAP_MIMO_PS_DYNAMIC:
Zhu Yib481de92007-09-25 17:54:57 -07004731 sta_flags |= STA_FLG_RTS_MIMO_PROT_MSK;
Tomas Winklere53cfe02008-01-30 22:05:13 -08004732 break;
4733 case WLAN_HT_CAP_MIMO_PS_DISABLED:
4734 break;
4735 default:
4736 IWL_WARNING("Invalid MIMO PS mode %d", mimo_ps_mode);
4737 break;
4738 }
Zhu Yib481de92007-09-25 17:54:57 -07004739
4740 sta_flags |= cpu_to_le32(
Ron Rindjunsky67d62032007-11-26 16:14:40 +02004741 (u32)sta_ht_inf->ampdu_factor << STA_FLG_MAX_AGG_SIZE_POS);
Zhu Yib481de92007-09-25 17:54:57 -07004742
4743 sta_flags |= cpu_to_le32(
Ron Rindjunsky67d62032007-11-26 16:14:40 +02004744 (u32)sta_ht_inf->ampdu_density << STA_FLG_AGG_MPDU_DENSITY_POS);
Zhu Yib481de92007-09-25 17:54:57 -07004745
Ron Rindjunsky67d62032007-11-26 16:14:40 +02004746 if (iwl4965_is_fat_tx_allowed(priv, sta_ht_inf))
Zhu Yib481de92007-09-25 17:54:57 -07004747 sta_flags |= STA_FLG_FAT_EN_MSK;
Ron Rindjunsky67d62032007-11-26 16:14:40 +02004748 else
Tomas Winklere53cfe02008-01-30 22:05:13 -08004749 sta_flags &= ~STA_FLG_FAT_EN_MSK;
Ron Rindjunsky67d62032007-11-26 16:14:40 +02004750
Zhu Yib481de92007-09-25 17:54:57 -07004751 priv->stations[index].sta.station_flags = sta_flags;
4752 done:
4753 return;
4754}
4755
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004756static void iwl4965_sta_modify_add_ba_tid(struct iwl4965_priv *priv,
Zhu Yib481de92007-09-25 17:54:57 -07004757 int sta_id, int tid, u16 ssn)
4758{
4759 unsigned long flags;
4760
4761 spin_lock_irqsave(&priv->sta_lock, flags);
4762 priv->stations[sta_id].sta.station_flags_msk = 0;
4763 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK;
4764 priv->stations[sta_id].sta.add_immediate_ba_tid = (u8)tid;
4765 priv->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn);
4766 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
4767 spin_unlock_irqrestore(&priv->sta_lock, flags);
4768
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004769 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
Zhu Yib481de92007-09-25 17:54:57 -07004770}
4771
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004772static void iwl4965_sta_modify_del_ba_tid(struct iwl4965_priv *priv,
Zhu Yib481de92007-09-25 17:54:57 -07004773 int sta_id, int tid)
4774{
4775 unsigned long flags;
4776
4777 spin_lock_irqsave(&priv->sta_lock, flags);
4778 priv->stations[sta_id].sta.station_flags_msk = 0;
4779 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
4780 priv->stations[sta_id].sta.remove_immediate_ba_tid = (u8)tid;
4781 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
4782 spin_unlock_irqrestore(&priv->sta_lock, flags);
4783
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004784 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
Zhu Yib481de92007-09-25 17:54:57 -07004785}
4786
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004787/*
4788 * Find first available (lowest unused) Tx Queue, mark it "active".
4789 * Called only when finding queue for aggregation.
4790 * Should never return anything < 7, because they should already
4791 * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
4792 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004793static int iwl4965_txq_ctx_activate_free(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -07004794{
4795 int txq_id;
4796
4797 for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++)
4798 if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
4799 return txq_id;
4800 return -1;
4801}
4802
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004803static int iwl4965_mac_ht_tx_agg_start(struct ieee80211_hw *hw, const u8 *da,
4804 u16 tid, u16 *start_seq_num)
Zhu Yib481de92007-09-25 17:54:57 -07004805{
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004806 struct iwl4965_priv *priv = hw->priv;
Zhu Yib481de92007-09-25 17:54:57 -07004807 int sta_id;
4808 int tx_fifo;
4809 int txq_id;
4810 int ssn = -1;
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004811 int rc = 0;
Zhu Yib481de92007-09-25 17:54:57 -07004812 unsigned long flags;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004813 struct iwl4965_tid_data *tid_data;
Joe Perches0795af52007-10-03 17:59:30 -07004814 DECLARE_MAC_BUF(mac);
Zhu Yib481de92007-09-25 17:54:57 -07004815
4816 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
4817 tx_fifo = default_tid_to_tx_fifo[tid];
4818 else
4819 return -EINVAL;
4820
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004821 IWL_WARNING("%s on da = %s tid = %d\n",
4822 __func__, print_mac(mac, da), tid);
Zhu Yib481de92007-09-25 17:54:57 -07004823
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004824 sta_id = iwl4965_hw_find_station(priv, da);
Zhu Yib481de92007-09-25 17:54:57 -07004825 if (sta_id == IWL_INVALID_STATION)
4826 return -ENXIO;
4827
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004828 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
4829 IWL_ERROR("Start AGG when state is not IWL_AGG_OFF !\n");
4830 return -ENXIO;
4831 }
4832
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004833 txq_id = iwl4965_txq_ctx_activate_free(priv);
Zhu Yib481de92007-09-25 17:54:57 -07004834 if (txq_id == -1)
4835 return -ENXIO;
4836
4837 spin_lock_irqsave(&priv->sta_lock, flags);
4838 tid_data = &priv->stations[sta_id].tid[tid];
4839 ssn = SEQ_TO_SN(tid_data->seq_number);
4840 tid_data->agg.txq_id = txq_id;
4841 spin_unlock_irqrestore(&priv->sta_lock, flags);
4842
4843 *start_seq_num = ssn;
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004844 rc = iwl4965_tx_queue_agg_enable(priv, txq_id, tx_fifo,
Zhu Yib481de92007-09-25 17:54:57 -07004845 sta_id, tid, ssn);
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004846 if (rc)
4847 return rc;
4848
4849 rc = 0;
4850 if (tid_data->tfds_in_queue == 0) {
4851 printk(KERN_ERR "HW queue is empty\n");
4852 tid_data->agg.state = IWL_AGG_ON;
4853 ieee80211_start_tx_ba_cb_irqsafe(hw, da, tid);
4854 } else {
4855 IWL_DEBUG_HT("HW queue is NOT empty: %d packets in HW queue\n",
4856 tid_data->tfds_in_queue);
4857 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
4858 }
4859 return rc;
Zhu Yib481de92007-09-25 17:54:57 -07004860}
4861
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004862static int iwl4965_mac_ht_tx_agg_stop(struct ieee80211_hw *hw, const u8 *da,
4863 u16 tid)
Zhu Yib481de92007-09-25 17:54:57 -07004864{
4865
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004866 struct iwl4965_priv *priv = hw->priv;
Zhu Yib481de92007-09-25 17:54:57 -07004867 int tx_fifo_id, txq_id, sta_id, ssn = -1;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004868 struct iwl4965_tid_data *tid_data;
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004869 int rc, write_ptr, read_ptr;
4870 unsigned long flags;
Joe Perches0795af52007-10-03 17:59:30 -07004871 DECLARE_MAC_BUF(mac);
4872
Zhu Yib481de92007-09-25 17:54:57 -07004873 if (!da) {
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004874 IWL_ERROR("da = NULL\n");
Zhu Yib481de92007-09-25 17:54:57 -07004875 return -EINVAL;
4876 }
4877
4878 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
4879 tx_fifo_id = default_tid_to_tx_fifo[tid];
4880 else
4881 return -EINVAL;
4882
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004883 sta_id = iwl4965_hw_find_station(priv, da);
Zhu Yib481de92007-09-25 17:54:57 -07004884
4885 if (sta_id == IWL_INVALID_STATION)
4886 return -ENXIO;
4887
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004888 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
4889 IWL_WARNING("Stopping AGG while state not IWL_AGG_ON\n");
4890
Zhu Yib481de92007-09-25 17:54:57 -07004891 tid_data = &priv->stations[sta_id].tid[tid];
4892 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
4893 txq_id = tid_data->agg.txq_id;
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004894 write_ptr = priv->txq[txq_id].q.write_ptr;
4895 read_ptr = priv->txq[txq_id].q.read_ptr;
Zhu Yib481de92007-09-25 17:54:57 -07004896
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004897 /* The queue is not empty */
4898 if (write_ptr != read_ptr) {
4899 IWL_DEBUG_HT("Stopping a non empty AGG HW QUEUE\n");
4900 priv->stations[sta_id].tid[tid].agg.state =
4901 IWL_EMPTYING_HW_QUEUE_DELBA;
4902 return 0;
4903 }
4904
4905 IWL_DEBUG_HT("HW queue empty\n");;
4906 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
4907
4908 spin_lock_irqsave(&priv->lock, flags);
4909 rc = iwl4965_grab_nic_access(priv);
4910 if (rc) {
4911 spin_unlock_irqrestore(&priv->lock, flags);
4912 return rc;
4913 }
Zhu Yib481de92007-09-25 17:54:57 -07004914 rc = iwl4965_tx_queue_agg_disable(priv, txq_id, ssn, tx_fifo_id);
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004915 iwl4965_release_nic_access(priv);
4916 spin_unlock_irqrestore(&priv->lock, flags);
4917
Zhu Yib481de92007-09-25 17:54:57 -07004918 if (rc)
4919 return rc;
4920
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004921 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, da, tid);
4922
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004923 IWL_DEBUG_INFO("iwl4965_mac_ht_tx_agg_stop on da=%s tid=%d\n",
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004924 print_mac(mac, da), tid);
Zhu Yib481de92007-09-25 17:54:57 -07004925
4926 return 0;
4927}
4928
Ron Rindjunsky8114fcf2008-01-28 14:07:23 +02004929int iwl4965_mac_ampdu_action(struct ieee80211_hw *hw,
4930 enum ieee80211_ampdu_mlme_action action,
4931 const u8 *addr, u16 tid, u16 *ssn)
4932{
4933 struct iwl4965_priv *priv = hw->priv;
4934 int sta_id;
4935 DECLARE_MAC_BUF(mac);
4936
4937 IWL_DEBUG_HT("A-MPDU action on da=%s tid=%d ",
4938 print_mac(mac, addr), tid);
4939 sta_id = iwl4965_hw_find_station(priv, addr);
4940 switch (action) {
4941 case IEEE80211_AMPDU_RX_START:
4942 IWL_DEBUG_HT("start Rx\n");
4943 iwl4965_sta_modify_add_ba_tid(priv, sta_id, tid, *ssn);
4944 break;
4945 case IEEE80211_AMPDU_RX_STOP:
4946 IWL_DEBUG_HT("stop Rx\n");
4947 iwl4965_sta_modify_del_ba_tid(priv, sta_id, tid);
4948 break;
4949 case IEEE80211_AMPDU_TX_START:
4950 IWL_DEBUG_HT("start Tx\n");
4951 return iwl4965_mac_ht_tx_agg_start(hw, addr, tid, ssn);
4952 case IEEE80211_AMPDU_TX_STOP:
4953 IWL_DEBUG_HT("stop Tx\n");
4954 return iwl4965_mac_ht_tx_agg_stop(hw, addr, tid);
4955 default:
4956 IWL_DEBUG_HT("unknown\n");
4957 return -EINVAL;
4958 break;
4959 }
4960 return 0;
4961}
4962
Christoph Hellwigc8b0e6e2007-10-25 17:15:51 +08004963#endif /* CONFIG_IWL4965_HT */
Zhu Yib481de92007-09-25 17:54:57 -07004964
4965/* Set up 4965-specific Rx frame reply handlers */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004966void iwl4965_hw_rx_handler_setup(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -07004967{
4968 /* Legacy Rx frames */
4969 priv->rx_handlers[REPLY_4965_RX] = iwl4965_rx_reply_rx;
4970
4971 /* High-throughput (HT) Rx frames */
4972 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl4965_rx_reply_rx_phy;
4973 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl4965_rx_reply_rx;
4974
4975 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
4976 iwl4965_rx_missed_beacon_notif;
4977
Christoph Hellwigc8b0e6e2007-10-25 17:15:51 +08004978#ifdef CONFIG_IWL4965_HT
Zhu Yib481de92007-09-25 17:54:57 -07004979 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl4965_rx_reply_compressed_ba;
Christoph Hellwigc8b0e6e2007-10-25 17:15:51 +08004980#endif /* CONFIG_IWL4965_HT */
Zhu Yib481de92007-09-25 17:54:57 -07004981}
4982
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004983void iwl4965_hw_setup_deferred_work(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -07004984{
4985 INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work);
4986 INIT_WORK(&priv->statistics_work, iwl4965_bg_statistics_work);
Christoph Hellwigc8b0e6e2007-10-25 17:15:51 +08004987#ifdef CONFIG_IWL4965_SENSITIVITY
Zhu Yib481de92007-09-25 17:54:57 -07004988 INIT_WORK(&priv->sensitivity_work, iwl4965_bg_sensitivity_work);
4989#endif
Christoph Hellwigc8b0e6e2007-10-25 17:15:51 +08004990#ifdef CONFIG_IWL4965_HT
4991#ifdef CONFIG_IWL4965_HT_AGG
Zhu Yib481de92007-09-25 17:54:57 -07004992 INIT_WORK(&priv->agg_work, iwl4965_bg_agg_work);
Reinette Chatre0054b342007-11-29 11:09:42 +08004993#endif /* CONFIG_IWL4965_HT_AGG */
Christoph Hellwigc8b0e6e2007-10-25 17:15:51 +08004994#endif /* CONFIG_IWL4965_HT */
Zhu Yib481de92007-09-25 17:54:57 -07004995 init_timer(&priv->statistics_periodic);
4996 priv->statistics_periodic.data = (unsigned long)priv;
4997 priv->statistics_periodic.function = iwl4965_bg_statistics_periodic;
4998}
4999
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08005000void iwl4965_hw_cancel_deferred_work(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -07005001{
5002 del_timer_sync(&priv->statistics_periodic);
5003
5004 cancel_delayed_work(&priv->init_alive_start);
5005}
5006
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08005007struct pci_device_id iwl4965_hw_card_ids[] = {
Zhu Yi3567c112007-11-06 22:06:24 -08005008 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4229)},
5009 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4230)},
Zhu Yib481de92007-09-25 17:54:57 -07005010 {0}
5011};
5012
Ben Cahill796083c2007-11-29 11:09:45 +08005013/*
5014 * The device's EEPROM semaphore prevents conflicts between driver and uCode
5015 * when accessing the EEPROM; each access is a series of pulses to/from the
5016 * EEPROM chip, not a single event, so even reads could conflict if they
5017 * weren't arbitrated by the semaphore.
5018 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08005019int iwl4965_eeprom_acquire_semaphore(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -07005020{
5021 u16 count;
5022 int rc;
5023
5024 for (count = 0; count < EEPROM_SEM_RETRY_LIMIT; count++) {
Ben Cahill796083c2007-11-29 11:09:45 +08005025 /* Request semaphore */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08005026 iwl4965_set_bit(priv, CSR_HW_IF_CONFIG_REG,
Zhu Yib481de92007-09-25 17:54:57 -07005027 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
Ben Cahill796083c2007-11-29 11:09:45 +08005028
5029 /* See if we got it */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08005030 rc = iwl4965_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
Zhu Yib481de92007-09-25 17:54:57 -07005031 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
5032 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
5033 EEPROM_SEM_TIMEOUT);
5034 if (rc >= 0) {
Ian Schram91e17472007-10-25 17:15:23 +08005035 IWL_DEBUG_IO("Acquired semaphore after %d tries.\n",
Zhu Yib481de92007-09-25 17:54:57 -07005036 count+1);
5037 return rc;
5038 }
5039 }
5040
5041 return rc;
5042}
5043
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08005044MODULE_DEVICE_TABLE(pci, iwl4965_hw_card_ids);