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Linus Walleij2744e8a2011-05-02 20:50:54 +02001PINCTRL (PIN CONTROL) subsystem
2This document outlines the pin control subsystem in Linux
3
4This subsystem deals with:
5
6- Enumerating and naming controllable pins
7
8- Multiplexing of pins, pads, fingers (etc) see below for details
9
Linus Walleijae6b4d82011-10-19 18:14:33 +020010- Configuration of pins, pads, fingers (etc), such as software-controlled
11 biasing and driving mode specific pins, such as pull-up/down, open drain,
12 load capacitance etc.
Linus Walleij2744e8a2011-05-02 20:50:54 +020013
14Top-level interface
15===================
16
17Definition of PIN CONTROLLER:
18
19- A pin controller is a piece of hardware, usually a set of registers, that
20 can control PINs. It may be able to multiplex, bias, set load capacitance,
21 set drive strength etc for individual pins or groups of pins.
22
23Definition of PIN:
24
25- PINS are equal to pads, fingers, balls or whatever packaging input or
26 output line you want to control and these are denoted by unsigned integers
27 in the range 0..maxpin. This numberspace is local to each PIN CONTROLLER, so
28 there may be several such number spaces in a system. This pin space may
29 be sparse - i.e. there may be gaps in the space with numbers where no
30 pin exists.
31
Linus Walleij336cdba02011-11-10 09:27:41 +010032When a PIN CONTROLLER is instantiated, it will register a descriptor to the
Linus Walleij2744e8a2011-05-02 20:50:54 +020033pin control framework, and this descriptor contains an array of pin descriptors
34describing the pins handled by this specific pin controller.
35
36Here is an example of a PGA (Pin Grid Array) chip seen from underneath:
37
38 A B C D E F G H
39
40 8 o o o o o o o o
41
42 7 o o o o o o o o
43
44 6 o o o o o o o o
45
46 5 o o o o o o o o
47
48 4 o o o o o o o o
49
50 3 o o o o o o o o
51
52 2 o o o o o o o o
53
54 1 o o o o o o o o
55
56To register a pin controller and name all the pins on this package we can do
57this in our driver:
58
59#include <linux/pinctrl/pinctrl.h>
60
Linus Walleij336cdba02011-11-10 09:27:41 +010061const struct pinctrl_pin_desc foo_pins[] = {
62 PINCTRL_PIN(0, "A8"),
63 PINCTRL_PIN(1, "B8"),
64 PINCTRL_PIN(2, "C8"),
Linus Walleij2744e8a2011-05-02 20:50:54 +020065 ...
Linus Walleij336cdba02011-11-10 09:27:41 +010066 PINCTRL_PIN(61, "F1"),
67 PINCTRL_PIN(62, "G1"),
68 PINCTRL_PIN(63, "H1"),
Linus Walleij2744e8a2011-05-02 20:50:54 +020069};
70
71static struct pinctrl_desc foo_desc = {
72 .name = "foo",
73 .pins = foo_pins,
74 .npins = ARRAY_SIZE(foo_pins),
75 .maxpin = 63,
76 .owner = THIS_MODULE,
77};
78
79int __init foo_probe(void)
80{
81 struct pinctrl_dev *pctl;
82
83 pctl = pinctrl_register(&foo_desc, <PARENT>, NULL);
Axel Line2b86b82013-08-18 20:43:33 +080084 if (!pctl)
Linus Walleij2744e8a2011-05-02 20:50:54 +020085 pr_err("could not register foo pin driver\n");
86}
87
Linus Walleijae6b4d82011-10-19 18:14:33 +020088To enable the pinctrl subsystem and the subgroups for PINMUX and PINCONF and
89selected drivers, you need to select them from your machine's Kconfig entry,
90since these are so tightly integrated with the machines they are used on.
91See for example arch/arm/mach-u300/Kconfig for an example.
92
Linus Walleij2744e8a2011-05-02 20:50:54 +020093Pins usually have fancier names than this. You can find these in the dataheet
94for your chip. Notice that the core pinctrl.h file provides a fancy macro
95called PINCTRL_PIN() to create the struct entries. As you can see I enumerated
Linus Walleij336cdba02011-11-10 09:27:41 +010096the pins from 0 in the upper left corner to 63 in the lower right corner.
97This enumeration was arbitrarily chosen, in practice you need to think
Linus Walleij2744e8a2011-05-02 20:50:54 +020098through your numbering system so that it matches the layout of registers
99and such things in your driver, or the code may become complicated. You must
100also consider matching of offsets to the GPIO ranges that may be handled by
101the pin controller.
102
103For a padring with 467 pads, as opposed to actual pins, I used an enumeration
104like this, walking around the edge of the chip, which seems to be industry
105standard too (all these pads had names, too):
106
107
108 0 ..... 104
109 466 105
110 . .
111 . .
112 358 224
113 357 .... 225
114
115
116Pin groups
117==========
118
119Many controllers need to deal with groups of pins, so the pin controller
120subsystem has a mechanism for enumerating groups of pins and retrieving the
121actual enumerated pins that are part of a certain group.
122
123For example, say that we have a group of pins dealing with an SPI interface
124on { 0, 8, 16, 24 }, and a group of pins dealing with an I2C interface on pins
125on { 24, 25 }.
126
127These two groups are presented to the pin control subsystem by implementing
128some generic pinctrl_ops like this:
129
130#include <linux/pinctrl/pinctrl.h>
131
132struct foo_group {
133 const char *name;
134 const unsigned int *pins;
135 const unsigned num_pins;
136};
137
Linus Walleij336cdba02011-11-10 09:27:41 +0100138static const unsigned int spi0_pins[] = { 0, 8, 16, 24 };
139static const unsigned int i2c0_pins[] = { 24, 25 };
Linus Walleij2744e8a2011-05-02 20:50:54 +0200140
141static const struct foo_group foo_groups[] = {
142 {
143 .name = "spi0_grp",
144 .pins = spi0_pins,
145 .num_pins = ARRAY_SIZE(spi0_pins),
146 },
147 {
148 .name = "i2c0_grp",
149 .pins = i2c0_pins,
150 .num_pins = ARRAY_SIZE(i2c0_pins),
151 },
152};
153
154
Viresh Kumard1e90e92012-03-30 11:25:40 +0530155static int foo_get_groups_count(struct pinctrl_dev *pctldev)
Linus Walleij2744e8a2011-05-02 20:50:54 +0200156{
Viresh Kumard1e90e92012-03-30 11:25:40 +0530157 return ARRAY_SIZE(foo_groups);
Linus Walleij2744e8a2011-05-02 20:50:54 +0200158}
159
160static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
161 unsigned selector)
162{
163 return foo_groups[selector].name;
164}
165
166static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
167 unsigned ** const pins,
168 unsigned * const num_pins)
169{
170 *pins = (unsigned *) foo_groups[selector].pins;
171 *num_pins = foo_groups[selector].num_pins;
172 return 0;
173}
174
175static struct pinctrl_ops foo_pctrl_ops = {
Viresh Kumard1e90e92012-03-30 11:25:40 +0530176 .get_groups_count = foo_get_groups_count,
Linus Walleij2744e8a2011-05-02 20:50:54 +0200177 .get_group_name = foo_get_group_name,
178 .get_group_pins = foo_get_group_pins,
179};
180
181
182static struct pinctrl_desc foo_desc = {
183 ...
184 .pctlops = &foo_pctrl_ops,
185};
186
Viresh Kumard1e90e92012-03-30 11:25:40 +0530187The pin control subsystem will call the .get_groups_count() function to
188determine total number of legal selectors, then it will call the other functions
189to retrieve the name and pins of the group. Maintaining the data structure of
190the groups is up to the driver, this is just a simple example - in practice you
191may need more entries in your group structure, for example specific register
192ranges associated with each group and so on.
Linus Walleij2744e8a2011-05-02 20:50:54 +0200193
194
Linus Walleijae6b4d82011-10-19 18:14:33 +0200195Pin configuration
196=================
197
198Pins can sometimes be software-configured in an various ways, mostly related
199to their electronic properties when used as inputs or outputs. For example you
200may be able to make an output pin high impedance, or "tristate" meaning it is
201effectively disconnected. You may be able to connect an input pin to VDD or GND
202using a certain resistor value - pull up and pull down - so that the pin has a
203stable value when nothing is driving the rail it is connected to, or when it's
204unconnected.
205
Linus Walleijad42fc62013-06-24 15:06:19 +0200206Pin configuration can be programmed by adding configuration entries into the
207mapping table; see section "Board/machine configuration" below.
Linus Walleijae6b4d82011-10-19 18:14:33 +0200208
Stephen Warren1e2082b2012-03-02 13:05:48 -0700209The format and meaning of the configuration parameter, PLATFORM_X_PULL_UP
210above, is entirely defined by the pin controller driver.
211
212The pin configuration driver implements callbacks for changing pin
213configuration in the pin controller ops like this:
Linus Walleijae6b4d82011-10-19 18:14:33 +0200214
215#include <linux/pinctrl/pinctrl.h>
216#include <linux/pinctrl/pinconf.h>
217#include "platform_x_pindefs.h"
218
Dong Aishenge6337c32011-12-20 17:51:59 +0800219static int foo_pin_config_get(struct pinctrl_dev *pctldev,
Linus Walleijae6b4d82011-10-19 18:14:33 +0200220 unsigned offset,
221 unsigned long *config)
222{
223 struct my_conftype conf;
224
225 ... Find setting for pin @ offset ...
226
227 *config = (unsigned long) conf;
228}
229
Dong Aishenge6337c32011-12-20 17:51:59 +0800230static int foo_pin_config_set(struct pinctrl_dev *pctldev,
Linus Walleijae6b4d82011-10-19 18:14:33 +0200231 unsigned offset,
232 unsigned long config)
233{
234 struct my_conftype *conf = (struct my_conftype *) config;
235
236 switch (conf) {
237 case PLATFORM_X_PULL_UP:
238 ...
239 }
240 }
241}
242
Dong Aishenge6337c32011-12-20 17:51:59 +0800243static int foo_pin_config_group_get (struct pinctrl_dev *pctldev,
Linus Walleijae6b4d82011-10-19 18:14:33 +0200244 unsigned selector,
245 unsigned long *config)
246{
247 ...
248}
249
Dong Aishenge6337c32011-12-20 17:51:59 +0800250static int foo_pin_config_group_set (struct pinctrl_dev *pctldev,
Linus Walleijae6b4d82011-10-19 18:14:33 +0200251 unsigned selector,
252 unsigned long config)
253{
254 ...
255}
256
257static struct pinconf_ops foo_pconf_ops = {
258 .pin_config_get = foo_pin_config_get,
259 .pin_config_set = foo_pin_config_set,
260 .pin_config_group_get = foo_pin_config_group_get,
261 .pin_config_group_set = foo_pin_config_group_set,
262};
263
264/* Pin config operations are handled by some pin controller */
265static struct pinctrl_desc foo_desc = {
266 ...
267 .confops = &foo_pconf_ops,
268};
269
270Since some controllers have special logic for handling entire groups of pins
271they can exploit the special whole-group pin control function. The
272pin_config_group_set() callback is allowed to return the error code -EAGAIN,
273for groups it does not want to handle, or if it just wants to do some
274group-level handling and then fall through to iterate over all pins, in which
275case each individual pin will be treated by separate pin_config_set() calls as
276well.
277
278
Linus Walleij2744e8a2011-05-02 20:50:54 +0200279Interaction with the GPIO subsystem
280===================================
281
282The GPIO drivers may want to perform operations of various types on the same
283physical pins that are also registered as pin controller pins.
284
Linus Walleijc31a00c2012-09-10 17:22:00 +0200285First and foremost, the two subsystems can be used as completely orthogonal,
286see the section named "pin control requests from drivers" and
287"drivers needing both pin control and GPIOs" below for details. But in some
288situations a cross-subsystem mapping between pins and GPIOs is needed.
289
Linus Walleij2744e8a2011-05-02 20:50:54 +0200290Since the pin controller subsystem have its pinspace local to the pin
291controller we need a mapping so that the pin control subsystem can figure out
292which pin controller handles control of a certain GPIO pin. Since a single
293pin controller may be muxing several GPIO ranges (typically SoCs that have
Anatol Pomozovf884ab12013-05-08 16:56:16 -0700294one set of pins but internally several GPIO silicon blocks, each modelled as
Linus Walleij2744e8a2011-05-02 20:50:54 +0200295a struct gpio_chip) any number of GPIO ranges can be added to a pin controller
296instance like this:
297
298struct gpio_chip chip_a;
299struct gpio_chip chip_b;
300
301static struct pinctrl_gpio_range gpio_range_a = {
302 .name = "chip a",
303 .id = 0,
304 .base = 32,
Chanho Park3c739ad2011-11-11 18:47:58 +0900305 .pin_base = 32,
Linus Walleij2744e8a2011-05-02 20:50:54 +0200306 .npins = 16,
307 .gc = &chip_a;
308};
309
Chanho Park3c739ad2011-11-11 18:47:58 +0900310static struct pinctrl_gpio_range gpio_range_b = {
Linus Walleij2744e8a2011-05-02 20:50:54 +0200311 .name = "chip b",
312 .id = 0,
313 .base = 48,
Chanho Park3c739ad2011-11-11 18:47:58 +0900314 .pin_base = 64,
Linus Walleij2744e8a2011-05-02 20:50:54 +0200315 .npins = 8,
316 .gc = &chip_b;
317};
318
Linus Walleij2744e8a2011-05-02 20:50:54 +0200319{
320 struct pinctrl_dev *pctl;
321 ...
322 pinctrl_add_gpio_range(pctl, &gpio_range_a);
323 pinctrl_add_gpio_range(pctl, &gpio_range_b);
324}
325
326So this complex system has one pin controller handling two different
Chanho Park3c739ad2011-11-11 18:47:58 +0900327GPIO chips. "chip a" has 16 pins and "chip b" has 8 pins. The "chip a" and
328"chip b" have different .pin_base, which means a start pin number of the
329GPIO range.
Linus Walleij2744e8a2011-05-02 20:50:54 +0200330
Chanho Park3c739ad2011-11-11 18:47:58 +0900331The GPIO range of "chip a" starts from the GPIO base of 32 and actual
332pin range also starts from 32. However "chip b" has different starting
333offset for the GPIO range and pin range. The GPIO range of "chip b" starts
334from GPIO number 48, while the pin range of "chip b" starts from 64.
335
336We can convert a gpio number to actual pin number using this "pin_base".
337They are mapped in the global GPIO pin space at:
338
339chip a:
340 - GPIO range : [32 .. 47]
341 - pin range : [32 .. 47]
342chip b:
343 - GPIO range : [48 .. 55]
344 - pin range : [64 .. 71]
Linus Walleij2744e8a2011-05-02 20:50:54 +0200345
Linus Walleij30cf8212013-06-16 12:15:36 +0200346The above examples assume the mapping between the GPIOs and pins is
347linear. If the mapping is sparse or haphazard, an array of arbitrary pin
348numbers can be encoded in the range like this:
349
350static const unsigned range_pins[] = { 14, 1, 22, 17, 10, 8, 6, 2 };
351
352static struct pinctrl_gpio_range gpio_range = {
353 .name = "chip",
354 .id = 0,
355 .base = 32,
356 .pins = &range_pins,
357 .npins = ARRAY_SIZE(range_pins),
358 .gc = &chip;
359};
360
Christian Ruppertfe610522013-10-16 14:56:54 +0200361In this case the pin_base property will be ignored. If the name of a pin
362group is known, the pins and npins elements of the above structure can be
363initialised using the function pinctrl_get_group_pins(), e.g. for pin
364group "foo":
365
366pinctrl_get_group_pins(pctl, "foo", &gpio_range.pins, &gpio_range.npins);
Linus Walleij30cf8212013-06-16 12:15:36 +0200367
Linus Walleij2744e8a2011-05-02 20:50:54 +0200368When GPIO-specific functions in the pin control subsystem are called, these
Linus Walleij336cdba02011-11-10 09:27:41 +0100369ranges will be used to look up the appropriate pin controller by inspecting
Linus Walleij2744e8a2011-05-02 20:50:54 +0200370and matching the pin to the pin ranges across all controllers. When a
371pin controller handling the matching range is found, GPIO-specific functions
372will be called on that specific pin controller.
373
374For all functionalities dealing with pin biasing, pin muxing etc, the pin
Linus Walleij30cf8212013-06-16 12:15:36 +0200375controller subsystem will look up the corresponding pin number from the passed
376in gpio number, and use the range's internals to retrive a pin number. After
377that, the subsystem passes it on to the pin control driver, so the driver
Chanho Park3c739ad2011-11-11 18:47:58 +0900378will get an pin number into its handled number range. Further it is also passed
Linus Walleij2744e8a2011-05-02 20:50:54 +0200379the range ID value, so that the pin controller knows which range it should
380deal with.
381
Shiraz Hashimf23f1512012-10-27 15:21:36 +0530382Calling pinctrl_add_gpio_range from pinctrl driver is DEPRECATED. Please see
383section 2.1 of Documentation/devicetree/bindings/gpio/gpio.txt on how to bind
384pinctrl and gpio drivers.
Linus Walleijc31a00c2012-09-10 17:22:00 +0200385
Linus Walleij30cf8212013-06-16 12:15:36 +0200386
Linus Walleij2744e8a2011-05-02 20:50:54 +0200387PINMUX interfaces
388=================
389
390These calls use the pinmux_* naming prefix. No other calls should use that
391prefix.
392
393
394What is pinmuxing?
395==================
396
397PINMUX, also known as padmux, ballmux, alternate functions or mission modes
398is a way for chip vendors producing some kind of electrical packages to use
399a certain physical pin (ball, pad, finger, etc) for multiple mutually exclusive
400functions, depending on the application. By "application" in this context
401we usually mean a way of soldering or wiring the package into an electronic
402system, even though the framework makes it possible to also change the function
403at runtime.
404
405Here is an example of a PGA (Pin Grid Array) chip seen from underneath:
406
407 A B C D E F G H
408 +---+
409 8 | o | o o o o o o o
410 | |
411 7 | o | o o o o o o o
412 | |
413 6 | o | o o o o o o o
414 +---+---+
415 5 | o | o | o o o o o o
416 +---+---+ +---+
417 4 o o o o o o | o | o
418 | |
419 3 o o o o o o | o | o
420 | |
421 2 o o o o o o | o | o
422 +-------+-------+-------+---+---+
423 1 | o o | o o | o o | o | o |
424 +-------+-------+-------+---+---+
425
426This is not tetris. The game to think of is chess. Not all PGA/BGA packages
427are chessboard-like, big ones have "holes" in some arrangement according to
428different design patterns, but we're using this as a simple example. Of the
429pins you see some will be taken by things like a few VCC and GND to feed power
430to the chip, and quite a few will be taken by large ports like an external
431memory interface. The remaining pins will often be subject to pin multiplexing.
432
433The example 8x8 PGA package above will have pin numbers 0 thru 63 assigned to
434its physical pins. It will name the pins { A1, A2, A3 ... H6, H7, H8 } using
435pinctrl_register_pins() and a suitable data set as shown earlier.
436
437In this 8x8 BGA package the pins { A8, A7, A6, A5 } can be used as an SPI port
438(these are four pins: CLK, RXD, TXD, FRM). In that case, pin B5 can be used as
439some general-purpose GPIO pin. However, in another setting, pins { A5, B5 } can
440be used as an I2C port (these are just two pins: SCL, SDA). Needless to say,
441we cannot use the SPI port and I2C port at the same time. However in the inside
442of the package the silicon performing the SPI logic can alternatively be routed
443out on pins { G4, G3, G2, G1 }.
444
445On the botton row at { A1, B1, C1, D1, E1, F1, G1, H1 } we have something
446special - it's an external MMC bus that can be 2, 4 or 8 bits wide, and it will
447consume 2, 4 or 8 pins respectively, so either { A1, B1 } are taken or
448{ A1, B1, C1, D1 } or all of them. If we use all 8 bits, we cannot use the SPI
449port on pins { G4, G3, G2, G1 } of course.
450
451This way the silicon blocks present inside the chip can be multiplexed "muxed"
452out on different pin ranges. Often contemporary SoC (systems on chip) will
453contain several I2C, SPI, SDIO/MMC, etc silicon blocks that can be routed to
454different pins by pinmux settings.
455
456Since general-purpose I/O pins (GPIO) are typically always in shortage, it is
457common to be able to use almost any pin as a GPIO pin if it is not currently
458in use by some other I/O port.
459
460
461Pinmux conventions
462==================
463
464The purpose of the pinmux functionality in the pin controller subsystem is to
465abstract and provide pinmux settings to the devices you choose to instantiate
466in your machine configuration. It is inspired by the clk, GPIO and regulator
467subsystems, so devices will request their mux setting, but it's also possible
468to request a single pin for e.g. GPIO.
469
470Definitions:
471
472- FUNCTIONS can be switched in and out by a driver residing with the pin
473 control subsystem in the drivers/pinctrl/* directory of the kernel. The
474 pin control driver knows the possible functions. In the example above you can
475 identify three pinmux functions, one for spi, one for i2c and one for mmc.
476
477- FUNCTIONS are assumed to be enumerable from zero in a one-dimensional array.
478 In this case the array could be something like: { spi0, i2c0, mmc0 }
479 for the three available functions.
480
481- FUNCTIONS have PIN GROUPS as defined on the generic level - so a certain
482 function is *always* associated with a certain set of pin groups, could
483 be just a single one, but could also be many. In the example above the
484 function i2c is associated with the pins { A5, B5 }, enumerated as
485 { 24, 25 } in the controller pin space.
486
487 The Function spi is associated with pin groups { A8, A7, A6, A5 }
488 and { G4, G3, G2, G1 }, which are enumerated as { 0, 8, 16, 24 } and
489 { 38, 46, 54, 62 } respectively.
490
491 Group names must be unique per pin controller, no two groups on the same
492 controller may have the same name.
493
494- The combination of a FUNCTION and a PIN GROUP determine a certain function
495 for a certain set of pins. The knowledge of the functions and pin groups
496 and their machine-specific particulars are kept inside the pinmux driver,
497 from the outside only the enumerators are known, and the driver core can:
498
499 - Request the name of a function with a certain selector (>= 0)
500 - A list of groups associated with a certain function
501 - Request that a certain group in that list to be activated for a certain
502 function
503
504 As already described above, pin groups are in turn self-descriptive, so
505 the core will retrieve the actual pin range in a certain group from the
506 driver.
507
508- FUNCTIONS and GROUPS on a certain PIN CONTROLLER are MAPPED to a certain
509 device by the board file, device tree or similar machine setup configuration
510 mechanism, similar to how regulators are connected to devices, usually by
511 name. Defining a pin controller, function and group thus uniquely identify
512 the set of pins to be used by a certain device. (If only one possible group
513 of pins is available for the function, no group name need to be supplied -
514 the core will simply select the first and only group available.)
515
516 In the example case we can define that this particular machine shall
517 use device spi0 with pinmux function fspi0 group gspi0 and i2c0 on function
518 fi2c0 group gi2c0, on the primary pin controller, we get mappings
519 like these:
520
521 {
522 {"map-spi0", spi0, pinctrl0, fspi0, gspi0},
523 {"map-i2c0", i2c0, pinctrl0, fi2c0, gi2c0}
524 }
525
Stephen Warren1681f5a2012-02-22 14:25:58 -0700526 Every map must be assigned a state name, pin controller, device and
527 function. The group is not compulsory - if it is omitted the first group
528 presented by the driver as applicable for the function will be selected,
529 which is useful for simple cases.
Linus Walleij2744e8a2011-05-02 20:50:54 +0200530
531 It is possible to map several groups to the same combination of device,
532 pin controller and function. This is for cases where a certain function on
533 a certain pin controller may use different sets of pins in different
534 configurations.
535
536- PINS for a certain FUNCTION using a certain PIN GROUP on a certain
537 PIN CONTROLLER are provided on a first-come first-serve basis, so if some
538 other device mux setting or GPIO pin request has already taken your physical
539 pin, you will be denied the use of it. To get (activate) a new setting, the
540 old one has to be put (deactivated) first.
541
542Sometimes the documentation and hardware registers will be oriented around
543pads (or "fingers") rather than pins - these are the soldering surfaces on the
544silicon inside the package, and may or may not match the actual number of
545pins/balls underneath the capsule. Pick some enumeration that makes sense to
546you. Define enumerators only for the pins you can control if that makes sense.
547
548Assumptions:
549
Linus Walleij336cdba02011-11-10 09:27:41 +0100550We assume that the number of possible function maps to pin groups is limited by
Linus Walleij2744e8a2011-05-02 20:50:54 +0200551the hardware. I.e. we assume that there is no system where any function can be
552mapped to any pin, like in a phone exchange. So the available pins groups for
553a certain function will be limited to a few choices (say up to eight or so),
554not hundreds or any amount of choices. This is the characteristic we have found
555by inspecting available pinmux hardware, and a necessary assumption since we
556expect pinmux drivers to present *all* possible function vs pin group mappings
557to the subsystem.
558
559
560Pinmux drivers
561==============
562
563The pinmux core takes care of preventing conflicts on pins and calling
564the pin controller driver to execute different settings.
565
566It is the responsibility of the pinmux driver to impose further restrictions
567(say for example infer electronic limitations due to load etc) to determine
568whether or not the requested function can actually be allowed, and in case it
569is possible to perform the requested mux setting, poke the hardware so that
570this happens.
571
572Pinmux drivers are required to supply a few callback functions, some are
573optional. Usually the enable() and disable() functions are implemented,
574writing values into some certain registers to activate a certain mux setting
575for a certain pin.
576
577A simple driver for the above example will work by setting bits 0, 1, 2, 3 or 4
578into some register named MUX to select a certain function with a certain
579group of pins would work something like this:
580
581#include <linux/pinctrl/pinctrl.h>
582#include <linux/pinctrl/pinmux.h>
583
584struct foo_group {
585 const char *name;
586 const unsigned int *pins;
587 const unsigned num_pins;
588};
589
590static const unsigned spi0_0_pins[] = { 0, 8, 16, 24 };
591static const unsigned spi0_1_pins[] = { 38, 46, 54, 62 };
592static const unsigned i2c0_pins[] = { 24, 25 };
593static const unsigned mmc0_1_pins[] = { 56, 57 };
594static const unsigned mmc0_2_pins[] = { 58, 59 };
595static const unsigned mmc0_3_pins[] = { 60, 61, 62, 63 };
596
597static const struct foo_group foo_groups[] = {
598 {
599 .name = "spi0_0_grp",
600 .pins = spi0_0_pins,
601 .num_pins = ARRAY_SIZE(spi0_0_pins),
602 },
603 {
604 .name = "spi0_1_grp",
605 .pins = spi0_1_pins,
606 .num_pins = ARRAY_SIZE(spi0_1_pins),
607 },
608 {
609 .name = "i2c0_grp",
610 .pins = i2c0_pins,
611 .num_pins = ARRAY_SIZE(i2c0_pins),
612 },
613 {
614 .name = "mmc0_1_grp",
615 .pins = mmc0_1_pins,
616 .num_pins = ARRAY_SIZE(mmc0_1_pins),
617 },
618 {
619 .name = "mmc0_2_grp",
620 .pins = mmc0_2_pins,
621 .num_pins = ARRAY_SIZE(mmc0_2_pins),
622 },
623 {
624 .name = "mmc0_3_grp",
625 .pins = mmc0_3_pins,
626 .num_pins = ARRAY_SIZE(mmc0_3_pins),
627 },
628};
629
630
Viresh Kumard1e90e92012-03-30 11:25:40 +0530631static int foo_get_groups_count(struct pinctrl_dev *pctldev)
Linus Walleij2744e8a2011-05-02 20:50:54 +0200632{
Viresh Kumard1e90e92012-03-30 11:25:40 +0530633 return ARRAY_SIZE(foo_groups);
Linus Walleij2744e8a2011-05-02 20:50:54 +0200634}
635
636static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
637 unsigned selector)
638{
639 return foo_groups[selector].name;
640}
641
642static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
643 unsigned ** const pins,
644 unsigned * const num_pins)
645{
646 *pins = (unsigned *) foo_groups[selector].pins;
647 *num_pins = foo_groups[selector].num_pins;
648 return 0;
649}
650
651static struct pinctrl_ops foo_pctrl_ops = {
Viresh Kumard1e90e92012-03-30 11:25:40 +0530652 .get_groups_count = foo_get_groups_count,
Linus Walleij2744e8a2011-05-02 20:50:54 +0200653 .get_group_name = foo_get_group_name,
654 .get_group_pins = foo_get_group_pins,
655};
656
657struct foo_pmx_func {
658 const char *name;
659 const char * const *groups;
660 const unsigned num_groups;
661};
662
Viresh Kumareb181c32012-03-29 11:03:27 +0530663static const char * const spi0_groups[] = { "spi0_0_grp", "spi0_1_grp" };
Linus Walleij2744e8a2011-05-02 20:50:54 +0200664static const char * const i2c0_groups[] = { "i2c0_grp" };
665static const char * const mmc0_groups[] = { "mmc0_1_grp", "mmc0_2_grp",
666 "mmc0_3_grp" };
667
668static const struct foo_pmx_func foo_functions[] = {
669 {
670 .name = "spi0",
671 .groups = spi0_groups,
672 .num_groups = ARRAY_SIZE(spi0_groups),
673 },
674 {
675 .name = "i2c0",
676 .groups = i2c0_groups,
677 .num_groups = ARRAY_SIZE(i2c0_groups),
678 },
679 {
680 .name = "mmc0",
681 .groups = mmc0_groups,
682 .num_groups = ARRAY_SIZE(mmc0_groups),
683 },
684};
685
Viresh Kumard1e90e92012-03-30 11:25:40 +0530686int foo_get_functions_count(struct pinctrl_dev *pctldev)
Linus Walleij2744e8a2011-05-02 20:50:54 +0200687{
Viresh Kumard1e90e92012-03-30 11:25:40 +0530688 return ARRAY_SIZE(foo_functions);
Linus Walleij2744e8a2011-05-02 20:50:54 +0200689}
690
691const char *foo_get_fname(struct pinctrl_dev *pctldev, unsigned selector)
692{
Linus Walleij336cdba02011-11-10 09:27:41 +0100693 return foo_functions[selector].name;
Linus Walleij2744e8a2011-05-02 20:50:54 +0200694}
695
696static int foo_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
697 const char * const **groups,
698 unsigned * const num_groups)
699{
700 *groups = foo_functions[selector].groups;
701 *num_groups = foo_functions[selector].num_groups;
702 return 0;
703}
704
705int foo_enable(struct pinctrl_dev *pctldev, unsigned selector,
706 unsigned group)
707{
Linus Walleij336cdba02011-11-10 09:27:41 +0100708 u8 regbit = (1 << selector + group);
Linus Walleij2744e8a2011-05-02 20:50:54 +0200709
710 writeb((readb(MUX)|regbit), MUX)
711 return 0;
712}
713
Linus Walleij336cdba02011-11-10 09:27:41 +0100714void foo_disable(struct pinctrl_dev *pctldev, unsigned selector,
Linus Walleij2744e8a2011-05-02 20:50:54 +0200715 unsigned group)
716{
Linus Walleij336cdba02011-11-10 09:27:41 +0100717 u8 regbit = (1 << selector + group);
Linus Walleij2744e8a2011-05-02 20:50:54 +0200718
719 writeb((readb(MUX) & ~(regbit)), MUX)
720 return 0;
721}
722
723struct pinmux_ops foo_pmxops = {
Viresh Kumard1e90e92012-03-30 11:25:40 +0530724 .get_functions_count = foo_get_functions_count,
Linus Walleij2744e8a2011-05-02 20:50:54 +0200725 .get_function_name = foo_get_fname,
726 .get_function_groups = foo_get_groups,
727 .enable = foo_enable,
728 .disable = foo_disable,
729};
730
731/* Pinmux operations are handled by some pin controller */
732static struct pinctrl_desc foo_desc = {
733 ...
734 .pctlops = &foo_pctrl_ops,
735 .pmxops = &foo_pmxops,
736};
737
738In the example activating muxing 0 and 1 at the same time setting bits
7390 and 1, uses one pin in common so they would collide.
740
741The beauty of the pinmux subsystem is that since it keeps track of all
742pins and who is using them, it will already have denied an impossible
743request like that, so the driver does not need to worry about such
744things - when it gets a selector passed in, the pinmux subsystem makes
745sure no other device or GPIO assignment is already using the selected
746pins. Thus bits 0 and 1 in the control register will never be set at the
747same time.
748
749All the above functions are mandatory to implement for a pinmux driver.
750
751
Linus Walleije93bcee2012-02-09 07:23:28 +0100752Pin control interaction with the GPIO subsystem
753===============================================
Linus Walleij2744e8a2011-05-02 20:50:54 +0200754
Linus Walleijfdba2d02013-03-15 12:01:20 +0100755Note that the following implies that the use case is to use a certain pin
756from the Linux kernel using the API in <linux/gpio.h> with gpio_request()
757and similar functions. There are cases where you may be using something
758that your datasheet calls "GPIO mode" but actually is just an electrical
759configuration for a certain device. See the section below named
760"GPIO mode pitfalls" for more details on this scenario.
761
Linus Walleije93bcee2012-02-09 07:23:28 +0100762The public pinmux API contains two functions named pinctrl_request_gpio()
763and pinctrl_free_gpio(). These two functions shall *ONLY* be called from
Linus Walleij542e7042011-11-14 10:06:22 +0100764gpiolib-based drivers as part of their gpio_request() and
Linus Walleije93bcee2012-02-09 07:23:28 +0100765gpio_free() semantics. Likewise the pinctrl_gpio_direction_[input|output]
Linus Walleij542e7042011-11-14 10:06:22 +0100766shall only be called from within respective gpio_direction_[input|output]
767gpiolib implementation.
768
769NOTE that platforms and individual drivers shall *NOT* request GPIO pins to be
Linus Walleije93bcee2012-02-09 07:23:28 +0100770controlled e.g. muxed in. Instead, implement a proper gpiolib driver and have
771that driver request proper muxing and other control for its pins.
Linus Walleij542e7042011-11-14 10:06:22 +0100772
Linus Walleij2744e8a2011-05-02 20:50:54 +0200773The function list could become long, especially if you can convert every
774individual pin into a GPIO pin independent of any other pins, and then try
775the approach to define every pin as a function.
776
777In this case, the function array would become 64 entries for each GPIO
778setting and then the device functions.
779
Linus Walleije93bcee2012-02-09 07:23:28 +0100780For this reason there are two functions a pin control driver can implement
Linus Walleij542e7042011-11-14 10:06:22 +0100781to enable only GPIO on an individual pin: .gpio_request_enable() and
782.gpio_disable_free().
Linus Walleij2744e8a2011-05-02 20:50:54 +0200783
784This function will pass in the affected GPIO range identified by the pin
785controller core, so you know which GPIO pins are being affected by the request
786operation.
787
Linus Walleij542e7042011-11-14 10:06:22 +0100788If your driver needs to have an indication from the framework of whether the
789GPIO pin shall be used for input or output you can implement the
790.gpio_set_direction() function. As described this shall be called from the
791gpiolib driver and the affected GPIO range, pin offset and desired direction
792will be passed along to this function.
793
794Alternatively to using these special functions, it is fully allowed to use
Linus Walleije93bcee2012-02-09 07:23:28 +0100795named functions for each GPIO pin, the pinctrl_request_gpio() will attempt to
Linus Walleij542e7042011-11-14 10:06:22 +0100796obtain the function "gpioN" where "N" is the global GPIO pin number if no
797special GPIO-handler is registered.
Linus Walleij2744e8a2011-05-02 20:50:54 +0200798
799
Linus Walleijfdba2d02013-03-15 12:01:20 +0100800GPIO mode pitfalls
801==================
802
Linus Walleijeb6002d2013-06-25 16:17:15 +0200803Due to the naming conventions used by hardware engineers, where "GPIO"
804is taken to mean different things than what the kernel does, the developer
805may be confused by a datasheet talking about a pin being possible to set
806into "GPIO mode". It appears that what hardware engineers mean with
807"GPIO mode" is not necessarily the use case that is implied in the kernel
808interface <linux/gpio.h>: a pin that you grab from kernel code and then
809either listen for input or drive high/low to assert/deassert some
810external line.
Linus Walleijfdba2d02013-03-15 12:01:20 +0100811
812Rather hardware engineers think that "GPIO mode" means that you can
813software-control a few electrical properties of the pin that you would
814not be able to control if the pin was in some other mode, such as muxed in
815for a device.
816
Linus Walleijeb6002d2013-06-25 16:17:15 +0200817The GPIO portions of a pin and its relation to a certain pin controller
818configuration and muxing logic can be constructed in several ways. Here
819are two examples:
820
821(A)
822 pin config
823 logic regs
824 | +- SPI
825 Physical pins --- pad --- pinmux -+- I2C
826 | +- mmc
827 | +- GPIO
828 pin
829 multiplex
830 logic regs
831
832Here some electrical properties of the pin can be configured no matter
833whether the pin is used for GPIO or not. If you multiplex a GPIO onto a
834pin, you can also drive it high/low from "GPIO" registers.
835Alternatively, the pin can be controlled by a certain peripheral, while
836still applying desired pin config properties. GPIO functionality is thus
837orthogonal to any other device using the pin.
838
839In this arrangement the registers for the GPIO portions of the pin controller,
840or the registers for the GPIO hardware module are likely to reside in a
841separate memory range only intended for GPIO driving, and the register
842range dealing with pin config and pin multiplexing get placed into a
843different memory range and a separate section of the data sheet.
844
845(B)
846
847 pin config
848 logic regs
849 | +- SPI
850 Physical pins --- pad --- pinmux -+- I2C
851 | | +- mmc
852 | |
853 GPIO pin
854 multiplex
855 logic regs
856
857In this arrangement, the GPIO functionality can always be enabled, such that
858e.g. a GPIO input can be used to "spy" on the SPI/I2C/MMC signal while it is
859pulsed out. It is likely possible to disrupt the traffic on the pin by doing
860wrong things on the GPIO block, as it is never really disconnected. It is
861possible that the GPIO, pin config and pin multiplex registers are placed into
862the same memory range and the same section of the data sheet, although that
863need not be the case.
864
865From a kernel point of view, however, these are different aspects of the
866hardware and shall be put into different subsystems:
867
868- Registers (or fields within registers) that control electrical
869 properties of the pin such as biasing and drive strength should be
870 exposed through the pinctrl subsystem, as "pin configuration" settings.
871
872- Registers (or fields within registers) that control muxing of signals
873 from various other HW blocks (e.g. I2C, MMC, or GPIO) onto pins should
874 be exposed through the pinctrl subssytem, as mux functions.
875
876- Registers (or fields within registers) that control GPIO functionality
877 such as setting a GPIO's output value, reading a GPIO's input value, or
878 setting GPIO pin direction should be exposed through the GPIO subsystem,
879 and if they also support interrupt capabilities, through the irqchip
880 abstraction.
881
882Depending on the exact HW register design, some functions exposed by the
883GPIO subsystem may call into the pinctrl subsystem in order to
884co-ordinate register settings across HW modules. In particular, this may
885be needed for HW with separate GPIO and pin controller HW modules, where
886e.g. GPIO direction is determined by a register in the pin controller HW
887module rather than the GPIO HW module.
888
889Electrical properties of the pin such as biasing and drive strength
890may be placed at some pin-specific register in all cases or as part
891of the GPIO register in case (B) especially. This doesn't mean that such
892properties necessarily pertain to what the Linux kernel calls "GPIO".
893
Linus Walleijfdba2d02013-03-15 12:01:20 +0100894Example: a pin is usually muxed in to be used as a UART TX line. But during
895system sleep, we need to put this pin into "GPIO mode" and ground it.
896
897If you make a 1-to-1 map to the GPIO subsystem for this pin, you may start
898to think that you need to come up with something real complex, that the
899pin shall be used for UART TX and GPIO at the same time, that you will grab
900a pin control handle and set it to a certain state to enable UART TX to be
901muxed in, then twist it over to GPIO mode and use gpio_direction_output()
902to drive it low during sleep, then mux it over to UART TX again when you
903wake up and maybe even gpio_request/gpio_free as part of this cycle. This
904all gets very complicated.
905
906The solution is to not think that what the datasheet calls "GPIO mode"
907has to be handled by the <linux/gpio.h> interface. Instead view this as
908a certain pin config setting. Look in e.g. <linux/pinctrl/pinconf-generic.h>
909and you find this in the documentation:
910
911 PIN_CONFIG_OUTPUT: this will configure the pin in output, use argument
912 1 to indicate high level, argument 0 to indicate low level.
913
914So it is perfectly possible to push a pin into "GPIO mode" and drive the
915line low as part of the usual pin control map. So for example your UART
916driver may look like this:
917
918#include <linux/pinctrl/consumer.h>
919
920struct pinctrl *pinctrl;
921struct pinctrl_state *pins_default;
922struct pinctrl_state *pins_sleep;
923
924pins_default = pinctrl_lookup_state(uap->pinctrl, PINCTRL_STATE_DEFAULT);
925pins_sleep = pinctrl_lookup_state(uap->pinctrl, PINCTRL_STATE_SLEEP);
926
927/* Normal mode */
928retval = pinctrl_select_state(pinctrl, pins_default);
929/* Sleep mode */
930retval = pinctrl_select_state(pinctrl, pins_sleep);
931
932And your machine configuration may look like this:
933--------------------------------------------------
934
935static unsigned long uart_default_mode[] = {
936 PIN_CONF_PACKED(PIN_CONFIG_DRIVE_PUSH_PULL, 0),
937};
938
939static unsigned long uart_sleep_mode[] = {
940 PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0),
941};
942
Sachin Kamat2868a072013-08-08 10:50:59 +0530943static struct pinctrl_map pinmap[] __initdata = {
Linus Walleijfdba2d02013-03-15 12:01:20 +0100944 PIN_MAP_MUX_GROUP("uart", PINCTRL_STATE_DEFAULT, "pinctrl-foo",
945 "u0_group", "u0"),
946 PIN_MAP_CONFIGS_PIN("uart", PINCTRL_STATE_DEFAULT, "pinctrl-foo",
947 "UART_TX_PIN", uart_default_mode),
948 PIN_MAP_MUX_GROUP("uart", PINCTRL_STATE_SLEEP, "pinctrl-foo",
949 "u0_group", "gpio-mode"),
950 PIN_MAP_CONFIGS_PIN("uart", PINCTRL_STATE_SLEEP, "pinctrl-foo",
951 "UART_TX_PIN", uart_sleep_mode),
952};
953
954foo_init(void) {
955 pinctrl_register_mappings(pinmap, ARRAY_SIZE(pinmap));
956}
957
958Here the pins we want to control are in the "u0_group" and there is some
959function called "u0" that can be enabled on this group of pins, and then
960everything is UART business as usual. But there is also some function
961named "gpio-mode" that can be mapped onto the same pins to move them into
962GPIO mode.
963
964This will give the desired effect without any bogus interaction with the
965GPIO subsystem. It is just an electrical configuration used by that device
966when going to sleep, it might imply that the pin is set into something the
967datasheet calls "GPIO mode" but that is not the point: it is still used
968by that UART device to control the pins that pertain to that very UART
969driver, putting them into modes needed by the UART. GPIO in the Linux
970kernel sense are just some 1-bit line, and is a different use case.
971
972How the registers are poked to attain the push/pull and output low
973configuration and the muxing of the "u0" or "gpio-mode" group onto these
974pins is a question for the driver.
975
976Some datasheets will be more helpful and refer to the "GPIO mode" as
977"low power mode" rather than anything to do with GPIO. This often means
978the same thing electrically speaking, but in this latter case the
979software engineers will usually quickly identify that this is some
980specific muxing/configuration rather than anything related to the GPIO
981API.
982
983
Stephen Warren1e2082b2012-03-02 13:05:48 -0700984Board/machine configuration
Linus Walleij2744e8a2011-05-02 20:50:54 +0200985==================================
986
987Boards and machines define how a certain complete running system is put
988together, including how GPIOs and devices are muxed, how regulators are
989constrained and how the clock tree looks. Of course pinmux settings are also
990part of this.
991
Stephen Warren1e2082b2012-03-02 13:05:48 -0700992A pin controller configuration for a machine looks pretty much like a simple
993regulator configuration, so for the example array above we want to enable i2c
994and spi on the second function mapping:
Linus Walleij2744e8a2011-05-02 20:50:54 +0200995
996#include <linux/pinctrl/machine.h>
997
Uwe Kleine-König122dbe72012-03-30 22:04:51 +0200998static const struct pinctrl_map mapping[] __initconst = {
Linus Walleij2744e8a2011-05-02 20:50:54 +0200999 {
Stephen Warren806d3142012-02-23 17:04:39 -07001000 .dev_name = "foo-spi.0",
Stephen Warren110e4ec2012-03-01 18:48:33 -07001001 .name = PINCTRL_STATE_DEFAULT,
Stephen Warren1e2082b2012-03-02 13:05:48 -07001002 .type = PIN_MAP_TYPE_MUX_GROUP,
Stephen Warren51cd24e2011-12-09 16:59:05 -07001003 .ctrl_dev_name = "pinctrl-foo",
Stephen Warren1e2082b2012-03-02 13:05:48 -07001004 .data.mux.function = "spi0",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001005 },
1006 {
Stephen Warren806d3142012-02-23 17:04:39 -07001007 .dev_name = "foo-i2c.0",
Stephen Warren110e4ec2012-03-01 18:48:33 -07001008 .name = PINCTRL_STATE_DEFAULT,
Stephen Warren1e2082b2012-03-02 13:05:48 -07001009 .type = PIN_MAP_TYPE_MUX_GROUP,
Stephen Warren51cd24e2011-12-09 16:59:05 -07001010 .ctrl_dev_name = "pinctrl-foo",
Stephen Warren1e2082b2012-03-02 13:05:48 -07001011 .data.mux.function = "i2c0",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001012 },
1013 {
Stephen Warren806d3142012-02-23 17:04:39 -07001014 .dev_name = "foo-mmc.0",
Stephen Warren110e4ec2012-03-01 18:48:33 -07001015 .name = PINCTRL_STATE_DEFAULT,
Stephen Warren1e2082b2012-03-02 13:05:48 -07001016 .type = PIN_MAP_TYPE_MUX_GROUP,
Stephen Warren51cd24e2011-12-09 16:59:05 -07001017 .ctrl_dev_name = "pinctrl-foo",
Stephen Warren1e2082b2012-03-02 13:05:48 -07001018 .data.mux.function = "mmc0",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001019 },
1020};
1021
1022The dev_name here matches to the unique device name that can be used to look
1023up the device struct (just like with clockdev or regulators). The function name
1024must match a function provided by the pinmux driver handling this pin range.
1025
1026As you can see we may have several pin controllers on the system and thus
1027we need to specify which one of them that contain the functions we wish
Linus Walleij9dfac4f2012-02-01 18:02:47 +01001028to map.
Linus Walleij2744e8a2011-05-02 20:50:54 +02001029
1030You register this pinmux mapping to the pinmux subsystem by simply:
1031
Linus Walleije93bcee2012-02-09 07:23:28 +01001032 ret = pinctrl_register_mappings(mapping, ARRAY_SIZE(mapping));
Linus Walleij2744e8a2011-05-02 20:50:54 +02001033
1034Since the above construct is pretty common there is a helper macro to make
Stephen Warren51cd24e2011-12-09 16:59:05 -07001035it even more compact which assumes you want to use pinctrl-foo and position
Linus Walleij2744e8a2011-05-02 20:50:54 +020010360 for mapping, for example:
1037
Sachin Kamat2868a072013-08-08 10:50:59 +05301038static struct pinctrl_map mapping[] __initdata = {
Stephen Warren1e2082b2012-03-02 13:05:48 -07001039 PIN_MAP_MUX_GROUP("foo-i2c.o", PINCTRL_STATE_DEFAULT, "pinctrl-foo", NULL, "i2c0"),
1040};
1041
1042The mapping table may also contain pin configuration entries. It's common for
1043each pin/group to have a number of configuration entries that affect it, so
1044the table entries for configuration reference an array of config parameters
1045and values. An example using the convenience macros is shown below:
1046
1047static unsigned long i2c_grp_configs[] = {
1048 FOO_PIN_DRIVEN,
1049 FOO_PIN_PULLUP,
1050};
1051
1052static unsigned long i2c_pin_configs[] = {
1053 FOO_OPEN_COLLECTOR,
1054 FOO_SLEW_RATE_SLOW,
1055};
1056
Sachin Kamat2868a072013-08-08 10:50:59 +05301057static struct pinctrl_map mapping[] __initdata = {
Stephen Warren1e2082b2012-03-02 13:05:48 -07001058 PIN_MAP_MUX_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0", "i2c0"),
Daniel Mackd1a83d32012-08-09 21:02:19 +02001059 PIN_MAP_CONFIGS_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0", i2c_grp_configs),
1060 PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0scl", i2c_pin_configs),
1061 PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0sda", i2c_pin_configs),
Stephen Warren1e2082b2012-03-02 13:05:48 -07001062};
1063
1064Finally, some devices expect the mapping table to contain certain specific
1065named states. When running on hardware that doesn't need any pin controller
1066configuration, the mapping table must still contain those named states, in
1067order to explicitly indicate that the states were provided and intended to
1068be empty. Table entry macro PIN_MAP_DUMMY_STATE serves the purpose of defining
1069a named state without causing any pin controller to be programmed:
1070
Sachin Kamat2868a072013-08-08 10:50:59 +05301071static struct pinctrl_map mapping[] __initdata = {
Stephen Warren1e2082b2012-03-02 13:05:48 -07001072 PIN_MAP_DUMMY_STATE("foo-i2c.0", PINCTRL_STATE_DEFAULT),
Linus Walleij2744e8a2011-05-02 20:50:54 +02001073};
1074
1075
1076Complex mappings
1077================
1078
1079As it is possible to map a function to different groups of pins an optional
1080.group can be specified like this:
1081
1082...
1083{
Stephen Warren806d3142012-02-23 17:04:39 -07001084 .dev_name = "foo-spi.0",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001085 .name = "spi0-pos-A",
Stephen Warren1e2082b2012-03-02 13:05:48 -07001086 .type = PIN_MAP_TYPE_MUX_GROUP,
Stephen Warren51cd24e2011-12-09 16:59:05 -07001087 .ctrl_dev_name = "pinctrl-foo",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001088 .function = "spi0",
1089 .group = "spi0_0_grp",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001090},
1091{
Stephen Warren806d3142012-02-23 17:04:39 -07001092 .dev_name = "foo-spi.0",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001093 .name = "spi0-pos-B",
Stephen Warren1e2082b2012-03-02 13:05:48 -07001094 .type = PIN_MAP_TYPE_MUX_GROUP,
Stephen Warren51cd24e2011-12-09 16:59:05 -07001095 .ctrl_dev_name = "pinctrl-foo",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001096 .function = "spi0",
1097 .group = "spi0_1_grp",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001098},
1099...
1100
1101This example mapping is used to switch between two positions for spi0 at
1102runtime, as described further below under the heading "Runtime pinmuxing".
1103
Stephen Warren6e5e9592012-03-02 13:05:47 -07001104Further it is possible for one named state to affect the muxing of several
1105groups of pins, say for example in the mmc0 example above, where you can
Linus Walleij2744e8a2011-05-02 20:50:54 +02001106additively expand the mmc0 bus from 2 to 4 to 8 pins. If we want to use all
1107three groups for a total of 2+2+4 = 8 pins (for an 8-bit MMC bus as is the
1108case), we define a mapping like this:
1109
1110...
1111{
Stephen Warren806d3142012-02-23 17:04:39 -07001112 .dev_name = "foo-mmc.0",
Uwe Kleine-Königf54367f2012-01-19 22:35:05 +01001113 .name = "2bit"
Stephen Warren1e2082b2012-03-02 13:05:48 -07001114 .type = PIN_MAP_TYPE_MUX_GROUP,
Stephen Warren51cd24e2011-12-09 16:59:05 -07001115 .ctrl_dev_name = "pinctrl-foo",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001116 .function = "mmc0",
Linus Walleij336cdba02011-11-10 09:27:41 +01001117 .group = "mmc0_1_grp",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001118},
1119{
Stephen Warren806d3142012-02-23 17:04:39 -07001120 .dev_name = "foo-mmc.0",
Uwe Kleine-Königf54367f2012-01-19 22:35:05 +01001121 .name = "4bit"
Stephen Warren1e2082b2012-03-02 13:05:48 -07001122 .type = PIN_MAP_TYPE_MUX_GROUP,
Stephen Warren51cd24e2011-12-09 16:59:05 -07001123 .ctrl_dev_name = "pinctrl-foo",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001124 .function = "mmc0",
1125 .group = "mmc0_1_grp",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001126},
1127{
Stephen Warren806d3142012-02-23 17:04:39 -07001128 .dev_name = "foo-mmc.0",
Uwe Kleine-Königf54367f2012-01-19 22:35:05 +01001129 .name = "4bit"
Stephen Warren1e2082b2012-03-02 13:05:48 -07001130 .type = PIN_MAP_TYPE_MUX_GROUP,
Stephen Warren51cd24e2011-12-09 16:59:05 -07001131 .ctrl_dev_name = "pinctrl-foo",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001132 .function = "mmc0",
Linus Walleij336cdba02011-11-10 09:27:41 +01001133 .group = "mmc0_2_grp",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001134},
1135{
Stephen Warren806d3142012-02-23 17:04:39 -07001136 .dev_name = "foo-mmc.0",
Uwe Kleine-Königf54367f2012-01-19 22:35:05 +01001137 .name = "8bit"
Stephen Warren1e2082b2012-03-02 13:05:48 -07001138 .type = PIN_MAP_TYPE_MUX_GROUP,
Stephen Warren51cd24e2011-12-09 16:59:05 -07001139 .ctrl_dev_name = "pinctrl-foo",
Stephen Warren6e5e9592012-03-02 13:05:47 -07001140 .function = "mmc0",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001141 .group = "mmc0_1_grp",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001142},
1143{
Stephen Warren806d3142012-02-23 17:04:39 -07001144 .dev_name = "foo-mmc.0",
Uwe Kleine-Königf54367f2012-01-19 22:35:05 +01001145 .name = "8bit"
Stephen Warren1e2082b2012-03-02 13:05:48 -07001146 .type = PIN_MAP_TYPE_MUX_GROUP,
Stephen Warren51cd24e2011-12-09 16:59:05 -07001147 .ctrl_dev_name = "pinctrl-foo",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001148 .function = "mmc0",
1149 .group = "mmc0_2_grp",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001150},
Linus Walleij336cdba02011-11-10 09:27:41 +01001151{
Stephen Warren806d3142012-02-23 17:04:39 -07001152 .dev_name = "foo-mmc.0",
Uwe Kleine-Königf54367f2012-01-19 22:35:05 +01001153 .name = "8bit"
Stephen Warren1e2082b2012-03-02 13:05:48 -07001154 .type = PIN_MAP_TYPE_MUX_GROUP,
Stephen Warren51cd24e2011-12-09 16:59:05 -07001155 .ctrl_dev_name = "pinctrl-foo",
Linus Walleij336cdba02011-11-10 09:27:41 +01001156 .function = "mmc0",
1157 .group = "mmc0_3_grp",
Linus Walleij336cdba02011-11-10 09:27:41 +01001158},
Linus Walleij2744e8a2011-05-02 20:50:54 +02001159...
1160
1161The result of grabbing this mapping from the device with something like
1162this (see next paragraph):
1163
Stephen Warren6d4ca1f2012-04-16 10:51:00 -06001164 p = devm_pinctrl_get(dev);
Stephen Warren6e5e9592012-03-02 13:05:47 -07001165 s = pinctrl_lookup_state(p, "8bit");
1166 ret = pinctrl_select_state(p, s);
1167
1168or more simply:
1169
Stephen Warren6d4ca1f2012-04-16 10:51:00 -06001170 p = devm_pinctrl_get_select(dev, "8bit");
Linus Walleij2744e8a2011-05-02 20:50:54 +02001171
1172Will be that you activate all the three bottom records in the mapping at
Stephen Warren6e5e9592012-03-02 13:05:47 -07001173once. Since they share the same name, pin controller device, function and
Linus Walleij2744e8a2011-05-02 20:50:54 +02001174device, and since we allow multiple groups to match to a single device, they
1175all get selected, and they all get enabled and disable simultaneously by the
1176pinmux core.
1177
1178
Linus Walleijc31a00c2012-09-10 17:22:00 +02001179Pin control requests from drivers
1180=================================
Linus Walleij2744e8a2011-05-02 20:50:54 +02001181
Linus Walleijab780292013-01-22 10:56:14 -07001182When a device driver is about to probe the device core will automatically
1183attempt to issue pinctrl_get_select_default() on these devices.
1184This way driver writers do not need to add any of the boilerplate code
1185of the type found below. However when doing fine-grained state selection
1186and not using the "default" state, you may have to do some device driver
1187handling of the pinctrl handles and states.
1188
1189So if you just want to put the pins for a certain device into the default
1190state and be done with it, there is nothing you need to do besides
1191providing the proper mapping table. The device core will take care of
1192the rest.
1193
Linus Walleije93bcee2012-02-09 07:23:28 +01001194Generally it is discouraged to let individual drivers get and enable pin
1195control. So if possible, handle the pin control in platform code or some other
1196place where you have access to all the affected struct device * pointers. In
1197some cases where a driver needs to e.g. switch between different mux mappings
1198at runtime this is not possible.
Linus Walleij2744e8a2011-05-02 20:50:54 +02001199
Linus Walleijc31a00c2012-09-10 17:22:00 +02001200A typical case is if a driver needs to switch bias of pins from normal
1201operation and going to sleep, moving from the PINCTRL_STATE_DEFAULT to
1202PINCTRL_STATE_SLEEP at runtime, re-biasing or even re-muxing pins to save
1203current in sleep mode.
1204
Linus Walleije93bcee2012-02-09 07:23:28 +01001205A driver may request a certain control state to be activated, usually just the
1206default state like this:
Linus Walleij2744e8a2011-05-02 20:50:54 +02001207
Linus Walleij28a8d142012-02-09 01:52:22 +01001208#include <linux/pinctrl/consumer.h>
Linus Walleij2744e8a2011-05-02 20:50:54 +02001209
1210struct foo_state {
Linus Walleije93bcee2012-02-09 07:23:28 +01001211 struct pinctrl *p;
Stephen Warren6e5e9592012-03-02 13:05:47 -07001212 struct pinctrl_state *s;
Linus Walleij2744e8a2011-05-02 20:50:54 +02001213 ...
1214};
1215
1216foo_probe()
1217{
Stephen Warren6e5e9592012-03-02 13:05:47 -07001218 /* Allocate a state holder named "foo" etc */
1219 struct foo_state *foo = ...;
Linus Walleij2744e8a2011-05-02 20:50:54 +02001220
Stephen Warren6d4ca1f2012-04-16 10:51:00 -06001221 foo->p = devm_pinctrl_get(&device);
Stephen Warren6e5e9592012-03-02 13:05:47 -07001222 if (IS_ERR(foo->p)) {
1223 /* FIXME: clean up "foo" here */
1224 return PTR_ERR(foo->p);
1225 }
Linus Walleij2744e8a2011-05-02 20:50:54 +02001226
Stephen Warren6e5e9592012-03-02 13:05:47 -07001227 foo->s = pinctrl_lookup_state(foo->p, PINCTRL_STATE_DEFAULT);
1228 if (IS_ERR(foo->s)) {
Stephen Warren6e5e9592012-03-02 13:05:47 -07001229 /* FIXME: clean up "foo" here */
1230 return PTR_ERR(s);
1231 }
1232
1233 ret = pinctrl_select_state(foo->s);
1234 if (ret < 0) {
Stephen Warren6e5e9592012-03-02 13:05:47 -07001235 /* FIXME: clean up "foo" here */
1236 return ret;
1237 }
Linus Walleij2744e8a2011-05-02 20:50:54 +02001238}
1239
Stephen Warren6e5e9592012-03-02 13:05:47 -07001240This get/lookup/select/put sequence can just as well be handled by bus drivers
Linus Walleij2744e8a2011-05-02 20:50:54 +02001241if you don't want each and every driver to handle it and you know the
1242arrangement on your bus.
1243
Stephen Warren6e5e9592012-03-02 13:05:47 -07001244The semantics of the pinctrl APIs are:
Linus Walleij2744e8a2011-05-02 20:50:54 +02001245
Stephen Warren6e5e9592012-03-02 13:05:47 -07001246- pinctrl_get() is called in process context to obtain a handle to all pinctrl
1247 information for a given client device. It will allocate a struct from the
1248 kernel memory to hold the pinmux state. All mapping table parsing or similar
1249 slow operations take place within this API.
Linus Walleij2744e8a2011-05-02 20:50:54 +02001250
Stephen Warren6d4ca1f2012-04-16 10:51:00 -06001251- devm_pinctrl_get() is a variant of pinctrl_get() that causes pinctrl_put()
1252 to be called automatically on the retrieved pointer when the associated
1253 device is removed. It is recommended to use this function over plain
1254 pinctrl_get().
1255
Stephen Warren6e5e9592012-03-02 13:05:47 -07001256- pinctrl_lookup_state() is called in process context to obtain a handle to a
1257 specific state for a the client device. This operation may be slow too.
Linus Walleij2744e8a2011-05-02 20:50:54 +02001258
Stephen Warren6e5e9592012-03-02 13:05:47 -07001259- pinctrl_select_state() programs pin controller hardware according to the
1260 definition of the state as given by the mapping table. In theory this is a
1261 fast-path operation, since it only involved blasting some register settings
1262 into hardware. However, note that some pin controllers may have their
1263 registers on a slow/IRQ-based bus, so client devices should not assume they
1264 can call pinctrl_select_state() from non-blocking contexts.
1265
1266- pinctrl_put() frees all information associated with a pinctrl handle.
Linus Walleij2744e8a2011-05-02 20:50:54 +02001267
Stephen Warren6d4ca1f2012-04-16 10:51:00 -06001268- devm_pinctrl_put() is a variant of pinctrl_put() that may be used to
1269 explicitly destroy a pinctrl object returned by devm_pinctrl_get().
1270 However, use of this function will be rare, due to the automatic cleanup
1271 that will occur even without calling it.
1272
1273 pinctrl_get() must be paired with a plain pinctrl_put().
1274 pinctrl_get() may not be paired with devm_pinctrl_put().
1275 devm_pinctrl_get() can optionally be paired with devm_pinctrl_put().
1276 devm_pinctrl_get() may not be paired with plain pinctrl_put().
1277
Linus Walleije93bcee2012-02-09 07:23:28 +01001278Usually the pin control core handled the get/put pair and call out to the
1279device drivers bookkeeping operations, like checking available functions and
1280the associated pins, whereas the enable/disable pass on to the pin controller
Linus Walleij2744e8a2011-05-02 20:50:54 +02001281driver which takes care of activating and/or deactivating the mux setting by
1282quickly poking some registers.
1283
Stephen Warren6d4ca1f2012-04-16 10:51:00 -06001284The pins are allocated for your device when you issue the devm_pinctrl_get()
1285call, after this you should be able to see this in the debugfs listing of all
1286pins.
Linus Walleij2744e8a2011-05-02 20:50:54 +02001287
Linus Walleijc05127c2012-04-10 10:00:38 +02001288NOTE: the pinctrl system will return -EPROBE_DEFER if it cannot find the
1289requested pinctrl handles, for example if the pinctrl driver has not yet
1290registered. Thus make sure that the error path in your driver gracefully
1291cleans up and is ready to retry the probing later in the startup process.
1292
Linus Walleij2744e8a2011-05-02 20:50:54 +02001293
Linus Walleijc31a00c2012-09-10 17:22:00 +02001294Drivers needing both pin control and GPIOs
1295==========================================
1296
1297Again, it is discouraged to let drivers lookup and select pin control states
1298themselves, but again sometimes this is unavoidable.
1299
1300So say that your driver is fetching its resources like this:
1301
1302#include <linux/pinctrl/consumer.h>
1303#include <linux/gpio.h>
1304
1305struct pinctrl *pinctrl;
1306int gpio;
1307
1308pinctrl = devm_pinctrl_get_select_default(&dev);
1309gpio = devm_gpio_request(&dev, 14, "foo");
1310
1311Here we first request a certain pin state and then request GPIO 14 to be
1312used. If you're using the subsystems orthogonally like this, you should
1313nominally always get your pinctrl handle and select the desired pinctrl
1314state BEFORE requesting the GPIO. This is a semantic convention to avoid
1315situations that can be electrically unpleasant, you will certainly want to
1316mux in and bias pins in a certain way before the GPIO subsystems starts to
1317deal with them.
1318
Linus Walleijab780292013-01-22 10:56:14 -07001319The above can be hidden: using the device core, the pinctrl core may be
1320setting up the config and muxing for the pins right before the device is
1321probing, nevertheless orthogonal to the GPIO subsystem.
Linus Walleijc31a00c2012-09-10 17:22:00 +02001322
1323But there are also situations where it makes sense for the GPIO subsystem
James Hogan7bbc87b2013-05-28 10:31:48 +01001324to communicate directly with the pinctrl subsystem, using the latter as a
1325back-end. This is when the GPIO driver may call out to the functions
Linus Walleijc31a00c2012-09-10 17:22:00 +02001326described in the section "Pin control interaction with the GPIO subsystem"
1327above. This only involves per-pin multiplexing, and will be completely
1328hidden behind the gpio_*() function namespace. In this case, the driver
1329need not interact with the pin control subsystem at all.
1330
1331If a pin control driver and a GPIO driver is dealing with the same pins
1332and the use cases involve multiplexing, you MUST implement the pin controller
1333as a back-end for the GPIO driver like this, unless your hardware design
1334is such that the GPIO controller can override the pin controller's
1335multiplexing state through hardware without the need to interact with the
1336pin control system.
1337
1338
Linus Walleije93bcee2012-02-09 07:23:28 +01001339System pin control hogging
1340==========================
Linus Walleij2744e8a2011-05-02 20:50:54 +02001341
Stephen Warren1681f5a2012-02-22 14:25:58 -07001342Pin control map entries can be hogged by the core when the pin controller
Stephen Warren6e5e9592012-03-02 13:05:47 -07001343is registered. This means that the core will attempt to call pinctrl_get(),
1344lookup_state() and select_state() on it immediately after the pin control
1345device has been registered.
Linus Walleij2744e8a2011-05-02 20:50:54 +02001346
Stephen Warren6e5e9592012-03-02 13:05:47 -07001347This occurs for mapping table entries where the client device name is equal
1348to the pin controller device name, and the state name is PINCTRL_STATE_DEFAULT.
Linus Walleij2744e8a2011-05-02 20:50:54 +02001349
1350{
Stephen Warren806d3142012-02-23 17:04:39 -07001351 .dev_name = "pinctrl-foo",
Stephen Warren46919ae2012-03-01 18:48:32 -07001352 .name = PINCTRL_STATE_DEFAULT,
Stephen Warren1e2082b2012-03-02 13:05:48 -07001353 .type = PIN_MAP_TYPE_MUX_GROUP,
Stephen Warren51cd24e2011-12-09 16:59:05 -07001354 .ctrl_dev_name = "pinctrl-foo",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001355 .function = "power_func",
Linus Walleij2744e8a2011-05-02 20:50:54 +02001356},
1357
1358Since it may be common to request the core to hog a few always-applicable
1359mux settings on the primary pin controller, there is a convenience macro for
1360this:
1361
Stephen Warren1e2082b2012-03-02 13:05:48 -07001362PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-foo", NULL /* group */, "power_func")
Linus Walleij2744e8a2011-05-02 20:50:54 +02001363
1364This gives the exact same result as the above construction.
1365
1366
1367Runtime pinmuxing
1368=================
1369
1370It is possible to mux a certain function in and out at runtime, say to move
1371an SPI port from one set of pins to another set of pins. Say for example for
1372spi0 in the example above, we expose two different groups of pins for the same
1373function, but with different named in the mapping as described under
Stephen Warren6e5e9592012-03-02 13:05:47 -07001374"Advanced mapping" above. So that for an SPI device, we have two states named
1375"pos-A" and "pos-B".
Linus Walleij2744e8a2011-05-02 20:50:54 +02001376
1377This snippet first muxes the function in the pins defined by group A, enables
1378it, disables and releases it, and muxes it in on the pins defined by group B:
1379
Linus Walleij28a8d142012-02-09 01:52:22 +01001380#include <linux/pinctrl/consumer.h>
1381
Stephen Warren6d4ca1f2012-04-16 10:51:00 -06001382struct pinctrl *p;
1383struct pinctrl_state *s1, *s2;
Stephen Warren6e5e9592012-03-02 13:05:47 -07001384
Stephen Warren6d4ca1f2012-04-16 10:51:00 -06001385foo_probe()
1386{
Stephen Warren6e5e9592012-03-02 13:05:47 -07001387 /* Setup */
Stephen Warren6d4ca1f2012-04-16 10:51:00 -06001388 p = devm_pinctrl_get(&device);
Stephen Warren6e5e9592012-03-02 13:05:47 -07001389 if (IS_ERR(p))
1390 ...
1391
1392 s1 = pinctrl_lookup_state(foo->p, "pos-A");
1393 if (IS_ERR(s1))
1394 ...
1395
1396 s2 = pinctrl_lookup_state(foo->p, "pos-B");
1397 if (IS_ERR(s2))
1398 ...
Stephen Warren6d4ca1f2012-04-16 10:51:00 -06001399}
Linus Walleij2744e8a2011-05-02 20:50:54 +02001400
Stephen Warren6d4ca1f2012-04-16 10:51:00 -06001401foo_switch()
1402{
Linus Walleij2744e8a2011-05-02 20:50:54 +02001403 /* Enable on position A */
Stephen Warren6e5e9592012-03-02 13:05:47 -07001404 ret = pinctrl_select_state(s1);
1405 if (ret < 0)
1406 ...
Linus Walleij2744e8a2011-05-02 20:50:54 +02001407
Stephen Warren6e5e9592012-03-02 13:05:47 -07001408 ...
Linus Walleij2744e8a2011-05-02 20:50:54 +02001409
1410 /* Enable on position B */
Stephen Warren6e5e9592012-03-02 13:05:47 -07001411 ret = pinctrl_select_state(s2);
1412 if (ret < 0)
1413 ...
1414
Linus Walleij2744e8a2011-05-02 20:50:54 +02001415 ...
Linus Walleij2744e8a2011-05-02 20:50:54 +02001416}
1417
Linus Walleij1a789582012-10-17 20:51:54 +02001418The above has to be done from process context. The reservation of the pins
1419will be done when the state is activated, so in effect one specific pin
1420can be used by different functions at different times on a running system.