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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* $Id: tg3.h,v 1.37.2.32 2002/03/11 12:18:18 davem Exp $
2 * tg3.h: Definitions for Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 */
8
9#ifndef _T3_H
10#define _T3_H
11
12#define TG3_64BIT_REG_HIGH 0x00UL
13#define TG3_64BIT_REG_LOW 0x04UL
14
15/* Descriptor block info. */
16#define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */
17#define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */
18#define BDINFO_FLAGS_USE_EXT_RECV 0x00000001 /* ext rx_buffer_desc */
19#define BDINFO_FLAGS_DISABLED 0x00000002
20#define BDINFO_FLAGS_MAXLEN_MASK 0xffff0000
21#define BDINFO_FLAGS_MAXLEN_SHIFT 16
22#define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */
23#define TG3_BDINFO_SIZE 0x10UL
24
25#define RX_COPY_THRESHOLD 256
26
Michael Chanb5d37722006-09-27 16:06:21 -070027#define TG3_RX_INTERNAL_RING_SZ_5906 32
28
Linus Torvalds1da177e2005-04-16 15:20:36 -070029#define RX_STD_MAX_SIZE 1536
30#define RX_STD_MAX_SIZE_5705 512
31#define RX_JUMBO_MAX_SIZE 0xdeadbeef /* XXX */
32
33/* First 256 bytes are a mirror of PCI config space. */
34#define TG3PCI_VENDOR 0x00000000
35#define TG3PCI_VENDOR_BROADCOM 0x14e4
36#define TG3PCI_DEVICE 0x00000002
37#define TG3PCI_DEVICE_TIGON3_1 0x1644 /* BCM5700 */
38#define TG3PCI_DEVICE_TIGON3_2 0x1645 /* BCM5701 */
39#define TG3PCI_DEVICE_TIGON3_3 0x1646 /* BCM5702 */
40#define TG3PCI_DEVICE_TIGON3_4 0x1647 /* BCM5703 */
Matt Carlsonc88e6682008-11-03 16:49:18 -080041#define TG3PCI_DEVICE_TIGON3_5761S 0x1688
42#define TG3PCI_DEVICE_TIGON3_5761SE 0x1689
Matt Carlson321d32a2008-11-21 17:22:19 -080043#define TG3PCI_DEVICE_TIGON3_57780 0x1692
44#define TG3PCI_DEVICE_TIGON3_57760 0x1690
45#define TG3PCI_DEVICE_TIGON3_57790 0x1694
46#define TG3PCI_DEVICE_TIGON3_57720 0x168c
Matt Carlsonaa10f272008-12-21 20:21:18 -080047/* 0x04 --> 0x64 unused */
Linus Torvalds1da177e2005-04-16 15:20:36 -070048#define TG3PCI_MSI_DATA 0x00000064
49/* 0x66 --> 0x68 unused */
50#define TG3PCI_MISC_HOST_CTRL 0x00000068
51#define MISC_HOST_CTRL_CLEAR_INT 0x00000001
52#define MISC_HOST_CTRL_MASK_PCI_INT 0x00000002
53#define MISC_HOST_CTRL_BYTE_SWAP 0x00000004
54#define MISC_HOST_CTRL_WORD_SWAP 0x00000008
55#define MISC_HOST_CTRL_PCISTATE_RW 0x00000010
56#define MISC_HOST_CTRL_CLKREG_RW 0x00000020
57#define MISC_HOST_CTRL_REGWORD_SWAP 0x00000040
58#define MISC_HOST_CTRL_INDIR_ACCESS 0x00000080
59#define MISC_HOST_CTRL_IRQ_MASK_MODE 0x00000100
60#define MISC_HOST_CTRL_TAGGED_STATUS 0x00000200
61#define MISC_HOST_CTRL_CHIPREV 0xffff0000
62#define MISC_HOST_CTRL_CHIPREV_SHIFT 16
63#define GET_CHIP_REV_ID(MISC_HOST_CTRL) \
64 (((MISC_HOST_CTRL) & MISC_HOST_CTRL_CHIPREV) >> \
65 MISC_HOST_CTRL_CHIPREV_SHIFT)
66#define CHIPREV_ID_5700_A0 0x7000
67#define CHIPREV_ID_5700_A1 0x7001
68#define CHIPREV_ID_5700_B0 0x7100
69#define CHIPREV_ID_5700_B1 0x7101
70#define CHIPREV_ID_5700_B3 0x7102
71#define CHIPREV_ID_5700_ALTIMA 0x7104
72#define CHIPREV_ID_5700_C0 0x7200
73#define CHIPREV_ID_5701_A0 0x0000
74#define CHIPREV_ID_5701_B0 0x0100
75#define CHIPREV_ID_5701_B2 0x0102
76#define CHIPREV_ID_5701_B5 0x0105
77#define CHIPREV_ID_5703_A0 0x1000
78#define CHIPREV_ID_5703_A1 0x1001
79#define CHIPREV_ID_5703_A2 0x1002
80#define CHIPREV_ID_5703_A3 0x1003
81#define CHIPREV_ID_5704_A0 0x2000
82#define CHIPREV_ID_5704_A1 0x2001
83#define CHIPREV_ID_5704_A2 0x2002
84#define CHIPREV_ID_5704_A3 0x2003
85#define CHIPREV_ID_5705_A0 0x3000
86#define CHIPREV_ID_5705_A1 0x3001
87#define CHIPREV_ID_5705_A2 0x3002
88#define CHIPREV_ID_5705_A3 0x3003
89#define CHIPREV_ID_5750_A0 0x4000
90#define CHIPREV_ID_5750_A1 0x4001
91#define CHIPREV_ID_5750_A3 0x4003
Michael Chan52c0fd82006-06-29 20:15:54 -070092#define CHIPREV_ID_5750_C2 0x4202
Michael Chanff645be2005-04-21 17:09:53 -070093#define CHIPREV_ID_5752_A0_HW 0x5000
94#define CHIPREV_ID_5752_A0 0x6000
John W. Linville053d7802005-04-21 17:03:52 -070095#define CHIPREV_ID_5752_A1 0x6001
Michael Chan7544b092007-05-05 13:08:32 -070096#define CHIPREV_ID_5714_A2 0x9002
Michael Chanb5d37722006-09-27 16:06:21 -070097#define CHIPREV_ID_5906_A1 0xc001
Linus Torvalds1da177e2005-04-16 15:20:36 -070098#define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12)
99#define ASIC_REV_5700 0x07
100#define ASIC_REV_5701 0x00
101#define ASIC_REV_5703 0x01
102#define ASIC_REV_5704 0x02
103#define ASIC_REV_5705 0x03
104#define ASIC_REV_5750 0x04
Michael Chanff645be2005-04-21 17:09:53 -0700105#define ASIC_REV_5752 0x06
Michael Chan4cf78e42005-07-25 12:29:19 -0700106#define ASIC_REV_5780 0x08
Michael Chana4e2b342005-10-26 15:46:52 -0700107#define ASIC_REV_5714 0x09
Michael Chanaf36e6b2006-03-23 01:28:06 -0800108#define ASIC_REV_5755 0x0a
Michael Chand9ab5ad2006-03-20 22:27:35 -0800109#define ASIC_REV_5787 0x0b
Michael Chanb5d37722006-09-27 16:06:21 -0700110#define ASIC_REV_5906 0x0c
Matt Carlson795d01c2007-10-07 23:28:17 -0700111#define ASIC_REV_USE_PROD_ID_REG 0x0f
Matt Carlsond30cdd22007-10-07 23:28:35 -0700112#define ASIC_REV_5784 0x5784
Matt Carlson6b91fa02007-10-10 18:01:09 -0700113#define ASIC_REV_5761 0x5761
Matt Carlson57e69832008-05-25 23:48:31 -0700114#define ASIC_REV_5785 0x5785
Matt Carlson321d32a2008-11-21 17:22:19 -0800115#define ASIC_REV_57780 0x57780
Linus Torvalds1da177e2005-04-16 15:20:36 -0700116#define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8)
117#define CHIPREV_5700_AX 0x70
118#define CHIPREV_5700_BX 0x71
119#define CHIPREV_5700_CX 0x72
120#define CHIPREV_5701_AX 0x00
121#define CHIPREV_5703_AX 0x10
122#define CHIPREV_5704_AX 0x20
123#define CHIPREV_5704_BX 0x21
124#define CHIPREV_5750_AX 0x40
125#define CHIPREV_5750_BX 0x41
Matt Carlsonb2a5c192008-04-03 21:44:44 -0700126#define CHIPREV_5784_AX 0x57840
127#define CHIPREV_5761_AX 0x57610
Linus Torvalds1da177e2005-04-16 15:20:36 -0700128#define GET_METAL_REV(CHIP_REV_ID) ((CHIP_REV_ID) & 0xff)
129#define METAL_REV_A0 0x00
130#define METAL_REV_A1 0x01
131#define METAL_REV_B0 0x00
132#define METAL_REV_B1 0x01
133#define METAL_REV_B2 0x02
134#define TG3PCI_DMA_RW_CTRL 0x0000006c
135#define DMA_RWCTRL_MIN_DMA 0x000000ff
136#define DMA_RWCTRL_MIN_DMA_SHIFT 0
137#define DMA_RWCTRL_READ_BNDRY_MASK 0x00000700
138#define DMA_RWCTRL_READ_BNDRY_DISAB 0x00000000
139#define DMA_RWCTRL_READ_BNDRY_16 0x00000100
140#define DMA_RWCTRL_READ_BNDRY_128_PCIX 0x00000100
141#define DMA_RWCTRL_READ_BNDRY_32 0x00000200
142#define DMA_RWCTRL_READ_BNDRY_256_PCIX 0x00000200
143#define DMA_RWCTRL_READ_BNDRY_64 0x00000300
144#define DMA_RWCTRL_READ_BNDRY_384_PCIX 0x00000300
145#define DMA_RWCTRL_READ_BNDRY_128 0x00000400
146#define DMA_RWCTRL_READ_BNDRY_256 0x00000500
147#define DMA_RWCTRL_READ_BNDRY_512 0x00000600
148#define DMA_RWCTRL_READ_BNDRY_1024 0x00000700
149#define DMA_RWCTRL_WRITE_BNDRY_MASK 0x00003800
150#define DMA_RWCTRL_WRITE_BNDRY_DISAB 0x00000000
151#define DMA_RWCTRL_WRITE_BNDRY_16 0x00000800
152#define DMA_RWCTRL_WRITE_BNDRY_128_PCIX 0x00000800
153#define DMA_RWCTRL_WRITE_BNDRY_32 0x00001000
154#define DMA_RWCTRL_WRITE_BNDRY_256_PCIX 0x00001000
155#define DMA_RWCTRL_WRITE_BNDRY_64 0x00001800
156#define DMA_RWCTRL_WRITE_BNDRY_384_PCIX 0x00001800
157#define DMA_RWCTRL_WRITE_BNDRY_128 0x00002000
158#define DMA_RWCTRL_WRITE_BNDRY_256 0x00002800
159#define DMA_RWCTRL_WRITE_BNDRY_512 0x00003000
160#define DMA_RWCTRL_WRITE_BNDRY_1024 0x00003800
161#define DMA_RWCTRL_ONE_DMA 0x00004000
162#define DMA_RWCTRL_READ_WATER 0x00070000
163#define DMA_RWCTRL_READ_WATER_SHIFT 16
164#define DMA_RWCTRL_WRITE_WATER 0x00380000
165#define DMA_RWCTRL_WRITE_WATER_SHIFT 19
166#define DMA_RWCTRL_USE_MEM_READ_MULT 0x00400000
167#define DMA_RWCTRL_ASSERT_ALL_BE 0x00800000
168#define DMA_RWCTRL_PCI_READ_CMD 0x0f000000
169#define DMA_RWCTRL_PCI_READ_CMD_SHIFT 24
170#define DMA_RWCTRL_PCI_WRITE_CMD 0xf0000000
171#define DMA_RWCTRL_PCI_WRITE_CMD_SHIFT 28
172#define DMA_RWCTRL_WRITE_BNDRY_64_PCIE 0x10000000
173#define DMA_RWCTRL_WRITE_BNDRY_128_PCIE 0x30000000
174#define DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE 0x70000000
175#define TG3PCI_PCISTATE 0x00000070
176#define PCISTATE_FORCE_RESET 0x00000001
177#define PCISTATE_INT_NOT_ACTIVE 0x00000002
178#define PCISTATE_CONV_PCI_MODE 0x00000004
179#define PCISTATE_BUS_SPEED_HIGH 0x00000008
180#define PCISTATE_BUS_32BIT 0x00000010
181#define PCISTATE_ROM_ENABLE 0x00000020
182#define PCISTATE_ROM_RETRY_ENABLE 0x00000040
183#define PCISTATE_FLAT_VIEW 0x00000100
184#define PCISTATE_RETRY_SAME_DMA 0x00002000
Matt Carlson0d3031d2007-10-10 18:02:43 -0700185#define PCISTATE_ALLOW_APE_CTLSPC_WR 0x00010000
186#define PCISTATE_ALLOW_APE_SHMEM_WR 0x00020000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700187#define TG3PCI_CLOCK_CTRL 0x00000074
188#define CLOCK_CTRL_CORECLK_DISABLE 0x00000200
189#define CLOCK_CTRL_RXCLK_DISABLE 0x00000400
190#define CLOCK_CTRL_TXCLK_DISABLE 0x00000800
191#define CLOCK_CTRL_ALTCLK 0x00001000
192#define CLOCK_CTRL_PWRDOWN_PLL133 0x00008000
193#define CLOCK_CTRL_44MHZ_CORE 0x00040000
194#define CLOCK_CTRL_625_CORE 0x00100000
195#define CLOCK_CTRL_FORCE_CLKRUN 0x00200000
196#define CLOCK_CTRL_CLKRUN_OENABLE 0x00400000
197#define CLOCK_CTRL_DELAY_PCI_GRANT 0x80000000
198#define TG3PCI_REG_BASE_ADDR 0x00000078
199#define TG3PCI_MEM_WIN_BASE_ADDR 0x0000007c
200#define TG3PCI_REG_DATA 0x00000080
201#define TG3PCI_MEM_WIN_DATA 0x00000084
202#define TG3PCI_MODE_CTRL 0x00000088
203#define TG3PCI_MISC_CFG 0x0000008c
204#define TG3PCI_MISC_LOCAL_CTRL 0x00000090
205/* 0x94 --> 0x98 unused */
206#define TG3PCI_STD_RING_PROD_IDX 0x00000098 /* 64-bit */
207#define TG3PCI_RCV_RET_RING_CON_IDX 0x000000a0 /* 64-bit */
208#define TG3PCI_SND_PROD_IDX 0x000000a8 /* 64-bit */
209/* 0xb0 --> 0xb8 unused */
210#define TG3PCI_DUAL_MAC_CTRL 0x000000b8
211#define DUAL_MAC_CTRL_CH_MASK 0x00000003
212#define DUAL_MAC_CTRL_ID 0x00000004
Matt Carlson795d01c2007-10-07 23:28:17 -0700213#define TG3PCI_PRODID_ASICREV 0x000000bc
214#define PROD_ID_ASIC_REV_MASK 0x0fffffff
215/* 0xc0 --> 0x100 unused */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700216
217/* 0x100 --> 0x200 unused */
218
219/* Mailbox registers */
220#define MAILBOX_INTERRUPT_0 0x00000200 /* 64-bit */
221#define MAILBOX_INTERRUPT_1 0x00000208 /* 64-bit */
222#define MAILBOX_INTERRUPT_2 0x00000210 /* 64-bit */
223#define MAILBOX_INTERRUPT_3 0x00000218 /* 64-bit */
224#define MAILBOX_GENERAL_0 0x00000220 /* 64-bit */
225#define MAILBOX_GENERAL_1 0x00000228 /* 64-bit */
226#define MAILBOX_GENERAL_2 0x00000230 /* 64-bit */
227#define MAILBOX_GENERAL_3 0x00000238 /* 64-bit */
228#define MAILBOX_GENERAL_4 0x00000240 /* 64-bit */
229#define MAILBOX_GENERAL_5 0x00000248 /* 64-bit */
230#define MAILBOX_GENERAL_6 0x00000250 /* 64-bit */
231#define MAILBOX_GENERAL_7 0x00000258 /* 64-bit */
232#define MAILBOX_RELOAD_STAT 0x00000260 /* 64-bit */
233#define MAILBOX_RCV_STD_PROD_IDX 0x00000268 /* 64-bit */
234#define MAILBOX_RCV_JUMBO_PROD_IDX 0x00000270 /* 64-bit */
235#define MAILBOX_RCV_MINI_PROD_IDX 0x00000278 /* 64-bit */
236#define MAILBOX_RCVRET_CON_IDX_0 0x00000280 /* 64-bit */
237#define MAILBOX_RCVRET_CON_IDX_1 0x00000288 /* 64-bit */
238#define MAILBOX_RCVRET_CON_IDX_2 0x00000290 /* 64-bit */
239#define MAILBOX_RCVRET_CON_IDX_3 0x00000298 /* 64-bit */
240#define MAILBOX_RCVRET_CON_IDX_4 0x000002a0 /* 64-bit */
241#define MAILBOX_RCVRET_CON_IDX_5 0x000002a8 /* 64-bit */
242#define MAILBOX_RCVRET_CON_IDX_6 0x000002b0 /* 64-bit */
243#define MAILBOX_RCVRET_CON_IDX_7 0x000002b8 /* 64-bit */
244#define MAILBOX_RCVRET_CON_IDX_8 0x000002c0 /* 64-bit */
245#define MAILBOX_RCVRET_CON_IDX_9 0x000002c8 /* 64-bit */
246#define MAILBOX_RCVRET_CON_IDX_10 0x000002d0 /* 64-bit */
247#define MAILBOX_RCVRET_CON_IDX_11 0x000002d8 /* 64-bit */
248#define MAILBOX_RCVRET_CON_IDX_12 0x000002e0 /* 64-bit */
249#define MAILBOX_RCVRET_CON_IDX_13 0x000002e8 /* 64-bit */
250#define MAILBOX_RCVRET_CON_IDX_14 0x000002f0 /* 64-bit */
251#define MAILBOX_RCVRET_CON_IDX_15 0x000002f8 /* 64-bit */
252#define MAILBOX_SNDHOST_PROD_IDX_0 0x00000300 /* 64-bit */
253#define MAILBOX_SNDHOST_PROD_IDX_1 0x00000308 /* 64-bit */
254#define MAILBOX_SNDHOST_PROD_IDX_2 0x00000310 /* 64-bit */
255#define MAILBOX_SNDHOST_PROD_IDX_3 0x00000318 /* 64-bit */
256#define MAILBOX_SNDHOST_PROD_IDX_4 0x00000320 /* 64-bit */
257#define MAILBOX_SNDHOST_PROD_IDX_5 0x00000328 /* 64-bit */
258#define MAILBOX_SNDHOST_PROD_IDX_6 0x00000330 /* 64-bit */
259#define MAILBOX_SNDHOST_PROD_IDX_7 0x00000338 /* 64-bit */
260#define MAILBOX_SNDHOST_PROD_IDX_8 0x00000340 /* 64-bit */
261#define MAILBOX_SNDHOST_PROD_IDX_9 0x00000348 /* 64-bit */
262#define MAILBOX_SNDHOST_PROD_IDX_10 0x00000350 /* 64-bit */
263#define MAILBOX_SNDHOST_PROD_IDX_11 0x00000358 /* 64-bit */
264#define MAILBOX_SNDHOST_PROD_IDX_12 0x00000360 /* 64-bit */
265#define MAILBOX_SNDHOST_PROD_IDX_13 0x00000368 /* 64-bit */
266#define MAILBOX_SNDHOST_PROD_IDX_14 0x00000370 /* 64-bit */
267#define MAILBOX_SNDHOST_PROD_IDX_15 0x00000378 /* 64-bit */
268#define MAILBOX_SNDNIC_PROD_IDX_0 0x00000380 /* 64-bit */
269#define MAILBOX_SNDNIC_PROD_IDX_1 0x00000388 /* 64-bit */
270#define MAILBOX_SNDNIC_PROD_IDX_2 0x00000390 /* 64-bit */
271#define MAILBOX_SNDNIC_PROD_IDX_3 0x00000398 /* 64-bit */
272#define MAILBOX_SNDNIC_PROD_IDX_4 0x000003a0 /* 64-bit */
273#define MAILBOX_SNDNIC_PROD_IDX_5 0x000003a8 /* 64-bit */
274#define MAILBOX_SNDNIC_PROD_IDX_6 0x000003b0 /* 64-bit */
275#define MAILBOX_SNDNIC_PROD_IDX_7 0x000003b8 /* 64-bit */
276#define MAILBOX_SNDNIC_PROD_IDX_8 0x000003c0 /* 64-bit */
277#define MAILBOX_SNDNIC_PROD_IDX_9 0x000003c8 /* 64-bit */
278#define MAILBOX_SNDNIC_PROD_IDX_10 0x000003d0 /* 64-bit */
279#define MAILBOX_SNDNIC_PROD_IDX_11 0x000003d8 /* 64-bit */
280#define MAILBOX_SNDNIC_PROD_IDX_12 0x000003e0 /* 64-bit */
281#define MAILBOX_SNDNIC_PROD_IDX_13 0x000003e8 /* 64-bit */
282#define MAILBOX_SNDNIC_PROD_IDX_14 0x000003f0 /* 64-bit */
283#define MAILBOX_SNDNIC_PROD_IDX_15 0x000003f8 /* 64-bit */
284
285/* MAC control registers */
286#define MAC_MODE 0x00000400
287#define MAC_MODE_RESET 0x00000001
288#define MAC_MODE_HALF_DUPLEX 0x00000002
289#define MAC_MODE_PORT_MODE_MASK 0x0000000c
290#define MAC_MODE_PORT_MODE_TBI 0x0000000c
291#define MAC_MODE_PORT_MODE_GMII 0x00000008
292#define MAC_MODE_PORT_MODE_MII 0x00000004
293#define MAC_MODE_PORT_MODE_NONE 0x00000000
294#define MAC_MODE_PORT_INT_LPBACK 0x00000010
295#define MAC_MODE_TAGGED_MAC_CTRL 0x00000080
296#define MAC_MODE_TX_BURSTING 0x00000100
297#define MAC_MODE_MAX_DEFER 0x00000200
298#define MAC_MODE_LINK_POLARITY 0x00000400
299#define MAC_MODE_RXSTAT_ENABLE 0x00000800
300#define MAC_MODE_RXSTAT_CLEAR 0x00001000
301#define MAC_MODE_RXSTAT_FLUSH 0x00002000
302#define MAC_MODE_TXSTAT_ENABLE 0x00004000
303#define MAC_MODE_TXSTAT_CLEAR 0x00008000
304#define MAC_MODE_TXSTAT_FLUSH 0x00010000
305#define MAC_MODE_SEND_CONFIGS 0x00020000
306#define MAC_MODE_MAGIC_PKT_ENABLE 0x00040000
307#define MAC_MODE_ACPI_ENABLE 0x00080000
308#define MAC_MODE_MIP_ENABLE 0x00100000
309#define MAC_MODE_TDE_ENABLE 0x00200000
310#define MAC_MODE_RDE_ENABLE 0x00400000
311#define MAC_MODE_FHDE_ENABLE 0x00800000
Matt Carlsonb2aee152008-11-03 16:51:11 -0800312#define MAC_MODE_KEEP_FRAME_IN_WOL 0x01000000
Matt Carlson3bda1252008-08-15 14:08:22 -0700313#define MAC_MODE_APE_RX_EN 0x08000000
314#define MAC_MODE_APE_TX_EN 0x10000000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700315#define MAC_STATUS 0x00000404
316#define MAC_STATUS_PCS_SYNCED 0x00000001
317#define MAC_STATUS_SIGNAL_DET 0x00000002
318#define MAC_STATUS_RCVD_CFG 0x00000004
319#define MAC_STATUS_CFG_CHANGED 0x00000008
320#define MAC_STATUS_SYNC_CHANGED 0x00000010
321#define MAC_STATUS_PORT_DEC_ERR 0x00000400
322#define MAC_STATUS_LNKSTATE_CHANGED 0x00001000
323#define MAC_STATUS_MI_COMPLETION 0x00400000
324#define MAC_STATUS_MI_INTERRUPT 0x00800000
325#define MAC_STATUS_AP_ERROR 0x01000000
326#define MAC_STATUS_ODI_ERROR 0x02000000
327#define MAC_STATUS_RXSTAT_OVERRUN 0x04000000
328#define MAC_STATUS_TXSTAT_OVERRUN 0x08000000
329#define MAC_EVENT 0x00000408
330#define MAC_EVENT_PORT_DECODE_ERR 0x00000400
331#define MAC_EVENT_LNKSTATE_CHANGED 0x00001000
332#define MAC_EVENT_MI_COMPLETION 0x00400000
333#define MAC_EVENT_MI_INTERRUPT 0x00800000
334#define MAC_EVENT_AP_ERROR 0x01000000
335#define MAC_EVENT_ODI_ERROR 0x02000000
336#define MAC_EVENT_RXSTAT_OVERRUN 0x04000000
337#define MAC_EVENT_TXSTAT_OVERRUN 0x08000000
338#define MAC_LED_CTRL 0x0000040c
339#define LED_CTRL_LNKLED_OVERRIDE 0x00000001
340#define LED_CTRL_1000MBPS_ON 0x00000002
341#define LED_CTRL_100MBPS_ON 0x00000004
342#define LED_CTRL_10MBPS_ON 0x00000008
343#define LED_CTRL_TRAFFIC_OVERRIDE 0x00000010
344#define LED_CTRL_TRAFFIC_BLINK 0x00000020
345#define LED_CTRL_TRAFFIC_LED 0x00000040
346#define LED_CTRL_1000MBPS_STATUS 0x00000080
347#define LED_CTRL_100MBPS_STATUS 0x00000100
348#define LED_CTRL_10MBPS_STATUS 0x00000200
349#define LED_CTRL_TRAFFIC_STATUS 0x00000400
350#define LED_CTRL_MODE_MAC 0x00000000
351#define LED_CTRL_MODE_PHY_1 0x00000800
352#define LED_CTRL_MODE_PHY_2 0x00001000
353#define LED_CTRL_MODE_SHASTA_MAC 0x00002000
354#define LED_CTRL_MODE_SHARED 0x00004000
355#define LED_CTRL_MODE_COMBO 0x00008000
356#define LED_CTRL_BLINK_RATE_MASK 0x7ff80000
357#define LED_CTRL_BLINK_RATE_SHIFT 19
358#define LED_CTRL_BLINK_PER_OVERRIDE 0x00080000
359#define LED_CTRL_BLINK_RATE_OVERRIDE 0x80000000
360#define MAC_ADDR_0_HIGH 0x00000410 /* upper 2 bytes */
361#define MAC_ADDR_0_LOW 0x00000414 /* lower 4 bytes */
362#define MAC_ADDR_1_HIGH 0x00000418 /* upper 2 bytes */
363#define MAC_ADDR_1_LOW 0x0000041c /* lower 4 bytes */
364#define MAC_ADDR_2_HIGH 0x00000420 /* upper 2 bytes */
365#define MAC_ADDR_2_LOW 0x00000424 /* lower 4 bytes */
366#define MAC_ADDR_3_HIGH 0x00000428 /* upper 2 bytes */
367#define MAC_ADDR_3_LOW 0x0000042c /* lower 4 bytes */
368#define MAC_ACPI_MBUF_PTR 0x00000430
369#define MAC_ACPI_LEN_OFFSET 0x00000434
370#define ACPI_LENOFF_LEN_MASK 0x0000ffff
371#define ACPI_LENOFF_LEN_SHIFT 0
372#define ACPI_LENOFF_OFF_MASK 0x0fff0000
373#define ACPI_LENOFF_OFF_SHIFT 16
374#define MAC_TX_BACKOFF_SEED 0x00000438
375#define TX_BACKOFF_SEED_MASK 0x000003ff
376#define MAC_RX_MTU_SIZE 0x0000043c
377#define RX_MTU_SIZE_MASK 0x0000ffff
378#define MAC_PCS_TEST 0x00000440
379#define PCS_TEST_PATTERN_MASK 0x000fffff
380#define PCS_TEST_PATTERN_SHIFT 0
381#define PCS_TEST_ENABLE 0x00100000
382#define MAC_TX_AUTO_NEG 0x00000444
383#define TX_AUTO_NEG_MASK 0x0000ffff
384#define TX_AUTO_NEG_SHIFT 0
385#define MAC_RX_AUTO_NEG 0x00000448
386#define RX_AUTO_NEG_MASK 0x0000ffff
387#define RX_AUTO_NEG_SHIFT 0
388#define MAC_MI_COM 0x0000044c
389#define MI_COM_CMD_MASK 0x0c000000
390#define MI_COM_CMD_WRITE 0x04000000
391#define MI_COM_CMD_READ 0x08000000
392#define MI_COM_READ_FAILED 0x10000000
393#define MI_COM_START 0x20000000
394#define MI_COM_BUSY 0x20000000
395#define MI_COM_PHY_ADDR_MASK 0x03e00000
396#define MI_COM_PHY_ADDR_SHIFT 21
397#define MI_COM_REG_ADDR_MASK 0x001f0000
398#define MI_COM_REG_ADDR_SHIFT 16
399#define MI_COM_DATA_MASK 0x0000ffff
400#define MAC_MI_STAT 0x00000450
401#define MAC_MI_STAT_LNKSTAT_ATTN_ENAB 0x00000001
Matt Carlsonfcb389d2008-11-03 16:55:44 -0800402#define MAC_MI_STAT_10MBPS_MODE 0x00000002
Linus Torvalds1da177e2005-04-16 15:20:36 -0700403#define MAC_MI_MODE 0x00000454
404#define MAC_MI_MODE_CLK_10MHZ 0x00000001
405#define MAC_MI_MODE_SHORT_PREAMBLE 0x00000002
406#define MAC_MI_MODE_AUTO_POLL 0x00000010
Matt Carlson8ef21422008-05-02 16:47:53 -0700407#define MAC_MI_MODE_500KHZ_CONST 0x00008000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700408#define MAC_MI_MODE_BASE 0x000c0000 /* XXX magic values XXX */
409#define MAC_AUTO_POLL_STATUS 0x00000458
410#define MAC_AUTO_POLL_ERROR 0x00000001
411#define MAC_TX_MODE 0x0000045c
412#define TX_MODE_RESET 0x00000001
413#define TX_MODE_ENABLE 0x00000002
414#define TX_MODE_FLOW_CTRL_ENABLE 0x00000010
415#define TX_MODE_BIG_BCKOFF_ENABLE 0x00000020
416#define TX_MODE_LONG_PAUSE_ENABLE 0x00000040
417#define MAC_TX_STATUS 0x00000460
418#define TX_STATUS_XOFFED 0x00000001
419#define TX_STATUS_SENT_XOFF 0x00000002
420#define TX_STATUS_SENT_XON 0x00000004
421#define TX_STATUS_LINK_UP 0x00000008
422#define TX_STATUS_ODI_UNDERRUN 0x00000010
423#define TX_STATUS_ODI_OVERRUN 0x00000020
424#define MAC_TX_LENGTHS 0x00000464
425#define TX_LENGTHS_SLOT_TIME_MASK 0x000000ff
426#define TX_LENGTHS_SLOT_TIME_SHIFT 0
427#define TX_LENGTHS_IPG_MASK 0x00000f00
428#define TX_LENGTHS_IPG_SHIFT 8
429#define TX_LENGTHS_IPG_CRS_MASK 0x00003000
430#define TX_LENGTHS_IPG_CRS_SHIFT 12
431#define MAC_RX_MODE 0x00000468
432#define RX_MODE_RESET 0x00000001
433#define RX_MODE_ENABLE 0x00000002
434#define RX_MODE_FLOW_CTRL_ENABLE 0x00000004
435#define RX_MODE_KEEP_MAC_CTRL 0x00000008
436#define RX_MODE_KEEP_PAUSE 0x00000010
437#define RX_MODE_ACCEPT_OVERSIZED 0x00000020
438#define RX_MODE_ACCEPT_RUNTS 0x00000040
439#define RX_MODE_LEN_CHECK 0x00000080
440#define RX_MODE_PROMISC 0x00000100
441#define RX_MODE_NO_CRC_CHECK 0x00000200
442#define RX_MODE_KEEP_VLAN_TAG 0x00000400
Michael Chanaf36e6b2006-03-23 01:28:06 -0800443#define RX_MODE_IPV6_CSUM_ENABLE 0x01000000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700444#define MAC_RX_STATUS 0x0000046c
445#define RX_STATUS_REMOTE_TX_XOFFED 0x00000001
446#define RX_STATUS_XOFF_RCVD 0x00000002
447#define RX_STATUS_XON_RCVD 0x00000004
448#define MAC_HASH_REG_0 0x00000470
449#define MAC_HASH_REG_1 0x00000474
450#define MAC_HASH_REG_2 0x00000478
451#define MAC_HASH_REG_3 0x0000047c
452#define MAC_RCV_RULE_0 0x00000480
453#define MAC_RCV_VALUE_0 0x00000484
454#define MAC_RCV_RULE_1 0x00000488
455#define MAC_RCV_VALUE_1 0x0000048c
456#define MAC_RCV_RULE_2 0x00000490
457#define MAC_RCV_VALUE_2 0x00000494
458#define MAC_RCV_RULE_3 0x00000498
459#define MAC_RCV_VALUE_3 0x0000049c
460#define MAC_RCV_RULE_4 0x000004a0
461#define MAC_RCV_VALUE_4 0x000004a4
462#define MAC_RCV_RULE_5 0x000004a8
463#define MAC_RCV_VALUE_5 0x000004ac
464#define MAC_RCV_RULE_6 0x000004b0
465#define MAC_RCV_VALUE_6 0x000004b4
466#define MAC_RCV_RULE_7 0x000004b8
467#define MAC_RCV_VALUE_7 0x000004bc
468#define MAC_RCV_RULE_8 0x000004c0
469#define MAC_RCV_VALUE_8 0x000004c4
470#define MAC_RCV_RULE_9 0x000004c8
471#define MAC_RCV_VALUE_9 0x000004cc
472#define MAC_RCV_RULE_10 0x000004d0
473#define MAC_RCV_VALUE_10 0x000004d4
474#define MAC_RCV_RULE_11 0x000004d8
475#define MAC_RCV_VALUE_11 0x000004dc
476#define MAC_RCV_RULE_12 0x000004e0
477#define MAC_RCV_VALUE_12 0x000004e4
478#define MAC_RCV_RULE_13 0x000004e8
479#define MAC_RCV_VALUE_13 0x000004ec
480#define MAC_RCV_RULE_14 0x000004f0
481#define MAC_RCV_VALUE_14 0x000004f4
482#define MAC_RCV_RULE_15 0x000004f8
483#define MAC_RCV_VALUE_15 0x000004fc
484#define RCV_RULE_DISABLE_MASK 0x7fffffff
485#define MAC_RCV_RULE_CFG 0x00000500
486#define RCV_RULE_CFG_DEFAULT_CLASS 0x00000008
487#define MAC_LOW_WMARK_MAX_RX_FRAME 0x00000504
488/* 0x508 --> 0x520 unused */
489#define MAC_HASHREGU_0 0x00000520
490#define MAC_HASHREGU_1 0x00000524
491#define MAC_HASHREGU_2 0x00000528
492#define MAC_HASHREGU_3 0x0000052c
493#define MAC_EXTADDR_0_HIGH 0x00000530
494#define MAC_EXTADDR_0_LOW 0x00000534
495#define MAC_EXTADDR_1_HIGH 0x00000538
496#define MAC_EXTADDR_1_LOW 0x0000053c
497#define MAC_EXTADDR_2_HIGH 0x00000540
498#define MAC_EXTADDR_2_LOW 0x00000544
499#define MAC_EXTADDR_3_HIGH 0x00000548
500#define MAC_EXTADDR_3_LOW 0x0000054c
501#define MAC_EXTADDR_4_HIGH 0x00000550
502#define MAC_EXTADDR_4_LOW 0x00000554
503#define MAC_EXTADDR_5_HIGH 0x00000558
504#define MAC_EXTADDR_5_LOW 0x0000055c
505#define MAC_EXTADDR_6_HIGH 0x00000560
506#define MAC_EXTADDR_6_LOW 0x00000564
507#define MAC_EXTADDR_7_HIGH 0x00000568
508#define MAC_EXTADDR_7_LOW 0x0000056c
509#define MAC_EXTADDR_8_HIGH 0x00000570
510#define MAC_EXTADDR_8_LOW 0x00000574
511#define MAC_EXTADDR_9_HIGH 0x00000578
512#define MAC_EXTADDR_9_LOW 0x0000057c
513#define MAC_EXTADDR_10_HIGH 0x00000580
514#define MAC_EXTADDR_10_LOW 0x00000584
515#define MAC_EXTADDR_11_HIGH 0x00000588
516#define MAC_EXTADDR_11_LOW 0x0000058c
517#define MAC_SERDES_CFG 0x00000590
518#define MAC_SERDES_CFG_EDGE_SELECT 0x00001000
519#define MAC_SERDES_STAT 0x00000594
Matt Carlsona9daf362008-05-25 23:49:44 -0700520/* 0x598 --> 0x5a0 unused */
521#define MAC_PHYCFG1 0x000005a0
522#define MAC_PHYCFG1_RGMII_INT 0x00000001
523#define MAC_PHYCFG1_RGMII_EXT_RX_DEC 0x02000000
524#define MAC_PHYCFG1_RGMII_SND_STAT_EN 0x04000000
525#define MAC_PHYCFG1_TXC_DRV 0x20000000
526#define MAC_PHYCFG2 0x000005a4
527#define MAC_PHYCFG2_INBAND_ENABLE 0x00000001
Matt Carlsonfcb389d2008-11-03 16:55:44 -0800528#define MAC_PHYCFG2_EMODE_MASK_MASK 0x000001c0
529#define MAC_PHYCFG2_EMODE_MASK_AC131 0x000000c0
530#define MAC_PHYCFG2_EMODE_MASK_50610 0x00000100
531#define MAC_PHYCFG2_EMODE_MASK_RT8211 0x00000000
532#define MAC_PHYCFG2_EMODE_MASK_RT8201 0x000001c0
533#define MAC_PHYCFG2_EMODE_COMP_MASK 0x00000e00
534#define MAC_PHYCFG2_EMODE_COMP_AC131 0x00000600
535#define MAC_PHYCFG2_EMODE_COMP_50610 0x00000400
536#define MAC_PHYCFG2_EMODE_COMP_RT8211 0x00000800
537#define MAC_PHYCFG2_EMODE_COMP_RT8201 0x00000000
538#define MAC_PHYCFG2_FMODE_MASK_MASK 0x00007000
539#define MAC_PHYCFG2_FMODE_MASK_AC131 0x00006000
540#define MAC_PHYCFG2_FMODE_MASK_50610 0x00004000
541#define MAC_PHYCFG2_FMODE_MASK_RT8211 0x00000000
542#define MAC_PHYCFG2_FMODE_MASK_RT8201 0x00007000
543#define MAC_PHYCFG2_FMODE_COMP_MASK 0x00038000
544#define MAC_PHYCFG2_FMODE_COMP_AC131 0x00030000
545#define MAC_PHYCFG2_FMODE_COMP_50610 0x00008000
546#define MAC_PHYCFG2_FMODE_COMP_RT8211 0x00038000
547#define MAC_PHYCFG2_FMODE_COMP_RT8201 0x00000000
548#define MAC_PHYCFG2_GMODE_MASK_MASK 0x001c0000
549#define MAC_PHYCFG2_GMODE_MASK_AC131 0x001c0000
550#define MAC_PHYCFG2_GMODE_MASK_50610 0x00100000
551#define MAC_PHYCFG2_GMODE_MASK_RT8211 0x00000000
552#define MAC_PHYCFG2_GMODE_MASK_RT8201 0x001c0000
553#define MAC_PHYCFG2_GMODE_COMP_MASK 0x00e00000
554#define MAC_PHYCFG2_GMODE_COMP_AC131 0x00e00000
555#define MAC_PHYCFG2_GMODE_COMP_50610 0x00000000
556#define MAC_PHYCFG2_GMODE_COMP_RT8211 0x00200000
557#define MAC_PHYCFG2_GMODE_COMP_RT8201 0x00000000
558#define MAC_PHYCFG2_ACT_MASK_MASK 0x03000000
559#define MAC_PHYCFG2_ACT_MASK_AC131 0x03000000
560#define MAC_PHYCFG2_ACT_MASK_50610 0x01000000
561#define MAC_PHYCFG2_ACT_MASK_RT8211 0x03000000
562#define MAC_PHYCFG2_ACT_MASK_RT8201 0x01000000
563#define MAC_PHYCFG2_ACT_COMP_MASK 0x0c000000
564#define MAC_PHYCFG2_ACT_COMP_AC131 0x00000000
565#define MAC_PHYCFG2_ACT_COMP_50610 0x00000000
566#define MAC_PHYCFG2_ACT_COMP_RT8211 0x00000000
567#define MAC_PHYCFG2_ACT_COMP_RT8201 0x08000000
568#define MAC_PHYCFG2_QUAL_MASK_MASK 0x30000000
569#define MAC_PHYCFG2_QUAL_MASK_AC131 0x30000000
570#define MAC_PHYCFG2_QUAL_MASK_50610 0x30000000
571#define MAC_PHYCFG2_QUAL_MASK_RT8211 0x30000000
572#define MAC_PHYCFG2_QUAL_MASK_RT8201 0x30000000
573#define MAC_PHYCFG2_QUAL_COMP_MASK 0xc0000000
574#define MAC_PHYCFG2_QUAL_COMP_AC131 0x00000000
575#define MAC_PHYCFG2_QUAL_COMP_50610 0x00000000
576#define MAC_PHYCFG2_QUAL_COMP_RT8211 0x00000000
577#define MAC_PHYCFG2_QUAL_COMP_RT8201 0x00000000
578#define MAC_PHYCFG2_50610_LED_MODES \
579 (MAC_PHYCFG2_EMODE_MASK_50610 | \
580 MAC_PHYCFG2_EMODE_COMP_50610 | \
581 MAC_PHYCFG2_FMODE_MASK_50610 | \
582 MAC_PHYCFG2_FMODE_COMP_50610 | \
583 MAC_PHYCFG2_GMODE_MASK_50610 | \
584 MAC_PHYCFG2_GMODE_COMP_50610 | \
585 MAC_PHYCFG2_ACT_MASK_50610 | \
586 MAC_PHYCFG2_ACT_COMP_50610 | \
587 MAC_PHYCFG2_QUAL_MASK_50610 | \
588 MAC_PHYCFG2_QUAL_COMP_50610)
589#define MAC_PHYCFG2_AC131_LED_MODES \
590 (MAC_PHYCFG2_EMODE_MASK_AC131 | \
591 MAC_PHYCFG2_EMODE_COMP_AC131 | \
592 MAC_PHYCFG2_FMODE_MASK_AC131 | \
593 MAC_PHYCFG2_FMODE_COMP_AC131 | \
594 MAC_PHYCFG2_GMODE_MASK_AC131 | \
595 MAC_PHYCFG2_GMODE_COMP_AC131 | \
596 MAC_PHYCFG2_ACT_MASK_AC131 | \
597 MAC_PHYCFG2_ACT_COMP_AC131 | \
598 MAC_PHYCFG2_QUAL_MASK_AC131 | \
599 MAC_PHYCFG2_QUAL_COMP_AC131)
600#define MAC_PHYCFG2_RTL8211C_LED_MODES \
601 (MAC_PHYCFG2_EMODE_MASK_RT8211 | \
602 MAC_PHYCFG2_EMODE_COMP_RT8211 | \
603 MAC_PHYCFG2_FMODE_MASK_RT8211 | \
604 MAC_PHYCFG2_FMODE_COMP_RT8211 | \
605 MAC_PHYCFG2_GMODE_MASK_RT8211 | \
606 MAC_PHYCFG2_GMODE_COMP_RT8211 | \
607 MAC_PHYCFG2_ACT_MASK_RT8211 | \
608 MAC_PHYCFG2_ACT_COMP_RT8211 | \
609 MAC_PHYCFG2_QUAL_MASK_RT8211 | \
610 MAC_PHYCFG2_QUAL_COMP_RT8211)
611#define MAC_PHYCFG2_RTL8201E_LED_MODES \
612 (MAC_PHYCFG2_EMODE_MASK_RT8201 | \
613 MAC_PHYCFG2_EMODE_COMP_RT8201 | \
614 MAC_PHYCFG2_FMODE_MASK_RT8201 | \
615 MAC_PHYCFG2_FMODE_COMP_RT8201 | \
616 MAC_PHYCFG2_GMODE_MASK_RT8201 | \
617 MAC_PHYCFG2_GMODE_COMP_RT8201 | \
618 MAC_PHYCFG2_ACT_MASK_RT8201 | \
619 MAC_PHYCFG2_ACT_COMP_RT8201 | \
620 MAC_PHYCFG2_QUAL_MASK_RT8201 | \
621 MAC_PHYCFG2_QUAL_COMP_RT8201)
Matt Carlsona9daf362008-05-25 23:49:44 -0700622#define MAC_EXT_RGMII_MODE 0x000005a8
623#define MAC_RGMII_MODE_TX_ENABLE 0x00000001
624#define MAC_RGMII_MODE_TX_LOWPWR 0x00000002
625#define MAC_RGMII_MODE_TX_RESET 0x00000004
626#define MAC_RGMII_MODE_RX_INT_B 0x00000100
627#define MAC_RGMII_MODE_RX_QUALITY 0x00000200
628#define MAC_RGMII_MODE_RX_ACTIVITY 0x00000400
629#define MAC_RGMII_MODE_RX_ENG_DET 0x00000800
630/* 0x5ac --> 0x5b0 unused */
Michael Chana4e2b342005-10-26 15:46:52 -0700631#define SERDES_RX_CTRL 0x000005b0 /* 5780/5714 only */
632#define SERDES_RX_SIG_DETECT 0x00000400
Linus Torvalds1da177e2005-04-16 15:20:36 -0700633#define SG_DIG_CTRL 0x000005b0
634#define SG_DIG_USING_HW_AUTONEG 0x80000000
635#define SG_DIG_SOFT_RESET 0x40000000
636#define SG_DIG_DISABLE_LINKRDY 0x20000000
637#define SG_DIG_CRC16_CLEAR_N 0x01000000
638#define SG_DIG_EN10B 0x00800000
639#define SG_DIG_CLEAR_STATUS 0x00400000
640#define SG_DIG_LOCAL_DUPLEX_STATUS 0x00200000
641#define SG_DIG_LOCAL_LINK_STATUS 0x00100000
642#define SG_DIG_SPEED_STATUS_MASK 0x000c0000
643#define SG_DIG_SPEED_STATUS_SHIFT 18
644#define SG_DIG_JUMBO_PACKET_DISABLE 0x00020000
645#define SG_DIG_RESTART_AUTONEG 0x00010000
646#define SG_DIG_FIBER_MODE 0x00008000
647#define SG_DIG_REMOTE_FAULT_MASK 0x00006000
648#define SG_DIG_PAUSE_MASK 0x00001800
Matt Carlsonc98f6e32007-12-20 20:08:32 -0800649#define SG_DIG_PAUSE_CAP 0x00000800
650#define SG_DIG_ASYM_PAUSE 0x00001000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700651#define SG_DIG_GBIC_ENABLE 0x00000400
652#define SG_DIG_CHECK_END_ENABLE 0x00000200
653#define SG_DIG_SGMII_AUTONEG_TIMER 0x00000100
654#define SG_DIG_CLOCK_PHASE_SELECT 0x00000080
655#define SG_DIG_GMII_INPUT_SELECT 0x00000040
656#define SG_DIG_MRADV_CRC16_SELECT 0x00000020
657#define SG_DIG_COMMA_DETECT_ENABLE 0x00000010
658#define SG_DIG_AUTONEG_TIMER_REDUCE 0x00000008
659#define SG_DIG_AUTONEG_LOW_ENABLE 0x00000004
660#define SG_DIG_REMOTE_LOOPBACK 0x00000002
661#define SG_DIG_LOOPBACK 0x00000001
Matt Carlsonc98f6e32007-12-20 20:08:32 -0800662#define SG_DIG_COMMON_SETUP (SG_DIG_CRC16_CLEAR_N | \
663 SG_DIG_LOCAL_DUPLEX_STATUS | \
664 SG_DIG_LOCAL_LINK_STATUS | \
665 (0x2 << SG_DIG_SPEED_STATUS_SHIFT) | \
666 SG_DIG_FIBER_MODE | SG_DIG_GBIC_ENABLE)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700667#define SG_DIG_STATUS 0x000005b4
668#define SG_DIG_CRC16_BUS_MASK 0xffff0000
669#define SG_DIG_PARTNER_FAULT_MASK 0x00600000 /* If !MRADV_CRC16_SELECT */
670#define SG_DIG_PARTNER_ASYM_PAUSE 0x00100000 /* If !MRADV_CRC16_SELECT */
671#define SG_DIG_PARTNER_PAUSE_CAPABLE 0x00080000 /* If !MRADV_CRC16_SELECT */
672#define SG_DIG_PARTNER_HALF_DUPLEX 0x00040000 /* If !MRADV_CRC16_SELECT */
673#define SG_DIG_PARTNER_FULL_DUPLEX 0x00020000 /* If !MRADV_CRC16_SELECT */
674#define SG_DIG_PARTNER_NEXT_PAGE 0x00010000 /* If !MRADV_CRC16_SELECT */
675#define SG_DIG_AUTONEG_STATE_MASK 0x00000ff0
676#define SG_DIG_COMMA_DETECTOR 0x00000008
677#define SG_DIG_MAC_ACK_STATUS 0x00000004
678#define SG_DIG_AUTONEG_COMPLETE 0x00000002
679#define SG_DIG_AUTONEG_ERROR 0x00000001
680/* 0x5b8 --> 0x600 unused */
681#define MAC_TX_MAC_STATE_BASE 0x00000600 /* 16 bytes */
682#define MAC_RX_MAC_STATE_BASE 0x00000610 /* 20 bytes */
683/* 0x624 --> 0x800 unused */
684#define MAC_TX_STATS_OCTETS 0x00000800
685#define MAC_TX_STATS_RESV1 0x00000804
686#define MAC_TX_STATS_COLLISIONS 0x00000808
687#define MAC_TX_STATS_XON_SENT 0x0000080c
688#define MAC_TX_STATS_XOFF_SENT 0x00000810
689#define MAC_TX_STATS_RESV2 0x00000814
690#define MAC_TX_STATS_MAC_ERRORS 0x00000818
691#define MAC_TX_STATS_SINGLE_COLLISIONS 0x0000081c
692#define MAC_TX_STATS_MULT_COLLISIONS 0x00000820
693#define MAC_TX_STATS_DEFERRED 0x00000824
694#define MAC_TX_STATS_RESV3 0x00000828
695#define MAC_TX_STATS_EXCESSIVE_COL 0x0000082c
696#define MAC_TX_STATS_LATE_COL 0x00000830
697#define MAC_TX_STATS_RESV4_1 0x00000834
698#define MAC_TX_STATS_RESV4_2 0x00000838
699#define MAC_TX_STATS_RESV4_3 0x0000083c
700#define MAC_TX_STATS_RESV4_4 0x00000840
701#define MAC_TX_STATS_RESV4_5 0x00000844
702#define MAC_TX_STATS_RESV4_6 0x00000848
703#define MAC_TX_STATS_RESV4_7 0x0000084c
704#define MAC_TX_STATS_RESV4_8 0x00000850
705#define MAC_TX_STATS_RESV4_9 0x00000854
706#define MAC_TX_STATS_RESV4_10 0x00000858
707#define MAC_TX_STATS_RESV4_11 0x0000085c
708#define MAC_TX_STATS_RESV4_12 0x00000860
709#define MAC_TX_STATS_RESV4_13 0x00000864
710#define MAC_TX_STATS_RESV4_14 0x00000868
711#define MAC_TX_STATS_UCAST 0x0000086c
712#define MAC_TX_STATS_MCAST 0x00000870
713#define MAC_TX_STATS_BCAST 0x00000874
714#define MAC_TX_STATS_RESV5_1 0x00000878
715#define MAC_TX_STATS_RESV5_2 0x0000087c
716#define MAC_RX_STATS_OCTETS 0x00000880
717#define MAC_RX_STATS_RESV1 0x00000884
718#define MAC_RX_STATS_FRAGMENTS 0x00000888
719#define MAC_RX_STATS_UCAST 0x0000088c
720#define MAC_RX_STATS_MCAST 0x00000890
721#define MAC_RX_STATS_BCAST 0x00000894
722#define MAC_RX_STATS_FCS_ERRORS 0x00000898
723#define MAC_RX_STATS_ALIGN_ERRORS 0x0000089c
724#define MAC_RX_STATS_XON_PAUSE_RECVD 0x000008a0
725#define MAC_RX_STATS_XOFF_PAUSE_RECVD 0x000008a4
726#define MAC_RX_STATS_MAC_CTRL_RECVD 0x000008a8
727#define MAC_RX_STATS_XOFF_ENTERED 0x000008ac
728#define MAC_RX_STATS_FRAME_TOO_LONG 0x000008b0
729#define MAC_RX_STATS_JABBERS 0x000008b4
730#define MAC_RX_STATS_UNDERSIZE 0x000008b8
731/* 0x8bc --> 0xc00 unused */
732
733/* Send data initiator control registers */
734#define SNDDATAI_MODE 0x00000c00
735#define SNDDATAI_MODE_RESET 0x00000001
736#define SNDDATAI_MODE_ENABLE 0x00000002
737#define SNDDATAI_MODE_STAT_OFLOW_ENAB 0x00000004
738#define SNDDATAI_STATUS 0x00000c04
739#define SNDDATAI_STATUS_STAT_OFLOW 0x00000004
740#define SNDDATAI_STATSCTRL 0x00000c08
741#define SNDDATAI_SCTRL_ENABLE 0x00000001
742#define SNDDATAI_SCTRL_FASTUPD 0x00000002
743#define SNDDATAI_SCTRL_CLEAR 0x00000004
744#define SNDDATAI_SCTRL_FLUSH 0x00000008
745#define SNDDATAI_SCTRL_FORCE_ZERO 0x00000010
746#define SNDDATAI_STATSENAB 0x00000c0c
747#define SNDDATAI_STATSINCMASK 0x00000c10
Michael Chanb5d37722006-09-27 16:06:21 -0700748#define ISO_PKT_TX 0x00000c20
749/* 0xc24 --> 0xc80 unused */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700750#define SNDDATAI_COS_CNT_0 0x00000c80
751#define SNDDATAI_COS_CNT_1 0x00000c84
752#define SNDDATAI_COS_CNT_2 0x00000c88
753#define SNDDATAI_COS_CNT_3 0x00000c8c
754#define SNDDATAI_COS_CNT_4 0x00000c90
755#define SNDDATAI_COS_CNT_5 0x00000c94
756#define SNDDATAI_COS_CNT_6 0x00000c98
757#define SNDDATAI_COS_CNT_7 0x00000c9c
758#define SNDDATAI_COS_CNT_8 0x00000ca0
759#define SNDDATAI_COS_CNT_9 0x00000ca4
760#define SNDDATAI_COS_CNT_10 0x00000ca8
761#define SNDDATAI_COS_CNT_11 0x00000cac
762#define SNDDATAI_COS_CNT_12 0x00000cb0
763#define SNDDATAI_COS_CNT_13 0x00000cb4
764#define SNDDATAI_COS_CNT_14 0x00000cb8
765#define SNDDATAI_COS_CNT_15 0x00000cbc
766#define SNDDATAI_DMA_RDQ_FULL_CNT 0x00000cc0
767#define SNDDATAI_DMA_PRIO_RDQ_FULL_CNT 0x00000cc4
768#define SNDDATAI_SDCQ_FULL_CNT 0x00000cc8
769#define SNDDATAI_NICRNG_SSND_PIDX_CNT 0x00000ccc
770#define SNDDATAI_STATS_UPDATED_CNT 0x00000cd0
771#define SNDDATAI_INTERRUPTS_CNT 0x00000cd4
772#define SNDDATAI_AVOID_INTERRUPTS_CNT 0x00000cd8
773#define SNDDATAI_SND_THRESH_HIT_CNT 0x00000cdc
774/* 0xce0 --> 0x1000 unused */
775
776/* Send data completion control registers */
777#define SNDDATAC_MODE 0x00001000
778#define SNDDATAC_MODE_RESET 0x00000001
779#define SNDDATAC_MODE_ENABLE 0x00000002
Matt Carlson9936bcf2007-10-10 18:03:07 -0700780#define SNDDATAC_MODE_CDELAY 0x00000010
Linus Torvalds1da177e2005-04-16 15:20:36 -0700781/* 0x1004 --> 0x1400 unused */
782
783/* Send BD ring selector */
784#define SNDBDS_MODE 0x00001400
785#define SNDBDS_MODE_RESET 0x00000001
786#define SNDBDS_MODE_ENABLE 0x00000002
787#define SNDBDS_MODE_ATTN_ENABLE 0x00000004
788#define SNDBDS_STATUS 0x00001404
789#define SNDBDS_STATUS_ERROR_ATTN 0x00000004
790#define SNDBDS_HWDIAG 0x00001408
791/* 0x140c --> 0x1440 */
792#define SNDBDS_SEL_CON_IDX_0 0x00001440
793#define SNDBDS_SEL_CON_IDX_1 0x00001444
794#define SNDBDS_SEL_CON_IDX_2 0x00001448
795#define SNDBDS_SEL_CON_IDX_3 0x0000144c
796#define SNDBDS_SEL_CON_IDX_4 0x00001450
797#define SNDBDS_SEL_CON_IDX_5 0x00001454
798#define SNDBDS_SEL_CON_IDX_6 0x00001458
799#define SNDBDS_SEL_CON_IDX_7 0x0000145c
800#define SNDBDS_SEL_CON_IDX_8 0x00001460
801#define SNDBDS_SEL_CON_IDX_9 0x00001464
802#define SNDBDS_SEL_CON_IDX_10 0x00001468
803#define SNDBDS_SEL_CON_IDX_11 0x0000146c
804#define SNDBDS_SEL_CON_IDX_12 0x00001470
805#define SNDBDS_SEL_CON_IDX_13 0x00001474
806#define SNDBDS_SEL_CON_IDX_14 0x00001478
807#define SNDBDS_SEL_CON_IDX_15 0x0000147c
808/* 0x1480 --> 0x1800 unused */
809
810/* Send BD initiator control registers */
811#define SNDBDI_MODE 0x00001800
812#define SNDBDI_MODE_RESET 0x00000001
813#define SNDBDI_MODE_ENABLE 0x00000002
814#define SNDBDI_MODE_ATTN_ENABLE 0x00000004
815#define SNDBDI_STATUS 0x00001804
816#define SNDBDI_STATUS_ERROR_ATTN 0x00000004
817#define SNDBDI_IN_PROD_IDX_0 0x00001808
818#define SNDBDI_IN_PROD_IDX_1 0x0000180c
819#define SNDBDI_IN_PROD_IDX_2 0x00001810
820#define SNDBDI_IN_PROD_IDX_3 0x00001814
821#define SNDBDI_IN_PROD_IDX_4 0x00001818
822#define SNDBDI_IN_PROD_IDX_5 0x0000181c
823#define SNDBDI_IN_PROD_IDX_6 0x00001820
824#define SNDBDI_IN_PROD_IDX_7 0x00001824
825#define SNDBDI_IN_PROD_IDX_8 0x00001828
826#define SNDBDI_IN_PROD_IDX_9 0x0000182c
827#define SNDBDI_IN_PROD_IDX_10 0x00001830
828#define SNDBDI_IN_PROD_IDX_11 0x00001834
829#define SNDBDI_IN_PROD_IDX_12 0x00001838
830#define SNDBDI_IN_PROD_IDX_13 0x0000183c
831#define SNDBDI_IN_PROD_IDX_14 0x00001840
832#define SNDBDI_IN_PROD_IDX_15 0x00001844
833/* 0x1848 --> 0x1c00 unused */
834
835/* Send BD completion control registers */
836#define SNDBDC_MODE 0x00001c00
837#define SNDBDC_MODE_RESET 0x00000001
838#define SNDBDC_MODE_ENABLE 0x00000002
839#define SNDBDC_MODE_ATTN_ENABLE 0x00000004
840/* 0x1c04 --> 0x2000 unused */
841
842/* Receive list placement control registers */
843#define RCVLPC_MODE 0x00002000
844#define RCVLPC_MODE_RESET 0x00000001
845#define RCVLPC_MODE_ENABLE 0x00000002
846#define RCVLPC_MODE_CLASS0_ATTN_ENAB 0x00000004
847#define RCVLPC_MODE_MAPOOR_AATTN_ENAB 0x00000008
848#define RCVLPC_MODE_STAT_OFLOW_ENAB 0x00000010
849#define RCVLPC_STATUS 0x00002004
850#define RCVLPC_STATUS_CLASS0 0x00000004
851#define RCVLPC_STATUS_MAPOOR 0x00000008
852#define RCVLPC_STATUS_STAT_OFLOW 0x00000010
853#define RCVLPC_LOCK 0x00002008
854#define RCVLPC_LOCK_REQ_MASK 0x0000ffff
855#define RCVLPC_LOCK_REQ_SHIFT 0
856#define RCVLPC_LOCK_GRANT_MASK 0xffff0000
857#define RCVLPC_LOCK_GRANT_SHIFT 16
858#define RCVLPC_NON_EMPTY_BITS 0x0000200c
859#define RCVLPC_NON_EMPTY_BITS_MASK 0x0000ffff
860#define RCVLPC_CONFIG 0x00002010
861#define RCVLPC_STATSCTRL 0x00002014
862#define RCVLPC_STATSCTRL_ENABLE 0x00000001
863#define RCVLPC_STATSCTRL_FASTUPD 0x00000002
864#define RCVLPC_STATS_ENABLE 0x00002018
Michael Chan16613942006-06-29 20:15:13 -0700865#define RCVLPC_STATSENAB_DACK_FIX 0x00040000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700866#define RCVLPC_STATSENAB_LNGBRST_RFIX 0x00400000
867#define RCVLPC_STATS_INCMASK 0x0000201c
868/* 0x2020 --> 0x2100 unused */
869#define RCVLPC_SELLST_BASE 0x00002100 /* 16 16-byte entries */
870#define SELLST_TAIL 0x00000004
871#define SELLST_CONT 0x00000008
872#define SELLST_UNUSED 0x0000000c
873#define RCVLPC_COS_CNTL_BASE 0x00002200 /* 16 4-byte entries */
874#define RCVLPC_DROP_FILTER_CNT 0x00002240
875#define RCVLPC_DMA_WQ_FULL_CNT 0x00002244
876#define RCVLPC_DMA_HIPRIO_WQ_FULL_CNT 0x00002248
877#define RCVLPC_NO_RCV_BD_CNT 0x0000224c
878#define RCVLPC_IN_DISCARDS_CNT 0x00002250
879#define RCVLPC_IN_ERRORS_CNT 0x00002254
880#define RCVLPC_RCV_THRESH_HIT_CNT 0x00002258
881/* 0x225c --> 0x2400 unused */
882
883/* Receive Data and Receive BD Initiator Control */
884#define RCVDBDI_MODE 0x00002400
885#define RCVDBDI_MODE_RESET 0x00000001
886#define RCVDBDI_MODE_ENABLE 0x00000002
887#define RCVDBDI_MODE_JUMBOBD_NEEDED 0x00000004
888#define RCVDBDI_MODE_FRM_TOO_BIG 0x00000008
889#define RCVDBDI_MODE_INV_RING_SZ 0x00000010
890#define RCVDBDI_STATUS 0x00002404
891#define RCVDBDI_STATUS_JUMBOBD_NEEDED 0x00000004
892#define RCVDBDI_STATUS_FRM_TOO_BIG 0x00000008
893#define RCVDBDI_STATUS_INV_RING_SZ 0x00000010
894#define RCVDBDI_SPLIT_FRAME_MINSZ 0x00002408
895/* 0x240c --> 0x2440 unused */
896#define RCVDBDI_JUMBO_BD 0x00002440 /* TG3_BDINFO_... */
897#define RCVDBDI_STD_BD 0x00002450 /* TG3_BDINFO_... */
898#define RCVDBDI_MINI_BD 0x00002460 /* TG3_BDINFO_... */
899#define RCVDBDI_JUMBO_CON_IDX 0x00002470
900#define RCVDBDI_STD_CON_IDX 0x00002474
901#define RCVDBDI_MINI_CON_IDX 0x00002478
902/* 0x247c --> 0x2480 unused */
903#define RCVDBDI_BD_PROD_IDX_0 0x00002480
904#define RCVDBDI_BD_PROD_IDX_1 0x00002484
905#define RCVDBDI_BD_PROD_IDX_2 0x00002488
906#define RCVDBDI_BD_PROD_IDX_3 0x0000248c
907#define RCVDBDI_BD_PROD_IDX_4 0x00002490
908#define RCVDBDI_BD_PROD_IDX_5 0x00002494
909#define RCVDBDI_BD_PROD_IDX_6 0x00002498
910#define RCVDBDI_BD_PROD_IDX_7 0x0000249c
911#define RCVDBDI_BD_PROD_IDX_8 0x000024a0
912#define RCVDBDI_BD_PROD_IDX_9 0x000024a4
913#define RCVDBDI_BD_PROD_IDX_10 0x000024a8
914#define RCVDBDI_BD_PROD_IDX_11 0x000024ac
915#define RCVDBDI_BD_PROD_IDX_12 0x000024b0
916#define RCVDBDI_BD_PROD_IDX_13 0x000024b4
917#define RCVDBDI_BD_PROD_IDX_14 0x000024b8
918#define RCVDBDI_BD_PROD_IDX_15 0x000024bc
919#define RCVDBDI_HWDIAG 0x000024c0
920/* 0x24c4 --> 0x2800 unused */
921
922/* Receive Data Completion Control */
923#define RCVDCC_MODE 0x00002800
924#define RCVDCC_MODE_RESET 0x00000001
925#define RCVDCC_MODE_ENABLE 0x00000002
926#define RCVDCC_MODE_ATTN_ENABLE 0x00000004
927/* 0x2804 --> 0x2c00 unused */
928
929/* Receive BD Initiator Control Registers */
930#define RCVBDI_MODE 0x00002c00
931#define RCVBDI_MODE_RESET 0x00000001
932#define RCVBDI_MODE_ENABLE 0x00000002
933#define RCVBDI_MODE_RCB_ATTN_ENAB 0x00000004
934#define RCVBDI_STATUS 0x00002c04
935#define RCVBDI_STATUS_RCB_ATTN 0x00000004
936#define RCVBDI_JUMBO_PROD_IDX 0x00002c08
937#define RCVBDI_STD_PROD_IDX 0x00002c0c
938#define RCVBDI_MINI_PROD_IDX 0x00002c10
939#define RCVBDI_MINI_THRESH 0x00002c14
940#define RCVBDI_STD_THRESH 0x00002c18
941#define RCVBDI_JUMBO_THRESH 0x00002c1c
942/* 0x2c20 --> 0x3000 unused */
943
944/* Receive BD Completion Control Registers */
945#define RCVCC_MODE 0x00003000
946#define RCVCC_MODE_RESET 0x00000001
947#define RCVCC_MODE_ENABLE 0x00000002
948#define RCVCC_MODE_ATTN_ENABLE 0x00000004
949#define RCVCC_STATUS 0x00003004
950#define RCVCC_STATUS_ERROR_ATTN 0x00000004
951#define RCVCC_JUMP_PROD_IDX 0x00003008
952#define RCVCC_STD_PROD_IDX 0x0000300c
953#define RCVCC_MINI_PROD_IDX 0x00003010
954/* 0x3014 --> 0x3400 unused */
955
956/* Receive list selector control registers */
957#define RCVLSC_MODE 0x00003400
958#define RCVLSC_MODE_RESET 0x00000001
959#define RCVLSC_MODE_ENABLE 0x00000002
960#define RCVLSC_MODE_ATTN_ENABLE 0x00000004
961#define RCVLSC_STATUS 0x00003404
962#define RCVLSC_STATUS_ERROR_ATTN 0x00000004
Matt Carlsond30cdd22007-10-07 23:28:35 -0700963/* 0x3408 --> 0x3600 unused */
964
965/* CPMU registers */
966#define TG3_CPMU_CTRL 0x00003600
967#define CPMU_CTRL_LINK_IDLE_MODE 0x00000200
968#define CPMU_CTRL_LINK_AWARE_MODE 0x00000400
Matt Carlson9936bcf2007-10-10 18:03:07 -0700969#define CPMU_CTRL_LINK_SPEED_MODE 0x00004000
Matt Carlsonb2a5c192008-04-03 21:44:44 -0700970#define CPMU_CTRL_GPHY_10MB_RXONLY 0x00010000
Matt Carlson9acb9612007-11-12 21:10:06 -0800971#define TG3_CPMU_LSPD_10MB_CLK 0x00003604
972#define CPMU_LSPD_10MB_MACCLK_MASK 0x001f0000
973#define CPMU_LSPD_10MB_MACCLK_6_25 0x00130000
974/* 0x3608 --> 0x360c unused */
Matt Carlsonce057f02007-11-12 21:08:03 -0800975
976#define TG3_CPMU_LSPD_1000MB_CLK 0x0000360c
977#define CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000
978#define CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000
979#define CPMU_LSPD_1000MB_MACCLK_MASK 0x001f0000
Matt Carlson9acb9612007-11-12 21:10:06 -0800980#define TG3_CPMU_LNK_AWARE_PWRMD 0x00003610
981#define CPMU_LNK_AWARE_MACCLK_MASK 0x001f0000
982#define CPMU_LNK_AWARE_MACCLK_6_25 0x00130000
983/* 0x3614 --> 0x361c unused */
984
985#define TG3_CPMU_HST_ACC 0x0000361c
986#define CPMU_HST_ACC_MACCLK_MASK 0x001f0000
987#define CPMU_HST_ACC_MACCLK_6_25 0x00130000
Matt Carlsonaa6c91f2007-11-12 21:18:04 -0800988/* 0x3620 --> 0x3630 unused */
989
990#define TG3_CPMU_CLCK_STAT 0x00003630
991#define CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001f0000
992#define CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000
993#define CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000
994#define CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000
995/* 0x3634 --> 0x365c unused */
Matt Carlson9936bcf2007-10-10 18:03:07 -0700996
997#define TG3_CPMU_MUTEX_REQ 0x0000365c
998#define CPMU_MUTEX_REQ_DRIVER 0x00001000
999#define TG3_CPMU_MUTEX_GNT 0x00003660
1000#define CPMU_MUTEX_GNT_DRIVER 0x00001000
1001/* 0x3664 --> 0x3800 unused */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001002
1003/* Mbuf cluster free registers */
1004#define MBFREE_MODE 0x00003800
1005#define MBFREE_MODE_RESET 0x00000001
1006#define MBFREE_MODE_ENABLE 0x00000002
1007#define MBFREE_STATUS 0x00003804
1008/* 0x3808 --> 0x3c00 unused */
1009
1010/* Host coalescing control registers */
1011#define HOSTCC_MODE 0x00003c00
1012#define HOSTCC_MODE_RESET 0x00000001
1013#define HOSTCC_MODE_ENABLE 0x00000002
1014#define HOSTCC_MODE_ATTN 0x00000004
1015#define HOSTCC_MODE_NOW 0x00000008
1016#define HOSTCC_MODE_FULL_STATUS 0x00000000
1017#define HOSTCC_MODE_64BYTE 0x00000080
1018#define HOSTCC_MODE_32BYTE 0x00000100
1019#define HOSTCC_MODE_CLRTICK_RXBD 0x00000200
1020#define HOSTCC_MODE_CLRTICK_TXBD 0x00000400
1021#define HOSTCC_MODE_NOINT_ON_NOW 0x00000800
1022#define HOSTCC_MODE_NOINT_ON_FORCE 0x00001000
1023#define HOSTCC_STATUS 0x00003c04
1024#define HOSTCC_STATUS_ERROR_ATTN 0x00000004
1025#define HOSTCC_RXCOL_TICKS 0x00003c08
1026#define LOW_RXCOL_TICKS 0x00000032
David S. Miller15f98502005-05-18 22:49:26 -07001027#define LOW_RXCOL_TICKS_CLRTCKS 0x00000014
Linus Torvalds1da177e2005-04-16 15:20:36 -07001028#define DEFAULT_RXCOL_TICKS 0x00000048
1029#define HIGH_RXCOL_TICKS 0x00000096
Michael Chand244c892005-07-05 14:42:33 -07001030#define MAX_RXCOL_TICKS 0x000003ff
Linus Torvalds1da177e2005-04-16 15:20:36 -07001031#define HOSTCC_TXCOL_TICKS 0x00003c0c
1032#define LOW_TXCOL_TICKS 0x00000096
David S. Miller15f98502005-05-18 22:49:26 -07001033#define LOW_TXCOL_TICKS_CLRTCKS 0x00000048
Linus Torvalds1da177e2005-04-16 15:20:36 -07001034#define DEFAULT_TXCOL_TICKS 0x0000012c
1035#define HIGH_TXCOL_TICKS 0x00000145
Michael Chand244c892005-07-05 14:42:33 -07001036#define MAX_TXCOL_TICKS 0x000003ff
Linus Torvalds1da177e2005-04-16 15:20:36 -07001037#define HOSTCC_RXMAX_FRAMES 0x00003c10
1038#define LOW_RXMAX_FRAMES 0x00000005
1039#define DEFAULT_RXMAX_FRAMES 0x00000008
1040#define HIGH_RXMAX_FRAMES 0x00000012
Michael Chand244c892005-07-05 14:42:33 -07001041#define MAX_RXMAX_FRAMES 0x000000ff
Linus Torvalds1da177e2005-04-16 15:20:36 -07001042#define HOSTCC_TXMAX_FRAMES 0x00003c14
1043#define LOW_TXMAX_FRAMES 0x00000035
1044#define DEFAULT_TXMAX_FRAMES 0x0000004b
1045#define HIGH_TXMAX_FRAMES 0x00000052
Michael Chand244c892005-07-05 14:42:33 -07001046#define MAX_TXMAX_FRAMES 0x000000ff
Linus Torvalds1da177e2005-04-16 15:20:36 -07001047#define HOSTCC_RXCOAL_TICK_INT 0x00003c18
1048#define DEFAULT_RXCOAL_TICK_INT 0x00000019
David S. Miller15f98502005-05-18 22:49:26 -07001049#define DEFAULT_RXCOAL_TICK_INT_CLRTCKS 0x00000014
Michael Chand244c892005-07-05 14:42:33 -07001050#define MAX_RXCOAL_TICK_INT 0x000003ff
Linus Torvalds1da177e2005-04-16 15:20:36 -07001051#define HOSTCC_TXCOAL_TICK_INT 0x00003c1c
1052#define DEFAULT_TXCOAL_TICK_INT 0x00000019
David S. Miller15f98502005-05-18 22:49:26 -07001053#define DEFAULT_TXCOAL_TICK_INT_CLRTCKS 0x00000014
Michael Chand244c892005-07-05 14:42:33 -07001054#define MAX_TXCOAL_TICK_INT 0x000003ff
Linus Torvalds1da177e2005-04-16 15:20:36 -07001055#define HOSTCC_RXCOAL_MAXF_INT 0x00003c20
1056#define DEFAULT_RXCOAL_MAXF_INT 0x00000005
Michael Chand244c892005-07-05 14:42:33 -07001057#define MAX_RXCOAL_MAXF_INT 0x000000ff
Linus Torvalds1da177e2005-04-16 15:20:36 -07001058#define HOSTCC_TXCOAL_MAXF_INT 0x00003c24
1059#define DEFAULT_TXCOAL_MAXF_INT 0x00000005
Michael Chand244c892005-07-05 14:42:33 -07001060#define MAX_TXCOAL_MAXF_INT 0x000000ff
Linus Torvalds1da177e2005-04-16 15:20:36 -07001061#define HOSTCC_STAT_COAL_TICKS 0x00003c28
1062#define DEFAULT_STAT_COAL_TICKS 0x000f4240
Michael Chand244c892005-07-05 14:42:33 -07001063#define MAX_STAT_COAL_TICKS 0xd693d400
1064#define MIN_STAT_COAL_TICKS 0x00000064
Linus Torvalds1da177e2005-04-16 15:20:36 -07001065/* 0x3c2c --> 0x3c30 unused */
1066#define HOSTCC_STATS_BLK_HOST_ADDR 0x00003c30 /* 64-bit */
1067#define HOSTCC_STATUS_BLK_HOST_ADDR 0x00003c38 /* 64-bit */
1068#define HOSTCC_STATS_BLK_NIC_ADDR 0x00003c40
1069#define HOSTCC_STATUS_BLK_NIC_ADDR 0x00003c44
1070#define HOSTCC_FLOW_ATTN 0x00003c48
1071/* 0x3c4c --> 0x3c50 unused */
1072#define HOSTCC_JUMBO_CON_IDX 0x00003c50
1073#define HOSTCC_STD_CON_IDX 0x00003c54
1074#define HOSTCC_MINI_CON_IDX 0x00003c58
1075/* 0x3c5c --> 0x3c80 unused */
1076#define HOSTCC_RET_PROD_IDX_0 0x00003c80
1077#define HOSTCC_RET_PROD_IDX_1 0x00003c84
1078#define HOSTCC_RET_PROD_IDX_2 0x00003c88
1079#define HOSTCC_RET_PROD_IDX_3 0x00003c8c
1080#define HOSTCC_RET_PROD_IDX_4 0x00003c90
1081#define HOSTCC_RET_PROD_IDX_5 0x00003c94
1082#define HOSTCC_RET_PROD_IDX_6 0x00003c98
1083#define HOSTCC_RET_PROD_IDX_7 0x00003c9c
1084#define HOSTCC_RET_PROD_IDX_8 0x00003ca0
1085#define HOSTCC_RET_PROD_IDX_9 0x00003ca4
1086#define HOSTCC_RET_PROD_IDX_10 0x00003ca8
1087#define HOSTCC_RET_PROD_IDX_11 0x00003cac
1088#define HOSTCC_RET_PROD_IDX_12 0x00003cb0
1089#define HOSTCC_RET_PROD_IDX_13 0x00003cb4
1090#define HOSTCC_RET_PROD_IDX_14 0x00003cb8
1091#define HOSTCC_RET_PROD_IDX_15 0x00003cbc
1092#define HOSTCC_SND_CON_IDX_0 0x00003cc0
1093#define HOSTCC_SND_CON_IDX_1 0x00003cc4
1094#define HOSTCC_SND_CON_IDX_2 0x00003cc8
1095#define HOSTCC_SND_CON_IDX_3 0x00003ccc
1096#define HOSTCC_SND_CON_IDX_4 0x00003cd0
1097#define HOSTCC_SND_CON_IDX_5 0x00003cd4
1098#define HOSTCC_SND_CON_IDX_6 0x00003cd8
1099#define HOSTCC_SND_CON_IDX_7 0x00003cdc
1100#define HOSTCC_SND_CON_IDX_8 0x00003ce0
1101#define HOSTCC_SND_CON_IDX_9 0x00003ce4
1102#define HOSTCC_SND_CON_IDX_10 0x00003ce8
1103#define HOSTCC_SND_CON_IDX_11 0x00003cec
1104#define HOSTCC_SND_CON_IDX_12 0x00003cf0
1105#define HOSTCC_SND_CON_IDX_13 0x00003cf4
1106#define HOSTCC_SND_CON_IDX_14 0x00003cf8
1107#define HOSTCC_SND_CON_IDX_15 0x00003cfc
1108/* 0x3d00 --> 0x4000 unused */
1109
1110/* Memory arbiter control registers */
1111#define MEMARB_MODE 0x00004000
1112#define MEMARB_MODE_RESET 0x00000001
1113#define MEMARB_MODE_ENABLE 0x00000002
1114#define MEMARB_STATUS 0x00004004
1115#define MEMARB_TRAP_ADDR_LOW 0x00004008
1116#define MEMARB_TRAP_ADDR_HIGH 0x0000400c
1117/* 0x4010 --> 0x4400 unused */
1118
1119/* Buffer manager control registers */
1120#define BUFMGR_MODE 0x00004400
1121#define BUFMGR_MODE_RESET 0x00000001
1122#define BUFMGR_MODE_ENABLE 0x00000002
1123#define BUFMGR_MODE_ATTN_ENABLE 0x00000004
1124#define BUFMGR_MODE_BM_TEST 0x00000008
1125#define BUFMGR_MODE_MBLOW_ATTN_ENAB 0x00000010
1126#define BUFMGR_STATUS 0x00004404
1127#define BUFMGR_STATUS_ERROR 0x00000004
1128#define BUFMGR_STATUS_MBLOW 0x00000010
1129#define BUFMGR_MB_POOL_ADDR 0x00004408
1130#define BUFMGR_MB_POOL_SIZE 0x0000440c
1131#define BUFMGR_MB_RDMA_LOW_WATER 0x00004410
1132#define DEFAULT_MB_RDMA_LOW_WATER 0x00000050
1133#define DEFAULT_MB_RDMA_LOW_WATER_5705 0x00000000
1134#define DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130
Michael Chanfdfec1722005-07-25 12:31:48 -07001135#define DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780 0x00000000
Linus Torvalds1da177e2005-04-16 15:20:36 -07001136#define BUFMGR_MB_MACRX_LOW_WATER 0x00004414
1137#define DEFAULT_MB_MACRX_LOW_WATER 0x00000020
1138#define DEFAULT_MB_MACRX_LOW_WATER_5705 0x00000010
Michael Chanb5d37722006-09-27 16:06:21 -07001139#define DEFAULT_MB_MACRX_LOW_WATER_5906 0x00000004
Linus Torvalds1da177e2005-04-16 15:20:36 -07001140#define DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098
Michael Chanfdfec1722005-07-25 12:31:48 -07001141#define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780 0x0000004b
Linus Torvalds1da177e2005-04-16 15:20:36 -07001142#define BUFMGR_MB_HIGH_WATER 0x00004418
1143#define DEFAULT_MB_HIGH_WATER 0x00000060
1144#define DEFAULT_MB_HIGH_WATER_5705 0x00000060
Michael Chanb5d37722006-09-27 16:06:21 -07001145#define DEFAULT_MB_HIGH_WATER_5906 0x00000010
Linus Torvalds1da177e2005-04-16 15:20:36 -07001146#define DEFAULT_MB_HIGH_WATER_JUMBO 0x0000017c
Michael Chanfdfec1722005-07-25 12:31:48 -07001147#define DEFAULT_MB_HIGH_WATER_JUMBO_5780 0x00000096
Linus Torvalds1da177e2005-04-16 15:20:36 -07001148#define BUFMGR_RX_MB_ALLOC_REQ 0x0000441c
1149#define BUFMGR_MB_ALLOC_BIT 0x10000000
1150#define BUFMGR_RX_MB_ALLOC_RESP 0x00004420
1151#define BUFMGR_TX_MB_ALLOC_REQ 0x00004424
1152#define BUFMGR_TX_MB_ALLOC_RESP 0x00004428
1153#define BUFMGR_DMA_DESC_POOL_ADDR 0x0000442c
1154#define BUFMGR_DMA_DESC_POOL_SIZE 0x00004430
1155#define BUFMGR_DMA_LOW_WATER 0x00004434
1156#define DEFAULT_DMA_LOW_WATER 0x00000005
1157#define BUFMGR_DMA_HIGH_WATER 0x00004438
1158#define DEFAULT_DMA_HIGH_WATER 0x0000000a
1159#define BUFMGR_RX_DMA_ALLOC_REQ 0x0000443c
1160#define BUFMGR_RX_DMA_ALLOC_RESP 0x00004440
1161#define BUFMGR_TX_DMA_ALLOC_REQ 0x00004444
1162#define BUFMGR_TX_DMA_ALLOC_RESP 0x00004448
1163#define BUFMGR_HWDIAG_0 0x0000444c
1164#define BUFMGR_HWDIAG_1 0x00004450
1165#define BUFMGR_HWDIAG_2 0x00004454
1166/* 0x4458 --> 0x4800 unused */
1167
1168/* Read DMA control registers */
1169#define RDMAC_MODE 0x00004800
1170#define RDMAC_MODE_RESET 0x00000001
1171#define RDMAC_MODE_ENABLE 0x00000002
1172#define RDMAC_MODE_TGTABORT_ENAB 0x00000004
1173#define RDMAC_MODE_MSTABORT_ENAB 0x00000008
1174#define RDMAC_MODE_PARITYERR_ENAB 0x00000010
1175#define RDMAC_MODE_ADDROFLOW_ENAB 0x00000020
1176#define RDMAC_MODE_FIFOOFLOW_ENAB 0x00000040
1177#define RDMAC_MODE_FIFOURUN_ENAB 0x00000080
1178#define RDMAC_MODE_FIFOOREAD_ENAB 0x00000100
1179#define RDMAC_MODE_LNGREAD_ENAB 0x00000200
1180#define RDMAC_MODE_SPLIT_ENABLE 0x00000800
Matt Carlsond30cdd22007-10-07 23:28:35 -07001181#define RDMAC_MODE_BD_SBD_CRPT_ENAB 0x00000800
Linus Torvalds1da177e2005-04-16 15:20:36 -07001182#define RDMAC_MODE_SPLIT_RESET 0x00001000
Matt Carlsond30cdd22007-10-07 23:28:35 -07001183#define RDMAC_MODE_MBUF_RBD_CRPT_ENAB 0x00001000
1184#define RDMAC_MODE_MBUF_SBD_CRPT_ENAB 0x00002000
Linus Torvalds1da177e2005-04-16 15:20:36 -07001185#define RDMAC_MODE_FIFO_SIZE_128 0x00020000
1186#define RDMAC_MODE_FIFO_LONG_BURST 0x00030000
Matt Carlson027455a2008-12-21 20:19:30 -08001187#define RDMAC_MODE_IPV4_LSO_EN 0x08000000
1188#define RDMAC_MODE_IPV6_LSO_EN 0x10000000
Linus Torvalds1da177e2005-04-16 15:20:36 -07001189#define RDMAC_STATUS 0x00004804
1190#define RDMAC_STATUS_TGTABORT 0x00000004
1191#define RDMAC_STATUS_MSTABORT 0x00000008
1192#define RDMAC_STATUS_PARITYERR 0x00000010
1193#define RDMAC_STATUS_ADDROFLOW 0x00000020
1194#define RDMAC_STATUS_FIFOOFLOW 0x00000040
1195#define RDMAC_STATUS_FIFOURUN 0x00000080
1196#define RDMAC_STATUS_FIFOOREAD 0x00000100
1197#define RDMAC_STATUS_LNGREAD 0x00000200
1198/* 0x4808 --> 0x4c00 unused */
1199
1200/* Write DMA control registers */
1201#define WDMAC_MODE 0x00004c00
1202#define WDMAC_MODE_RESET 0x00000001
1203#define WDMAC_MODE_ENABLE 0x00000002
1204#define WDMAC_MODE_TGTABORT_ENAB 0x00000004
1205#define WDMAC_MODE_MSTABORT_ENAB 0x00000008
1206#define WDMAC_MODE_PARITYERR_ENAB 0x00000010
1207#define WDMAC_MODE_ADDROFLOW_ENAB 0x00000020
1208#define WDMAC_MODE_FIFOOFLOW_ENAB 0x00000040
1209#define WDMAC_MODE_FIFOURUN_ENAB 0x00000080
1210#define WDMAC_MODE_FIFOOREAD_ENAB 0x00000100
1211#define WDMAC_MODE_LNGREAD_ENAB 0x00000200
1212#define WDMAC_MODE_RX_ACCEL 0x00000400
Matt Carlsonf51f3562008-05-25 23:45:08 -07001213#define WDMAC_MODE_STATUS_TAG_FIX 0x20000000
Linus Torvalds1da177e2005-04-16 15:20:36 -07001214#define WDMAC_STATUS 0x00004c04
1215#define WDMAC_STATUS_TGTABORT 0x00000004
1216#define WDMAC_STATUS_MSTABORT 0x00000008
1217#define WDMAC_STATUS_PARITYERR 0x00000010
1218#define WDMAC_STATUS_ADDROFLOW 0x00000020
1219#define WDMAC_STATUS_FIFOOFLOW 0x00000040
1220#define WDMAC_STATUS_FIFOURUN 0x00000080
1221#define WDMAC_STATUS_FIFOOREAD 0x00000100
1222#define WDMAC_STATUS_LNGREAD 0x00000200
1223/* 0x4c08 --> 0x5000 unused */
1224
1225/* Per-cpu register offsets (arm9) */
1226#define CPU_MODE 0x00000000
1227#define CPU_MODE_RESET 0x00000001
1228#define CPU_MODE_HALT 0x00000400
1229#define CPU_STATE 0x00000004
1230#define CPU_EVTMASK 0x00000008
1231/* 0xc --> 0x1c reserved */
1232#define CPU_PC 0x0000001c
1233#define CPU_INSN 0x00000020
1234#define CPU_SPAD_UFLOW 0x00000024
1235#define CPU_WDOG_CLEAR 0x00000028
1236#define CPU_WDOG_VECTOR 0x0000002c
1237#define CPU_WDOG_PC 0x00000030
1238#define CPU_HW_BP 0x00000034
1239/* 0x38 --> 0x44 unused */
1240#define CPU_WDOG_SAVED_STATE 0x00000044
1241#define CPU_LAST_BRANCH_ADDR 0x00000048
1242#define CPU_SPAD_UFLOW_SET 0x0000004c
1243/* 0x50 --> 0x200 unused */
1244#define CPU_R0 0x00000200
1245#define CPU_R1 0x00000204
1246#define CPU_R2 0x00000208
1247#define CPU_R3 0x0000020c
1248#define CPU_R4 0x00000210
1249#define CPU_R5 0x00000214
1250#define CPU_R6 0x00000218
1251#define CPU_R7 0x0000021c
1252#define CPU_R8 0x00000220
1253#define CPU_R9 0x00000224
1254#define CPU_R10 0x00000228
1255#define CPU_R11 0x0000022c
1256#define CPU_R12 0x00000230
1257#define CPU_R13 0x00000234
1258#define CPU_R14 0x00000238
1259#define CPU_R15 0x0000023c
1260#define CPU_R16 0x00000240
1261#define CPU_R17 0x00000244
1262#define CPU_R18 0x00000248
1263#define CPU_R19 0x0000024c
1264#define CPU_R20 0x00000250
1265#define CPU_R21 0x00000254
1266#define CPU_R22 0x00000258
1267#define CPU_R23 0x0000025c
1268#define CPU_R24 0x00000260
1269#define CPU_R25 0x00000264
1270#define CPU_R26 0x00000268
1271#define CPU_R27 0x0000026c
1272#define CPU_R28 0x00000270
1273#define CPU_R29 0x00000274
1274#define CPU_R30 0x00000278
1275#define CPU_R31 0x0000027c
1276/* 0x280 --> 0x400 unused */
1277
1278#define RX_CPU_BASE 0x00005000
Chris Elmquist091465d2005-12-20 13:25:19 -08001279#define RX_CPU_MODE 0x00005000
1280#define RX_CPU_STATE 0x00005004
1281#define RX_CPU_PGMCTR 0x0000501c
1282#define RX_CPU_HWBKPT 0x00005034
Linus Torvalds1da177e2005-04-16 15:20:36 -07001283#define TX_CPU_BASE 0x00005400
Chris Elmquist091465d2005-12-20 13:25:19 -08001284#define TX_CPU_MODE 0x00005400
1285#define TX_CPU_STATE 0x00005404
1286#define TX_CPU_PGMCTR 0x0000541c
Linus Torvalds1da177e2005-04-16 15:20:36 -07001287
Michael Chanb5d37722006-09-27 16:06:21 -07001288#define VCPU_STATUS 0x00005100
1289#define VCPU_STATUS_INIT_DONE 0x04000000
1290#define VCPU_STATUS_DRV_RESET 0x08000000
1291
Matt Carlson8ed5d972007-05-07 00:25:49 -07001292#define VCPU_CFGSHDW 0x00005104
Matt Carlson0527ba32007-10-10 18:03:30 -07001293#define VCPU_CFGSHDW_WOL_ENABLE 0x00000001
1294#define VCPU_CFGSHDW_WOL_MAGPKT 0x00000004
Matt Carlson8ed5d972007-05-07 00:25:49 -07001295#define VCPU_CFGSHDW_ASPM_DBNC 0x00001000
1296
Linus Torvalds1da177e2005-04-16 15:20:36 -07001297/* Mailboxes */
Michael Chanb5d37722006-09-27 16:06:21 -07001298#define GRCMBOX_BASE 0x00005600
Linus Torvalds1da177e2005-04-16 15:20:36 -07001299#define GRCMBOX_INTERRUPT_0 0x00005800 /* 64-bit */
1300#define GRCMBOX_INTERRUPT_1 0x00005808 /* 64-bit */
1301#define GRCMBOX_INTERRUPT_2 0x00005810 /* 64-bit */
1302#define GRCMBOX_INTERRUPT_3 0x00005818 /* 64-bit */
1303#define GRCMBOX_GENERAL_0 0x00005820 /* 64-bit */
1304#define GRCMBOX_GENERAL_1 0x00005828 /* 64-bit */
1305#define GRCMBOX_GENERAL_2 0x00005830 /* 64-bit */
1306#define GRCMBOX_GENERAL_3 0x00005838 /* 64-bit */
1307#define GRCMBOX_GENERAL_4 0x00005840 /* 64-bit */
1308#define GRCMBOX_GENERAL_5 0x00005848 /* 64-bit */
1309#define GRCMBOX_GENERAL_6 0x00005850 /* 64-bit */
1310#define GRCMBOX_GENERAL_7 0x00005858 /* 64-bit */
1311#define GRCMBOX_RELOAD_STAT 0x00005860 /* 64-bit */
1312#define GRCMBOX_RCVSTD_PROD_IDX 0x00005868 /* 64-bit */
1313#define GRCMBOX_RCVJUMBO_PROD_IDX 0x00005870 /* 64-bit */
1314#define GRCMBOX_RCVMINI_PROD_IDX 0x00005878 /* 64-bit */
1315#define GRCMBOX_RCVRET_CON_IDX_0 0x00005880 /* 64-bit */
1316#define GRCMBOX_RCVRET_CON_IDX_1 0x00005888 /* 64-bit */
1317#define GRCMBOX_RCVRET_CON_IDX_2 0x00005890 /* 64-bit */
1318#define GRCMBOX_RCVRET_CON_IDX_3 0x00005898 /* 64-bit */
1319#define GRCMBOX_RCVRET_CON_IDX_4 0x000058a0 /* 64-bit */
1320#define GRCMBOX_RCVRET_CON_IDX_5 0x000058a8 /* 64-bit */
1321#define GRCMBOX_RCVRET_CON_IDX_6 0x000058b0 /* 64-bit */
1322#define GRCMBOX_RCVRET_CON_IDX_7 0x000058b8 /* 64-bit */
1323#define GRCMBOX_RCVRET_CON_IDX_8 0x000058c0 /* 64-bit */
1324#define GRCMBOX_RCVRET_CON_IDX_9 0x000058c8 /* 64-bit */
1325#define GRCMBOX_RCVRET_CON_IDX_10 0x000058d0 /* 64-bit */
1326#define GRCMBOX_RCVRET_CON_IDX_11 0x000058d8 /* 64-bit */
1327#define GRCMBOX_RCVRET_CON_IDX_12 0x000058e0 /* 64-bit */
1328#define GRCMBOX_RCVRET_CON_IDX_13 0x000058e8 /* 64-bit */
1329#define GRCMBOX_RCVRET_CON_IDX_14 0x000058f0 /* 64-bit */
1330#define GRCMBOX_RCVRET_CON_IDX_15 0x000058f8 /* 64-bit */
1331#define GRCMBOX_SNDHOST_PROD_IDX_0 0x00005900 /* 64-bit */
1332#define GRCMBOX_SNDHOST_PROD_IDX_1 0x00005908 /* 64-bit */
1333#define GRCMBOX_SNDHOST_PROD_IDX_2 0x00005910 /* 64-bit */
1334#define GRCMBOX_SNDHOST_PROD_IDX_3 0x00005918 /* 64-bit */
1335#define GRCMBOX_SNDHOST_PROD_IDX_4 0x00005920 /* 64-bit */
1336#define GRCMBOX_SNDHOST_PROD_IDX_5 0x00005928 /* 64-bit */
1337#define GRCMBOX_SNDHOST_PROD_IDX_6 0x00005930 /* 64-bit */
1338#define GRCMBOX_SNDHOST_PROD_IDX_7 0x00005938 /* 64-bit */
1339#define GRCMBOX_SNDHOST_PROD_IDX_8 0x00005940 /* 64-bit */
1340#define GRCMBOX_SNDHOST_PROD_IDX_9 0x00005948 /* 64-bit */
1341#define GRCMBOX_SNDHOST_PROD_IDX_10 0x00005950 /* 64-bit */
1342#define GRCMBOX_SNDHOST_PROD_IDX_11 0x00005958 /* 64-bit */
1343#define GRCMBOX_SNDHOST_PROD_IDX_12 0x00005960 /* 64-bit */
1344#define GRCMBOX_SNDHOST_PROD_IDX_13 0x00005968 /* 64-bit */
1345#define GRCMBOX_SNDHOST_PROD_IDX_14 0x00005970 /* 64-bit */
1346#define GRCMBOX_SNDHOST_PROD_IDX_15 0x00005978 /* 64-bit */
1347#define GRCMBOX_SNDNIC_PROD_IDX_0 0x00005980 /* 64-bit */
1348#define GRCMBOX_SNDNIC_PROD_IDX_1 0x00005988 /* 64-bit */
1349#define GRCMBOX_SNDNIC_PROD_IDX_2 0x00005990 /* 64-bit */
1350#define GRCMBOX_SNDNIC_PROD_IDX_3 0x00005998 /* 64-bit */
1351#define GRCMBOX_SNDNIC_PROD_IDX_4 0x000059a0 /* 64-bit */
1352#define GRCMBOX_SNDNIC_PROD_IDX_5 0x000059a8 /* 64-bit */
1353#define GRCMBOX_SNDNIC_PROD_IDX_6 0x000059b0 /* 64-bit */
1354#define GRCMBOX_SNDNIC_PROD_IDX_7 0x000059b8 /* 64-bit */
1355#define GRCMBOX_SNDNIC_PROD_IDX_8 0x000059c0 /* 64-bit */
1356#define GRCMBOX_SNDNIC_PROD_IDX_9 0x000059c8 /* 64-bit */
1357#define GRCMBOX_SNDNIC_PROD_IDX_10 0x000059d0 /* 64-bit */
1358#define GRCMBOX_SNDNIC_PROD_IDX_11 0x000059d8 /* 64-bit */
1359#define GRCMBOX_SNDNIC_PROD_IDX_12 0x000059e0 /* 64-bit */
1360#define GRCMBOX_SNDNIC_PROD_IDX_13 0x000059e8 /* 64-bit */
1361#define GRCMBOX_SNDNIC_PROD_IDX_14 0x000059f0 /* 64-bit */
1362#define GRCMBOX_SNDNIC_PROD_IDX_15 0x000059f8 /* 64-bit */
1363#define GRCMBOX_HIGH_PRIO_EV_VECTOR 0x00005a00
1364#define GRCMBOX_HIGH_PRIO_EV_MASK 0x00005a04
1365#define GRCMBOX_LOW_PRIO_EV_VEC 0x00005a08
1366#define GRCMBOX_LOW_PRIO_EV_MASK 0x00005a0c
1367/* 0x5a10 --> 0x5c00 */
1368
1369/* Flow Through queues */
1370#define FTQ_RESET 0x00005c00
1371/* 0x5c04 --> 0x5c10 unused */
1372#define FTQ_DMA_NORM_READ_CTL 0x00005c10
1373#define FTQ_DMA_NORM_READ_FULL_CNT 0x00005c14
1374#define FTQ_DMA_NORM_READ_FIFO_ENQDEQ 0x00005c18
1375#define FTQ_DMA_NORM_READ_WRITE_PEEK 0x00005c1c
1376#define FTQ_DMA_HIGH_READ_CTL 0x00005c20
1377#define FTQ_DMA_HIGH_READ_FULL_CNT 0x00005c24
1378#define FTQ_DMA_HIGH_READ_FIFO_ENQDEQ 0x00005c28
1379#define FTQ_DMA_HIGH_READ_WRITE_PEEK 0x00005c2c
1380#define FTQ_DMA_COMP_DISC_CTL 0x00005c30
1381#define FTQ_DMA_COMP_DISC_FULL_CNT 0x00005c34
1382#define FTQ_DMA_COMP_DISC_FIFO_ENQDEQ 0x00005c38
1383#define FTQ_DMA_COMP_DISC_WRITE_PEEK 0x00005c3c
1384#define FTQ_SEND_BD_COMP_CTL 0x00005c40
1385#define FTQ_SEND_BD_COMP_FULL_CNT 0x00005c44
1386#define FTQ_SEND_BD_COMP_FIFO_ENQDEQ 0x00005c48
1387#define FTQ_SEND_BD_COMP_WRITE_PEEK 0x00005c4c
1388#define FTQ_SEND_DATA_INIT_CTL 0x00005c50
1389#define FTQ_SEND_DATA_INIT_FULL_CNT 0x00005c54
1390#define FTQ_SEND_DATA_INIT_FIFO_ENQDEQ 0x00005c58
1391#define FTQ_SEND_DATA_INIT_WRITE_PEEK 0x00005c5c
1392#define FTQ_DMA_NORM_WRITE_CTL 0x00005c60
1393#define FTQ_DMA_NORM_WRITE_FULL_CNT 0x00005c64
1394#define FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ 0x00005c68
1395#define FTQ_DMA_NORM_WRITE_WRITE_PEEK 0x00005c6c
1396#define FTQ_DMA_HIGH_WRITE_CTL 0x00005c70
1397#define FTQ_DMA_HIGH_WRITE_FULL_CNT 0x00005c74
1398#define FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ 0x00005c78
1399#define FTQ_DMA_HIGH_WRITE_WRITE_PEEK 0x00005c7c
1400#define FTQ_SWTYPE1_CTL 0x00005c80
1401#define FTQ_SWTYPE1_FULL_CNT 0x00005c84
1402#define FTQ_SWTYPE1_FIFO_ENQDEQ 0x00005c88
1403#define FTQ_SWTYPE1_WRITE_PEEK 0x00005c8c
1404#define FTQ_SEND_DATA_COMP_CTL 0x00005c90
1405#define FTQ_SEND_DATA_COMP_FULL_CNT 0x00005c94
1406#define FTQ_SEND_DATA_COMP_FIFO_ENQDEQ 0x00005c98
1407#define FTQ_SEND_DATA_COMP_WRITE_PEEK 0x00005c9c
1408#define FTQ_HOST_COAL_CTL 0x00005ca0
1409#define FTQ_HOST_COAL_FULL_CNT 0x00005ca4
1410#define FTQ_HOST_COAL_FIFO_ENQDEQ 0x00005ca8
1411#define FTQ_HOST_COAL_WRITE_PEEK 0x00005cac
1412#define FTQ_MAC_TX_CTL 0x00005cb0
1413#define FTQ_MAC_TX_FULL_CNT 0x00005cb4
1414#define FTQ_MAC_TX_FIFO_ENQDEQ 0x00005cb8
1415#define FTQ_MAC_TX_WRITE_PEEK 0x00005cbc
1416#define FTQ_MB_FREE_CTL 0x00005cc0
1417#define FTQ_MB_FREE_FULL_CNT 0x00005cc4
1418#define FTQ_MB_FREE_FIFO_ENQDEQ 0x00005cc8
1419#define FTQ_MB_FREE_WRITE_PEEK 0x00005ccc
1420#define FTQ_RCVBD_COMP_CTL 0x00005cd0
1421#define FTQ_RCVBD_COMP_FULL_CNT 0x00005cd4
1422#define FTQ_RCVBD_COMP_FIFO_ENQDEQ 0x00005cd8
1423#define FTQ_RCVBD_COMP_WRITE_PEEK 0x00005cdc
1424#define FTQ_RCVLST_PLMT_CTL 0x00005ce0
1425#define FTQ_RCVLST_PLMT_FULL_CNT 0x00005ce4
1426#define FTQ_RCVLST_PLMT_FIFO_ENQDEQ 0x00005ce8
1427#define FTQ_RCVLST_PLMT_WRITE_PEEK 0x00005cec
1428#define FTQ_RCVDATA_INI_CTL 0x00005cf0
1429#define FTQ_RCVDATA_INI_FULL_CNT 0x00005cf4
1430#define FTQ_RCVDATA_INI_FIFO_ENQDEQ 0x00005cf8
1431#define FTQ_RCVDATA_INI_WRITE_PEEK 0x00005cfc
1432#define FTQ_RCVDATA_COMP_CTL 0x00005d00
1433#define FTQ_RCVDATA_COMP_FULL_CNT 0x00005d04
1434#define FTQ_RCVDATA_COMP_FIFO_ENQDEQ 0x00005d08
1435#define FTQ_RCVDATA_COMP_WRITE_PEEK 0x00005d0c
1436#define FTQ_SWTYPE2_CTL 0x00005d10
1437#define FTQ_SWTYPE2_FULL_CNT 0x00005d14
1438#define FTQ_SWTYPE2_FIFO_ENQDEQ 0x00005d18
1439#define FTQ_SWTYPE2_WRITE_PEEK 0x00005d1c
1440/* 0x5d20 --> 0x6000 unused */
1441
1442/* Message signaled interrupt registers */
1443#define MSGINT_MODE 0x00006000
1444#define MSGINT_MODE_RESET 0x00000001
1445#define MSGINT_MODE_ENABLE 0x00000002
1446#define MSGINT_STATUS 0x00006004
1447#define MSGINT_FIFO 0x00006008
1448/* 0x600c --> 0x6400 unused */
1449
1450/* DMA completion registers */
1451#define DMAC_MODE 0x00006400
1452#define DMAC_MODE_RESET 0x00000001
1453#define DMAC_MODE_ENABLE 0x00000002
1454/* 0x6404 --> 0x6800 unused */
1455
1456/* GRC registers */
1457#define GRC_MODE 0x00006800
1458#define GRC_MODE_UPD_ON_COAL 0x00000001
1459#define GRC_MODE_BSWAP_NONFRM_DATA 0x00000002
1460#define GRC_MODE_WSWAP_NONFRM_DATA 0x00000004
1461#define GRC_MODE_BSWAP_DATA 0x00000010
1462#define GRC_MODE_WSWAP_DATA 0x00000020
1463#define GRC_MODE_SPLITHDR 0x00000100
1464#define GRC_MODE_NOFRM_CRACKING 0x00000200
1465#define GRC_MODE_INCL_CRC 0x00000400
1466#define GRC_MODE_ALLOW_BAD_FRMS 0x00000800
1467#define GRC_MODE_NOIRQ_ON_SENDS 0x00002000
1468#define GRC_MODE_NOIRQ_ON_RCV 0x00004000
1469#define GRC_MODE_FORCE_PCI32BIT 0x00008000
1470#define GRC_MODE_HOST_STACKUP 0x00010000
1471#define GRC_MODE_HOST_SENDBDS 0x00020000
1472#define GRC_MODE_NO_TX_PHDR_CSUM 0x00100000
1473#define GRC_MODE_NVRAM_WR_ENABLE 0x00200000
1474#define GRC_MODE_NO_RX_PHDR_CSUM 0x00800000
1475#define GRC_MODE_IRQ_ON_TX_CPU_ATTN 0x01000000
1476#define GRC_MODE_IRQ_ON_RX_CPU_ATTN 0x02000000
1477#define GRC_MODE_IRQ_ON_MAC_ATTN 0x04000000
1478#define GRC_MODE_IRQ_ON_DMA_ATTN 0x08000000
1479#define GRC_MODE_IRQ_ON_FLOW_ATTN 0x10000000
1480#define GRC_MODE_4X_NIC_SEND_RINGS 0x20000000
1481#define GRC_MODE_MCAST_FRM_ENABLE 0x40000000
1482#define GRC_MISC_CFG 0x00006804
1483#define GRC_MISC_CFG_CORECLK_RESET 0x00000001
1484#define GRC_MISC_CFG_PRESCALAR_MASK 0x000000fe
1485#define GRC_MISC_CFG_PRESCALAR_SHIFT 1
1486#define GRC_MISC_CFG_BOARD_ID_MASK 0x0001e000
1487#define GRC_MISC_CFG_BOARD_ID_5700 0x0001e000
1488#define GRC_MISC_CFG_BOARD_ID_5701 0x00000000
1489#define GRC_MISC_CFG_BOARD_ID_5702FE 0x00004000
1490#define GRC_MISC_CFG_BOARD_ID_5703 0x00000000
1491#define GRC_MISC_CFG_BOARD_ID_5703S 0x00002000
1492#define GRC_MISC_CFG_BOARD_ID_5704 0x00000000
1493#define GRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000
1494#define GRC_MISC_CFG_BOARD_ID_5704_A2 0x00008000
1495#define GRC_MISC_CFG_BOARD_ID_5788 0x00010000
1496#define GRC_MISC_CFG_BOARD_ID_5788M 0x00018000
1497#define GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000
Michael Chan60189dd2006-12-17 17:08:07 -08001498#define GRC_MISC_CFG_EPHY_IDDQ 0x00200000
Linus Torvalds1da177e2005-04-16 15:20:36 -07001499#define GRC_MISC_CFG_KEEP_GPHY_POWER 0x04000000
1500#define GRC_LOCAL_CTRL 0x00006808
1501#define GRC_LCLCTRL_INT_ACTIVE 0x00000001
1502#define GRC_LCLCTRL_CLEARINT 0x00000002
1503#define GRC_LCLCTRL_SETINT 0x00000004
1504#define GRC_LCLCTRL_INT_ON_ATTN 0x00000008
Michael Chanaf36e6b2006-03-23 01:28:06 -08001505#define GRC_LCLCTRL_GPIO_UART_SEL 0x00000010 /* 5755 only */
Michael Chana4e2b342005-10-26 15:46:52 -07001506#define GRC_LCLCTRL_USE_SIG_DETECT 0x00000010 /* 5714/5780 only */
1507#define GRC_LCLCTRL_USE_EXT_SIG_DETECT 0x00000020 /* 5714/5780 only */
Michael Chan3e7d83b2005-04-21 17:10:36 -07001508#define GRC_LCLCTRL_GPIO_INPUT3 0x00000020
1509#define GRC_LCLCTRL_GPIO_OE3 0x00000040
1510#define GRC_LCLCTRL_GPIO_OUTPUT3 0x00000080
Linus Torvalds1da177e2005-04-16 15:20:36 -07001511#define GRC_LCLCTRL_GPIO_INPUT0 0x00000100
1512#define GRC_LCLCTRL_GPIO_INPUT1 0x00000200
1513#define GRC_LCLCTRL_GPIO_INPUT2 0x00000400
1514#define GRC_LCLCTRL_GPIO_OE0 0x00000800
1515#define GRC_LCLCTRL_GPIO_OE1 0x00001000
1516#define GRC_LCLCTRL_GPIO_OE2 0x00002000
1517#define GRC_LCLCTRL_GPIO_OUTPUT0 0x00004000
1518#define GRC_LCLCTRL_GPIO_OUTPUT1 0x00008000
1519#define GRC_LCLCTRL_GPIO_OUTPUT2 0x00010000
1520#define GRC_LCLCTRL_EXTMEM_ENABLE 0x00020000
1521#define GRC_LCLCTRL_MEMSZ_MASK 0x001c0000
1522#define GRC_LCLCTRL_MEMSZ_256K 0x00000000
1523#define GRC_LCLCTRL_MEMSZ_512K 0x00040000
1524#define GRC_LCLCTRL_MEMSZ_1M 0x00080000
1525#define GRC_LCLCTRL_MEMSZ_2M 0x000c0000
1526#define GRC_LCLCTRL_MEMSZ_4M 0x00100000
1527#define GRC_LCLCTRL_MEMSZ_8M 0x00140000
1528#define GRC_LCLCTRL_MEMSZ_16M 0x00180000
1529#define GRC_LCLCTRL_BANK_SELECT 0x00200000
1530#define GRC_LCLCTRL_SSRAM_TYPE 0x00400000
1531#define GRC_LCLCTRL_AUTO_SEEPROM 0x01000000
1532#define GRC_TIMER 0x0000680c
1533#define GRC_RX_CPU_EVENT 0x00006810
Matt Carlson7c5026a2008-05-02 16:49:29 -07001534#define GRC_RX_CPU_DRIVER_EVENT 0x00004000
Linus Torvalds1da177e2005-04-16 15:20:36 -07001535#define GRC_RX_TIMER_REF 0x00006814
1536#define GRC_RX_CPU_SEM 0x00006818
1537#define GRC_REMOTE_RX_CPU_ATTN 0x0000681c
1538#define GRC_TX_CPU_EVENT 0x00006820
1539#define GRC_TX_TIMER_REF 0x00006824
1540#define GRC_TX_CPU_SEM 0x00006828
1541#define GRC_REMOTE_TX_CPU_ATTN 0x0000682c
1542#define GRC_MEM_POWER_UP 0x00006830 /* 64-bit */
1543#define GRC_EEPROM_ADDR 0x00006838
1544#define EEPROM_ADDR_WRITE 0x00000000
1545#define EEPROM_ADDR_READ 0x80000000
1546#define EEPROM_ADDR_COMPLETE 0x40000000
1547#define EEPROM_ADDR_FSM_RESET 0x20000000
1548#define EEPROM_ADDR_DEVID_MASK 0x1c000000
1549#define EEPROM_ADDR_DEVID_SHIFT 26
1550#define EEPROM_ADDR_START 0x02000000
1551#define EEPROM_ADDR_CLKPERD_SHIFT 16
1552#define EEPROM_ADDR_ADDR_MASK 0x0000ffff
1553#define EEPROM_ADDR_ADDR_SHIFT 0
1554#define EEPROM_DEFAULT_CLOCK_PERIOD 0x60
1555#define EEPROM_CHIP_SIZE (64 * 1024)
1556#define GRC_EEPROM_DATA 0x0000683c
1557#define GRC_EEPROM_CTRL 0x00006840
1558#define GRC_MDI_CTRL 0x00006844
1559#define GRC_SEEPROM_DELAY 0x00006848
Michael Chanb5d37722006-09-27 16:06:21 -07001560/* 0x684c --> 0x6890 unused */
1561#define GRC_VCPU_EXT_CTRL 0x00006890
1562#define GRC_VCPU_EXT_CTRL_HALT_CPU 0x00400000
1563#define GRC_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000
Michael Chand9ab5ad2006-03-20 22:27:35 -08001564#define GRC_FASTBOOT_PC 0x00006894 /* 5752, 5755, 5787 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001565
1566/* 0x6c00 --> 0x7000 unused */
1567
1568/* NVRAM Control registers */
1569#define NVRAM_CMD 0x00007000
1570#define NVRAM_CMD_RESET 0x00000001
1571#define NVRAM_CMD_DONE 0x00000008
1572#define NVRAM_CMD_GO 0x00000010
1573#define NVRAM_CMD_WR 0x00000020
1574#define NVRAM_CMD_RD 0x00000000
1575#define NVRAM_CMD_ERASE 0x00000040
1576#define NVRAM_CMD_FIRST 0x00000080
1577#define NVRAM_CMD_LAST 0x00000100
1578#define NVRAM_CMD_WREN 0x00010000
1579#define NVRAM_CMD_WRDI 0x00020000
1580#define NVRAM_STAT 0x00007004
1581#define NVRAM_WRDATA 0x00007008
1582#define NVRAM_ADDR 0x0000700c
1583#define NVRAM_ADDR_MSK 0x00ffffff
1584#define NVRAM_RDDATA 0x00007010
1585#define NVRAM_CFG1 0x00007014
1586#define NVRAM_CFG1_FLASHIF_ENAB 0x00000001
1587#define NVRAM_CFG1_BUFFERED_MODE 0x00000002
1588#define NVRAM_CFG1_PASS_THRU 0x00000004
1589#define NVRAM_CFG1_STATUS_BITS 0x00000070
1590#define NVRAM_CFG1_BIT_BANG 0x00000008
1591#define NVRAM_CFG1_FLASH_SIZE 0x02000000
1592#define NVRAM_CFG1_COMPAT_BYPASS 0x80000000
1593#define NVRAM_CFG1_VENDOR_MASK 0x03000003
1594#define FLASH_VENDOR_ATMEL_EEPROM 0x02000000
1595#define FLASH_VENDOR_ATMEL_FLASH_BUFFERED 0x02000003
1596#define FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED 0x00000003
1597#define FLASH_VENDOR_ST 0x03000001
1598#define FLASH_VENDOR_SAIFUN 0x01000003
1599#define FLASH_VENDOR_SST_SMALL 0x00000001
1600#define FLASH_VENDOR_SST_LARGE 0x02000001
Michael Chan361b4ac2005-04-21 17:11:21 -07001601#define NVRAM_CFG1_5752VENDOR_MASK 0x03c00003
1602#define FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ 0x00000000
1603#define FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ 0x02000000
1604#define FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED 0x02000003
1605#define FLASH_5752VENDOR_ST_M45PE10 0x02400000
1606#define FLASH_5752VENDOR_ST_M45PE20 0x02400002
1607#define FLASH_5752VENDOR_ST_M45PE40 0x02400001
Michael Chan1b277772006-03-20 22:27:48 -08001608#define FLASH_5755VENDOR_ATMEL_FLASH_1 0x03400001
1609#define FLASH_5755VENDOR_ATMEL_FLASH_2 0x03400002
1610#define FLASH_5755VENDOR_ATMEL_FLASH_3 0x03400000
Michael Chand3c7b882006-03-23 01:28:25 -08001611#define FLASH_5755VENDOR_ATMEL_FLASH_4 0x00000003
Matt Carlson70b65a22007-07-11 19:48:50 -07001612#define FLASH_5755VENDOR_ATMEL_FLASH_5 0x02000003
Michael Chand3c7b882006-03-23 01:28:25 -08001613#define FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ 0x03c00003
1614#define FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ 0x03c00002
Michael Chan1b277772006-03-20 22:27:48 -08001615#define FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ 0x03000003
1616#define FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ 0x03000002
1617#define FLASH_5787VENDOR_MICRO_EEPROM_64KHZ 0x03000000
1618#define FLASH_5787VENDOR_MICRO_EEPROM_376KHZ 0x02000000
Matt Carlson6b91fa02007-10-10 18:01:09 -07001619#define FLASH_5761VENDOR_ATMEL_MDB021D 0x00800003
1620#define FLASH_5761VENDOR_ATMEL_MDB041D 0x00800000
1621#define FLASH_5761VENDOR_ATMEL_MDB081D 0x00800002
1622#define FLASH_5761VENDOR_ATMEL_MDB161D 0x00800001
1623#define FLASH_5761VENDOR_ATMEL_ADB021D 0x00000003
1624#define FLASH_5761VENDOR_ATMEL_ADB041D 0x00000000
1625#define FLASH_5761VENDOR_ATMEL_ADB081D 0x00000002
1626#define FLASH_5761VENDOR_ATMEL_ADB161D 0x00000001
1627#define FLASH_5761VENDOR_ST_M_M45PE20 0x02800001
1628#define FLASH_5761VENDOR_ST_M_M45PE40 0x02800000
1629#define FLASH_5761VENDOR_ST_M_M45PE80 0x02800002
1630#define FLASH_5761VENDOR_ST_M_M45PE16 0x02800003
1631#define FLASH_5761VENDOR_ST_A_M45PE20 0x02000001
1632#define FLASH_5761VENDOR_ST_A_M45PE40 0x02000000
1633#define FLASH_5761VENDOR_ST_A_M45PE80 0x02000002
1634#define FLASH_5761VENDOR_ST_A_M45PE16 0x02000003
Matt Carlson321d32a2008-11-21 17:22:19 -08001635#define FLASH_57780VENDOR_ATMEL_AT45DB011D 0x00400000
1636#define FLASH_57780VENDOR_ATMEL_AT45DB011B 0x03400000
1637#define FLASH_57780VENDOR_ATMEL_AT45DB021D 0x00400002
1638#define FLASH_57780VENDOR_ATMEL_AT45DB021B 0x03400002
1639#define FLASH_57780VENDOR_ATMEL_AT45DB041D 0x00400001
1640#define FLASH_57780VENDOR_ATMEL_AT45DB041B 0x03400001
Michael Chan361b4ac2005-04-21 17:11:21 -07001641#define NVRAM_CFG1_5752PAGE_SIZE_MASK 0x70000000
1642#define FLASH_5752PAGE_SIZE_256 0x00000000
1643#define FLASH_5752PAGE_SIZE_512 0x10000000
1644#define FLASH_5752PAGE_SIZE_1K 0x20000000
1645#define FLASH_5752PAGE_SIZE_2K 0x30000000
1646#define FLASH_5752PAGE_SIZE_4K 0x40000000
1647#define FLASH_5752PAGE_SIZE_264 0x50000000
Matt Carlson321d32a2008-11-21 17:22:19 -08001648#define FLASH_5752PAGE_SIZE_528 0x60000000
Linus Torvalds1da177e2005-04-16 15:20:36 -07001649#define NVRAM_CFG2 0x00007018
1650#define NVRAM_CFG3 0x0000701c
1651#define NVRAM_SWARB 0x00007020
1652#define SWARB_REQ_SET0 0x00000001
1653#define SWARB_REQ_SET1 0x00000002
1654#define SWARB_REQ_SET2 0x00000004
1655#define SWARB_REQ_SET3 0x00000008
1656#define SWARB_REQ_CLR0 0x00000010
1657#define SWARB_REQ_CLR1 0x00000020
1658#define SWARB_REQ_CLR2 0x00000040
1659#define SWARB_REQ_CLR3 0x00000080
1660#define SWARB_GNT0 0x00000100
1661#define SWARB_GNT1 0x00000200
1662#define SWARB_GNT2 0x00000400
1663#define SWARB_GNT3 0x00000800
1664#define SWARB_REQ0 0x00001000
1665#define SWARB_REQ1 0x00002000
1666#define SWARB_REQ2 0x00004000
1667#define SWARB_REQ3 0x00008000
1668#define NVRAM_ACCESS 0x00007024
1669#define ACCESS_ENABLE 0x00000001
1670#define ACCESS_WR_ENABLE 0x00000002
1671#define NVRAM_WRITE1 0x00007028
Matt Carlson6b91fa02007-10-10 18:01:09 -07001672/* 0x702c unused */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001673
Matt Carlson6b91fa02007-10-10 18:01:09 -07001674#define NVRAM_ADDR_LOCKOUT 0x00007030
Matt Carlsonb2a5c192008-04-03 21:44:44 -07001675/* 0x7034 --> 0x7500 unused */
1676
1677#define OTP_MODE 0x00007500
1678#define OTP_MODE_OTP_THRU_GRC 0x00000001
1679#define OTP_CTRL 0x00007504
1680#define OTP_CTRL_OTP_PROG_ENABLE 0x00200000
1681#define OTP_CTRL_OTP_CMD_READ 0x00000000
1682#define OTP_CTRL_OTP_CMD_INIT 0x00000008
1683#define OTP_CTRL_OTP_CMD_START 0x00000001
1684#define OTP_STATUS 0x00007508
1685#define OTP_STATUS_CMD_DONE 0x00000001
1686#define OTP_ADDRESS 0x0000750c
1687#define OTP_ADDRESS_MAGIC1 0x000000a0
1688#define OTP_ADDRESS_MAGIC2 0x00000080
1689/* 0x7510 unused */
1690
1691#define OTP_READ_DATA 0x00007514
1692/* 0x7518 --> 0x7c04 unused */
Matt Carlson6b91fa02007-10-10 18:01:09 -07001693
Michael Chanb5d37722006-09-27 16:06:21 -07001694#define PCIE_TRANSACTION_CFG 0x00007c04
1695#define PCIE_TRANS_CFG_1SHOT_MSI 0x20000000
1696#define PCIE_TRANS_CFG_LOM 0x00000020
1697
Matt Carlson8ed5d972007-05-07 00:25:49 -07001698#define PCIE_PWR_MGMT_THRESH 0x00007d28
1699#define PCIE_PWR_MGMT_L1_THRESH_MSK 0x0000ff00
Linus Torvalds1da177e2005-04-16 15:20:36 -07001700
Matt Carlsonb2a5c192008-04-03 21:44:44 -07001701
1702/* OTP bit definitions */
1703#define TG3_OTP_AGCTGT_MASK 0x000000e0
1704#define TG3_OTP_AGCTGT_SHIFT 1
1705#define TG3_OTP_HPFFLTR_MASK 0x00000300
1706#define TG3_OTP_HPFFLTR_SHIFT 1
1707#define TG3_OTP_HPFOVER_MASK 0x00000400
1708#define TG3_OTP_HPFOVER_SHIFT 1
1709#define TG3_OTP_LPFDIS_MASK 0x00000800
1710#define TG3_OTP_LPFDIS_SHIFT 11
1711#define TG3_OTP_VDAC_MASK 0xff000000
1712#define TG3_OTP_VDAC_SHIFT 24
1713#define TG3_OTP_10BTAMP_MASK 0x0000f000
1714#define TG3_OTP_10BTAMP_SHIFT 8
1715#define TG3_OTP_ROFF_MASK 0x00e00000
1716#define TG3_OTP_ROFF_SHIFT 11
1717#define TG3_OTP_RCOFF_MASK 0x001c0000
1718#define TG3_OTP_RCOFF_SHIFT 16
1719
1720#define TG3_OTP_DEFAULT 0x286c1640
1721
1722
Linus Torvalds1da177e2005-04-16 15:20:36 -07001723#define TG3_EEPROM_MAGIC 0x669955aa
Michael Chanb16250e2006-09-27 16:10:14 -07001724#define TG3_EEPROM_MAGIC_FW 0xa5000000
1725#define TG3_EEPROM_MAGIC_FW_MSK 0xff000000
Matt Carlsona5767de2007-11-12 21:10:58 -08001726#define TG3_EEPROM_SB_FORMAT_MASK 0x00e00000
1727#define TG3_EEPROM_SB_FORMAT_1 0x00200000
1728#define TG3_EEPROM_SB_REVISION_MASK 0x001f0000
1729#define TG3_EEPROM_SB_REVISION_0 0x00000000
1730#define TG3_EEPROM_SB_REVISION_2 0x00020000
1731#define TG3_EEPROM_SB_REVISION_3 0x00030000
Michael Chanb16250e2006-09-27 16:10:14 -07001732#define TG3_EEPROM_MAGIC_HW 0xabcd
1733#define TG3_EEPROM_MAGIC_HW_MSK 0xffff
Linus Torvalds1da177e2005-04-16 15:20:36 -07001734
Matt Carlson9c8a6202007-10-21 16:16:08 -07001735#define TG3_NVM_DIR_START 0x18
1736#define TG3_NVM_DIR_END 0x78
1737#define TG3_NVM_DIRENT_SIZE 0xc
1738#define TG3_NVM_DIRTYPE_SHIFT 24
1739#define TG3_NVM_DIRTYPE_ASFINI 1
1740
Matt Carlsondfe00d72008-11-21 17:19:41 -08001741#define TG3_EEPROM_SB_F1R0_EDH_OFF 0x10
1742#define TG3_EEPROM_SB_F1R2_EDH_OFF 0x14
1743#define TG3_EEPROM_SB_F1R2_MBA_OFF 0x10
1744#define TG3_EEPROM_SB_F1R3_EDH_OFF 0x18
1745#define TG3_EEPROM_SB_EDH_MAJ_MASK 0x00000700
1746#define TG3_EEPROM_SB_EDH_MAJ_SHFT 8
1747#define TG3_EEPROM_SB_EDH_MIN_MASK 0x000000ff
1748#define TG3_EEPROM_SB_EDH_BLD_MASK 0x0000f800
1749#define TG3_EEPROM_SB_EDH_BLD_SHFT 11
1750
1751
Linus Torvalds1da177e2005-04-16 15:20:36 -07001752/* 32K Window into NIC internal memory */
1753#define NIC_SRAM_WIN_BASE 0x00008000
1754
1755/* Offsets into first 32k of NIC internal memory. */
1756#define NIC_SRAM_PAGE_ZERO 0x00000000
1757#define NIC_SRAM_SEND_RCB 0x00000100 /* 16 * TG3_BDINFO_... */
1758#define NIC_SRAM_RCV_RET_RCB 0x00000200 /* 16 * TG3_BDINFO_... */
1759#define NIC_SRAM_STATS_BLK 0x00000300
1760#define NIC_SRAM_STATUS_BLK 0x00000b00
1761
1762#define NIC_SRAM_FIRMWARE_MBOX 0x00000b50
1763#define NIC_SRAM_FIRMWARE_MBOX_MAGIC1 0x4B657654
1764#define NIC_SRAM_FIRMWARE_MBOX_MAGIC2 0x4861764b /* !dma on linkchg */
1765
1766#define NIC_SRAM_DATA_SIG 0x00000b54
1767#define NIC_SRAM_DATA_SIG_MAGIC 0x4b657654 /* ascii for 'KevT' */
1768
1769#define NIC_SRAM_DATA_CFG 0x00000b58
1770#define NIC_SRAM_DATA_CFG_LED_MODE_MASK 0x0000000c
1771#define NIC_SRAM_DATA_CFG_LED_MODE_MAC 0x00000000
1772#define NIC_SRAM_DATA_CFG_LED_MODE_PHY_1 0x00000004
1773#define NIC_SRAM_DATA_CFG_LED_MODE_PHY_2 0x00000008
1774#define NIC_SRAM_DATA_CFG_PHY_TYPE_MASK 0x00000030
1775#define NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN 0x00000000
1776#define NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER 0x00000010
1777#define NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER 0x00000020
1778#define NIC_SRAM_DATA_CFG_WOL_ENABLE 0x00000040
1779#define NIC_SRAM_DATA_CFG_ASF_ENABLE 0x00000080
1780#define NIC_SRAM_DATA_CFG_EEPROM_WP 0x00000100
1781#define NIC_SRAM_DATA_CFG_MINI_PCI 0x00001000
1782#define NIC_SRAM_DATA_CFG_FIBER_WOL 0x00004000
1783#define NIC_SRAM_DATA_CFG_NO_GPIO2 0x00100000
Matt Carlson0d3031d2007-10-10 18:02:43 -07001784#define NIC_SRAM_DATA_CFG_APE_ENABLE 0x00200000
Linus Torvalds1da177e2005-04-16 15:20:36 -07001785
1786#define NIC_SRAM_DATA_VER 0x00000b5c
1787#define NIC_SRAM_DATA_VER_SHIFT 16
1788
1789#define NIC_SRAM_DATA_PHY_ID 0x00000b74
1790#define NIC_SRAM_DATA_PHY_ID1_MASK 0xffff0000
1791#define NIC_SRAM_DATA_PHY_ID2_MASK 0x0000ffff
1792
1793#define NIC_SRAM_FW_CMD_MBOX 0x00000b78
1794#define FWCMD_NICDRV_ALIVE 0x00000001
1795#define FWCMD_NICDRV_PAUSE_FW 0x00000002
1796#define FWCMD_NICDRV_IPV4ADDR_CHG 0x00000003
1797#define FWCMD_NICDRV_IPV6ADDR_CHG 0x00000004
1798#define FWCMD_NICDRV_FIX_DMAR 0x00000005
1799#define FWCMD_NICDRV_FIX_DMAW 0x00000006
Matt Carlson7c5026a2008-05-02 16:49:29 -07001800#define FWCMD_NICDRV_LINK_UPDATE 0x0000000c
Michael Chan28fbef72005-10-26 15:48:35 -07001801#define FWCMD_NICDRV_ALIVE2 0x0000000d
Michael Chan130b8e42006-09-27 16:00:40 -07001802#define FWCMD_NICDRV_ALIVE3 0x0000000e
Linus Torvalds1da177e2005-04-16 15:20:36 -07001803#define NIC_SRAM_FW_CMD_LEN_MBOX 0x00000b7c
1804#define NIC_SRAM_FW_CMD_DATA_MBOX 0x00000b80
1805#define NIC_SRAM_FW_ASF_STATUS_MBOX 0x00000c00
1806#define NIC_SRAM_FW_DRV_STATE_MBOX 0x00000c04
1807#define DRV_STATE_START 0x00000001
1808#define DRV_STATE_START_DONE 0x80000001
1809#define DRV_STATE_UNLOAD 0x00000002
1810#define DRV_STATE_UNLOAD_DONE 0x80000002
1811#define DRV_STATE_WOL 0x00000003
1812#define DRV_STATE_SUSPEND 0x00000004
1813
1814#define NIC_SRAM_FW_RESET_TYPE_MBOX 0x00000c08
1815
1816#define NIC_SRAM_MAC_ADDR_HIGH_MBOX 0x00000c14
1817#define NIC_SRAM_MAC_ADDR_LOW_MBOX 0x00000c18
1818
Michael Chan6921d202005-12-13 21:15:53 -08001819#define NIC_SRAM_WOL_MBOX 0x00000d30
1820#define WOL_SIGNATURE 0x474c0000
1821#define WOL_DRV_STATE_SHUTDOWN 0x00000001
1822#define WOL_DRV_WOL 0x00000002
1823#define WOL_SET_MAGIC_PKT 0x00000004
1824
Linus Torvalds1da177e2005-04-16 15:20:36 -07001825#define NIC_SRAM_DATA_CFG_2 0x00000d38
1826
Matt Carlson6833c042008-11-21 17:18:59 -08001827#define NIC_SRAM_DATA_CFG_2_APD_EN 0x00000400
Linus Torvalds1da177e2005-04-16 15:20:36 -07001828#define SHASTA_EXT_LED_MODE_MASK 0x00018000
1829#define SHASTA_EXT_LED_LEGACY 0x00000000
1830#define SHASTA_EXT_LED_SHARED 0x00008000
1831#define SHASTA_EXT_LED_MAC 0x00010000
1832#define SHASTA_EXT_LED_COMBO 0x00018000
1833
Matt Carlson8ed5d972007-05-07 00:25:49 -07001834#define NIC_SRAM_DATA_CFG_3 0x00000d3c
1835#define NIC_SRAM_ASPM_DEBOUNCE 0x00000002
1836
Matt Carlsona9daf362008-05-25 23:49:44 -07001837#define NIC_SRAM_DATA_CFG_4 0x00000d60
1838#define NIC_SRAM_GMII_MODE 0x00000002
1839#define NIC_SRAM_RGMII_STD_IBND_DISABLE 0x00000004
1840#define NIC_SRAM_RGMII_EXT_IBND_RX_EN 0x00000008
1841#define NIC_SRAM_RGMII_EXT_IBND_TX_EN 0x00000010
1842
Linus Torvalds1da177e2005-04-16 15:20:36 -07001843#define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000
1844
1845#define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000
1846#define NIC_SRAM_DMA_DESC_POOL_SIZE 0x00002000
1847#define NIC_SRAM_TX_BUFFER_DESC 0x00004000 /* 512 entries */
1848#define NIC_SRAM_RX_BUFFER_DESC 0x00006000 /* 256 entries */
1849#define NIC_SRAM_RX_JUMBO_BUFFER_DESC 0x00007000 /* 256 entries */
1850#define NIC_SRAM_MBUF_POOL_BASE 0x00008000
1851#define NIC_SRAM_MBUF_POOL_SIZE96 0x00018000
1852#define NIC_SRAM_MBUF_POOL_SIZE64 0x00010000
1853#define NIC_SRAM_MBUF_POOL_BASE5705 0x00010000
1854#define NIC_SRAM_MBUF_POOL_SIZE5705 0x0000e000
1855
1856/* Currently this is fixed. */
1857#define PHY_ADDR 0x01
1858
1859/* Tigon3 specific PHY MII registers. */
1860#define TG3_BMCR_SPEED1000 0x0040
1861
1862#define MII_TG3_CTRL 0x09 /* 1000-baseT control register */
1863#define MII_TG3_CTRL_ADV_1000_HALF 0x0100
1864#define MII_TG3_CTRL_ADV_1000_FULL 0x0200
1865#define MII_TG3_CTRL_AS_MASTER 0x0800
1866#define MII_TG3_CTRL_ENABLE_AS_MASTER 0x1000
1867
1868#define MII_TG3_EXT_CTRL 0x10 /* Extended control register */
1869#define MII_TG3_EXT_CTRL_FIFO_ELASTIC 0x0001
1870#define MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002
Michael Chan6921d202005-12-13 21:15:53 -08001871#define MII_TG3_EXT_CTRL_FORCE_LED_OFF 0x0008
Linus Torvalds1da177e2005-04-16 15:20:36 -07001872#define MII_TG3_EXT_CTRL_TBI 0x8000
1873
1874#define MII_TG3_EXT_STAT 0x11 /* Extended status register */
1875#define MII_TG3_EXT_STAT_LPASS 0x0100
1876
1877#define MII_TG3_DSP_RW_PORT 0x15 /* DSP coefficient read/write port */
1878
Michael Chan715116a2006-09-27 16:09:25 -07001879#define MII_TG3_EPHY_PTEST 0x17 /* 5906 PHY register */
Matt Carlsonb2a5c192008-04-03 21:44:44 -07001880#define MII_TG3_DSP_ADDRESS 0x17 /* DSP address register */
1881
1882#define MII_TG3_DSP_TAP1 0x0001
1883#define MII_TG3_DSP_TAP1_AGCTGT_DFLT 0x0007
1884#define MII_TG3_DSP_AADJ1CH0 0x001f
1885#define MII_TG3_DSP_AADJ1CH3 0x601f
1886#define MII_TG3_DSP_AADJ1CH3_ADCCKADJ 0x0002
1887#define MII_TG3_DSP_EXP8 0x0708
1888#define MII_TG3_DSP_EXP8_REJ2MHz 0x0001
1889#define MII_TG3_DSP_EXP8_AEDW 0x0200
1890#define MII_TG3_DSP_EXP75 0x0f75
1891#define MII_TG3_DSP_EXP96 0x0f96
1892#define MII_TG3_DSP_EXP97 0x0f97
Linus Torvalds1da177e2005-04-16 15:20:36 -07001893
1894#define MII_TG3_AUX_CTRL 0x18 /* auxilliary control register */
1895
Matt Carlson0a459aa2008-11-03 16:54:15 -08001896#define MII_TG3_AUXCTL_PCTL_100TX_LPWR 0x0010
1897#define MII_TG3_AUXCTL_PCTL_SPR_ISOLATE 0x0020
1898#define MII_TG3_AUXCTL_PCTL_VREG_11V 0x0180
1899#define MII_TG3_AUXCTL_SHDWSEL_PWRCTL 0x0002
1900
Matt Carlson9ef8ca92007-07-11 19:48:29 -07001901#define MII_TG3_AUXCTL_MISC_WREN 0x8000
1902#define MII_TG3_AUXCTL_MISC_FORCE_AMDIX 0x0200
1903#define MII_TG3_AUXCTL_MISC_RDSEL_MISC 0x7000
Matt Carlsonb2a5c192008-04-03 21:44:44 -07001904#define MII_TG3_AUXCTL_SHDWSEL_MISC 0x0007
1905
1906#define MII_TG3_AUXCTL_ACTL_SMDSP_ENA 0x0800
1907#define MII_TG3_AUXCTL_ACTL_TX_6DB 0x0400
1908#define MII_TG3_AUXCTL_SHDWSEL_AUXCTL 0x0000
Matt Carlson9ef8ca92007-07-11 19:48:29 -07001909
Linus Torvalds1da177e2005-04-16 15:20:36 -07001910#define MII_TG3_AUX_STAT 0x19 /* auxilliary status register */
1911#define MII_TG3_AUX_STAT_LPASS 0x0004
1912#define MII_TG3_AUX_STAT_SPDMASK 0x0700
1913#define MII_TG3_AUX_STAT_10HALF 0x0100
1914#define MII_TG3_AUX_STAT_10FULL 0x0200
1915#define MII_TG3_AUX_STAT_100HALF 0x0300
1916#define MII_TG3_AUX_STAT_100_4 0x0400
1917#define MII_TG3_AUX_STAT_100FULL 0x0500
1918#define MII_TG3_AUX_STAT_1000HALF 0x0600
1919#define MII_TG3_AUX_STAT_1000FULL 0x0700
Michael Chan715116a2006-09-27 16:09:25 -07001920#define MII_TG3_AUX_STAT_100 0x0008
1921#define MII_TG3_AUX_STAT_FULL 0x0001
Linus Torvalds1da177e2005-04-16 15:20:36 -07001922
1923#define MII_TG3_ISTAT 0x1a /* IRQ status register */
1924#define MII_TG3_IMASK 0x1b /* IRQ mask register */
1925
1926/* ISTAT/IMASK event bits */
1927#define MII_TG3_INT_LINKCHG 0x0002
1928#define MII_TG3_INT_SPEEDCHG 0x0004
1929#define MII_TG3_INT_DUPLEXCHG 0x0008
1930#define MII_TG3_INT_ANEG_PAGE_RX 0x0400
1931
Matt Carlsonb2a5c192008-04-03 21:44:44 -07001932#define MII_TG3_MISC_SHDW 0x1c
1933#define MII_TG3_MISC_SHDW_WREN 0x8000
Matt Carlsonaa10f272008-12-21 20:21:18 -08001934
1935#define MII_TG3_MISC_SHDW_APD_WKTM_84MS 0x0001
1936#define MII_TG3_MISC_SHDW_APD_ENABLE 0x0020
Matt Carlsonb2a5c192008-04-03 21:44:44 -07001937#define MII_TG3_MISC_SHDW_APD_SEL 0x2800
1938
1939#define MII_TG3_MISC_SHDW_SCR5_C125OE 0x0001
1940#define MII_TG3_MISC_SHDW_SCR5_DLLAPD 0x0002
1941#define MII_TG3_MISC_SHDW_SCR5_SDTL 0x0004
1942#define MII_TG3_MISC_SHDW_SCR5_DLPTLM 0x0008
1943#define MII_TG3_MISC_SHDW_SCR5_LPED 0x0010
Matt Carlsonaa10f272008-12-21 20:21:18 -08001944#define MII_TG3_MISC_SHDW_SCR5_SEL 0x1400
Matt Carlsonb2a5c192008-04-03 21:44:44 -07001945
Matt Carlsonb2a5c192008-04-03 21:44:44 -07001946
Michael Chan715116a2006-09-27 16:09:25 -07001947#define MII_TG3_EPHY_TEST 0x1f /* 5906 PHY register */
1948#define MII_TG3_EPHY_SHADOW_EN 0x80
1949
Matt Carlson9ef8ca92007-07-11 19:48:29 -07001950#define MII_TG3_EPHYTST_MISCCTRL 0x10 /* 5906 EPHY misc ctrl shadow register */
1951#define MII_TG3_EPHYTST_MISCCTRL_MDIX 0x4000
1952
Michael Chanc1d2a192007-01-08 19:57:20 -08001953#define MII_TG3_TEST1 0x1e
1954#define MII_TG3_TEST1_TRIM_EN 0x0010
Michael Chan569a5df2007-02-13 12:18:15 -08001955#define MII_TG3_TEST1_CRC_EN 0x8000
Michael Chanc1d2a192007-01-08 19:57:20 -08001956
Matt Carlson0d3031d2007-10-10 18:02:43 -07001957/* APE registers. Accessible through BAR1 */
1958#define TG3_APE_EVENT 0x000c
1959#define APE_EVENT_1 0x00000001
1960#define TG3_APE_LOCK_REQ 0x002c
1961#define APE_LOCK_REQ_DRIVER 0x00001000
1962#define TG3_APE_LOCK_GRANT 0x004c
1963#define APE_LOCK_GRANT_DRIVER 0x00001000
1964#define TG3_APE_SEG_SIG 0x4000
1965#define APE_SEG_SIG_MAGIC 0x41504521
1966
1967/* APE shared memory. Accessible through BAR1 */
1968#define TG3_APE_FW_STATUS 0x400c
1969#define APE_FW_STATUS_READY 0x00000100
1970#define TG3_APE_HOST_SEG_SIG 0x4200
1971#define APE_HOST_SEG_SIG_MAGIC 0x484f5354
1972#define TG3_APE_HOST_SEG_LEN 0x4204
1973#define APE_HOST_SEG_LEN_MAGIC 0x0000001c
1974#define TG3_APE_HOST_INIT_COUNT 0x4208
1975#define TG3_APE_HOST_DRIVER_ID 0x420c
1976#define APE_HOST_DRIVER_ID_MAGIC 0xf0035100
1977#define TG3_APE_HOST_BEHAVIOR 0x4210
1978#define APE_HOST_BEHAV_NO_PHYLOCK 0x00000001
1979#define TG3_APE_HOST_HEARTBEAT_INT_MS 0x4214
1980#define APE_HOST_HEARTBEAT_INT_DISABLE 0
1981#define APE_HOST_HEARTBEAT_INT_5SEC 5000
1982#define TG3_APE_HOST_HEARTBEAT_COUNT 0x4218
1983
1984#define TG3_APE_EVENT_STATUS 0x4300
1985
1986#define APE_EVENT_STATUS_DRIVER_EVNT 0x00000010
1987#define APE_EVENT_STATUS_STATE_CHNGE 0x00000500
1988#define APE_EVENT_STATUS_STATE_START 0x00010000
1989#define APE_EVENT_STATUS_STATE_UNLOAD 0x00020000
1990#define APE_EVENT_STATUS_STATE_WOL 0x00030000
1991#define APE_EVENT_STATUS_STATE_SUSPEND 0x00040000
1992#define APE_EVENT_STATUS_EVENT_PENDING 0x80000000
1993
1994/* APE convenience enumerations. */
Matt Carlson77b483f2008-08-15 14:07:24 -07001995#define TG3_APE_LOCK_GRC 1
Matt Carlson0d3031d2007-10-10 18:02:43 -07001996#define TG3_APE_LOCK_MEM 4
1997
Matt Carlsona5767de2007-11-12 21:10:58 -08001998#define TG3_EEPROM_SB_F1R2_MBA_OFF 0x10
1999
Matt Carlson0d3031d2007-10-10 18:02:43 -07002000
Linus Torvalds1da177e2005-04-16 15:20:36 -07002001/* There are two ways to manage the TX descriptors on the tigon3.
2002 * Either the descriptors are in host DMA'able memory, or they
2003 * exist only in the cards on-chip SRAM. All 16 send bds are under
2004 * the same mode, they may not be configured individually.
2005 *
2006 * This driver always uses host memory TX descriptors.
2007 *
2008 * To use host memory TX descriptors:
2009 * 1) Set GRC_MODE_HOST_SENDBDS in GRC_MODE register.
2010 * Make sure GRC_MODE_4X_NIC_SEND_RINGS is clear.
2011 * 2) Allocate DMA'able memory.
2012 * 3) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
2013 * a) Set TG3_BDINFO_HOST_ADDR to DMA address of memory
2014 * obtained in step 2
2015 * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC.
2016 * c) Set len field of TG3_BDINFO_MAXLEN_FLAGS to number
2017 * of TX descriptors. Leave flags field clear.
2018 * 4) Access TX descriptors via host memory. The chip
2019 * will refetch into local SRAM as needed when producer
2020 * index mailboxes are updated.
2021 *
2022 * To use on-chip TX descriptors:
2023 * 1) Set GRC_MODE_4X_NIC_SEND_RINGS in GRC_MODE register.
2024 * Make sure GRC_MODE_HOST_SENDBDS is clear.
2025 * 2) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
2026 * a) Set TG3_BDINFO_HOST_ADDR to zero.
2027 * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC
2028 * c) TG3_BDINFO_MAXLEN_FLAGS is don't care.
2029 * 3) Access TX descriptors directly in on-chip SRAM
2030 * using normal {read,write}l(). (and not using
2031 * pointer dereferencing of ioremap()'d memory like
2032 * the broken Broadcom driver does)
2033 *
2034 * Note that BDINFO_FLAGS_DISABLED should be set in the flags field of
2035 * TG3_BDINFO_MAXLEN_FLAGS of all unused SEND_RCB indices.
2036 */
2037struct tg3_tx_buffer_desc {
2038 u32 addr_hi;
2039 u32 addr_lo;
2040
2041 u32 len_flags;
2042#define TXD_FLAG_TCPUDP_CSUM 0x0001
2043#define TXD_FLAG_IP_CSUM 0x0002
2044#define TXD_FLAG_END 0x0004
2045#define TXD_FLAG_IP_FRAG 0x0008
2046#define TXD_FLAG_IP_FRAG_END 0x0010
2047#define TXD_FLAG_VLAN 0x0040
2048#define TXD_FLAG_COAL_NOW 0x0080
2049#define TXD_FLAG_CPU_PRE_DMA 0x0100
2050#define TXD_FLAG_CPU_POST_DMA 0x0200
2051#define TXD_FLAG_ADD_SRC_ADDR 0x1000
2052#define TXD_FLAG_CHOOSE_SRC_ADDR 0x6000
2053#define TXD_FLAG_NO_CRC 0x8000
2054#define TXD_LEN_SHIFT 16
2055
2056 u32 vlan_tag;
2057#define TXD_VLAN_TAG_SHIFT 0
2058#define TXD_MSS_SHIFT 16
2059};
2060
2061#define TXD_ADDR 0x00UL /* 64-bit */
2062#define TXD_LEN_FLAGS 0x08UL /* 32-bit (upper 16-bits are len) */
2063#define TXD_VLAN_TAG 0x0cUL /* 32-bit (upper 16-bits are tag) */
2064#define TXD_SIZE 0x10UL
2065
2066struct tg3_rx_buffer_desc {
2067 u32 addr_hi;
2068 u32 addr_lo;
2069
2070 u32 idx_len;
2071#define RXD_IDX_MASK 0xffff0000
2072#define RXD_IDX_SHIFT 16
2073#define RXD_LEN_MASK 0x0000ffff
2074#define RXD_LEN_SHIFT 0
2075
2076 u32 type_flags;
2077#define RXD_TYPE_SHIFT 16
2078#define RXD_FLAGS_SHIFT 0
2079
2080#define RXD_FLAG_END 0x0004
2081#define RXD_FLAG_MINI 0x0800
2082#define RXD_FLAG_JUMBO 0x0020
2083#define RXD_FLAG_VLAN 0x0040
2084#define RXD_FLAG_ERROR 0x0400
2085#define RXD_FLAG_IP_CSUM 0x1000
2086#define RXD_FLAG_TCPUDP_CSUM 0x2000
2087#define RXD_FLAG_IS_TCP 0x4000
2088
2089 u32 ip_tcp_csum;
2090#define RXD_IPCSUM_MASK 0xffff0000
2091#define RXD_IPCSUM_SHIFT 16
2092#define RXD_TCPCSUM_MASK 0x0000ffff
2093#define RXD_TCPCSUM_SHIFT 0
2094
2095 u32 err_vlan;
2096
2097#define RXD_VLAN_MASK 0x0000ffff
2098
2099#define RXD_ERR_BAD_CRC 0x00010000
2100#define RXD_ERR_COLLISION 0x00020000
2101#define RXD_ERR_LINK_LOST 0x00040000
2102#define RXD_ERR_PHY_DECODE 0x00080000
2103#define RXD_ERR_ODD_NIBBLE_RCVD_MII 0x00100000
2104#define RXD_ERR_MAC_ABRT 0x00200000
2105#define RXD_ERR_TOO_SMALL 0x00400000
2106#define RXD_ERR_NO_RESOURCES 0x00800000
2107#define RXD_ERR_HUGE_FRAME 0x01000000
2108#define RXD_ERR_MASK 0xffff0000
2109
2110 u32 reserved;
2111 u32 opaque;
2112#define RXD_OPAQUE_INDEX_MASK 0x0000ffff
2113#define RXD_OPAQUE_INDEX_SHIFT 0
2114#define RXD_OPAQUE_RING_STD 0x00010000
2115#define RXD_OPAQUE_RING_JUMBO 0x00020000
2116#define RXD_OPAQUE_RING_MINI 0x00040000
2117#define RXD_OPAQUE_RING_MASK 0x00070000
2118};
2119
2120struct tg3_ext_rx_buffer_desc {
2121 struct {
2122 u32 addr_hi;
2123 u32 addr_lo;
2124 } addrlist[3];
2125 u32 len2_len1;
2126 u32 resv_len3;
2127 struct tg3_rx_buffer_desc std;
2128};
2129
2130/* We only use this when testing out the DMA engine
2131 * at probe time. This is the internal format of buffer
2132 * descriptors used by the chip at NIC_SRAM_DMA_DESCS.
2133 */
2134struct tg3_internal_buffer_desc {
2135 u32 addr_hi;
2136 u32 addr_lo;
2137 u32 nic_mbuf;
2138 /* XXX FIX THIS */
2139#ifdef __BIG_ENDIAN
2140 u16 cqid_sqid;
2141 u16 len;
2142#else
2143 u16 len;
2144 u16 cqid_sqid;
2145#endif
2146 u32 flags;
2147 u32 __cookie1;
2148 u32 __cookie2;
2149 u32 __cookie3;
2150};
2151
2152#define TG3_HW_STATUS_SIZE 0x50
2153struct tg3_hw_status {
2154 u32 status;
2155#define SD_STATUS_UPDATED 0x00000001
2156#define SD_STATUS_LINK_CHG 0x00000002
2157#define SD_STATUS_ERROR 0x00000004
2158
2159 u32 status_tag;
2160
2161#ifdef __BIG_ENDIAN
2162 u16 rx_consumer;
2163 u16 rx_jumbo_consumer;
2164#else
2165 u16 rx_jumbo_consumer;
2166 u16 rx_consumer;
2167#endif
2168
2169#ifdef __BIG_ENDIAN
2170 u16 reserved;
2171 u16 rx_mini_consumer;
2172#else
2173 u16 rx_mini_consumer;
2174 u16 reserved;
2175#endif
2176 struct {
2177#ifdef __BIG_ENDIAN
2178 u16 tx_consumer;
2179 u16 rx_producer;
2180#else
2181 u16 rx_producer;
2182 u16 tx_consumer;
2183#endif
2184 } idx[16];
2185};
2186
2187typedef struct {
2188 u32 high, low;
2189} tg3_stat64_t;
2190
2191struct tg3_hw_stats {
2192 u8 __reserved0[0x400-0x300];
2193
2194 /* Statistics maintained by Receive MAC. */
2195 tg3_stat64_t rx_octets;
2196 u64 __reserved1;
2197 tg3_stat64_t rx_fragments;
2198 tg3_stat64_t rx_ucast_packets;
2199 tg3_stat64_t rx_mcast_packets;
2200 tg3_stat64_t rx_bcast_packets;
2201 tg3_stat64_t rx_fcs_errors;
2202 tg3_stat64_t rx_align_errors;
2203 tg3_stat64_t rx_xon_pause_rcvd;
2204 tg3_stat64_t rx_xoff_pause_rcvd;
2205 tg3_stat64_t rx_mac_ctrl_rcvd;
2206 tg3_stat64_t rx_xoff_entered;
2207 tg3_stat64_t rx_frame_too_long_errors;
2208 tg3_stat64_t rx_jabbers;
2209 tg3_stat64_t rx_undersize_packets;
2210 tg3_stat64_t rx_in_length_errors;
2211 tg3_stat64_t rx_out_length_errors;
2212 tg3_stat64_t rx_64_or_less_octet_packets;
2213 tg3_stat64_t rx_65_to_127_octet_packets;
2214 tg3_stat64_t rx_128_to_255_octet_packets;
2215 tg3_stat64_t rx_256_to_511_octet_packets;
2216 tg3_stat64_t rx_512_to_1023_octet_packets;
2217 tg3_stat64_t rx_1024_to_1522_octet_packets;
2218 tg3_stat64_t rx_1523_to_2047_octet_packets;
2219 tg3_stat64_t rx_2048_to_4095_octet_packets;
2220 tg3_stat64_t rx_4096_to_8191_octet_packets;
2221 tg3_stat64_t rx_8192_to_9022_octet_packets;
2222
2223 u64 __unused0[37];
2224
2225 /* Statistics maintained by Transmit MAC. */
2226 tg3_stat64_t tx_octets;
2227 u64 __reserved2;
2228 tg3_stat64_t tx_collisions;
2229 tg3_stat64_t tx_xon_sent;
2230 tg3_stat64_t tx_xoff_sent;
2231 tg3_stat64_t tx_flow_control;
2232 tg3_stat64_t tx_mac_errors;
2233 tg3_stat64_t tx_single_collisions;
2234 tg3_stat64_t tx_mult_collisions;
2235 tg3_stat64_t tx_deferred;
2236 u64 __reserved3;
2237 tg3_stat64_t tx_excessive_collisions;
2238 tg3_stat64_t tx_late_collisions;
2239 tg3_stat64_t tx_collide_2times;
2240 tg3_stat64_t tx_collide_3times;
2241 tg3_stat64_t tx_collide_4times;
2242 tg3_stat64_t tx_collide_5times;
2243 tg3_stat64_t tx_collide_6times;
2244 tg3_stat64_t tx_collide_7times;
2245 tg3_stat64_t tx_collide_8times;
2246 tg3_stat64_t tx_collide_9times;
2247 tg3_stat64_t tx_collide_10times;
2248 tg3_stat64_t tx_collide_11times;
2249 tg3_stat64_t tx_collide_12times;
2250 tg3_stat64_t tx_collide_13times;
2251 tg3_stat64_t tx_collide_14times;
2252 tg3_stat64_t tx_collide_15times;
2253 tg3_stat64_t tx_ucast_packets;
2254 tg3_stat64_t tx_mcast_packets;
2255 tg3_stat64_t tx_bcast_packets;
2256 tg3_stat64_t tx_carrier_sense_errors;
2257 tg3_stat64_t tx_discards;
2258 tg3_stat64_t tx_errors;
2259
2260 u64 __unused1[31];
2261
2262 /* Statistics maintained by Receive List Placement. */
2263 tg3_stat64_t COS_rx_packets[16];
2264 tg3_stat64_t COS_rx_filter_dropped;
2265 tg3_stat64_t dma_writeq_full;
2266 tg3_stat64_t dma_write_prioq_full;
2267 tg3_stat64_t rxbds_empty;
2268 tg3_stat64_t rx_discards;
2269 tg3_stat64_t rx_errors;
2270 tg3_stat64_t rx_threshold_hit;
2271
2272 u64 __unused2[9];
2273
2274 /* Statistics maintained by Send Data Initiator. */
2275 tg3_stat64_t COS_out_packets[16];
2276 tg3_stat64_t dma_readq_full;
2277 tg3_stat64_t dma_read_prioq_full;
2278 tg3_stat64_t tx_comp_queue_full;
2279
2280 /* Statistics maintained by Host Coalescing. */
2281 tg3_stat64_t ring_set_send_prod_index;
2282 tg3_stat64_t ring_status_update;
2283 tg3_stat64_t nic_irqs;
2284 tg3_stat64_t nic_avoided_irqs;
2285 tg3_stat64_t nic_tx_threshold_hit;
2286
2287 u8 __reserved4[0xb00-0x9c0];
2288};
2289
2290/* 'mapping' is superfluous as the chip does not write into
2291 * the tx/rx post rings so we could just fetch it from there.
2292 * But the cache behavior is better how we are doing it now.
2293 */
2294struct ring_info {
2295 struct sk_buff *skb;
2296 DECLARE_PCI_UNMAP_ADDR(mapping)
2297};
2298
2299struct tx_ring_info {
2300 struct sk_buff *skb;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002301 u32 prev_vlan_tag;
2302};
2303
2304struct tg3_config_info {
2305 u32 flags;
2306};
2307
2308struct tg3_link_config {
2309 /* Describes what we're trying to get. */
2310 u32 advertising;
2311 u16 speed;
2312 u8 duplex;
2313 u8 autoneg;
Matt Carlson8d018622007-12-20 20:05:44 -08002314 u8 flowctrl;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002315
2316 /* Describes what we actually have. */
Matt Carlson8d018622007-12-20 20:05:44 -08002317 u8 active_flowctrl;
2318
Linus Torvalds1da177e2005-04-16 15:20:36 -07002319 u8 active_duplex;
2320#define SPEED_INVALID 0xffff
2321#define DUPLEX_INVALID 0xff
2322#define AUTONEG_INVALID 0xff
Matt Carlson8d018622007-12-20 20:05:44 -08002323 u16 active_speed;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002324
2325 /* When we go in and out of low power mode we need
2326 * to swap with this state.
2327 */
2328 int phy_is_low_power;
2329 u16 orig_speed;
2330 u8 orig_duplex;
2331 u8 orig_autoneg;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07002332 u32 orig_advertising;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002333};
2334
2335struct tg3_bufmgr_config {
2336 u32 mbuf_read_dma_low_water;
2337 u32 mbuf_mac_rx_low_water;
2338 u32 mbuf_high_water;
2339
2340 u32 mbuf_read_dma_low_water_jumbo;
2341 u32 mbuf_mac_rx_low_water_jumbo;
2342 u32 mbuf_high_water_jumbo;
2343
2344 u32 dma_low_water;
2345 u32 dma_high_water;
2346};
2347
2348struct tg3_ethtool_stats {
2349 /* Statistics maintained by Receive MAC. */
2350 u64 rx_octets;
2351 u64 rx_fragments;
2352 u64 rx_ucast_packets;
2353 u64 rx_mcast_packets;
2354 u64 rx_bcast_packets;
2355 u64 rx_fcs_errors;
2356 u64 rx_align_errors;
2357 u64 rx_xon_pause_rcvd;
2358 u64 rx_xoff_pause_rcvd;
2359 u64 rx_mac_ctrl_rcvd;
2360 u64 rx_xoff_entered;
2361 u64 rx_frame_too_long_errors;
2362 u64 rx_jabbers;
2363 u64 rx_undersize_packets;
2364 u64 rx_in_length_errors;
2365 u64 rx_out_length_errors;
2366 u64 rx_64_or_less_octet_packets;
2367 u64 rx_65_to_127_octet_packets;
2368 u64 rx_128_to_255_octet_packets;
2369 u64 rx_256_to_511_octet_packets;
2370 u64 rx_512_to_1023_octet_packets;
2371 u64 rx_1024_to_1522_octet_packets;
2372 u64 rx_1523_to_2047_octet_packets;
2373 u64 rx_2048_to_4095_octet_packets;
2374 u64 rx_4096_to_8191_octet_packets;
2375 u64 rx_8192_to_9022_octet_packets;
2376
2377 /* Statistics maintained by Transmit MAC. */
2378 u64 tx_octets;
2379 u64 tx_collisions;
2380 u64 tx_xon_sent;
2381 u64 tx_xoff_sent;
2382 u64 tx_flow_control;
2383 u64 tx_mac_errors;
2384 u64 tx_single_collisions;
2385 u64 tx_mult_collisions;
2386 u64 tx_deferred;
2387 u64 tx_excessive_collisions;
2388 u64 tx_late_collisions;
2389 u64 tx_collide_2times;
2390 u64 tx_collide_3times;
2391 u64 tx_collide_4times;
2392 u64 tx_collide_5times;
2393 u64 tx_collide_6times;
2394 u64 tx_collide_7times;
2395 u64 tx_collide_8times;
2396 u64 tx_collide_9times;
2397 u64 tx_collide_10times;
2398 u64 tx_collide_11times;
2399 u64 tx_collide_12times;
2400 u64 tx_collide_13times;
2401 u64 tx_collide_14times;
2402 u64 tx_collide_15times;
2403 u64 tx_ucast_packets;
2404 u64 tx_mcast_packets;
2405 u64 tx_bcast_packets;
2406 u64 tx_carrier_sense_errors;
2407 u64 tx_discards;
2408 u64 tx_errors;
2409
2410 /* Statistics maintained by Receive List Placement. */
2411 u64 dma_writeq_full;
2412 u64 dma_write_prioq_full;
2413 u64 rxbds_empty;
2414 u64 rx_discards;
2415 u64 rx_errors;
2416 u64 rx_threshold_hit;
2417
2418 /* Statistics maintained by Send Data Initiator. */
2419 u64 dma_readq_full;
2420 u64 dma_read_prioq_full;
2421 u64 tx_comp_queue_full;
2422
2423 /* Statistics maintained by Host Coalescing. */
2424 u64 ring_set_send_prod_index;
2425 u64 ring_status_update;
2426 u64 nic_irqs;
2427 u64 nic_avoided_irqs;
2428 u64 nic_tx_threshold_hit;
2429};
2430
2431struct tg3 {
2432 /* begin "general, frequently-used members" cacheline section */
2433
David S. Millerf47c11e2005-06-24 20:18:35 -07002434 /* If the IRQ handler (which runs lockless) needs to be
2435 * quiesced, the following bitmask state is used. The
2436 * SYNC flag is set by non-IRQ context code to initiate
2437 * the quiescence.
2438 *
2439 * When the IRQ handler notices that SYNC is set, it
2440 * disables interrupts and returns.
2441 *
2442 * When all outstanding IRQ handlers have returned after
2443 * the SYNC flag has been set, the setter can be assured
2444 * that interrupts will no longer get run.
2445 *
2446 * In this way all SMP driver locks are never acquired
2447 * in hw IRQ context, only sw IRQ context or lower.
2448 */
2449 unsigned int irq_sync;
2450
Linus Torvalds1da177e2005-04-16 15:20:36 -07002451 /* SMP locking strategy:
2452 *
Michael Chan00b70502006-06-17 21:58:45 -07002453 * lock: Held during reset, PHY access, timer, and when
2454 * updating tg3_flags and tg3_flags2.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002455 *
Michael Chan1b2a7202006-08-07 21:46:02 -07002456 * netif_tx_lock: Held during tg3_start_xmit. tg3_tx holds
2457 * netif_tx_lock when it needs to call
2458 * netif_wake_queue.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002459 *
David S. Millerf47c11e2005-06-24 20:18:35 -07002460 * Both of these locks are to be held with BH safety.
Michael Chan00b70502006-06-17 21:58:45 -07002461 *
2462 * Because the IRQ handler, tg3_poll, and tg3_start_xmit
2463 * are running lockless, it is necessary to completely
2464 * quiesce the chip with tg3_netif_stop and tg3_full_lock
2465 * before reconfiguring the device.
2466 *
2467 * indirect_lock: Held when accessing registers indirectly
2468 * with IRQ disabling.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002469 */
2470 spinlock_t lock;
2471 spinlock_t indirect_lock;
2472
Michael Chan20094932005-08-09 20:16:32 -07002473 u32 (*read32) (struct tg3 *, u32);
2474 void (*write32) (struct tg3 *, u32, u32);
Michael Chan09ee9292005-08-09 20:17:00 -07002475 u32 (*read32_mbox) (struct tg3 *, u32);
Michael Chan20094932005-08-09 20:16:32 -07002476 void (*write32_mbox) (struct tg3 *, u32,
2477 u32);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002478 void __iomem *regs;
Matt Carlson0d3031d2007-10-10 18:02:43 -07002479 void __iomem *aperegs;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002480 struct net_device *dev;
2481 struct pci_dev *pdev;
2482
2483 struct tg3_hw_status *hw_status;
2484 dma_addr_t status_mapping;
David S. Millerfac9b832005-05-18 22:46:34 -07002485 u32 last_tag;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002486
2487 u32 msg_enable;
2488
2489 /* begin "tx thread" cacheline section */
Michael Chan20094932005-08-09 20:16:32 -07002490 void (*write32_tx_mbox) (struct tg3 *, u32,
2491 u32);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002492 u32 tx_prod;
2493 u32 tx_cons;
2494 u32 tx_pending;
2495
Linus Torvalds1da177e2005-04-16 15:20:36 -07002496 struct tg3_tx_buffer_desc *tx_ring;
2497 struct tx_ring_info *tx_buffers;
2498 dma_addr_t tx_desc_mapping;
2499
2500 /* begin "rx thread" cacheline section */
Stephen Hemmingerbea33482007-10-03 16:41:36 -07002501 struct napi_struct napi;
Michael Chan20094932005-08-09 20:16:32 -07002502 void (*write32_rx_mbox) (struct tg3 *, u32,
2503 u32);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002504 u32 rx_rcb_ptr;
2505 u32 rx_std_ptr;
2506 u32 rx_jumbo_ptr;
2507 u32 rx_pending;
2508 u32 rx_jumbo_pending;
2509#if TG3_VLAN_TAG_USED
2510 struct vlan_group *vlgrp;
2511#endif
2512
2513 struct tg3_rx_buffer_desc *rx_std;
2514 struct ring_info *rx_std_buffers;
2515 dma_addr_t rx_std_mapping;
Michael Chanf92905d2006-06-29 20:14:29 -07002516 u32 rx_std_max_post;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002517
2518 struct tg3_rx_buffer_desc *rx_jumbo;
2519 struct ring_info *rx_jumbo_buffers;
2520 dma_addr_t rx_jumbo_mapping;
2521
2522 struct tg3_rx_buffer_desc *rx_rcb;
2523 dma_addr_t rx_rcb_mapping;
2524
Michael Chan7e72aad2005-07-25 12:31:17 -07002525 u32 rx_pkt_buf_sz;
2526
Linus Torvalds1da177e2005-04-16 15:20:36 -07002527 /* begin "everything else" cacheline(s) section */
2528 struct net_device_stats net_stats;
2529 struct net_device_stats net_stats_prev;
2530 struct tg3_ethtool_stats estats;
2531 struct tg3_ethtool_stats estats_prev;
2532
Matt Carlson4ba526c2008-08-15 14:10:04 -07002533 union {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002534 unsigned long phy_crc_errors;
Matt Carlson4ba526c2008-08-15 14:10:04 -07002535 unsigned long last_event_jiffies;
2536 };
Linus Torvalds1da177e2005-04-16 15:20:36 -07002537
2538 u32 rx_offset;
2539 u32 tg3_flags;
David S. Millerfac9b832005-05-18 22:46:34 -07002540#define TG3_FLAG_TAGGED_STATUS 0x00000001
Linus Torvalds1da177e2005-04-16 15:20:36 -07002541#define TG3_FLAG_TXD_MBOX_HWBUG 0x00000002
2542#define TG3_FLAG_RX_CHECKSUMS 0x00000004
2543#define TG3_FLAG_USE_LINKCHG_REG 0x00000008
2544#define TG3_FLAG_USE_MI_INTERRUPT 0x00000010
2545#define TG3_FLAG_ENABLE_ASF 0x00000020
Matt Carlson8ed5d972007-05-07 00:25:49 -07002546#define TG3_FLAG_ASPM_WORKAROUND 0x00000040
Linus Torvalds1da177e2005-04-16 15:20:36 -07002547#define TG3_FLAG_POLL_SERDES 0x00000080
Linus Torvalds1da177e2005-04-16 15:20:36 -07002548#define TG3_FLAG_MBOX_WRITE_REORDER 0x00000100
Linus Torvalds1da177e2005-04-16 15:20:36 -07002549#define TG3_FLAG_PCIX_TARGET_HWBUG 0x00000200
2550#define TG3_FLAG_WOL_SPEED_100MB 0x00000400
2551#define TG3_FLAG_WOL_ENABLE 0x00000800
2552#define TG3_FLAG_EEPROM_WRITE_PROT 0x00001000
2553#define TG3_FLAG_NVRAM 0x00002000
2554#define TG3_FLAG_NVRAM_BUFFERED 0x00004000
Linus Torvalds1da177e2005-04-16 15:20:36 -07002555#define TG3_FLAG_PCIX_MODE 0x00020000
2556#define TG3_FLAG_PCI_HIGH_SPEED 0x00040000
2557#define TG3_FLAG_PCI_32BIT 0x00080000
Michael Chanbbadf502006-04-06 21:46:34 -07002558#define TG3_FLAG_SRAM_USE_CONFIG 0x00100000
Michael Chandf3e6542006-05-26 17:48:07 -07002559#define TG3_FLAG_TX_RECOVERY_PENDING 0x00200000
Gary Zambranoa85feb82007-05-05 11:52:19 -07002560#define TG3_FLAG_WOL_CAP 0x00400000
Michael Chan0f893dc2005-07-25 12:30:38 -07002561#define TG3_FLAG_JUMBO_RING_ENABLE 0x00800000
Linus Torvalds1da177e2005-04-16 15:20:36 -07002562#define TG3_FLAG_10_100_ONLY 0x01000000
2563#define TG3_FLAG_PAUSE_AUTONEG 0x02000000
Matt Carlson795d01c2007-10-07 23:28:17 -07002564#define TG3_FLAG_CPMU_PRESENT 0x04000000
Michael Chan4a29cc22006-03-19 13:21:12 -08002565#define TG3_FLAG_40BIT_DMA_BUG 0x08000000
Linus Torvalds1da177e2005-04-16 15:20:36 -07002566#define TG3_FLAG_BROKEN_CHECKSUMS 0x10000000
Michael Chan7544b092007-05-05 13:08:32 -07002567#define TG3_FLAG_SUPPORT_MSI 0x20000000
Michael Chand18edcb2007-03-24 20:57:11 -07002568#define TG3_FLAG_CHIP_RESETTING 0x40000000
Linus Torvalds1da177e2005-04-16 15:20:36 -07002569#define TG3_FLAG_INIT_COMPLETE 0x80000000
2570 u32 tg3_flags2;
2571#define TG3_FLG2_RESTART_TIMER 0x00000001
Michael Chan7f62ad52007-02-20 23:25:40 -08002572#define TG3_FLG2_TSO_BUG 0x00000002
Linus Torvalds1da177e2005-04-16 15:20:36 -07002573#define TG3_FLG2_NO_ETH_WIRE_SPEED 0x00000004
2574#define TG3_FLG2_IS_5788 0x00000008
2575#define TG3_FLG2_MAX_RXPEND_64 0x00000010
2576#define TG3_FLG2_TSO_CAPABLE 0x00000020
2577#define TG3_FLG2_PHY_ADC_BUG 0x00000040
2578#define TG3_FLG2_PHY_5704_A0_BUG 0x00000080
2579#define TG3_FLG2_PHY_BER_BUG 0x00000100
2580#define TG3_FLG2_PCI_EXPRESS 0x00000200
2581#define TG3_FLG2_ASF_NEW_HANDSHAKE 0x00000400
2582#define TG3_FLG2_HW_AUTONEG 0x00000800
Michael Chan9d26e212006-12-07 00:21:14 -08002583#define TG3_FLG2_IS_NIC 0x00001000
Linus Torvalds1da177e2005-04-16 15:20:36 -07002584#define TG3_FLG2_PHY_SERDES 0x00002000
2585#define TG3_FLG2_CAPACITIVE_COUPLING 0x00004000
2586#define TG3_FLG2_FLASH 0x00008000
Michael Chan5a6f3072006-03-20 22:28:05 -08002587#define TG3_FLG2_HW_TSO_1 0x00010000
Linus Torvalds1da177e2005-04-16 15:20:36 -07002588#define TG3_FLG2_SERDES_PREEMPHASIS 0x00020000
2589#define TG3_FLG2_5705_PLUS 0x00040000
John W. Linville6708e5c2005-04-21 17:00:52 -07002590#define TG3_FLG2_5750_PLUS 0x00080000
Michael Chane6af3012005-04-21 17:12:05 -07002591#define TG3_FLG2_PROTECTED_NVRAM 0x00100000
Michael Chan88b06bc22005-04-21 17:13:25 -07002592#define TG3_FLG2_USING_MSI 0x00200000
Michael Chan0f893dc2005-07-25 12:30:38 -07002593#define TG3_FLG2_JUMBO_CAPABLE 0x00400000
Michael Chan747e8f82005-07-25 12:33:22 -07002594#define TG3_FLG2_MII_SERDES 0x00800000
2595#define TG3_FLG2_ANY_SERDES (TG3_FLG2_PHY_SERDES | \
2596 TG3_FLG2_MII_SERDES)
2597#define TG3_FLG2_PARALLEL_DETECT 0x01000000
Michael Chan68929142005-08-09 20:17:14 -07002598#define TG3_FLG2_ICH_WORKAROUND 0x02000000
Michael Chana4e2b342005-10-26 15:46:52 -07002599#define TG3_FLG2_5780_CLASS 0x04000000
Michael Chan5a6f3072006-03-20 22:28:05 -08002600#define TG3_FLG2_HW_TSO_2 0x08000000
2601#define TG3_FLG2_HW_TSO (TG3_FLG2_HW_TSO_1 | TG3_FLG2_HW_TSO_2)
Michael Chanfcfa0a32006-03-20 22:28:41 -08002602#define TG3_FLG2_1SHOT_MSI 0x10000000
Michael Chanc424cb22006-04-29 18:56:34 -07002603#define TG3_FLG2_PHY_JITTER_BUG 0x20000000
David S. Millerf49639e2006-06-09 11:58:36 -07002604#define TG3_FLG2_NO_FWARE_REPORTED 0x40000000
Michael Chanc1d2a192007-01-08 19:57:20 -08002605#define TG3_FLG2_PHY_ADJUST_TRIM 0x80000000
Matt Carlson6b91fa02007-10-10 18:01:09 -07002606 u32 tg3_flags3;
2607#define TG3_FLG3_NO_NVRAM_ADDR_TRANS 0x00000001
Matt Carlson0d3031d2007-10-10 18:02:43 -07002608#define TG3_FLG3_ENABLE_APE 0x00000002
Matt Carlson41588ba2008-04-19 18:12:33 -07002609#define TG3_FLG3_5701_DMA_BUG 0x00000008
Matt Carlsondd477002008-05-25 23:45:58 -07002610#define TG3_FLG3_USE_PHYLIB 0x00000010
Matt Carlson158d7ab2008-05-29 01:37:54 -07002611#define TG3_FLG3_MDIOBUS_INITED 0x00000020
2612#define TG3_FLG3_MDIOBUS_PAUSED 0x00000040
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07002613#define TG3_FLG3_PHY_CONNECTED 0x00000080
Matt Carlsona9daf362008-05-25 23:49:44 -07002614#define TG3_FLG3_RGMII_STD_IBND_DISABLE 0x00000100
2615#define TG3_FLG3_RGMII_EXT_IBND_RX_EN 0x00000200
2616#define TG3_FLG3_RGMII_EXT_IBND_TX_EN 0x00000400
Matt Carlson5e7dfd02008-11-21 17:18:16 -08002617#define TG3_FLG3_CLKREQ_BUG 0x00000800
Matt Carlson6833c042008-11-21 17:18:59 -08002618#define TG3_FLG3_PHY_ENABLE_APD 0x00001000
Matt Carlson321d32a2008-11-21 17:22:19 -08002619#define TG3_FLG3_5755_PLUS 0x00002000
Linus Torvalds1da177e2005-04-16 15:20:36 -07002620
Linus Torvalds1da177e2005-04-16 15:20:36 -07002621 struct timer_list timer;
2622 u16 timer_counter;
2623 u16 timer_multiplier;
2624 u32 timer_offset;
2625 u16 asf_counter;
2626 u16 asf_multiplier;
2627
Michael Chan3d3ebe72006-09-27 15:59:15 -07002628 /* 1 second counter for transient serdes link events */
2629 u32 serdes_counter;
2630#define SERDES_AN_TIMEOUT_5704S 2
2631#define SERDES_PARALLEL_DET_TIMEOUT 1
2632#define SERDES_AN_TIMEOUT_5714S 1
2633
Linus Torvalds1da177e2005-04-16 15:20:36 -07002634 struct tg3_link_config link_config;
2635 struct tg3_bufmgr_config bufmgr_config;
2636
2637 /* cache h/w values, often passed straight to h/w */
2638 u32 rx_mode;
2639 u32 tx_mode;
2640 u32 mac_mode;
2641 u32 mi_mode;
2642 u32 misc_host_ctrl;
2643 u32 grc_mode;
2644 u32 grc_local_ctrl;
2645 u32 dma_rwctrl;
2646 u32 coalesce_mode;
Matt Carlson8ed5d972007-05-07 00:25:49 -07002647 u32 pwrmgmt_thresh;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002648
2649 /* PCI block */
Matt Carlson795d01c2007-10-07 23:28:17 -07002650 u32 pci_chip_rev_id;
Matt Carlson69fc4052008-12-21 20:19:57 -08002651 u16 pci_cmd;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002652 u8 pci_cacheline_sz;
2653 u8 pci_lat_timer;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002654
2655 int pm_cap;
Michael Chan4cf78e42005-07-25 12:29:19 -07002656 int msi_cap;
Matt Carlson5e7dfd02008-11-21 17:18:16 -08002657 union {
Matt Carlson9974a352007-10-07 23:27:28 -07002658 int pcix_cap;
Matt Carlson5e7dfd02008-11-21 17:18:16 -08002659 int pcie_cap;
2660 };
Linus Torvalds1da177e2005-04-16 15:20:36 -07002661
Lennert Buytenhek298cf9be2008-10-08 16:29:57 -07002662 struct mii_bus *mdio_bus;
Matt Carlson158d7ab2008-05-29 01:37:54 -07002663 int mdio_irq[PHY_MAX_ADDR];
2664
Linus Torvalds1da177e2005-04-16 15:20:36 -07002665 /* PHY info */
2666 u32 phy_id;
2667#define PHY_ID_MASK 0xfffffff0
2668#define PHY_ID_BCM5400 0x60008040
2669#define PHY_ID_BCM5401 0x60008050
2670#define PHY_ID_BCM5411 0x60008070
2671#define PHY_ID_BCM5701 0x60008110
2672#define PHY_ID_BCM5703 0x60008160
2673#define PHY_ID_BCM5704 0x60008190
2674#define PHY_ID_BCM5705 0x600081a0
2675#define PHY_ID_BCM5750 0x60008180
Michael Chan85e94ce2005-04-21 17:05:28 -07002676#define PHY_ID_BCM5752 0x60008100
Michael Chana4e2b342005-10-26 15:46:52 -07002677#define PHY_ID_BCM5714 0x60008340
Michael Chan4cf78e42005-07-25 12:29:19 -07002678#define PHY_ID_BCM5780 0x60008350
Michael Chanaf36e6b2006-03-23 01:28:06 -08002679#define PHY_ID_BCM5755 0xbc050cc0
Michael Chand9ab5ad2006-03-20 22:27:35 -08002680#define PHY_ID_BCM5787 0xbc050ce0
Michael Chan126a3362006-09-27 16:03:07 -07002681#define PHY_ID_BCM5756 0xbc050ed0
Matt Carlsond30cdd22007-10-07 23:28:35 -07002682#define PHY_ID_BCM5784 0xbc050fa0
Matt Carlson9936bcf2007-10-10 18:03:07 -07002683#define PHY_ID_BCM5761 0xbc050fd0
Michael Chanb5d37722006-09-27 16:06:21 -07002684#define PHY_ID_BCM5906 0xdc00ac40
Linus Torvalds1da177e2005-04-16 15:20:36 -07002685#define PHY_ID_BCM8002 0x60010140
2686#define PHY_ID_INVALID 0xffffffff
2687#define PHY_ID_REV_MASK 0x0000000f
2688#define PHY_REV_BCM5401_B0 0x1
2689#define PHY_REV_BCM5401_B2 0x3
2690#define PHY_REV_BCM5401_C0 0x6
2691#define PHY_REV_BCM5411_X0 0x1 /* Found on Netgear GA302T */
Matt Carlsona9daf362008-05-25 23:49:44 -07002692#define TG3_PHY_ID_BCM50610 0x143bd60
2693#define TG3_PHY_ID_BCMAC131 0x143bc70
Matt Carlsonfcb389d2008-11-03 16:55:44 -08002694#define TG3_PHY_ID_RTL8211C 0x001cc910
2695#define TG3_PHY_ID_RTL8201E 0x00008200
Matt Carlson321d32a2008-11-21 17:22:19 -08002696#define TG3_PHY_ID_BCM57780 0x03625d90
Matt Carlson0a459aa2008-11-03 16:54:15 -08002697#define TG3_PHY_OUI_MASK 0xfffffc00
2698#define TG3_PHY_OUI_1 0x00206000
2699#define TG3_PHY_OUI_2 0x0143bc00
2700#define TG3_PHY_OUI_3 0x03625c00
Linus Torvalds1da177e2005-04-16 15:20:36 -07002701
2702 u32 led_ctrl;
Matt Carlsonb2a5c192008-04-03 21:44:44 -07002703 u32 phy_otp;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002704
2705 char board_part_number[24];
Matt Carlson9c8a6202007-10-21 16:16:08 -07002706#define TG3_VER_SIZE 32
2707 char fw_ver[TG3_VER_SIZE];
Linus Torvalds1da177e2005-04-16 15:20:36 -07002708 u32 nic_sram_data_cfg;
2709 u32 pci_clock_ctrl;
2710 struct pci_dev *pdev_peer;
2711
2712 /* This macro assumes the passed PHY ID is already masked
2713 * with PHY_ID_MASK.
2714 */
2715#define KNOWN_PHY_ID(X) \
2716 ((X) == PHY_ID_BCM5400 || (X) == PHY_ID_BCM5401 || \
2717 (X) == PHY_ID_BCM5411 || (X) == PHY_ID_BCM5701 || \
2718 (X) == PHY_ID_BCM5703 || (X) == PHY_ID_BCM5704 || \
2719 (X) == PHY_ID_BCM5705 || (X) == PHY_ID_BCM5750 || \
Michael Chana4e2b342005-10-26 15:46:52 -07002720 (X) == PHY_ID_BCM5752 || (X) == PHY_ID_BCM5714 || \
Michael Chand9ab5ad2006-03-20 22:27:35 -08002721 (X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \
Michael Chan126a3362006-09-27 16:03:07 -07002722 (X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM5756 || \
Matt Carlson9936bcf2007-10-10 18:03:07 -07002723 (X) == PHY_ID_BCM5906 || (X) == PHY_ID_BCM5761 || \
2724 (X) == PHY_ID_BCM8002)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002725
2726 struct tg3_hw_stats *hw_stats;
2727 dma_addr_t stats_mapping;
2728 struct work_struct reset_task;
2729
Michael Chanec41c7d2006-01-17 02:40:55 -08002730 int nvram_lock_cnt;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002731 u32 nvram_size;
Matt Carlsonfd1122a2008-05-02 16:48:36 -07002732#define TG3_NVRAM_SIZE_64KB 0x00010000
2733#define TG3_NVRAM_SIZE_128KB 0x00020000
2734#define TG3_NVRAM_SIZE_256KB 0x00040000
2735#define TG3_NVRAM_SIZE_512KB 0x00080000
2736#define TG3_NVRAM_SIZE_1MB 0x00100000
2737#define TG3_NVRAM_SIZE_2MB 0x00200000
2738
Linus Torvalds1da177e2005-04-16 15:20:36 -07002739 u32 nvram_pagesize;
2740 u32 nvram_jedecnum;
2741
2742#define JEDEC_ATMEL 0x1f
2743#define JEDEC_ST 0x20
2744#define JEDEC_SAIFUN 0x4f
2745#define JEDEC_SST 0xbf
2746
Matt Carlsonfd1122a2008-05-02 16:48:36 -07002747#define ATMEL_AT24C64_CHIP_SIZE TG3_NVRAM_SIZE_64KB
Linus Torvalds1da177e2005-04-16 15:20:36 -07002748#define ATMEL_AT24C64_PAGE_SIZE (32)
2749
Matt Carlsonfd1122a2008-05-02 16:48:36 -07002750#define ATMEL_AT24C512_CHIP_SIZE TG3_NVRAM_SIZE_512KB
Linus Torvalds1da177e2005-04-16 15:20:36 -07002751#define ATMEL_AT24C512_PAGE_SIZE (128)
2752
2753#define ATMEL_AT45DB0X1B_PAGE_POS 9
2754#define ATMEL_AT45DB0X1B_PAGE_SIZE 264
2755
2756#define ATMEL_AT25F512_PAGE_SIZE 256
2757
2758#define ST_M45PEX0_PAGE_SIZE 256
2759
2760#define SAIFUN_SA25F0XX_PAGE_SIZE 256
2761
2762#define SST_25VF0X0_PAGE_SIZE 4098
2763
David S. Miller15f98502005-05-18 22:49:26 -07002764 struct ethtool_coalesce coal;
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -08002765
2766 /* firmware info */
Matt Carlson9e9fd122009-01-19 16:57:45 -08002767 const char *fw_needed;
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -08002768 const struct firmware *fw;
2769 u32 fw_len; /* includes BSS */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002770};
2771
2772#endif /* !(_T3_H) */