blob: e6c09a9174ce9ad30deb7de562f0557a6a395816 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * DTC controller, taken from T128 driver by...
3 * Copyright 1993, Drew Eckhardt
4 * Visionary Computing
5 * (Unix and Linux consulting and custom programming)
6 * drew@colorado.edu
7 * +1 (303) 440-4894
Linus Torvalds1da177e2005-04-16 15:20:36 -07008 */
9
10#ifndef DTC3280_H
11#define DTC3280_H
12
Linus Torvalds1da177e2005-04-16 15:20:36 -070013#ifndef CMD_PER_LUN
14#define CMD_PER_LUN 2
15#endif
16
17#ifndef CAN_QUEUE
18#define CAN_QUEUE 32
19#endif
20
21#define NCR5380_implementation_fields \
22 void __iomem *base
23
Finn Thain54d8fe42016-01-03 16:05:06 +110024#define DTC_address(reg) \
25 (((struct NCR5380_hostdata *)shost_priv(instance))->base + DTC_5380_OFFSET + reg)
Linus Torvalds1da177e2005-04-16 15:20:36 -070026
Linus Torvalds1da177e2005-04-16 15:20:36 -070027#define NCR5380_read(reg) (readb(DTC_address(reg)))
28#define NCR5380_write(reg, value) (writeb(value, DTC_address(reg)))
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
Finn Thainff3d4572016-01-03 16:05:25 +110030#define NCR5380_dma_xfer_len(instance, cmd, phase) \
31 dtc_dma_xfer_len(cmd)
32
Linus Torvalds1da177e2005-04-16 15:20:36 -070033#define NCR5380_intr dtc_intr
34#define NCR5380_queue_command dtc_queue_command
35#define NCR5380_abort dtc_abort
36#define NCR5380_bus_reset dtc_bus_reset
Finn Thain8c325132014-11-12 16:11:58 +110037#define NCR5380_info dtc_info
Al Virodd7ab712013-03-31 01:15:54 -040038#define NCR5380_show_info dtc_show_info
39#define NCR5380_write_info dtc_write_info
Linus Torvalds1da177e2005-04-16 15:20:36 -070040
41/* 15 12 11 10
42 1001 1100 0000 0000 */
43
44#define DTC_IRQS 0x9c00
45
46
47#endif /* DTC3280_H */