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Zhang Xiantao1d737c82007-12-14 09:35:10 +08001#ifndef __KVM_X86_MMU_H
2#define __KVM_X86_MMU_H
3
Avi Kivityedf88412007-12-16 11:02:48 +02004#include <linux/kvm_host.h>
Avi Kivityfc78f512009-12-07 12:16:48 +02005#include "kvm_cache_regs.h"
Zhang Xiantao1d737c82007-12-14 09:35:10 +08006
Sheng Yang8c6d6ad2008-04-25 10:17:08 +08007#define PT64_PT_BITS 9
8#define PT64_ENT_PER_PAGE (1 << PT64_PT_BITS)
9#define PT32_PT_BITS 10
10#define PT32_ENT_PER_PAGE (1 << PT32_PT_BITS)
11
12#define PT_WRITABLE_SHIFT 1
13
14#define PT_PRESENT_MASK (1ULL << 0)
15#define PT_WRITABLE_MASK (1ULL << PT_WRITABLE_SHIFT)
16#define PT_USER_MASK (1ULL << 2)
17#define PT_PWT_MASK (1ULL << 3)
18#define PT_PCD_MASK (1ULL << 4)
Avi Kivity1b7fcd32008-05-15 13:51:35 +030019#define PT_ACCESSED_SHIFT 5
20#define PT_ACCESSED_MASK (1ULL << PT_ACCESSED_SHIFT)
Sheng Yang8c6d6ad2008-04-25 10:17:08 +080021#define PT_DIRTY_MASK (1ULL << 6)
22#define PT_PAGE_SIZE_MASK (1ULL << 7)
23#define PT_PAT_MASK (1ULL << 7)
24#define PT_GLOBAL_MASK (1ULL << 8)
25#define PT64_NX_SHIFT 63
26#define PT64_NX_MASK (1ULL << PT64_NX_SHIFT)
27
28#define PT_PAT_SHIFT 7
29#define PT_DIR_PAT_SHIFT 12
30#define PT_DIR_PAT_MASK (1ULL << PT_DIR_PAT_SHIFT)
31
32#define PT32_DIR_PSE36_SIZE 4
33#define PT32_DIR_PSE36_SHIFT 13
34#define PT32_DIR_PSE36_MASK \
35 (((1ULL << PT32_DIR_PSE36_SIZE) - 1) << PT32_DIR_PSE36_SHIFT)
36
37#define PT64_ROOT_LEVEL 4
38#define PT32_ROOT_LEVEL 2
39#define PT32E_ROOT_LEVEL 3
40
Sheng Yangc9c54172010-01-05 19:02:26 +080041#define PT_PDPE_LEVEL 3
42#define PT_DIRECTORY_LEVEL 2
43#define PT_PAGE_TABLE_LEVEL 1
44
Gleb Natapov1871c602010-02-10 14:21:32 +020045#define PFERR_PRESENT_MASK (1U << 0)
46#define PFERR_WRITE_MASK (1U << 1)
47#define PFERR_USER_MASK (1U << 2)
48#define PFERR_RSVD_MASK (1U << 3)
49#define PFERR_FETCH_MASK (1U << 4)
50
Marcelo Tosatti94d8b052009-06-11 12:07:42 -030051int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4]);
Xiao Guangrongce88dec2011-07-12 03:33:44 +080052void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask);
53int handle_mmio_page_fault_common(struct kvm_vcpu *vcpu, u64 addr, bool direct);
Joerg Roedel52fde8d2010-09-10 17:30:44 +020054int kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context);
Marcelo Tosatti94d8b052009-06-11 12:07:42 -030055
Dave Hansene0df7b92010-08-19 18:11:05 -070056static inline unsigned int kvm_mmu_available_pages(struct kvm *kvm)
57{
Dave Hansen49d5ca22010-08-19 18:11:28 -070058 return kvm->arch.n_max_mmu_pages -
59 kvm->arch.n_used_mmu_pages;
Dave Hansene0df7b92010-08-19 18:11:05 -070060}
61
Zhang Xiantao1d737c82007-12-14 09:35:10 +080062static inline void kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
63{
Dave Hansene0df7b92010-08-19 18:11:05 -070064 if (unlikely(kvm_mmu_available_pages(vcpu->kvm)< KVM_MIN_FREE_MMU_PAGES))
Zhang Xiantao1d737c82007-12-14 09:35:10 +080065 __kvm_mmu_free_some_pages(vcpu);
66}
67
68static inline int kvm_mmu_reload(struct kvm_vcpu *vcpu)
69{
70 if (likely(vcpu->arch.mmu.root_hpa != INVALID_PAGE))
71 return 0;
72
73 return kvm_mmu_load(vcpu);
74}
75
Avi Kivity43a37952009-06-10 14:12:05 +030076static inline int is_present_gpte(unsigned long pte)
Dong, Eddie20c466b2009-03-31 23:03:45 +080077{
78 return pte & PT_PRESENT_MASK;
79}
80
Xiao Guangrongbebb1062011-07-12 03:23:20 +080081static inline int is_writable_pte(unsigned long pte)
82{
83 return pte & PT_WRITABLE_MASK;
84}
85
86static inline bool is_write_protection(struct kvm_vcpu *vcpu)
87{
88 return kvm_read_cr0_bits(vcpu, X86_CR0_WP);
89}
90
91static inline bool check_write_user_access(struct kvm_vcpu *vcpu,
92 bool write_fault, bool user_fault,
93 unsigned long pte)
94{
95 if (unlikely(write_fault && !is_writable_pte(pte)
96 && (user_fault || is_write_protection(vcpu))))
97 return false;
98
99 if (unlikely(user_fault && !(pte & PT_USER_MASK)))
100 return false;
101
102 return true;
103}
Zhang Xiantao1d737c82007-12-14 09:35:10 +0800104#endif