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Jayachandran C5c64250672011-05-07 01:36:40 +05301/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/kernel.h>
36#include <linux/delay.h>
37#include <linux/init.h>
38#include <linux/smp.h>
39#include <linux/irq.h>
40
41#include <asm/mmu_context.h>
42
43#include <asm/netlogic/interrupt.h>
44#include <asm/netlogic/mips-extns.h>
Jayachandran C0c965402011-11-11 17:08:29 +053045#include <asm/netlogic/haldefs.h>
46#include <asm/netlogic/common.h>
Jayachandran C5c64250672011-05-07 01:36:40 +053047
Jayachandran C65040e22011-11-16 00:21:28 +000048#if defined(CONFIG_CPU_XLP)
49#include <asm/netlogic/xlp-hal/iomap.h>
Jayachandran C66d29982011-11-16 00:21:29 +000050#include <asm/netlogic/xlp-hal/xlp.h>
Jayachandran C65040e22011-11-16 00:21:28 +000051#include <asm/netlogic/xlp-hal/pic.h>
52#elif defined(CONFIG_CPU_XLR)
Jayachandran C5c64250672011-05-07 01:36:40 +053053#include <asm/netlogic/xlr/iomap.h>
54#include <asm/netlogic/xlr/pic.h>
Jayachandran C66d29982011-11-16 00:21:29 +000055#include <asm/netlogic/xlr/xlr.h>
Jayachandran C65040e22011-11-16 00:21:28 +000056#else
57#error "Unknown CPU"
58#endif
Jayachandran C5c64250672011-05-07 01:36:40 +053059
Jayachandran C0c965402011-11-11 17:08:29 +053060void nlm_send_ipi_single(int logical_cpu, unsigned int action)
Jayachandran C5c64250672011-05-07 01:36:40 +053061{
Jayachandran Cc2736522015-01-07 16:58:30 +053062 unsigned int hwtid;
Jayachandran C77ae7982012-10-31 12:01:39 +000063 uint64_t picbase;
64
Jayachandran Cc2736522015-01-07 16:58:30 +053065 /* node id is part of hwtid, and needed for send_ipi */
66 hwtid = cpu_logical_map(logical_cpu);
67 picbase = nlm_get_node(nlm_hwtid_to_node(hwtid))->picbase;
Jayachandran C5c64250672011-05-07 01:36:40 +053068
69 if (action & SMP_CALL_FUNCTION)
Jayachandran Cc2736522015-01-07 16:58:30 +053070 nlm_pic_send_ipi(picbase, hwtid, IRQ_IPI_SMP_FUNCTION, 0);
Jayachandran C0c965402011-11-11 17:08:29 +053071 if (action & SMP_RESCHEDULE_YOURSELF)
Jayachandran Cc2736522015-01-07 16:58:30 +053072 nlm_pic_send_ipi(picbase, hwtid, IRQ_IPI_SMP_RESCHEDULE, 0);
Jayachandran C5c64250672011-05-07 01:36:40 +053073}
74
75void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action)
76{
77 int cpu;
78
79 for_each_cpu(cpu, mask) {
Jayachandran C0c965402011-11-11 17:08:29 +053080 nlm_send_ipi_single(cpu, action);
Jayachandran C5c64250672011-05-07 01:36:40 +053081 }
82}
83
84/* IRQ_IPI_SMP_FUNCTION Handler */
Thomas Gleixnerbd0b9ac2015-09-14 10:42:37 +020085void nlm_smp_function_ipi_handler(struct irq_desc *desc)
Jayachandran C5c64250672011-05-07 01:36:40 +053086{
Thomas Gleixner31429d12015-07-13 20:46:09 +000087 unsigned int irq = irq_desc_get_irq(desc);
Jayachandran C220d9122013-01-14 15:11:54 +000088 clear_c0_eimr(irq);
89 ack_c0_eirr(irq);
Alex Smith4ace6132015-07-24 16:57:49 +010090 generic_smp_call_function_interrupt();
Jayachandran C220d9122013-01-14 15:11:54 +000091 set_c0_eimr(irq);
Jayachandran C5c64250672011-05-07 01:36:40 +053092}
93
94/* IRQ_IPI_SMP_RESCHEDULE handler */
Thomas Gleixnerbd0b9ac2015-09-14 10:42:37 +020095void nlm_smp_resched_ipi_handler(struct irq_desc *desc)
Jayachandran C5c64250672011-05-07 01:36:40 +053096{
Thomas Gleixner31429d12015-07-13 20:46:09 +000097 unsigned int irq = irq_desc_get_irq(desc);
Jayachandran C220d9122013-01-14 15:11:54 +000098 clear_c0_eimr(irq);
99 ack_c0_eirr(irq);
Jayachandran C65040e22011-11-16 00:21:28 +0000100 scheduler_ipi();
Jayachandran C220d9122013-01-14 15:11:54 +0000101 set_c0_eimr(irq);
Jayachandran C5c64250672011-05-07 01:36:40 +0530102}
103
104/*
105 * Called before going into mips code, early cpu init
106 */
Jayachandran C0c965402011-11-11 17:08:29 +0530107void nlm_early_init_secondary(int cpu)
Jayachandran C5c64250672011-05-07 01:36:40 +0530108{
Jayachandran C65040e22011-11-16 00:21:28 +0000109 change_c0_config(CONF_CM_CMASK, 0x3);
Jayachandran C65040e22011-11-16 00:21:28 +0000110#ifdef CONFIG_CPU_XLP
Jayachandran C5b6ff352013-08-11 14:43:55 +0530111 xlp_mmu_init();
Jayachandran C0c965402011-11-11 17:08:29 +0530112#endif
Jayachandran C77ae7982012-10-31 12:01:39 +0000113 write_c0_ebase(nlm_current_node()->ebase);
Jayachandran C5c64250672011-05-07 01:36:40 +0530114}
115
116/*
117 * Code to run on secondary just after probing the CPU
118 */
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000119static void nlm_init_secondary(void)
Jayachandran C5c64250672011-05-07 01:36:40 +0530120{
Jayachandran C38541742012-10-31 12:01:41 +0000121 int hwtid;
122
123 hwtid = hard_smp_processor_id();
124 current_cpu_data.core = hwtid / NLM_THREADS_PER_CORE;
Jayachandran Cc2736522015-01-07 16:58:30 +0530125 current_cpu_data.package = nlm_nodeid();
Ganesan Ramalingamed21cfe2012-10-31 12:01:42 +0000126 nlm_percpu_init(hwtid);
Jayachandran C38541742012-10-31 12:01:41 +0000127 nlm_smp_irq_init(hwtid);
Jayachandran C5c64250672011-05-07 01:36:40 +0530128}
129
Hillf Dantonb3ea5812011-11-16 00:21:29 +0000130void nlm_prepare_cpus(unsigned int max_cpus)
131{
132 /* declare we are SMT capable */
133 smp_num_siblings = nlm_threads_per_core;
134}
135
Jayachandran C5c64250672011-05-07 01:36:40 +0530136void nlm_smp_finish(void)
137{
Jayachandran C39263ee2011-06-07 03:14:12 +0530138 local_irq_enable();
Jayachandran C5c64250672011-05-07 01:36:40 +0530139}
140
Jayachandran C5c64250672011-05-07 01:36:40 +0530141/*
142 * Boot all other cpus in the system, initialize them, and bring them into
143 * the boot function
144 */
Jayachandran C5c64250672011-05-07 01:36:40 +0530145unsigned long nlm_next_gp;
146unsigned long nlm_next_sp;
Jayachandran C62b734d2013-03-23 17:27:55 +0000147static cpumask_t phys_cpu_present_mask;
Jayachandran C5c64250672011-05-07 01:36:40 +0530148
149void nlm_boot_secondary(int logical_cpu, struct task_struct *idle)
150{
Jayachandran Cc2736522015-01-07 16:58:30 +0530151 uint64_t picbase;
152 int hwtid;
Jayachandran C5c64250672011-05-07 01:36:40 +0530153
Jayachandran Cc2736522015-01-07 16:58:30 +0530154 hwtid = cpu_logical_map(logical_cpu);
155 picbase = nlm_get_node(nlm_hwtid_to_node(hwtid))->picbase;
156
Jayachandran C77ae7982012-10-31 12:01:39 +0000157 nlm_next_sp = (unsigned long)__KSTK_TOS(idle);
158 nlm_next_gp = (unsigned long)task_thread_info(idle);
Jayachandran C5c64250672011-05-07 01:36:40 +0530159
Jayachandran C77ae7982012-10-31 12:01:39 +0000160 /* barrier for sp/gp store above */
Jayachandran C5c64250672011-05-07 01:36:40 +0530161 __sync();
Jayachandran Cc2736522015-01-07 16:58:30 +0530162 nlm_pic_send_ipi(picbase, hwtid, 1, 1); /* NMI */
Jayachandran C5c64250672011-05-07 01:36:40 +0530163}
164
165void __init nlm_smp_setup(void)
166{
167 unsigned int boot_cpu;
Jayachandran C98d48842013-12-21 16:52:26 +0530168 int num_cpus, i, ncore, node;
Jayachandran C919f9ab2013-06-10 06:41:04 +0000169 volatile u32 *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY);
Jayachandran C5c64250672011-05-07 01:36:40 +0530170
171 boot_cpu = hard_smp_processor_id();
Jayachandran C62b734d2013-03-23 17:27:55 +0000172 cpumask_clear(&phys_cpu_present_mask);
Jayachandran C5c64250672011-05-07 01:36:40 +0530173
Jayachandran C62b734d2013-03-23 17:27:55 +0000174 cpumask_set_cpu(boot_cpu, &phys_cpu_present_mask);
Jayachandran C5c64250672011-05-07 01:36:40 +0530175 __cpu_number_map[boot_cpu] = 0;
176 __cpu_logical_map[0] = boot_cpu;
Rusty Russell0b5f9c02012-03-29 15:38:30 +1030177 set_cpu_possible(0, true);
Jayachandran C5c64250672011-05-07 01:36:40 +0530178
179 num_cpus = 1;
180 for (i = 0; i < NR_CPUS; i++) {
Hillf Dantonb2788962011-09-24 02:29:54 +0200181 /*
Jayachandran C919f9ab2013-06-10 06:41:04 +0000182 * cpu_ready array is not set for the boot_cpu,
Jayachandran C0c965402011-11-11 17:08:29 +0530183 * it is only set for ASPs (see smpboot.S)
Hillf Dantonb2788962011-09-24 02:29:54 +0200184 */
Jayachandran C919f9ab2013-06-10 06:41:04 +0000185 if (cpu_ready[i]) {
Jayachandran C62b734d2013-03-23 17:27:55 +0000186 cpumask_set_cpu(i, &phys_cpu_present_mask);
Jayachandran C5c64250672011-05-07 01:36:40 +0530187 __cpu_number_map[i] = num_cpus;
188 __cpu_logical_map[num_cpus] = i;
Rusty Russell0b5f9c02012-03-29 15:38:30 +1030189 set_cpu_possible(num_cpus, true);
Jayachandran Cc2736522015-01-07 16:58:30 +0530190 node = nlm_hwtid_to_node(i);
Jayachandran C98d48842013-12-21 16:52:26 +0530191 cpumask_set_cpu(num_cpus, &nlm_get_node(node)->cpumask);
Jayachandran C5c64250672011-05-07 01:36:40 +0530192 ++num_cpus;
193 }
194 }
195
Tejun Heo729d8e02015-02-13 14:37:03 -0800196 pr_info("Physical CPU mask: %*pb\n",
197 cpumask_pr_args(&phys_cpu_present_mask));
198 pr_info("Possible CPU mask: %*pb\n",
199 cpumask_pr_args(cpu_possible_mask));
Jayachandran C62b734d2013-03-23 17:27:55 +0000200
Jayachandran C2e240dd2014-05-09 16:34:54 +0530201 /* check with the cores we have woken up */
Jayachandran C77ae7982012-10-31 12:01:39 +0000202 for (ncore = 0, i = 0; i < NLM_NR_NODES; i++)
203 ncore += hweight32(nlm_get_node(i)->coremask);
204
Jayachandran C77ae7982012-10-31 12:01:39 +0000205 pr_info("Detected (%dc%dt) %d Slave CPU(s)\n", ncore,
206 nlm_threads_per_core, num_cpus);
Jayachandran C62b734d2013-03-23 17:27:55 +0000207
208 /* switch NMI handler to boot CPUs */
Jayachandran C66d29982011-11-16 00:21:29 +0000209 nlm_set_nmi_handler(nlm_boot_secondary_cpus);
Jayachandran C5c64250672011-05-07 01:36:40 +0530210}
211
Jayachandran C2a37b1a2012-10-31 12:01:37 +0000212static int nlm_parse_cpumask(cpumask_t *wakeup_mask)
Jayachandran C66d29982011-11-16 00:21:29 +0000213{
214 uint32_t core0_thr_mask, core_thr_mask;
Jayachandran C2a37b1a2012-10-31 12:01:37 +0000215 int threadmode, i, j;
Jayachandran C66d29982011-11-16 00:21:29 +0000216
Jayachandran C2a37b1a2012-10-31 12:01:37 +0000217 core0_thr_mask = 0;
Jayachandran C77ae7982012-10-31 12:01:39 +0000218 for (i = 0; i < NLM_THREADS_PER_CORE; i++)
Jayachandran C2a37b1a2012-10-31 12:01:37 +0000219 if (cpumask_test_cpu(i, wakeup_mask))
220 core0_thr_mask |= (1 << i);
Jayachandran C66d29982011-11-16 00:21:29 +0000221 switch (core0_thr_mask) {
222 case 1:
223 nlm_threads_per_core = 1;
224 threadmode = 0;
225 break;
226 case 3:
227 nlm_threads_per_core = 2;
228 threadmode = 2;
229 break;
230 case 0xf:
231 nlm_threads_per_core = 4;
232 threadmode = 3;
233 break;
234 default:
235 goto unsupp;
236 }
237
238 /* Verify other cores CPU masks */
Jayachandran C77ae7982012-10-31 12:01:39 +0000239 for (i = 0; i < NR_CPUS; i += NLM_THREADS_PER_CORE) {
Jayachandran C2a37b1a2012-10-31 12:01:37 +0000240 core_thr_mask = 0;
Jayachandran C77ae7982012-10-31 12:01:39 +0000241 for (j = 0; j < NLM_THREADS_PER_CORE; j++)
Jayachandran C2a37b1a2012-10-31 12:01:37 +0000242 if (cpumask_test_cpu(i + j, wakeup_mask))
243 core_thr_mask |= (1 << j);
244 if (core_thr_mask != 0 && core_thr_mask != core0_thr_mask)
Jayachandran C66d29982011-11-16 00:21:29 +0000245 goto unsupp;
Jayachandran C66d29982011-11-16 00:21:29 +0000246 }
247 return threadmode;
248
249unsupp:
Tejun Heo729d8e02015-02-13 14:37:03 -0800250 panic("Unsupported CPU mask %*pb", cpumask_pr_args(wakeup_mask));
Jayachandran C66d29982011-11-16 00:21:29 +0000251 return 0;
252}
253
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000254int nlm_wakeup_secondary_cpus(void)
Jayachandran C66d29982011-11-16 00:21:29 +0000255{
Jayachandran C53c83212013-06-10 06:41:03 +0000256 u32 *reset_data;
Jayachandran C66d29982011-11-16 00:21:29 +0000257 int threadmode;
258
Jayachandran C66d29982011-11-16 00:21:29 +0000259 /* verify the mask and setup core config variables */
Jayachandran C2a37b1a2012-10-31 12:01:37 +0000260 threadmode = nlm_parse_cpumask(&nlm_cpumask);
Jayachandran C66d29982011-11-16 00:21:29 +0000261
262 /* Setup CPU init parameters */
Jayachandran C53c83212013-06-10 06:41:03 +0000263 reset_data = nlm_get_boot_data(BOOT_THREAD_MODE);
264 *reset_data = threadmode;
Jayachandran C66d29982011-11-16 00:21:29 +0000265
266#ifdef CONFIG_CPU_XLP
267 xlp_wakeup_secondary_cpus();
268#else
269 xlr_wakeup_secondary_cpus();
270#endif
271 return 0;
272}
273
Jayachandran C5c64250672011-05-07 01:36:40 +0530274struct plat_smp_ops nlm_smp_ops = {
275 .send_ipi_single = nlm_send_ipi_single,
276 .send_ipi_mask = nlm_send_ipi_mask,
277 .init_secondary = nlm_init_secondary,
278 .smp_finish = nlm_smp_finish,
Jayachandran C5c64250672011-05-07 01:36:40 +0530279 .boot_secondary = nlm_boot_secondary,
280 .smp_setup = nlm_smp_setup,
281 .prepare_cpus = nlm_prepare_cpus,
282};