Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 1 | /* |
Thadeu Lima de Souza Cascardo | 6c504d4 | 2010-01-17 11:23:14 +0000 | [diff] [blame] | 2 | * Low level TLB miss handlers for Book3E |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2008-2009 |
| 5 | * Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License |
| 9 | * as published by the Free Software Foundation; either version |
| 10 | * 2 of the License, or (at your option) any later version. |
| 11 | */ |
| 12 | |
| 13 | #include <asm/processor.h> |
| 14 | #include <asm/reg.h> |
| 15 | #include <asm/page.h> |
| 16 | #include <asm/mmu.h> |
| 17 | #include <asm/ppc_asm.h> |
| 18 | #include <asm/asm-offsets.h> |
| 19 | #include <asm/cputable.h> |
| 20 | #include <asm/pgtable.h> |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 21 | #include <asm/exception-64e.h> |
| 22 | #include <asm/ppc-opcode.h> |
Mihai Caraman | fecff0f | 2012-08-06 03:27:05 +0000 | [diff] [blame] | 23 | #include <asm/kvm_asm.h> |
| 24 | #include <asm/kvm_booke_hv_asm.h> |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 25 | |
| 26 | #ifdef CONFIG_PPC_64K_PAGES |
| 27 | #define VPTE_PMD_SHIFT (PTE_INDEX_SIZE+1) |
| 28 | #else |
| 29 | #define VPTE_PMD_SHIFT (PTE_INDEX_SIZE) |
| 30 | #endif |
| 31 | #define VPTE_PUD_SHIFT (VPTE_PMD_SHIFT + PMD_INDEX_SIZE) |
| 32 | #define VPTE_PGD_SHIFT (VPTE_PUD_SHIFT + PUD_INDEX_SIZE) |
| 33 | #define VPTE_INDEX_SIZE (VPTE_PGD_SHIFT + PGD_INDEX_SIZE) |
| 34 | |
Scott Wood | f67f4ef | 2011-06-22 11:25:42 +0000 | [diff] [blame] | 35 | /********************************************************************** |
| 36 | * * |
| 37 | * TLB miss handling for Book3E with a bolted linear mapping * |
| 38 | * No virtual page table, no nested TLB misses * |
| 39 | * * |
| 40 | **********************************************************************/ |
| 41 | |
Scott Wood | a3dc620 | 2014-03-10 17:29:38 -0500 | [diff] [blame] | 42 | /* |
| 43 | * Note that, unlike non-bolted handlers, TLB_EXFRAME is not |
| 44 | * modified by the TLB miss handlers themselves, since the TLB miss |
| 45 | * handler code will not itself cause a recursive TLB miss. |
| 46 | * |
| 47 | * TLB_EXFRAME will be modified when crit/mc/debug exceptions are |
| 48 | * entered/exited. |
| 49 | */ |
Mihai Caraman | fecff0f | 2012-08-06 03:27:05 +0000 | [diff] [blame] | 50 | .macro tlb_prolog_bolted intnum addr |
Scott Wood | a3dc620 | 2014-03-10 17:29:38 -0500 | [diff] [blame] | 51 | mtspr SPRN_SPRG_GEN_SCRATCH,r12 |
| 52 | mfspr r12,SPRN_SPRG_TLB_EXFRAME |
| 53 | std r13,EX_TLB_R13(r12) |
| 54 | std r10,EX_TLB_R10(r12) |
Scott Wood | f67f4ef | 2011-06-22 11:25:42 +0000 | [diff] [blame] | 55 | mfspr r13,SPRN_SPRG_PACA |
Scott Wood | a3dc620 | 2014-03-10 17:29:38 -0500 | [diff] [blame] | 56 | |
Scott Wood | f67f4ef | 2011-06-22 11:25:42 +0000 | [diff] [blame] | 57 | mfcr r10 |
Scott Wood | a3dc620 | 2014-03-10 17:29:38 -0500 | [diff] [blame] | 58 | std r11,EX_TLB_R11(r12) |
Mihai Caraman | fecff0f | 2012-08-06 03:27:05 +0000 | [diff] [blame] | 59 | #ifdef CONFIG_KVM_BOOKE_HV |
| 60 | BEGIN_FTR_SECTION |
| 61 | mfspr r11, SPRN_SRR1 |
| 62 | END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV) |
| 63 | #endif |
| 64 | DO_KVM \intnum, SPRN_SRR1 |
Scott Wood | a3dc620 | 2014-03-10 17:29:38 -0500 | [diff] [blame] | 65 | std r16,EX_TLB_R16(r12) |
Scott Wood | f67f4ef | 2011-06-22 11:25:42 +0000 | [diff] [blame] | 66 | mfspr r16,\addr /* get faulting address */ |
Scott Wood | a3dc620 | 2014-03-10 17:29:38 -0500 | [diff] [blame] | 67 | std r14,EX_TLB_R14(r12) |
Scott Wood | f67f4ef | 2011-06-22 11:25:42 +0000 | [diff] [blame] | 68 | ld r14,PACAPGD(r13) |
Scott Wood | a3dc620 | 2014-03-10 17:29:38 -0500 | [diff] [blame] | 69 | std r15,EX_TLB_R15(r12) |
| 70 | std r10,EX_TLB_CR(r12) |
Kevin Hao | e1f580e8 | 2015-10-22 20:23:48 +0800 | [diff] [blame] | 71 | #ifdef CONFIG_PPC_FSL_BOOK3E |
Diana Craciun | dd8bf94 | 2019-04-11 21:46:23 +1000 | [diff] [blame] | 72 | START_BTB_FLUSH_SECTION |
| 73 | mfspr r11, SPRN_SRR1 |
| 74 | andi. r10,r11,MSR_PR |
| 75 | beq 1f |
| 76 | BTB_FLUSH(r10) |
| 77 | 1: |
| 78 | END_BTB_FLUSH_SECTION |
Kevin Hao | e1f580e8 | 2015-10-22 20:23:48 +0800 | [diff] [blame] | 79 | std r7,EX_TLB_R7(r12) |
| 80 | #endif |
Scott Wood | a3dc620 | 2014-03-10 17:29:38 -0500 | [diff] [blame] | 81 | TLB_MISS_PROLOG_STATS |
Scott Wood | f67f4ef | 2011-06-22 11:25:42 +0000 | [diff] [blame] | 82 | .endm |
| 83 | |
| 84 | .macro tlb_epilog_bolted |
Scott Wood | a3dc620 | 2014-03-10 17:29:38 -0500 | [diff] [blame] | 85 | ld r14,EX_TLB_CR(r12) |
Kevin Hao | e1f580e8 | 2015-10-22 20:23:48 +0800 | [diff] [blame] | 86 | #ifdef CONFIG_PPC_FSL_BOOK3E |
| 87 | ld r7,EX_TLB_R7(r12) |
| 88 | #endif |
Scott Wood | a3dc620 | 2014-03-10 17:29:38 -0500 | [diff] [blame] | 89 | ld r10,EX_TLB_R10(r12) |
| 90 | ld r11,EX_TLB_R11(r12) |
| 91 | ld r13,EX_TLB_R13(r12) |
Scott Wood | f67f4ef | 2011-06-22 11:25:42 +0000 | [diff] [blame] | 92 | mtcr r14 |
Scott Wood | a3dc620 | 2014-03-10 17:29:38 -0500 | [diff] [blame] | 93 | ld r14,EX_TLB_R14(r12) |
| 94 | ld r15,EX_TLB_R15(r12) |
| 95 | TLB_MISS_RESTORE_STATS |
| 96 | ld r16,EX_TLB_R16(r12) |
| 97 | mfspr r12,SPRN_SPRG_GEN_SCRATCH |
Scott Wood | f67f4ef | 2011-06-22 11:25:42 +0000 | [diff] [blame] | 98 | .endm |
| 99 | |
| 100 | /* Data TLB miss */ |
| 101 | START_EXCEPTION(data_tlb_miss_bolted) |
Mihai Caraman | fecff0f | 2012-08-06 03:27:05 +0000 | [diff] [blame] | 102 | tlb_prolog_bolted BOOKE_INTERRUPT_DTLB_MISS SPRN_DEAR |
Scott Wood | f67f4ef | 2011-06-22 11:25:42 +0000 | [diff] [blame] | 103 | |
| 104 | /* We need _PAGE_PRESENT and _PAGE_ACCESSED set */ |
| 105 | |
| 106 | /* We do the user/kernel test for the PID here along with the RW test |
| 107 | */ |
| 108 | /* We pre-test some combination of permissions to avoid double |
| 109 | * faults: |
| 110 | * |
| 111 | * We move the ESR:ST bit into the position of _PAGE_BAP_SW in the PTE |
| 112 | * ESR_ST is 0x00800000 |
| 113 | * _PAGE_BAP_SW is 0x00000010 |
| 114 | * So the shift is >> 19. This tests for supervisor writeability. |
| 115 | * If the page happens to be supervisor writeable and not user |
| 116 | * writeable, we will take a new fault later, but that should be |
| 117 | * a rare enough case. |
| 118 | * |
| 119 | * We also move ESR_ST in _PAGE_DIRTY position |
| 120 | * _PAGE_DIRTY is 0x00001000 so the shift is >> 11 |
| 121 | * |
| 122 | * MAS1 is preset for all we need except for TID that needs to |
| 123 | * be cleared for kernel translations |
| 124 | */ |
| 125 | |
| 126 | mfspr r11,SPRN_ESR |
| 127 | |
| 128 | srdi r15,r16,60 /* get region */ |
| 129 | rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4 |
Becky Bruce | 27609a4 | 2011-10-10 10:50:41 +0000 | [diff] [blame] | 130 | bne- dtlb_miss_fault_bolted /* Bail if fault addr is invalid */ |
Scott Wood | f67f4ef | 2011-06-22 11:25:42 +0000 | [diff] [blame] | 131 | |
| 132 | rlwinm r10,r11,32-19,27,27 |
| 133 | rlwimi r10,r11,32-16,19,19 |
Becky Bruce | 27609a4 | 2011-10-10 10:50:41 +0000 | [diff] [blame] | 134 | cmpwi r15,0 /* user vs kernel check */ |
Scott Wood | f67f4ef | 2011-06-22 11:25:42 +0000 | [diff] [blame] | 135 | ori r10,r10,_PAGE_PRESENT |
| 136 | oris r11,r10,_PAGE_ACCESSED@h |
| 137 | |
| 138 | TLB_MISS_STATS_SAVE_INFO_BOLTED |
| 139 | bne tlb_miss_kernel_bolted |
| 140 | |
| 141 | tlb_miss_common_bolted: |
| 142 | /* |
| 143 | * This is the guts of the TLB miss handler for bolted-linear. |
| 144 | * We are entered with: |
| 145 | * |
| 146 | * r16 = faulting address |
| 147 | * r15 = crap (free to use) |
| 148 | * r14 = page table base |
| 149 | * r13 = PACA |
| 150 | * r11 = PTE permission mask |
| 151 | * r10 = crap (free to use) |
| 152 | */ |
| 153 | rldicl r15,r16,64-PGDIR_SHIFT+3,64-PGD_INDEX_SIZE-3 |
| 154 | cmpldi cr0,r14,0 |
| 155 | clrrdi r15,r15,3 |
Becky Bruce | 27609a4 | 2011-10-10 10:50:41 +0000 | [diff] [blame] | 156 | beq tlb_miss_fault_bolted /* No PGDIR, bail */ |
Scott Wood | f67f4ef | 2011-06-22 11:25:42 +0000 | [diff] [blame] | 157 | |
| 158 | BEGIN_MMU_FTR_SECTION |
| 159 | /* Set the TLB reservation and search for existing entry. Then load |
| 160 | * the entry. |
| 161 | */ |
Michael Neuling | 962cffb | 2012-06-25 13:33:25 +0000 | [diff] [blame] | 162 | PPC_TLBSRX_DOT(0,R16) |
Becky Bruce | 27609a4 | 2011-10-10 10:50:41 +0000 | [diff] [blame] | 163 | ldx r14,r14,r15 /* grab pgd entry */ |
Scott Wood | 1149e8a | 2012-06-12 17:02:32 -0500 | [diff] [blame] | 164 | beq tlb_miss_done_bolted /* tlb exists already, bail */ |
Scott Wood | f67f4ef | 2011-06-22 11:25:42 +0000 | [diff] [blame] | 165 | MMU_FTR_SECTION_ELSE |
Becky Bruce | 27609a4 | 2011-10-10 10:50:41 +0000 | [diff] [blame] | 166 | ldx r14,r14,r15 /* grab pgd entry */ |
Scott Wood | f67f4ef | 2011-06-22 11:25:42 +0000 | [diff] [blame] | 167 | ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBRSRV) |
| 168 | |
| 169 | #ifndef CONFIG_PPC_64K_PAGES |
| 170 | rldicl r15,r16,64-PUD_SHIFT+3,64-PUD_INDEX_SIZE-3 |
| 171 | clrrdi r15,r15,3 |
Becky Bruce | d1b9b12 | 2011-10-10 10:50:42 +0000 | [diff] [blame] | 172 | cmpdi cr0,r14,0 |
| 173 | bge tlb_miss_fault_bolted /* Bad pgd entry or hugepage; bail */ |
Becky Bruce | 27609a4 | 2011-10-10 10:50:41 +0000 | [diff] [blame] | 174 | ldx r14,r14,r15 /* grab pud entry */ |
Scott Wood | f67f4ef | 2011-06-22 11:25:42 +0000 | [diff] [blame] | 175 | #endif /* CONFIG_PPC_64K_PAGES */ |
| 176 | |
| 177 | rldicl r15,r16,64-PMD_SHIFT+3,64-PMD_INDEX_SIZE-3 |
| 178 | clrrdi r15,r15,3 |
Becky Bruce | d1b9b12 | 2011-10-10 10:50:42 +0000 | [diff] [blame] | 179 | cmpdi cr0,r14,0 |
| 180 | bge tlb_miss_fault_bolted |
Becky Bruce | 27609a4 | 2011-10-10 10:50:41 +0000 | [diff] [blame] | 181 | ldx r14,r14,r15 /* Grab pmd entry */ |
Scott Wood | f67f4ef | 2011-06-22 11:25:42 +0000 | [diff] [blame] | 182 | |
| 183 | rldicl r15,r16,64-PAGE_SHIFT+3,64-PTE_INDEX_SIZE-3 |
| 184 | clrrdi r15,r15,3 |
Becky Bruce | d1b9b12 | 2011-10-10 10:50:42 +0000 | [diff] [blame] | 185 | cmpdi cr0,r14,0 |
| 186 | bge tlb_miss_fault_bolted |
| 187 | ldx r14,r14,r15 /* Grab PTE, normal (!huge) page */ |
Scott Wood | f67f4ef | 2011-06-22 11:25:42 +0000 | [diff] [blame] | 188 | |
| 189 | /* Check if required permissions are met */ |
| 190 | andc. r15,r11,r14 |
| 191 | rldicr r15,r14,64-(PTE_RPN_SHIFT-PAGE_SHIFT),63-PAGE_SHIFT |
| 192 | bne- tlb_miss_fault_bolted |
| 193 | |
| 194 | /* Now we build the MAS: |
| 195 | * |
| 196 | * MAS 0 : Fully setup with defaults in MAS4 and TLBnCFG |
| 197 | * MAS 1 : Almost fully setup |
| 198 | * - PID already updated by caller if necessary |
| 199 | * - TSIZE need change if !base page size, not |
| 200 | * yet implemented for now |
| 201 | * MAS 2 : Defaults not useful, need to be redone |
| 202 | * MAS 3+7 : Needs to be done |
| 203 | */ |
| 204 | clrrdi r11,r16,12 /* Clear low crap in EA */ |
| 205 | clrldi r15,r15,12 /* Clear crap at the top */ |
| 206 | rlwimi r11,r14,32-19,27,31 /* Insert WIMGE */ |
| 207 | rlwimi r15,r14,32-8,22,25 /* Move in U bits */ |
| 208 | mtspr SPRN_MAS2,r11 |
| 209 | andi. r11,r14,_PAGE_DIRTY |
| 210 | rlwimi r15,r14,32-2,26,31 /* Move in BAP bits */ |
| 211 | |
| 212 | /* Mask out SW and UW if !DIRTY (XXX optimize this !) */ |
| 213 | bne 1f |
| 214 | li r11,MAS3_SW|MAS3_UW |
| 215 | andc r15,r15,r11 |
| 216 | 1: |
| 217 | mtspr SPRN_MAS7_MAS3,r15 |
| 218 | tlbwe |
| 219 | |
Scott Wood | 1149e8a | 2012-06-12 17:02:32 -0500 | [diff] [blame] | 220 | tlb_miss_done_bolted: |
Scott Wood | f67f4ef | 2011-06-22 11:25:42 +0000 | [diff] [blame] | 221 | TLB_MISS_STATS_X(MMSTAT_TLB_MISS_NORM_OK) |
| 222 | tlb_epilog_bolted |
| 223 | rfi |
| 224 | |
| 225 | itlb_miss_kernel_bolted: |
| 226 | li r11,_PAGE_PRESENT|_PAGE_BAP_SX /* Base perm */ |
| 227 | oris r11,r11,_PAGE_ACCESSED@h |
| 228 | tlb_miss_kernel_bolted: |
| 229 | mfspr r10,SPRN_MAS1 |
| 230 | ld r14,PACA_KERNELPGD(r13) |
| 231 | cmpldi cr0,r15,8 /* Check for vmalloc region */ |
| 232 | rlwinm r10,r10,0,16,1 /* Clear TID */ |
| 233 | mtspr SPRN_MAS1,r10 |
| 234 | beq+ tlb_miss_common_bolted |
| 235 | |
| 236 | tlb_miss_fault_bolted: |
| 237 | /* We need to check if it was an instruction miss */ |
| 238 | andi. r10,r11,_PAGE_EXEC|_PAGE_BAP_SX |
| 239 | bne itlb_miss_fault_bolted |
| 240 | dtlb_miss_fault_bolted: |
| 241 | TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT) |
| 242 | tlb_epilog_bolted |
| 243 | b exc_data_storage_book3e |
| 244 | itlb_miss_fault_bolted: |
| 245 | TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT) |
| 246 | tlb_epilog_bolted |
| 247 | b exc_instruction_storage_book3e |
| 248 | |
| 249 | /* Instruction TLB miss */ |
| 250 | START_EXCEPTION(instruction_tlb_miss_bolted) |
Mihai Caraman | fecff0f | 2012-08-06 03:27:05 +0000 | [diff] [blame] | 251 | tlb_prolog_bolted BOOKE_INTERRUPT_ITLB_MISS SPRN_SRR0 |
Scott Wood | f67f4ef | 2011-06-22 11:25:42 +0000 | [diff] [blame] | 252 | |
| 253 | rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4 |
| 254 | srdi r15,r16,60 /* get region */ |
| 255 | TLB_MISS_STATS_SAVE_INFO_BOLTED |
| 256 | bne- itlb_miss_fault_bolted |
| 257 | |
| 258 | li r11,_PAGE_PRESENT|_PAGE_EXEC /* Base perm */ |
| 259 | |
| 260 | /* We do the user/kernel test for the PID here along with the RW test |
| 261 | */ |
| 262 | |
| 263 | cmpldi cr0,r15,0 /* Check for user region */ |
| 264 | oris r11,r11,_PAGE_ACCESSED@h |
| 265 | beq tlb_miss_common_bolted |
| 266 | b itlb_miss_kernel_bolted |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 267 | |
Scott Wood | 9841c79 | 2014-01-17 18:36:38 -0600 | [diff] [blame] | 268 | #ifdef CONFIG_PPC_FSL_BOOK3E |
Scott Wood | 28efc35 | 2013-10-11 19:22:38 -0500 | [diff] [blame] | 269 | /* |
| 270 | * TLB miss handling for e6500 and derivatives, using hardware tablewalk. |
| 271 | * |
| 272 | * Linear mapping is bolted: no virtual page table or nested TLB misses |
| 273 | * Indirect entries in TLB1, hardware loads resulting direct entries |
| 274 | * into TLB0 |
| 275 | * No HES or NV hint on TLB1, so we need to do software round-robin |
| 276 | * No tlbsrx. so we need a spinlock, and we have to deal |
| 277 | * with MAS-damage caused by tlbsx |
| 278 | * 4K pages only |
| 279 | */ |
| 280 | |
| 281 | START_EXCEPTION(instruction_tlb_miss_e6500) |
| 282 | tlb_prolog_bolted BOOKE_INTERRUPT_ITLB_MISS SPRN_SRR0 |
| 283 | |
| 284 | ld r11,PACA_TCD_PTR(r13) |
| 285 | srdi. r15,r16,60 /* get region */ |
| 286 | ori r16,r16,1 |
| 287 | |
| 288 | TLB_MISS_STATS_SAVE_INFO_BOLTED |
| 289 | bne tlb_miss_kernel_e6500 /* user/kernel test */ |
| 290 | |
| 291 | b tlb_miss_common_e6500 |
| 292 | |
| 293 | START_EXCEPTION(data_tlb_miss_e6500) |
| 294 | tlb_prolog_bolted BOOKE_INTERRUPT_DTLB_MISS SPRN_DEAR |
| 295 | |
| 296 | ld r11,PACA_TCD_PTR(r13) |
| 297 | srdi. r15,r16,60 /* get region */ |
| 298 | rldicr r16,r16,0,62 |
| 299 | |
| 300 | TLB_MISS_STATS_SAVE_INFO_BOLTED |
| 301 | bne tlb_miss_kernel_e6500 /* user vs kernel check */ |
| 302 | |
| 303 | /* |
| 304 | * This is the guts of the TLB miss handler for e6500 and derivatives. |
| 305 | * We are entered with: |
| 306 | * |
| 307 | * r16 = page of faulting address (low bit 0 if data, 1 if instruction) |
| 308 | * r15 = crap (free to use) |
| 309 | * r14 = page table base |
| 310 | * r13 = PACA |
| 311 | * r11 = tlb_per_core ptr |
Scott Wood | 1cb4ed9 | 2014-05-22 16:10:35 -0500 | [diff] [blame] | 312 | * r10 = crap (free to use) |
Kevin Hao | e1f580e8 | 2015-10-22 20:23:48 +0800 | [diff] [blame] | 313 | * r7 = esel_next |
Scott Wood | 28efc35 | 2013-10-11 19:22:38 -0500 | [diff] [blame] | 314 | */ |
| 315 | tlb_miss_common_e6500: |
Scott Wood | 48cd9b5 | 2014-06-11 16:09:32 -0500 | [diff] [blame] | 316 | crmove cr2*4+2,cr0*4+2 /* cr2.eq != 0 if kernel address */ |
| 317 | |
| 318 | BEGIN_FTR_SECTION /* CPU_FTR_SMT */ |
Scott Wood | 28efc35 | 2013-10-11 19:22:38 -0500 | [diff] [blame] | 319 | /* |
| 320 | * Search if we already have an indirect entry for that virtual |
| 321 | * address, and if we do, bail out. |
| 322 | * |
| 323 | * MAS6:IND should be already set based on MAS4 |
| 324 | */ |
Scott Wood | 82d86de | 2014-03-07 14:48:35 -0600 | [diff] [blame] | 325 | lhz r10,PACAPACAINDEX(r13) |
Scott Wood | 1cb4ed9 | 2014-05-22 16:10:35 -0500 | [diff] [blame] | 326 | addi r10,r10,1 |
Kevin Hao | 69399ee | 2015-08-13 19:51:36 +0800 | [diff] [blame] | 327 | crclr cr1*4+eq /* set cr1.eq = 0 for non-recursive */ |
| 328 | 1: lbarx r15,0,r11 |
| 329 | cmpdi r15,0 |
Scott Wood | 28efc35 | 2013-10-11 19:22:38 -0500 | [diff] [blame] | 330 | bne 2f |
Scott Wood | 82d86de | 2014-03-07 14:48:35 -0600 | [diff] [blame] | 331 | stbcx. r10,0,r11 |
Scott Wood | 28efc35 | 2013-10-11 19:22:38 -0500 | [diff] [blame] | 332 | bne 1b |
Scott Wood | 82d86de | 2014-03-07 14:48:35 -0600 | [diff] [blame] | 333 | 3: |
Scott Wood | 28efc35 | 2013-10-11 19:22:38 -0500 | [diff] [blame] | 334 | .subsection 1 |
Scott Wood | 82d86de | 2014-03-07 14:48:35 -0600 | [diff] [blame] | 335 | 2: cmpd cr1,r15,r10 /* recursive lock due to mcheck/crit/etc? */ |
| 336 | beq cr1,3b /* unlock will happen if cr1.eq = 0 */ |
Kevin Hao | 69399ee | 2015-08-13 19:51:36 +0800 | [diff] [blame] | 337 | 10: lbz r15,0(r11) |
Scott Wood | 28efc35 | 2013-10-11 19:22:38 -0500 | [diff] [blame] | 338 | cmpdi r15,0 |
Kevin Hao | 69399ee | 2015-08-13 19:51:36 +0800 | [diff] [blame] | 339 | bne 10b |
Scott Wood | 28efc35 | 2013-10-11 19:22:38 -0500 | [diff] [blame] | 340 | b 1b |
| 341 | .previous |
Kevin Hao | e1f580e8 | 2015-10-22 20:23:48 +0800 | [diff] [blame] | 342 | END_FTR_SECTION_IFSET(CPU_FTR_SMT) |
Scott Wood | 28efc35 | 2013-10-11 19:22:38 -0500 | [diff] [blame] | 343 | |
Kevin Hao | e1f580e8 | 2015-10-22 20:23:48 +0800 | [diff] [blame] | 344 | lbz r7,TCD_ESEL_NEXT(r11) |
| 345 | |
| 346 | BEGIN_FTR_SECTION /* CPU_FTR_SMT */ |
Scott Wood | 48cd9b5 | 2014-06-11 16:09:32 -0500 | [diff] [blame] | 347 | /* |
| 348 | * Erratum A-008139 says that we can't use tlbwe to change |
| 349 | * an indirect entry in any way (including replacing or |
| 350 | * invalidating) if the other thread could be in the process |
| 351 | * of a lookup. The workaround is to invalidate the entry |
| 352 | * with tlbilx before overwriting. |
| 353 | */ |
| 354 | |
Kevin Hao | e1f580e8 | 2015-10-22 20:23:48 +0800 | [diff] [blame] | 355 | rlwinm r10,r7,16,0xff0000 |
Scott Wood | 48cd9b5 | 2014-06-11 16:09:32 -0500 | [diff] [blame] | 356 | oris r10,r10,MAS0_TLBSEL(1)@h |
| 357 | mtspr SPRN_MAS0,r10 |
| 358 | isync |
| 359 | tlbre |
Scott Wood | bbd08c7 | 2014-05-19 23:04:55 -0500 | [diff] [blame] | 360 | mfspr r15,SPRN_MAS1 |
Scott Wood | 48cd9b5 | 2014-06-11 16:09:32 -0500 | [diff] [blame] | 361 | andis. r15,r15,MAS1_VALID@h |
| 362 | beq 5f |
| 363 | |
| 364 | BEGIN_FTR_SECTION_NESTED(532) |
| 365 | mfspr r10,SPRN_MAS8 |
| 366 | rlwinm r10,r10,0,0x80000fff /* tgs,tlpid -> sgs,slpid */ |
| 367 | mtspr SPRN_MAS5,r10 |
| 368 | END_FTR_SECTION_NESTED(CPU_FTR_EMB_HV,CPU_FTR_EMB_HV,532) |
| 369 | |
| 370 | mfspr r10,SPRN_MAS1 |
| 371 | rlwinm r15,r10,0,0x3fff0000 /* tid -> spid */ |
| 372 | rlwimi r15,r10,20,0x00000003 /* ind,ts -> sind,sas */ |
| 373 | mfspr r10,SPRN_MAS6 |
| 374 | mtspr SPRN_MAS6,r15 |
| 375 | |
| 376 | mfspr r15,SPRN_MAS2 |
| 377 | isync |
| 378 | tlbilxva 0,r15 |
| 379 | isync |
| 380 | |
| 381 | mtspr SPRN_MAS6,r10 |
| 382 | |
| 383 | 5: |
| 384 | BEGIN_FTR_SECTION_NESTED(532) |
| 385 | li r10,0 |
| 386 | mtspr SPRN_MAS8,r10 |
| 387 | mtspr SPRN_MAS5,r10 |
| 388 | END_FTR_SECTION_NESTED(CPU_FTR_EMB_HV,CPU_FTR_EMB_HV,532) |
Scott Wood | 28efc35 | 2013-10-11 19:22:38 -0500 | [diff] [blame] | 389 | |
| 390 | tlbsx 0,r16 |
| 391 | mfspr r10,SPRN_MAS1 |
Scott Wood | 48cd9b5 | 2014-06-11 16:09:32 -0500 | [diff] [blame] | 392 | andis. r15,r10,MAS1_VALID@h |
Scott Wood | 28efc35 | 2013-10-11 19:22:38 -0500 | [diff] [blame] | 393 | bne tlb_miss_done_e6500 |
Scott Wood | 48cd9b5 | 2014-06-11 16:09:32 -0500 | [diff] [blame] | 394 | FTR_SECTION_ELSE |
| 395 | mfspr r10,SPRN_MAS1 |
| 396 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_SMT) |
| 397 | |
| 398 | oris r10,r10,MAS1_VALID@h |
| 399 | beq cr2,4f |
| 400 | rlwinm r10,r10,0,16,1 /* Clear TID */ |
| 401 | 4: mtspr SPRN_MAS1,r10 |
Scott Wood | 28efc35 | 2013-10-11 19:22:38 -0500 | [diff] [blame] | 402 | |
Scott Wood | 28efc35 | 2013-10-11 19:22:38 -0500 | [diff] [blame] | 403 | /* Now, we need to walk the page tables. First check if we are in |
| 404 | * range. |
| 405 | */ |
| 406 | rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4 |
| 407 | bne- tlb_miss_fault_e6500 |
| 408 | |
| 409 | rldicl r15,r16,64-PGDIR_SHIFT+3,64-PGD_INDEX_SIZE-3 |
| 410 | cmpldi cr0,r14,0 |
| 411 | clrrdi r15,r15,3 |
| 412 | beq- tlb_miss_fault_e6500 /* No PGDIR, bail */ |
| 413 | ldx r14,r14,r15 /* grab pgd entry */ |
| 414 | |
| 415 | rldicl r15,r16,64-PUD_SHIFT+3,64-PUD_INDEX_SIZE-3 |
| 416 | clrrdi r15,r15,3 |
| 417 | cmpdi cr0,r14,0 |
Scott Wood | c89ca8a | 2015-04-02 22:14:11 -0500 | [diff] [blame] | 418 | bge tlb_miss_huge_e6500 /* Bad pgd entry or hugepage; bail */ |
Scott Wood | 28efc35 | 2013-10-11 19:22:38 -0500 | [diff] [blame] | 419 | ldx r14,r14,r15 /* grab pud entry */ |
| 420 | |
| 421 | rldicl r15,r16,64-PMD_SHIFT+3,64-PMD_INDEX_SIZE-3 |
| 422 | clrrdi r15,r15,3 |
| 423 | cmpdi cr0,r14,0 |
Scott Wood | c89ca8a | 2015-04-02 22:14:11 -0500 | [diff] [blame] | 424 | bge tlb_miss_huge_e6500 |
Scott Wood | 28efc35 | 2013-10-11 19:22:38 -0500 | [diff] [blame] | 425 | ldx r14,r14,r15 /* Grab pmd entry */ |
| 426 | |
| 427 | mfspr r10,SPRN_MAS0 |
| 428 | cmpdi cr0,r14,0 |
Scott Wood | c89ca8a | 2015-04-02 22:14:11 -0500 | [diff] [blame] | 429 | bge tlb_miss_huge_e6500 |
Scott Wood | 28efc35 | 2013-10-11 19:22:38 -0500 | [diff] [blame] | 430 | |
| 431 | /* Now we build the MAS for a 2M indirect page: |
| 432 | * |
| 433 | * MAS 0 : ESEL needs to be filled by software round-robin |
| 434 | * MAS 1 : Fully set up |
| 435 | * - PID already updated by caller if necessary |
| 436 | * - TSIZE for now is base ind page size always |
| 437 | * - TID already cleared if necessary |
| 438 | * MAS 2 : Default not 2M-aligned, need to be redone |
| 439 | * MAS 3+7 : Needs to be done |
| 440 | */ |
| 441 | |
| 442 | ori r14,r14,(BOOK3E_PAGESZ_4K << MAS3_SPSIZE_SHIFT) |
| 443 | mtspr SPRN_MAS7_MAS3,r14 |
| 444 | |
| 445 | clrrdi r15,r16,21 /* make EA 2M-aligned */ |
| 446 | mtspr SPRN_MAS2,r15 |
| 447 | |
Scott Wood | c89ca8a | 2015-04-02 22:14:11 -0500 | [diff] [blame] | 448 | tlb_miss_huge_done_e6500: |
Scott Wood | 28efc35 | 2013-10-11 19:22:38 -0500 | [diff] [blame] | 449 | lbz r16,TCD_ESEL_MAX(r11) |
| 450 | lbz r14,TCD_ESEL_FIRST(r11) |
Kevin Hao | e1f580e8 | 2015-10-22 20:23:48 +0800 | [diff] [blame] | 451 | rlwimi r10,r7,16,0x00ff0000 /* insert esel_next into MAS0 */ |
| 452 | addi r7,r7,1 /* increment esel_next */ |
Scott Wood | 28efc35 | 2013-10-11 19:22:38 -0500 | [diff] [blame] | 453 | mtspr SPRN_MAS0,r10 |
Kevin Hao | e1f580e8 | 2015-10-22 20:23:48 +0800 | [diff] [blame] | 454 | cmpw r7,r16 |
| 455 | iseleq r7,r14,r7 /* if next == last use first */ |
| 456 | stb r7,TCD_ESEL_NEXT(r11) |
Scott Wood | 28efc35 | 2013-10-11 19:22:38 -0500 | [diff] [blame] | 457 | |
| 458 | tlbwe |
| 459 | |
| 460 | tlb_miss_done_e6500: |
| 461 | .macro tlb_unlock_e6500 |
Laurentiu Tudor | 7c48005 | 2014-05-30 17:59:15 +0300 | [diff] [blame] | 462 | BEGIN_FTR_SECTION |
Scott Wood | 82d86de | 2014-03-07 14:48:35 -0600 | [diff] [blame] | 463 | beq cr1,1f /* no unlock if lock was recursively grabbed */ |
Scott Wood | 28efc35 | 2013-10-11 19:22:38 -0500 | [diff] [blame] | 464 | li r15,0 |
| 465 | isync |
Scott Wood | 82d86de | 2014-03-07 14:48:35 -0600 | [diff] [blame] | 466 | stb r15,0(r11) |
| 467 | 1: |
Laurentiu Tudor | 7c48005 | 2014-05-30 17:59:15 +0300 | [diff] [blame] | 468 | END_FTR_SECTION_IFSET(CPU_FTR_SMT) |
Scott Wood | 28efc35 | 2013-10-11 19:22:38 -0500 | [diff] [blame] | 469 | .endm |
| 470 | |
| 471 | tlb_unlock_e6500 |
| 472 | TLB_MISS_STATS_X(MMSTAT_TLB_MISS_NORM_OK) |
| 473 | tlb_epilog_bolted |
| 474 | rfi |
| 475 | |
Scott Wood | c89ca8a | 2015-04-02 22:14:11 -0500 | [diff] [blame] | 476 | tlb_miss_huge_e6500: |
| 477 | beq tlb_miss_fault_e6500 |
| 478 | li r10,1 |
| 479 | andi. r15,r14,HUGEPD_SHIFT_MASK@l /* r15 = psize */ |
| 480 | rldimi r14,r10,63,0 /* Set PD_HUGE */ |
| 481 | xor r14,r14,r15 /* Clear size bits */ |
| 482 | ldx r14,0,r14 |
| 483 | |
| 484 | /* |
| 485 | * Now we build the MAS for a huge page. |
| 486 | * |
| 487 | * MAS 0 : ESEL needs to be filled by software round-robin |
| 488 | * - can be handled by indirect code |
| 489 | * MAS 1 : Need to clear IND and set TSIZE |
| 490 | * MAS 2,3+7: Needs to be redone similar to non-tablewalk handler |
| 491 | */ |
| 492 | |
| 493 | subi r15,r15,10 /* Convert psize to tsize */ |
| 494 | mfspr r10,SPRN_MAS1 |
| 495 | rlwinm r10,r10,0,~MAS1_IND |
| 496 | rlwimi r10,r15,MAS1_TSIZE_SHIFT,MAS1_TSIZE_MASK |
| 497 | mtspr SPRN_MAS1,r10 |
| 498 | |
| 499 | li r10,-0x400 |
| 500 | sld r15,r10,r15 /* Generate mask based on size */ |
| 501 | and r10,r16,r15 |
| 502 | rldicr r15,r14,64-(PTE_RPN_SHIFT-PAGE_SHIFT),63-PAGE_SHIFT |
| 503 | rlwimi r10,r14,32-19,27,31 /* Insert WIMGE */ |
| 504 | clrldi r15,r15,PAGE_SHIFT /* Clear crap at the top */ |
| 505 | rlwimi r15,r14,32-8,22,25 /* Move in U bits */ |
| 506 | mtspr SPRN_MAS2,r10 |
| 507 | andi. r10,r14,_PAGE_DIRTY |
| 508 | rlwimi r15,r14,32-2,26,31 /* Move in BAP bits */ |
| 509 | |
| 510 | /* Mask out SW and UW if !DIRTY (XXX optimize this !) */ |
| 511 | bne 1f |
| 512 | li r10,MAS3_SW|MAS3_UW |
| 513 | andc r15,r15,r10 |
| 514 | 1: |
| 515 | mtspr SPRN_MAS7_MAS3,r15 |
| 516 | |
| 517 | mfspr r10,SPRN_MAS0 |
| 518 | b tlb_miss_huge_done_e6500 |
| 519 | |
Scott Wood | 28efc35 | 2013-10-11 19:22:38 -0500 | [diff] [blame] | 520 | tlb_miss_kernel_e6500: |
Scott Wood | 28efc35 | 2013-10-11 19:22:38 -0500 | [diff] [blame] | 521 | ld r14,PACA_KERNELPGD(r13) |
Scott Wood | 48cd9b5 | 2014-06-11 16:09:32 -0500 | [diff] [blame] | 522 | cmpldi cr1,r15,8 /* Check for vmalloc region */ |
| 523 | beq+ cr1,tlb_miss_common_e6500 |
Scott Wood | 28efc35 | 2013-10-11 19:22:38 -0500 | [diff] [blame] | 524 | |
| 525 | tlb_miss_fault_e6500: |
| 526 | tlb_unlock_e6500 |
| 527 | /* We need to check if it was an instruction miss */ |
| 528 | andi. r16,r16,1 |
| 529 | bne itlb_miss_fault_e6500 |
| 530 | dtlb_miss_fault_e6500: |
| 531 | TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT) |
| 532 | tlb_epilog_bolted |
| 533 | b exc_data_storage_book3e |
| 534 | itlb_miss_fault_e6500: |
| 535 | TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT) |
| 536 | tlb_epilog_bolted |
| 537 | b exc_instruction_storage_book3e |
Scott Wood | 9841c79 | 2014-01-17 18:36:38 -0600 | [diff] [blame] | 538 | #endif /* CONFIG_PPC_FSL_BOOK3E */ |
Scott Wood | 28efc35 | 2013-10-11 19:22:38 -0500 | [diff] [blame] | 539 | |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 540 | /********************************************************************** |
| 541 | * * |
| 542 | * TLB miss handling for Book3E with TLB reservation and HES support * |
| 543 | * * |
| 544 | **********************************************************************/ |
| 545 | |
| 546 | |
| 547 | /* Data TLB miss */ |
| 548 | START_EXCEPTION(data_tlb_miss) |
| 549 | TLB_MISS_PROLOG |
| 550 | |
| 551 | /* Now we handle the fault proper. We only save DEAR in normal |
| 552 | * fault case since that's the only interesting values here. |
| 553 | * We could probably also optimize by not saving SRR0/1 in the |
| 554 | * linear mapping case but I'll leave that for later |
| 555 | */ |
| 556 | mfspr r14,SPRN_ESR |
| 557 | mfspr r16,SPRN_DEAR /* get faulting address */ |
| 558 | srdi r15,r16,60 /* get region */ |
| 559 | cmpldi cr0,r15,0xc /* linear mapping ? */ |
| 560 | TLB_MISS_STATS_SAVE_INFO |
| 561 | beq tlb_load_linear /* yes -> go to linear map load */ |
| 562 | |
| 563 | /* The page tables are mapped virtually linear. At this point, though, |
| 564 | * we don't know whether we are trying to fault in a first level |
| 565 | * virtual address or a virtual page table address. We can get that |
| 566 | * from bit 0x1 of the region ID which we have set for a page table |
| 567 | */ |
| 568 | andi. r10,r15,0x1 |
| 569 | bne- virt_page_table_tlb_miss |
| 570 | |
| 571 | std r14,EX_TLB_ESR(r12); /* save ESR */ |
| 572 | std r16,EX_TLB_DEAR(r12); /* save DEAR */ |
| 573 | |
| 574 | /* We need _PAGE_PRESENT and _PAGE_ACCESSED set */ |
| 575 | li r11,_PAGE_PRESENT |
| 576 | oris r11,r11,_PAGE_ACCESSED@h |
| 577 | |
| 578 | /* We do the user/kernel test for the PID here along with the RW test |
| 579 | */ |
| 580 | cmpldi cr0,r15,0 /* Check for user region */ |
| 581 | |
| 582 | /* We pre-test some combination of permissions to avoid double |
| 583 | * faults: |
| 584 | * |
| 585 | * We move the ESR:ST bit into the position of _PAGE_BAP_SW in the PTE |
| 586 | * ESR_ST is 0x00800000 |
| 587 | * _PAGE_BAP_SW is 0x00000010 |
| 588 | * So the shift is >> 19. This tests for supervisor writeability. |
| 589 | * If the page happens to be supervisor writeable and not user |
| 590 | * writeable, we will take a new fault later, but that should be |
| 591 | * a rare enough case. |
| 592 | * |
| 593 | * We also move ESR_ST in _PAGE_DIRTY position |
| 594 | * _PAGE_DIRTY is 0x00001000 so the shift is >> 11 |
| 595 | * |
| 596 | * MAS1 is preset for all we need except for TID that needs to |
| 597 | * be cleared for kernel translations |
| 598 | */ |
| 599 | rlwimi r11,r14,32-19,27,27 |
| 600 | rlwimi r11,r14,32-16,19,19 |
| 601 | beq normal_tlb_miss |
| 602 | /* XXX replace the RMW cycles with immediate loads + writes */ |
| 603 | 1: mfspr r10,SPRN_MAS1 |
| 604 | cmpldi cr0,r15,8 /* Check for vmalloc region */ |
| 605 | rlwinm r10,r10,0,16,1 /* Clear TID */ |
| 606 | mtspr SPRN_MAS1,r10 |
| 607 | beq+ normal_tlb_miss |
| 608 | |
| 609 | /* We got a crappy address, just fault with whatever DEAR and ESR |
| 610 | * are here |
| 611 | */ |
| 612 | TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT) |
| 613 | TLB_MISS_EPILOG_ERROR |
| 614 | b exc_data_storage_book3e |
| 615 | |
| 616 | /* Instruction TLB miss */ |
| 617 | START_EXCEPTION(instruction_tlb_miss) |
| 618 | TLB_MISS_PROLOG |
| 619 | |
| 620 | /* If we take a recursive fault, the second level handler may need |
| 621 | * to know whether we are handling a data or instruction fault in |
| 622 | * order to get to the right store fault handler. We provide that |
| 623 | * info by writing a crazy value in ESR in our exception frame |
| 624 | */ |
| 625 | li r14,-1 /* store to exception frame is done later */ |
| 626 | |
| 627 | /* Now we handle the fault proper. We only save DEAR in the non |
| 628 | * linear mapping case since we know the linear mapping case will |
| 629 | * not re-enter. We could indeed optimize and also not save SRR0/1 |
| 630 | * in the linear mapping case but I'll leave that for later |
| 631 | * |
| 632 | * Faulting address is SRR0 which is already in r16 |
| 633 | */ |
| 634 | srdi r15,r16,60 /* get region */ |
| 635 | cmpldi cr0,r15,0xc /* linear mapping ? */ |
| 636 | TLB_MISS_STATS_SAVE_INFO |
| 637 | beq tlb_load_linear /* yes -> go to linear map load */ |
| 638 | |
| 639 | /* We do the user/kernel test for the PID here along with the RW test |
| 640 | */ |
Benjamin Herrenschmidt | ea3cc33 | 2009-08-18 19:00:34 +0000 | [diff] [blame] | 641 | li r11,_PAGE_PRESENT|_PAGE_EXEC /* Base perm */ |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 642 | oris r11,r11,_PAGE_ACCESSED@h |
| 643 | |
| 644 | cmpldi cr0,r15,0 /* Check for user region */ |
| 645 | std r14,EX_TLB_ESR(r12) /* write crazy -1 to frame */ |
| 646 | beq normal_tlb_miss |
Kumar Gala | 82ae5ea | 2010-11-17 07:20:32 +0000 | [diff] [blame] | 647 | |
| 648 | li r11,_PAGE_PRESENT|_PAGE_BAP_SX /* Base perm */ |
| 649 | oris r11,r11,_PAGE_ACCESSED@h |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 650 | /* XXX replace the RMW cycles with immediate loads + writes */ |
Kumar Gala | 82ae5ea | 2010-11-17 07:20:32 +0000 | [diff] [blame] | 651 | mfspr r10,SPRN_MAS1 |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 652 | cmpldi cr0,r15,8 /* Check for vmalloc region */ |
| 653 | rlwinm r10,r10,0,16,1 /* Clear TID */ |
| 654 | mtspr SPRN_MAS1,r10 |
| 655 | beq+ normal_tlb_miss |
| 656 | |
| 657 | /* We got a crappy address, just fault */ |
| 658 | TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT) |
| 659 | TLB_MISS_EPILOG_ERROR |
| 660 | b exc_instruction_storage_book3e |
| 661 | |
| 662 | /* |
| 663 | * This is the guts of the first-level TLB miss handler for direct |
| 664 | * misses. We are entered with: |
| 665 | * |
| 666 | * r16 = faulting address |
| 667 | * r15 = region ID |
| 668 | * r14 = crap (free to use) |
| 669 | * r13 = PACA |
| 670 | * r12 = TLB exception frame in PACA |
| 671 | * r11 = PTE permission mask |
| 672 | * r10 = crap (free to use) |
| 673 | */ |
| 674 | normal_tlb_miss: |
| 675 | /* So we first construct the page table address. We do that by |
| 676 | * shifting the bottom of the address (not the region ID) by |
| 677 | * PAGE_SHIFT-3, clearing the bottom 3 bits (get a PTE ptr) and |
| 678 | * or'ing the fourth high bit. |
| 679 | * |
| 680 | * NOTE: For 64K pages, we do things slightly differently in |
| 681 | * order to handle the weird page table format used by linux |
| 682 | */ |
| 683 | ori r10,r15,0x1 |
| 684 | #ifdef CONFIG_PPC_64K_PAGES |
| 685 | /* For the top bits, 16 bytes per PTE */ |
| 686 | rldicl r14,r16,64-(PAGE_SHIFT-4),PAGE_SHIFT-4+4 |
| 687 | /* Now create the bottom bits as 0 in position 0x8000 and |
| 688 | * the rest calculated for 8 bytes per PTE |
| 689 | */ |
| 690 | rldicl r15,r16,64-(PAGE_SHIFT-3),64-15 |
| 691 | /* Insert the bottom bits in */ |
| 692 | rlwimi r14,r15,0,16,31 |
| 693 | #else |
| 694 | rldicl r14,r16,64-(PAGE_SHIFT-3),PAGE_SHIFT-3+4 |
| 695 | #endif |
| 696 | sldi r15,r10,60 |
| 697 | clrrdi r14,r14,3 |
| 698 | or r10,r15,r14 |
| 699 | |
Kumar Gala | df5d6ec | 2009-08-24 15:52:48 +0000 | [diff] [blame] | 700 | BEGIN_MMU_FTR_SECTION |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 701 | /* Set the TLB reservation and search for existing entry. Then load |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 702 | * the entry. |
| 703 | */ |
Michael Neuling | 962cffb | 2012-06-25 13:33:25 +0000 | [diff] [blame] | 704 | PPC_TLBSRX_DOT(0,R16) |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 705 | ld r14,0(r10) |
| 706 | beq normal_tlb_miss_done |
Kumar Gala | df5d6ec | 2009-08-24 15:52:48 +0000 | [diff] [blame] | 707 | MMU_FTR_SECTION_ELSE |
| 708 | ld r14,0(r10) |
| 709 | ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBRSRV) |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 710 | |
| 711 | finish_normal_tlb_miss: |
| 712 | /* Check if required permissions are met */ |
| 713 | andc. r15,r11,r14 |
| 714 | bne- normal_tlb_miss_access_fault |
| 715 | |
| 716 | /* Now we build the MAS: |
| 717 | * |
| 718 | * MAS 0 : Fully setup with defaults in MAS4 and TLBnCFG |
| 719 | * MAS 1 : Almost fully setup |
| 720 | * - PID already updated by caller if necessary |
| 721 | * - TSIZE need change if !base page size, not |
| 722 | * yet implemented for now |
| 723 | * MAS 2 : Defaults not useful, need to be redone |
| 724 | * MAS 3+7 : Needs to be done |
| 725 | * |
| 726 | * TODO: mix up code below for better scheduling |
| 727 | */ |
| 728 | clrrdi r11,r16,12 /* Clear low crap in EA */ |
| 729 | rlwimi r11,r14,32-19,27,31 /* Insert WIMGE */ |
| 730 | mtspr SPRN_MAS2,r11 |
| 731 | |
| 732 | /* Check page size, if not standard, update MAS1 */ |
| 733 | rldicl r11,r14,64-8,64-8 |
| 734 | #ifdef CONFIG_PPC_64K_PAGES |
| 735 | cmpldi cr0,r11,BOOK3E_PAGESZ_64K |
| 736 | #else |
| 737 | cmpldi cr0,r11,BOOK3E_PAGESZ_4K |
| 738 | #endif |
| 739 | beq- 1f |
| 740 | mfspr r11,SPRN_MAS1 |
| 741 | rlwimi r11,r14,31,21,24 |
| 742 | rlwinm r11,r11,0,21,19 |
| 743 | mtspr SPRN_MAS1,r11 |
| 744 | 1: |
| 745 | /* Move RPN in position */ |
| 746 | rldicr r11,r14,64-(PTE_RPN_SHIFT-PAGE_SHIFT),63-PAGE_SHIFT |
| 747 | clrldi r15,r11,12 /* Clear crap at the top */ |
| 748 | rlwimi r15,r14,32-8,22,25 /* Move in U bits */ |
| 749 | rlwimi r15,r14,32-2,26,31 /* Move in BAP bits */ |
| 750 | |
| 751 | /* Mask out SW and UW if !DIRTY (XXX optimize this !) */ |
| 752 | andi. r11,r14,_PAGE_DIRTY |
| 753 | bne 1f |
| 754 | li r11,MAS3_SW|MAS3_UW |
| 755 | andc r15,r15,r11 |
Kumar Gala | df5d6ec | 2009-08-24 15:52:48 +0000 | [diff] [blame] | 756 | 1: |
| 757 | BEGIN_MMU_FTR_SECTION |
| 758 | srdi r16,r15,32 |
| 759 | mtspr SPRN_MAS3,r15 |
| 760 | mtspr SPRN_MAS7,r16 |
| 761 | MMU_FTR_SECTION_ELSE |
| 762 | mtspr SPRN_MAS7_MAS3,r15 |
| 763 | ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS) |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 764 | |
| 765 | tlbwe |
| 766 | |
| 767 | normal_tlb_miss_done: |
| 768 | /* We don't bother with restoring DEAR or ESR since we know we are |
| 769 | * level 0 and just going back to userland. They are only needed |
| 770 | * if you are going to take an access fault |
| 771 | */ |
| 772 | TLB_MISS_STATS_X(MMSTAT_TLB_MISS_NORM_OK) |
| 773 | TLB_MISS_EPILOG_SUCCESS |
| 774 | rfi |
| 775 | |
| 776 | normal_tlb_miss_access_fault: |
| 777 | /* We need to check if it was an instruction miss */ |
Benjamin Herrenschmidt | ea3cc33 | 2009-08-18 19:00:34 +0000 | [diff] [blame] | 778 | andi. r10,r11,_PAGE_EXEC |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 779 | bne 1f |
| 780 | ld r14,EX_TLB_DEAR(r12) |
| 781 | ld r15,EX_TLB_ESR(r12) |
| 782 | mtspr SPRN_DEAR,r14 |
| 783 | mtspr SPRN_ESR,r15 |
| 784 | TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT) |
| 785 | TLB_MISS_EPILOG_ERROR |
| 786 | b exc_data_storage_book3e |
| 787 | 1: TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT) |
| 788 | TLB_MISS_EPILOG_ERROR |
| 789 | b exc_instruction_storage_book3e |
| 790 | |
| 791 | |
| 792 | /* |
| 793 | * This is the guts of the second-level TLB miss handler for direct |
| 794 | * misses. We are entered with: |
| 795 | * |
| 796 | * r16 = virtual page table faulting address |
| 797 | * r15 = region (top 4 bits of address) |
| 798 | * r14 = crap (free to use) |
| 799 | * r13 = PACA |
| 800 | * r12 = TLB exception frame in PACA |
| 801 | * r11 = crap (free to use) |
| 802 | * r10 = crap (free to use) |
| 803 | * |
| 804 | * Note that this should only ever be called as a second level handler |
| 805 | * with the current scheme when using SW load. |
| 806 | * That means we can always get the original fault DEAR at |
| 807 | * EX_TLB_DEAR-EX_TLB_SIZE(r12) |
| 808 | * |
| 809 | * It can be re-entered by the linear mapping miss handler. However, to |
| 810 | * avoid too much complication, it will restart the whole fault at level |
| 811 | * 0 so we don't care too much about clobbers |
| 812 | * |
| 813 | * XXX That code was written back when we couldn't clobber r14. We can now, |
| 814 | * so we could probably optimize things a bit |
| 815 | */ |
| 816 | virt_page_table_tlb_miss: |
| 817 | /* Are we hitting a kernel page table ? */ |
| 818 | andi. r10,r15,0x8 |
| 819 | |
| 820 | /* The cool thing now is that r10 contains 0 for user and 8 for kernel, |
| 821 | * and we happen to have the swapper_pg_dir at offset 8 from the user |
| 822 | * pgdir in the PACA :-). |
| 823 | */ |
| 824 | add r11,r10,r13 |
| 825 | |
| 826 | /* If kernel, we need to clear MAS1 TID */ |
| 827 | beq 1f |
| 828 | /* XXX replace the RMW cycles with immediate loads + writes */ |
| 829 | mfspr r10,SPRN_MAS1 |
| 830 | rlwinm r10,r10,0,16,1 /* Clear TID */ |
| 831 | mtspr SPRN_MAS1,r10 |
| 832 | 1: |
Kumar Gala | df5d6ec | 2009-08-24 15:52:48 +0000 | [diff] [blame] | 833 | BEGIN_MMU_FTR_SECTION |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 834 | /* Search if we already have a TLB entry for that virtual address, and |
| 835 | * if we do, bail out. |
| 836 | */ |
Michael Neuling | 962cffb | 2012-06-25 13:33:25 +0000 | [diff] [blame] | 837 | PPC_TLBSRX_DOT(0,R16) |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 838 | beq virt_page_table_tlb_miss_done |
Kumar Gala | df5d6ec | 2009-08-24 15:52:48 +0000 | [diff] [blame] | 839 | END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_TLBRSRV) |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 840 | |
| 841 | /* Now, we need to walk the page tables. First check if we are in |
| 842 | * range. |
| 843 | */ |
| 844 | rldicl. r10,r16,64-(VPTE_INDEX_SIZE+3),VPTE_INDEX_SIZE+3+4 |
| 845 | bne- virt_page_table_tlb_miss_fault |
| 846 | |
| 847 | /* Get the PGD pointer */ |
| 848 | ld r15,PACAPGD(r11) |
| 849 | cmpldi cr0,r15,0 |
| 850 | beq- virt_page_table_tlb_miss_fault |
| 851 | |
| 852 | /* Get to PGD entry */ |
| 853 | rldicl r11,r16,64-VPTE_PGD_SHIFT,64-PGD_INDEX_SIZE-3 |
| 854 | clrrdi r10,r11,3 |
| 855 | ldx r15,r10,r15 |
Becky Bruce | 41151e7 | 2011-06-28 09:54:48 +0000 | [diff] [blame] | 856 | cmpdi cr0,r15,0 |
| 857 | bge virt_page_table_tlb_miss_fault |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 858 | |
| 859 | #ifndef CONFIG_PPC_64K_PAGES |
| 860 | /* Get to PUD entry */ |
| 861 | rldicl r11,r16,64-VPTE_PUD_SHIFT,64-PUD_INDEX_SIZE-3 |
| 862 | clrrdi r10,r11,3 |
| 863 | ldx r15,r10,r15 |
Becky Bruce | 41151e7 | 2011-06-28 09:54:48 +0000 | [diff] [blame] | 864 | cmpdi cr0,r15,0 |
| 865 | bge virt_page_table_tlb_miss_fault |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 866 | #endif /* CONFIG_PPC_64K_PAGES */ |
| 867 | |
| 868 | /* Get to PMD entry */ |
| 869 | rldicl r11,r16,64-VPTE_PMD_SHIFT,64-PMD_INDEX_SIZE-3 |
| 870 | clrrdi r10,r11,3 |
| 871 | ldx r15,r10,r15 |
Becky Bruce | 41151e7 | 2011-06-28 09:54:48 +0000 | [diff] [blame] | 872 | cmpdi cr0,r15,0 |
| 873 | bge virt_page_table_tlb_miss_fault |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 874 | |
| 875 | /* Ok, we're all right, we can now create a kernel translation for |
| 876 | * a 4K or 64K page from r16 -> r15. |
| 877 | */ |
| 878 | /* Now we build the MAS: |
| 879 | * |
| 880 | * MAS 0 : Fully setup with defaults in MAS4 and TLBnCFG |
| 881 | * MAS 1 : Almost fully setup |
| 882 | * - PID already updated by caller if necessary |
| 883 | * - TSIZE for now is base page size always |
| 884 | * MAS 2 : Use defaults |
| 885 | * MAS 3+7 : Needs to be done |
| 886 | * |
| 887 | * So we only do MAS 2 and 3 for now... |
| 888 | */ |
| 889 | clrldi r11,r15,4 /* remove region ID from RPN */ |
| 890 | ori r10,r11,1 /* Or-in SR */ |
Kumar Gala | df5d6ec | 2009-08-24 15:52:48 +0000 | [diff] [blame] | 891 | |
| 892 | BEGIN_MMU_FTR_SECTION |
| 893 | srdi r16,r10,32 |
| 894 | mtspr SPRN_MAS3,r10 |
| 895 | mtspr SPRN_MAS7,r16 |
| 896 | MMU_FTR_SECTION_ELSE |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 897 | mtspr SPRN_MAS7_MAS3,r10 |
Kumar Gala | df5d6ec | 2009-08-24 15:52:48 +0000 | [diff] [blame] | 898 | ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS) |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 899 | |
| 900 | tlbwe |
| 901 | |
Kumar Gala | df5d6ec | 2009-08-24 15:52:48 +0000 | [diff] [blame] | 902 | BEGIN_MMU_FTR_SECTION |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 903 | virt_page_table_tlb_miss_done: |
| 904 | |
Adam Buchbinder | 446957b | 2016-02-24 10:51:11 -0800 | [diff] [blame] | 905 | /* We have overridden MAS2:EPN but currently our primary TLB miss |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 906 | * handler will always restore it so that should not be an issue, |
| 907 | * if we ever optimize the primary handler to not write MAS2 on |
| 908 | * some cases, we'll have to restore MAS2:EPN here based on the |
| 909 | * original fault's DEAR. If we do that we have to modify the |
| 910 | * ITLB miss handler to also store SRR0 in the exception frame |
| 911 | * as DEAR. |
| 912 | * |
| 913 | * However, one nasty thing we did is we cleared the reservation |
| 914 | * (well, potentially we did). We do a trick here thus if we |
| 915 | * are not a level 0 exception (we interrupted the TLB miss) we |
| 916 | * offset the return address by -4 in order to replay the tlbsrx |
| 917 | * instruction there |
| 918 | */ |
| 919 | subf r10,r13,r12 |
| 920 | cmpldi cr0,r10,PACA_EXTLB+EX_TLB_SIZE |
| 921 | bne- 1f |
| 922 | ld r11,PACA_EXTLB+EX_TLB_SIZE+EX_TLB_SRR0(r13) |
| 923 | addi r10,r11,-4 |
| 924 | std r10,PACA_EXTLB+EX_TLB_SIZE+EX_TLB_SRR0(r13) |
| 925 | 1: |
Kumar Gala | df5d6ec | 2009-08-24 15:52:48 +0000 | [diff] [blame] | 926 | END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_TLBRSRV) |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 927 | /* Return to caller, normal case */ |
| 928 | TLB_MISS_STATS_X(MMSTAT_TLB_MISS_PT_OK); |
| 929 | TLB_MISS_EPILOG_SUCCESS |
| 930 | rfi |
| 931 | |
| 932 | virt_page_table_tlb_miss_fault: |
| 933 | /* If we fault here, things are a little bit tricky. We need to call |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 934 | * either data or instruction store fault, and we need to retrieve |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 935 | * the original fault address and ESR (for data). |
| 936 | * |
| 937 | * The thing is, we know that in normal circumstances, this is |
| 938 | * always called as a second level tlb miss for SW load or as a first |
| 939 | * level TLB miss for HW load, so we should be able to peek at the |
Sylvestre Ledru | f65e51d | 2011-04-04 15:04:46 -0700 | [diff] [blame] | 940 | * relevant information in the first exception frame in the PACA. |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 941 | * |
| 942 | * However, we do need to double check that, because we may just hit |
| 943 | * a stray kernel pointer or a userland attack trying to hit those |
| 944 | * areas. If that is the case, we do a data fault. (We can't get here |
| 945 | * from an instruction tlb miss anyway). |
| 946 | * |
| 947 | * Note also that when going to a fault, we must unwind the previous |
| 948 | * level as well. Since we are doing that, we don't need to clear or |
| 949 | * restore the TLB reservation neither. |
| 950 | */ |
| 951 | subf r10,r13,r12 |
| 952 | cmpldi cr0,r10,PACA_EXTLB+EX_TLB_SIZE |
| 953 | bne- virt_page_table_tlb_miss_whacko_fault |
| 954 | |
| 955 | /* We dig the original DEAR and ESR from slot 0 */ |
| 956 | ld r15,EX_TLB_DEAR+PACA_EXTLB(r13) |
| 957 | ld r16,EX_TLB_ESR+PACA_EXTLB(r13) |
| 958 | |
| 959 | /* We check for the "special" ESR value for instruction faults */ |
| 960 | cmpdi cr0,r16,-1 |
| 961 | beq 1f |
| 962 | mtspr SPRN_DEAR,r15 |
| 963 | mtspr SPRN_ESR,r16 |
| 964 | TLB_MISS_STATS_D(MMSTAT_TLB_MISS_PT_FAULT); |
| 965 | TLB_MISS_EPILOG_ERROR |
| 966 | b exc_data_storage_book3e |
| 967 | 1: TLB_MISS_STATS_I(MMSTAT_TLB_MISS_PT_FAULT); |
| 968 | TLB_MISS_EPILOG_ERROR |
| 969 | b exc_instruction_storage_book3e |
| 970 | |
| 971 | virt_page_table_tlb_miss_whacko_fault: |
| 972 | /* The linear fault will restart everything so ESR and DEAR will |
| 973 | * not have been clobbered, let's just fault with what we have |
| 974 | */ |
| 975 | TLB_MISS_STATS_X(MMSTAT_TLB_MISS_PT_FAULT); |
| 976 | TLB_MISS_EPILOG_ERROR |
| 977 | b exc_data_storage_book3e |
| 978 | |
| 979 | |
| 980 | /************************************************************** |
| 981 | * * |
| 982 | * TLB miss handling for Book3E with hw page table support * |
| 983 | * * |
| 984 | **************************************************************/ |
| 985 | |
| 986 | |
| 987 | /* Data TLB miss */ |
| 988 | START_EXCEPTION(data_tlb_miss_htw) |
| 989 | TLB_MISS_PROLOG |
| 990 | |
| 991 | /* Now we handle the fault proper. We only save DEAR in normal |
| 992 | * fault case since that's the only interesting values here. |
| 993 | * We could probably also optimize by not saving SRR0/1 in the |
| 994 | * linear mapping case but I'll leave that for later |
| 995 | */ |
| 996 | mfspr r14,SPRN_ESR |
| 997 | mfspr r16,SPRN_DEAR /* get faulting address */ |
| 998 | srdi r11,r16,60 /* get region */ |
| 999 | cmpldi cr0,r11,0xc /* linear mapping ? */ |
| 1000 | TLB_MISS_STATS_SAVE_INFO |
| 1001 | beq tlb_load_linear /* yes -> go to linear map load */ |
| 1002 | |
| 1003 | /* We do the user/kernel test for the PID here along with the RW test |
| 1004 | */ |
| 1005 | cmpldi cr0,r11,0 /* Check for user region */ |
| 1006 | ld r15,PACAPGD(r13) /* Load user pgdir */ |
| 1007 | beq htw_tlb_miss |
| 1008 | |
| 1009 | /* XXX replace the RMW cycles with immediate loads + writes */ |
| 1010 | 1: mfspr r10,SPRN_MAS1 |
| 1011 | cmpldi cr0,r11,8 /* Check for vmalloc region */ |
| 1012 | rlwinm r10,r10,0,16,1 /* Clear TID */ |
| 1013 | mtspr SPRN_MAS1,r10 |
| 1014 | ld r15,PACA_KERNELPGD(r13) /* Load kernel pgdir */ |
| 1015 | beq+ htw_tlb_miss |
| 1016 | |
| 1017 | /* We got a crappy address, just fault with whatever DEAR and ESR |
| 1018 | * are here |
| 1019 | */ |
| 1020 | TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT) |
| 1021 | TLB_MISS_EPILOG_ERROR |
| 1022 | b exc_data_storage_book3e |
| 1023 | |
| 1024 | /* Instruction TLB miss */ |
| 1025 | START_EXCEPTION(instruction_tlb_miss_htw) |
| 1026 | TLB_MISS_PROLOG |
| 1027 | |
| 1028 | /* If we take a recursive fault, the second level handler may need |
| 1029 | * to know whether we are handling a data or instruction fault in |
| 1030 | * order to get to the right store fault handler. We provide that |
| 1031 | * info by keeping a crazy value for ESR in r14 |
| 1032 | */ |
| 1033 | li r14,-1 /* store to exception frame is done later */ |
| 1034 | |
| 1035 | /* Now we handle the fault proper. We only save DEAR in the non |
| 1036 | * linear mapping case since we know the linear mapping case will |
| 1037 | * not re-enter. We could indeed optimize and also not save SRR0/1 |
| 1038 | * in the linear mapping case but I'll leave that for later |
| 1039 | * |
| 1040 | * Faulting address is SRR0 which is already in r16 |
| 1041 | */ |
| 1042 | srdi r11,r16,60 /* get region */ |
| 1043 | cmpldi cr0,r11,0xc /* linear mapping ? */ |
| 1044 | TLB_MISS_STATS_SAVE_INFO |
| 1045 | beq tlb_load_linear /* yes -> go to linear map load */ |
| 1046 | |
| 1047 | /* We do the user/kernel test for the PID here along with the RW test |
| 1048 | */ |
| 1049 | cmpldi cr0,r11,0 /* Check for user region */ |
| 1050 | ld r15,PACAPGD(r13) /* Load user pgdir */ |
| 1051 | beq htw_tlb_miss |
| 1052 | |
| 1053 | /* XXX replace the RMW cycles with immediate loads + writes */ |
| 1054 | 1: mfspr r10,SPRN_MAS1 |
| 1055 | cmpldi cr0,r11,8 /* Check for vmalloc region */ |
| 1056 | rlwinm r10,r10,0,16,1 /* Clear TID */ |
| 1057 | mtspr SPRN_MAS1,r10 |
| 1058 | ld r15,PACA_KERNELPGD(r13) /* Load kernel pgdir */ |
| 1059 | beq+ htw_tlb_miss |
| 1060 | |
| 1061 | /* We got a crappy address, just fault */ |
| 1062 | TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT) |
| 1063 | TLB_MISS_EPILOG_ERROR |
| 1064 | b exc_instruction_storage_book3e |
| 1065 | |
| 1066 | |
| 1067 | /* |
| 1068 | * This is the guts of the second-level TLB miss handler for direct |
| 1069 | * misses. We are entered with: |
| 1070 | * |
| 1071 | * r16 = virtual page table faulting address |
| 1072 | * r15 = PGD pointer |
| 1073 | * r14 = ESR |
| 1074 | * r13 = PACA |
| 1075 | * r12 = TLB exception frame in PACA |
| 1076 | * r11 = crap (free to use) |
| 1077 | * r10 = crap (free to use) |
| 1078 | * |
| 1079 | * It can be re-entered by the linear mapping miss handler. However, to |
| 1080 | * avoid too much complication, it will save/restore things for us |
| 1081 | */ |
| 1082 | htw_tlb_miss: |
| 1083 | /* Search if we already have a TLB entry for that virtual address, and |
| 1084 | * if we do, bail out. |
| 1085 | * |
| 1086 | * MAS1:IND should be already set based on MAS4 |
| 1087 | */ |
Michael Neuling | 962cffb | 2012-06-25 13:33:25 +0000 | [diff] [blame] | 1088 | PPC_TLBSRX_DOT(0,R16) |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 1089 | beq htw_tlb_miss_done |
| 1090 | |
| 1091 | /* Now, we need to walk the page tables. First check if we are in |
| 1092 | * range. |
| 1093 | */ |
| 1094 | rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4 |
| 1095 | bne- htw_tlb_miss_fault |
| 1096 | |
| 1097 | /* Get the PGD pointer */ |
| 1098 | cmpldi cr0,r15,0 |
| 1099 | beq- htw_tlb_miss_fault |
| 1100 | |
| 1101 | /* Get to PGD entry */ |
| 1102 | rldicl r11,r16,64-(PGDIR_SHIFT-3),64-PGD_INDEX_SIZE-3 |
| 1103 | clrrdi r10,r11,3 |
| 1104 | ldx r15,r10,r15 |
Becky Bruce | 41151e7 | 2011-06-28 09:54:48 +0000 | [diff] [blame] | 1105 | cmpdi cr0,r15,0 |
| 1106 | bge htw_tlb_miss_fault |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 1107 | |
| 1108 | #ifndef CONFIG_PPC_64K_PAGES |
| 1109 | /* Get to PUD entry */ |
| 1110 | rldicl r11,r16,64-(PUD_SHIFT-3),64-PUD_INDEX_SIZE-3 |
| 1111 | clrrdi r10,r11,3 |
| 1112 | ldx r15,r10,r15 |
Becky Bruce | 41151e7 | 2011-06-28 09:54:48 +0000 | [diff] [blame] | 1113 | cmpdi cr0,r15,0 |
| 1114 | bge htw_tlb_miss_fault |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 1115 | #endif /* CONFIG_PPC_64K_PAGES */ |
| 1116 | |
| 1117 | /* Get to PMD entry */ |
| 1118 | rldicl r11,r16,64-(PMD_SHIFT-3),64-PMD_INDEX_SIZE-3 |
| 1119 | clrrdi r10,r11,3 |
| 1120 | ldx r15,r10,r15 |
Becky Bruce | 41151e7 | 2011-06-28 09:54:48 +0000 | [diff] [blame] | 1121 | cmpdi cr0,r15,0 |
| 1122 | bge htw_tlb_miss_fault |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 1123 | |
| 1124 | /* Ok, we're all right, we can now create an indirect entry for |
| 1125 | * a 1M or 256M page. |
| 1126 | * |
| 1127 | * The last trick is now that because we use "half" pages for |
| 1128 | * the HTW (1M IND is 2K and 256M IND is 32K) we need to account |
| 1129 | * for an added LSB bit to the RPN. For 64K pages, there is no |
| 1130 | * problem as we already use 32K arrays (half PTE pages), but for |
| 1131 | * 4K page we need to extract a bit from the virtual address and |
| 1132 | * insert it into the "PA52" bit of the RPN. |
| 1133 | */ |
| 1134 | #ifndef CONFIG_PPC_64K_PAGES |
| 1135 | rlwimi r15,r16,32-9,20,20 |
| 1136 | #endif |
| 1137 | /* Now we build the MAS: |
| 1138 | * |
| 1139 | * MAS 0 : Fully setup with defaults in MAS4 and TLBnCFG |
| 1140 | * MAS 1 : Almost fully setup |
| 1141 | * - PID already updated by caller if necessary |
| 1142 | * - TSIZE for now is base ind page size always |
| 1143 | * MAS 2 : Use defaults |
| 1144 | * MAS 3+7 : Needs to be done |
| 1145 | */ |
| 1146 | #ifdef CONFIG_PPC_64K_PAGES |
| 1147 | ori r10,r15,(BOOK3E_PAGESZ_64K << MAS3_SPSIZE_SHIFT) |
| 1148 | #else |
| 1149 | ori r10,r15,(BOOK3E_PAGESZ_4K << MAS3_SPSIZE_SHIFT) |
| 1150 | #endif |
Kumar Gala | df5d6ec | 2009-08-24 15:52:48 +0000 | [diff] [blame] | 1151 | |
| 1152 | BEGIN_MMU_FTR_SECTION |
| 1153 | srdi r16,r10,32 |
| 1154 | mtspr SPRN_MAS3,r10 |
| 1155 | mtspr SPRN_MAS7,r16 |
| 1156 | MMU_FTR_SECTION_ELSE |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 1157 | mtspr SPRN_MAS7_MAS3,r10 |
Kumar Gala | df5d6ec | 2009-08-24 15:52:48 +0000 | [diff] [blame] | 1158 | ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS) |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 1159 | |
| 1160 | tlbwe |
| 1161 | |
| 1162 | htw_tlb_miss_done: |
| 1163 | /* We don't bother with restoring DEAR or ESR since we know we are |
| 1164 | * level 0 and just going back to userland. They are only needed |
| 1165 | * if you are going to take an access fault |
| 1166 | */ |
| 1167 | TLB_MISS_STATS_X(MMSTAT_TLB_MISS_PT_OK) |
| 1168 | TLB_MISS_EPILOG_SUCCESS |
| 1169 | rfi |
| 1170 | |
| 1171 | htw_tlb_miss_fault: |
| 1172 | /* We need to check if it was an instruction miss. We know this |
| 1173 | * though because r14 would contain -1 |
| 1174 | */ |
| 1175 | cmpdi cr0,r14,-1 |
| 1176 | beq 1f |
| 1177 | mtspr SPRN_DEAR,r16 |
| 1178 | mtspr SPRN_ESR,r14 |
| 1179 | TLB_MISS_STATS_D(MMSTAT_TLB_MISS_PT_FAULT) |
| 1180 | TLB_MISS_EPILOG_ERROR |
| 1181 | b exc_data_storage_book3e |
| 1182 | 1: TLB_MISS_STATS_I(MMSTAT_TLB_MISS_PT_FAULT) |
| 1183 | TLB_MISS_EPILOG_ERROR |
| 1184 | b exc_instruction_storage_book3e |
| 1185 | |
| 1186 | /* |
| 1187 | * This is the guts of "any" level TLB miss handler for kernel linear |
| 1188 | * mapping misses. We are entered with: |
| 1189 | * |
| 1190 | * |
| 1191 | * r16 = faulting address |
| 1192 | * r15 = crap (free to use) |
| 1193 | * r14 = ESR (data) or -1 (instruction) |
| 1194 | * r13 = PACA |
| 1195 | * r12 = TLB exception frame in PACA |
| 1196 | * r11 = crap (free to use) |
| 1197 | * r10 = crap (free to use) |
| 1198 | * |
| 1199 | * In addition we know that we will not re-enter, so in theory, we could |
| 1200 | * use a simpler epilog not restoring SRR0/1 etc.. but we'll do that later. |
| 1201 | * |
| 1202 | * We also need to be careful about MAS registers here & TLB reservation, |
| 1203 | * as we know we'll have clobbered them if we interrupt the main TLB miss |
| 1204 | * handlers in which case we probably want to do a full restart at level |
| 1205 | * 0 rather than saving / restoring the MAS. |
| 1206 | * |
| 1207 | * Note: If we care about performance of that core, we can easily shuffle |
| 1208 | * a few things around |
| 1209 | */ |
| 1210 | tlb_load_linear: |
| 1211 | /* For now, we assume the linear mapping is contiguous and stops at |
| 1212 | * linear_map_top. We also assume the size is a multiple of 1G, thus |
| 1213 | * we only use 1G pages for now. That might have to be changed in a |
| 1214 | * final implementation, especially when dealing with hypervisors |
| 1215 | */ |
| 1216 | ld r11,PACATOC(r13) |
| 1217 | ld r11,linear_map_top@got(r11) |
| 1218 | ld r10,0(r11) |
Benjamin Krill | 60b9622 | 2014-02-27 15:49:21 +0100 | [diff] [blame] | 1219 | tovirt(10,10) |
| 1220 | cmpld cr0,r16,r10 |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 1221 | bge tlb_load_linear_fault |
| 1222 | |
| 1223 | /* MAS1 need whole new setup. */ |
| 1224 | li r15,(BOOK3E_PAGESZ_1GB<<MAS1_TSIZE_SHIFT) |
| 1225 | oris r15,r15,MAS1_VALID@h /* MAS1 needs V and TSIZE */ |
| 1226 | mtspr SPRN_MAS1,r15 |
| 1227 | |
| 1228 | /* Already somebody there ? */ |
Michael Neuling | 962cffb | 2012-06-25 13:33:25 +0000 | [diff] [blame] | 1229 | PPC_TLBSRX_DOT(0,R16) |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 1230 | beq tlb_load_linear_done |
| 1231 | |
| 1232 | /* Now we build the remaining MAS. MAS0 and 2 should be fine |
| 1233 | * with their defaults, which leaves us with MAS 3 and 7. The |
| 1234 | * mapping is linear, so we just take the address, clear the |
| 1235 | * region bits, and or in the permission bits which are currently |
| 1236 | * hard wired |
| 1237 | */ |
| 1238 | clrrdi r10,r16,30 /* 1G page index */ |
| 1239 | clrldi r10,r10,4 /* clear region bits */ |
| 1240 | ori r10,r10,MAS3_SR|MAS3_SW|MAS3_SX |
Kumar Gala | df5d6ec | 2009-08-24 15:52:48 +0000 | [diff] [blame] | 1241 | |
| 1242 | BEGIN_MMU_FTR_SECTION |
| 1243 | srdi r16,r10,32 |
| 1244 | mtspr SPRN_MAS3,r10 |
| 1245 | mtspr SPRN_MAS7,r16 |
| 1246 | MMU_FTR_SECTION_ELSE |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 1247 | mtspr SPRN_MAS7_MAS3,r10 |
Kumar Gala | df5d6ec | 2009-08-24 15:52:48 +0000 | [diff] [blame] | 1248 | ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS) |
Benjamin Herrenschmidt | 25d21ad | 2009-07-23 23:15:47 +0000 | [diff] [blame] | 1249 | |
| 1250 | tlbwe |
| 1251 | |
| 1252 | tlb_load_linear_done: |
| 1253 | /* We use the "error" epilog for success as we do want to |
| 1254 | * restore to the initial faulting context, whatever it was. |
| 1255 | * We do that because we can't resume a fault within a TLB |
| 1256 | * miss handler, due to MAS and TLB reservation being clobbered. |
| 1257 | */ |
| 1258 | TLB_MISS_STATS_X(MMSTAT_TLB_MISS_LINEAR) |
| 1259 | TLB_MISS_EPILOG_ERROR |
| 1260 | rfi |
| 1261 | |
| 1262 | tlb_load_linear_fault: |
| 1263 | /* We keep the DEAR and ESR around, this shouldn't have happened */ |
| 1264 | cmpdi cr0,r14,-1 |
| 1265 | beq 1f |
| 1266 | TLB_MISS_EPILOG_ERROR_SPECIAL |
| 1267 | b exc_data_storage_book3e |
| 1268 | 1: TLB_MISS_EPILOG_ERROR_SPECIAL |
| 1269 | b exc_instruction_storage_book3e |
| 1270 | |
| 1271 | |
| 1272 | #ifdef CONFIG_BOOK3E_MMU_TLB_STATS |
| 1273 | .tlb_stat_inc: |
| 1274 | 1: ldarx r8,0,r9 |
| 1275 | addi r8,r8,1 |
| 1276 | stdcx. r8,0,r9 |
| 1277 | bne- 1b |
| 1278 | blr |
| 1279 | #endif |