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gerrit-public.fairphone.software / kernel / msm-4.9 / refs/tags/FP3-REL-Q-3.A.0129 / . / drivers / phy / phy-qcom-ufs-qmp-v3.h
blob: 4d008780c828e4b387596201fa4f6e49de1b6b40 [file] [log] [blame]
Subhash Jadavanicce6fbc2016-08-11 11:35:26 -0700[diff] [blame]1/*
Subhash Jadavani9c807702017-04-01 00:35:51 -0700[diff] [blame]2 * Copyright (c) 2013-2017, The Linux Foundation. All rights reserved.
Subhash Jadavanicce6fbc2016-08-11 11:35:26 -0700[diff] [blame]3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 */
14
15#ifndef UFS_QCOM_PHY_QMP_V3_H_
16#define UFS_QCOM_PHY_QMP_V3_H_
17
18#include "phy-qcom-ufs-i.h"
19
20/* QCOM UFS PHY control registers */
Subhash Jadavani9c807702017-04-01 00:35:51 -0700[diff] [blame]21#define COM_BASE 0x000
22#define COM_SIZE 0x18C
23#define PHY_BASE 0xC00
24#define PHY_SIZE 0x1DC
25#define TX_BASE(n) (0x400 + (0x400 * n))
26#define TX_SIZE 0x128
27#define RX_BASE(n) (0x600 + (0x400 * n))
28#define RX_SIZE 0x1FC
29#define COM_OFF(x) (COM_BASE + x)
30#define PHY_OFF(x) (PHY_BASE + x)
31#define TX_OFF(n, x) (TX_BASE(n) + x)
32#define RX_OFF(n, x) (RX_BASE(n) + x)
Subhash Jadavanicce6fbc2016-08-11 11:35:26 -0700[diff] [blame]33
34/* UFS PHY QSERDES COM registers */
35#define QSERDES_COM_ATB_SEL1 COM_OFF(0x00)
36#define QSERDES_COM_ATB_SEL2 COM_OFF(0x04)
37#define QSERDES_COM_FREQ_UPDATE COM_OFF(0x08)
38#define QSERDES_COM_BG_TIMER COM_OFF(0x0C)
39#define QSERDES_COM_SSC_EN_CENTER COM_OFF(0x10)
40#define QSERDES_COM_SSC_ADJ_PER1 COM_OFF(0x14)
41#define QSERDES_COM_SSC_ADJ_PER2 COM_OFF(0x18)
42#define QSERDES_COM_SSC_PER1 COM_OFF(0x1C)
43#define QSERDES_COM_SSC_PER2 COM_OFF(0x20)
44#define QSERDES_COM_SSC_STEP_SIZE1 COM_OFF(0x24)
45#define QSERDES_COM_SSC_STEP_SIZE2 COM_OFF(0x28)
46#define QSERDES_COM_POST_DIV COM_OFF(0x2C)
47#define QSERDES_COM_POST_DIV_MUX COM_OFF(0x30)
48#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN COM_OFF(0x34)
49#define QSERDES_COM_CLK_ENABLE1 COM_OFF(0x38)
50#define QSERDES_COM_SYS_CLK_CTRL COM_OFF(0x3C)
51#define QSERDES_COM_SYSCLK_BUF_ENABLE COM_OFF(0x40)
52#define QSERDES_COM_PLL_EN COM_OFF(0x44)
53#define QSERDES_COM_PLL_IVCO COM_OFF(0x48)
54#define QSERDES_COM_CMN_IETRIM COM_OFF(0x4C)
55#define QSERDES_COM_CMN_IPTRIM COM_OFF(0x50)
56#define QSERDES_COM_EP_CLOCK_DETECT_CTR COM_OFF(0x54)
57#define QSERDES_COM_SYSCLK_DET_COMP_STATUS COM_OFF(0x58)
58#define QSERDES_COM_CLK_EP_DIV COM_OFF(0x5C)
59#define QSERDES_COM_CP_CTRL_MODE0 COM_OFF(0x60)
60#define QSERDES_COM_CP_CTRL_MODE1 COM_OFF(0x64)
61#define QSERDES_COM_PLL_RCTRL_MODE0 COM_OFF(0x68)
62#define QSERDES_COM_PLL_RCTRL_MODE1 COM_OFF(0x6C)
63#define QSERDES_COM_PLL_CCTRL_MODE0 COM_OFF(0x70)
64#define QSERDES_COM_PLL_CCTRL_MODE1 COM_OFF(0x74)
65#define QSERDES_COM_PLL_CNTRL COM_OFF(0x78)
66#define SERDES_COM_BIAS_EN_CTRL_BY_PSM COM_OFF(0x7C)
67#define QSERDES_COM_SYSCLK_EN_SEL COM_OFF(0x80)
68#define QSERDES_COM_CML_SYSCLK_SEL COM_OFF(0x84)
69#define QSERDES_COM_RESETSM_CNTRL COM_OFF(0x88)
70#define QSERDES_COM_RESETSM_CNTRL2 COM_OFF(0x8C)
71#define QSERDES_COM_LOCK_CMP_EN COM_OFF(0x90)
72#define QSERDES_COM_LOCK_CMP_CFG COM_OFF(0x94)
73#define QSERDES_COM_LOCK_CMP1_MODE0 COM_OFF(0x98)
74#define QSERDES_COM_LOCK_CMP2_MODE0 COM_OFF(0x9C)
75#define QSERDES_COM_LOCK_CMP3_MODE0 COM_OFF(0xA0)
76#define QSERDES_COM_LOCK_CMP1_MODE1 COM_OFF(0xA4)
77#define QSERDES_COM_LOCK_CMP2_MODE1 COM_OFF(0xA8)
78#define QSERDES_COM_LOCK_CMP3_MODE1 COM_OFF(0xAC)
79#define QSERDES_COM_DEC_START_MODE0 COM_OFF(0xB0)
80#define QSERDES_COM_DEC_START_MODE1 COM_OFF(0xB4)
81#define QSERDES_COM_DIV_FRAC_START1_MODE0 COM_OFF(0xB8)
82#define QSERDES_COM_DIV_FRAC_START2_MODE0 COM_OFF(0xBC)
83#define QSERDES_COM_DIV_FRAC_START3_MODE0 COM_OFF(0xC0)
84#define QSERDES_COM_DIV_FRAC_START1_MODE1 COM_OFF(0xC4)
85#define QSERDES_COM_DIV_FRAC_START2_MODE1 COM_OFF(0xC8)
86#define QSERDES_COM_DIV_FRAC_START3_MODE1 COM_OFF(0xCC)
87#define QSERDES_COM_INTEGLOOP_INITVAL COM_OFF(0xD0)
88#define QSERDES_COM_INTEGLOOP_EN COM_OFF(0xD4)
89#define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 COM_OFF(0xD8)
90#define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 COM_OFF(0xDC)
91#define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 COM_OFF(0xE0)
92#define QSERDES_COM_INTEGLOOP_GAIN1_MODE1 COM_OFF(0xE4)
93#define QSERDES_COM_VCOCAL_DEADMAN_CTRL COM_OFF(0xE8)
94#define QSERDES_COM_VCO_TUNE_CTRL COM_OFF(0xEC)
95#define QSERDES_COM_VCO_TUNE_MAP COM_OFF(0xF0)
96#define QSERDES_COM_VCO_TUNE1_MODE0 COM_OFF(0xF4)
97#define QSERDES_COM_VCO_TUNE2_MODE0 COM_OFF(0xF8)
98#define QSERDES_COM_VCO_TUNE1_MODE1 COM_OFF(0xFC)
99#define QSERDES_COM_VCO_TUNE2_MODE1 COM_OFF(0x100)
100#define QSERDES_COM_VCO_TUNE_INITVAL1 COM_OFF(0x104)
101#define QSERDES_COM_VCO_TUNE_INITVAL2 COM_OFF(0x108)
102#define QSERDES_COM_VCO_TUNE_MINVAL1 COM_OFF(0x10C)
103#define QSERDES_COM_VCO_TUNE_MINVAL2 COM_OFF(0x110)
104#define QSERDES_COM_VCO_TUNE_MAXVAL1 COM_OFF(0x114)
105#define QSERDES_COM_VCO_TUNE_MAXVAL2 COM_OFF(0x118)
106#define QSERDES_COM_VCO_TUNE_TIMER1 COM_OFF(0x11C)
107#define QSERDES_COM_VCO_TUNE_TIMER2 COM_OFF(0x120)
108#define QSERDES_COM_CMN_STATUS COM_OFF(0x124)
109#define QSERDES_COM_RESET_SM_STATUS COM_OFF(0x128)
110#define QSERDES_COM_RESTRIM_CODE_STATUS COM_OFF(0x12C)
111#define QSERDES_COM_PLLCAL_CODE1_STATUS COM_OFF(0x130)
112#define QSERDES_COM_PLLCAL_CODE2_STATUS COM_OFF(0x134)
113#define QSERDES_COM_CLK_SELECT COM_OFF(0x138)
114#define QSERDES_COM_HSCLK_SEL COM_OFF(0x13C)
115#define QSERDES_COM_INTEGLOOP_BINCODE_STATUS COM_OFF(0x140)
116#define QSERDES_COM_PLL_ANALOG COM_OFF(0x144)
117#define QSERDES_COM_CORECLK_DIV_MODE0 COM_OFF(0x148)
118#define QSERDES_COM_CORECLK_DIV_MODE1 COM_OFF(0x14C)
119#define QSERDES_COM_SW_RESET COM_OFF(0x150)
120#define QSERDES_COM_CORE_CLK_EN COM_OFF(0x154)
121#define QSERDES_COM_C_READY_STATUS COM_OFF(0x158)
122#define QSERDES_COM_CMN_CONFIG COM_OFF(0x15C)
123#define QSERDES_COM_CMN_RATE_OVERRIDE COM_OFF(0x160)
124#define QSERDES_COM_SVS_MODE_CLK_SEL COM_OFF(0x164)
125#define QSERDES_COM_DEBUG_BUS0 COM_OFF(0x168)
126#define QSERDES_COM_DEBUG_BUS1 COM_OFF(0x16C)
127#define QSERDES_COM_DEBUG_BUS2 COM_OFF(0x170)
128#define QSERDES_COM_DEBUG_BUS3 COM_OFF(0x174)
129#define QSERDES_COM_DEBUG_BUS_SEL COM_OFF(0x178)
130#define QSERDES_COM_CMN_MISC1 COM_OFF(0x17C)
131#define QSERDES_COM_CMN_MISC2 COM_OFF(0x180)
132#define QSERDES_COM_CMN_MODE COM_OFF(0x184)
133#define QSERDES_COM_CMN_VREG_SEL COM_OFF(0x188)
134
135/* UFS PHY registers */
136#define UFS_PHY_PHY_START PHY_OFF(0x00)
137#define UFS_PHY_POWER_DOWN_CONTROL PHY_OFF(0x04)
138#define UFS_PHY_TIMER_20US_CORECLK_STEPS_MSB PHY_OFF(0x08)
139#define UFS_PHY_TIMER_20US_CORECLK_STEPS_LSB PHY_OFF(0x0C)
140#define UFS_PHY_TX_LARGE_AMP_DRV_LVL PHY_OFF(0x2C)
141#define UFS_PHY_TX_SMALL_AMP_DRV_LVL PHY_OFF(0x34)
142#define UFS_PHY_LINECFG_DISABLE PHY_OFF(0x130)
143#define UFS_PHY_RX_SYM_RESYNC_CTRL PHY_OFF(0x134)
Subhash Jadavani9c807702017-04-01 00:35:51 -0700[diff] [blame]144#define UFS_PHY_RX_MIN_HIBERN8_TIME PHY_OFF(0x138)
145#define UFS_PHY_RX_SIGDET_CTRL1 PHY_OFF(0x13C)
Subhash Jadavanicce6fbc2016-08-11 11:35:26 -0700[diff] [blame]146#define UFS_PHY_RX_SIGDET_CTRL2 PHY_OFF(0x140)
147#define UFS_PHY_RX_PWM_GEAR_BAND PHY_OFF(0x14C)
148#define UFS_PHY_PCS_READY_STATUS PHY_OFF(0x160)
Subhash Jadavani9c807702017-04-01 00:35:51 -0700[diff] [blame]149#define UFS_PHY_TX_MID_TERM_CTRL1 PHY_OFF(0x1BC)
150#define UFS_PHY_MULTI_LANE_CTRL1 PHY_OFF(0x1C4)
Subhash Jadavanicce6fbc2016-08-11 11:35:26 -0700[diff] [blame]151
152/* UFS PHY TX registers */
Subhash Jadavani19b47dd2017-07-25 11:48:37 -0700[diff] [blame]153#define QSERDES_TX0_RES_CODE_LANE_OFFSET_TX TX_OFF(0, 0x44)
154#define QSERDES_TX0_RES_CODE_LANE_OFFSET_RX TX_OFF(0, 0x48)
Subhash Jadavanicce6fbc2016-08-11 11:35:26 -0700[diff] [blame]155#define QSERDES_TX0_TRANSCEIVER_BIAS_EN TX_OFF(0, 0x5C)
156#define QSERDES_TX0_LANE_MODE_1 TX_OFF(0, 0x8C)
157#define QSERDES_TX0_LANE_MODE_2 TX_OFF(0, 0x90)
158#define QSERDES_TX0_LANE_MODE_3 TX_OFF(0, 0x94)
159
Subhash Jadavani19b47dd2017-07-25 11:48:37 -0700[diff] [blame]160#define QSERDES_TX1_RES_CODE_LANE_OFFSET_TX TX_OFF(1, 0x44)
161#define QSERDES_TX1_RES_CODE_LANE_OFFSET_RX TX_OFF(1, 0x48)
Subhash Jadavani9c807702017-04-01 00:35:51 -0700[diff] [blame]162#define QSERDES_TX1_LANE_MODE_1 TX_OFF(1, 0x8C)
163
164
Subhash Jadavanicce6fbc2016-08-11 11:35:26 -0700[diff] [blame]165/* UFS PHY RX registers */
166#define QSERDES_RX0_UCDR_SVS_SO_GAIN_HALF RX_OFF(0, 0x24)
167#define QSERDES_RX0_UCDR_SVS_SO_GAIN_QUARTER RX_OFF(0, 0x28)
168#define QSERDES_RX0_UCDR_SVS_SO_GAIN RX_OFF(0, 0x2C)
169#define QSERDES_RX0_UCDR_FASTLOCK_FO_GAIN RX_OFF(0, 0x30)
170#define QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE RX_OFF(0, 0x34)
171#define QSERDES_RX0_UCDR_FASTLOCK_COUNT_LOW RX_OFF(0, 0x3C)
172#define QSERDES_RX0_UCDR_PI_CONTROLS RX_OFF(0, 0x44)
173#define QSERDES_RX0_RX_TERM_BW RX_OFF(0, 0x7C)
174#define QSERDES_RX0_RX_EQ_GAIN2_LSB RX_OFF(0, 0xC8)
175#define QSERDES_RX0_RX_EQ_GAIN2_MSB RX_OFF(0, 0xCC)
176#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL1 RX_OFF(0, 0xD0)
177#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2 RX_OFF(0, 0xD4)
178#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3 RX_OFF(0, 0xD8)
179#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4 RX_OFF(0, 0xDC)
180#define QSERDES_RX0_SIGDET_CNTRL RX_OFF(0, 0x104)
181#define QSERDES_RX0_SIGDET_LVL RX_OFF(0, 0x108)
182#define QSERDES_RX0_SIGDET_DEGLITCH_CNTRL RX_OFF(0, 0x10C)
183#define QSERDES_RX0_RX_INTERFACE_MODE RX_OFF(0, 0x11C)
Subhash Jadavani19b47dd2017-07-25 11:48:37 -0700[diff] [blame]184#define QSERDES_RX0_RX_MODE_00 RX_OFF(0, 0x164)
Subhash Jadavanicce6fbc2016-08-11 11:35:26 -0700[diff] [blame]185
Subhash Jadavani9c807702017-04-01 00:35:51 -0700[diff] [blame]186#define QSERDES_RX1_UCDR_SVS_SO_GAIN_HALF RX_OFF(1, 0x24)
187#define QSERDES_RX1_UCDR_SVS_SO_GAIN_QUARTER RX_OFF(1, 0x28)
188#define QSERDES_RX1_UCDR_SVS_SO_GAIN RX_OFF(1, 0x2C)
189#define QSERDES_RX1_UCDR_FASTLOCK_FO_GAIN RX_OFF(1, 0x30)
190#define QSERDES_RX1_UCDR_SO_SATURATION_AND_ENABLE RX_OFF(1, 0x34)
191#define QSERDES_RX1_UCDR_FASTLOCK_COUNT_LOW RX_OFF(1, 0x3C)
192#define QSERDES_RX1_UCDR_PI_CONTROLS RX_OFF(1, 0x44)
193#define QSERDES_RX1_RX_TERM_BW RX_OFF(1, 0x7C)
194#define QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL2 RX_OFF(1, 0xD4)
195#define QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL3 RX_OFF(1, 0xD8)
196#define QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL4 RX_OFF(1, 0xDC)
197#define QSERDES_RX1_SIGDET_CNTRL RX_OFF(1, 0x104)
198#define QSERDES_RX1_SIGDET_LVL RX_OFF(1, 0x108)
199#define QSERDES_RX1_SIGDET_DEGLITCH_CNTRL RX_OFF(1, 0x10C)
200#define QSERDES_RX1_RX_INTERFACE_MODE RX_OFF(1, 0x11C)
Subhash Jadavani19b47dd2017-07-25 11:48:37 -0700[diff] [blame]201#define QSERDES_RX1_RX_MODE_00 RX_OFF(1, 0x164)
Subhash Jadavani9c807702017-04-01 00:35:51 -0700[diff] [blame]202
Subhash Jadavanicce6fbc2016-08-11 11:35:26 -0700[diff] [blame]203#define UFS_PHY_RX_LINECFG_DISABLE_BIT BIT(1)
204
205/*
206 * This structure represents the v3 specific phy.
207 * common_cfg MUST remain the first field in this structure
208 * in case extra fields are added. This way, when calling
209 * get_ufs_qcom_phy() of generic phy, we can extract the
210 * common phy structure (struct ufs_qcom_phy) out of it
211 * regardless of the relevant specific phy.
212 */
213struct ufs_qcom_phy_qmp_v3 {
214 struct ufs_qcom_phy common_cfg;
215};
216
Subhash Jadavanie5bb92b2017-04-03 16:19:51 -0700[diff] [blame]217static struct ufs_qcom_phy_calibration phy_cal_table_rate_A[] = {
Subhash Jadavani9c807702017-04-01 00:35:51 -0700[diff] [blame]218 UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01),
219 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CMN_CONFIG, 0x06),
220 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL, 0xD5),
221 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL, 0x20),
222 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CLK_SELECT, 0x30),
223 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYS_CLK_CTRL, 0x02),
224 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
225 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BG_TIMER, 0x0A),
226 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_HSCLK_SEL, 0x00),
227 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP_EN, 0x01),
228 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
229 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORE_CLK_EN, 0x00),
230 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x04),
231 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
Subhash Jadavani19b47dd2017-07-25 11:48:37 -0700[diff] [blame]232 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IVCO, 0x07),
Subhash Jadavani9c807702017-04-01 00:35:51 -0700[diff] [blame]233 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_INITVAL1, 0xFF),
234 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
235 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE0, 0x82),
236 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE0, 0x06),
237 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
238 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE0, 0x36),
239 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x3F),
240 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
241 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE1_MODE0, 0xDA),
242 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE2_MODE0, 0x01),
243 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE0, 0xFF),
244 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE0, 0x0C),
245 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE1, 0x98),
246 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE1, 0x06),
247 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
248 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE1, 0x36),
249 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x3F),
250 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
251 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE1_MODE1, 0xC1),
252 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
253 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
254 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE1, 0x0F),
255 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_LANE_MODE_1, 0x06),
256 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_SIGDET_LVL, 0x24),
257 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_SIGDET_CNTRL, 0x0F),
258 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x1E),
259 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_INTERFACE_MODE, 0x40),
260 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FASTLOCK_FO_GAIN, 0x0B),
261 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_TERM_BW, 0x5B),
262 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x06),
263 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
Subhash Jadavani19b47dd2017-07-25 11:48:37 -0700[diff] [blame]264 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1B),
Subhash Jadavani9c807702017-04-01 00:35:51 -0700[diff] [blame]265 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SVS_SO_GAIN_HALF, 0x04),
266 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
267 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SVS_SO_GAIN, 0x04),
268 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x4B),
Subhash Jadavani86c539b2017-06-13 15:29:42 -0700[diff] [blame]269 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_PI_CONTROLS, 0x81),
Subhash Jadavani9c807702017-04-01 00:35:51 -0700[diff] [blame]270 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FASTLOCK_COUNT_LOW, 0x80),
Subhash Jadavani19b47dd2017-07-25 11:48:37 -0700[diff] [blame]271 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x04),
272 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX0_RES_CODE_LANE_OFFSET_RX, 0x07),
273 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_00, 0x59),
Asutosh Dasc8e43072017-06-01 14:50:41 +0530[diff] [blame]274 UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL2, 0x6E),
Subhash Jadavani8bfeb632017-04-03 17:14:30 -0700[diff] [blame]275 UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x0A),
276 UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_DRV_LVL, 0x02),
277 UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SYM_RESYNC_CTRL, 0x03),
278 UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_MID_TERM_CTRL1, 0x43),
279 UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL1, 0x0F),
280 UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_MIN_HIBERN8_TIME, 0x9A), /* 8 us */
281};
282
283static struct ufs_qcom_phy_calibration phy_cal_table_2nd_lane[] = {
Subhash Jadavani9c807702017-04-01 00:35:51 -0700[diff] [blame]284 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_LANE_MODE_1, 0x06),
285 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_SIGDET_LVL, 0x24),
286 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_SIGDET_CNTRL, 0x0F),
287 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_SIGDET_DEGLITCH_CNTRL, 0x1E),
288 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_INTERFACE_MODE, 0x40),
289 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FASTLOCK_FO_GAIN, 0x0B),
290 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_TERM_BW, 0x5B),
291 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL2, 0x06),
292 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL3, 0x04),
Subhash Jadavani19b47dd2017-07-25 11:48:37 -0700[diff] [blame]293 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL4, 0x1B),
Subhash Jadavani9c807702017-04-01 00:35:51 -0700[diff] [blame]294 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SVS_SO_GAIN_HALF, 0x04),
295 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
296 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SVS_SO_GAIN, 0x04),
297 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SO_SATURATION_AND_ENABLE, 0x4B),
Subhash Jadavani86c539b2017-06-13 15:29:42 -0700[diff] [blame]298 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_PI_CONTROLS, 0x81),
Subhash Jadavani9c807702017-04-01 00:35:51 -0700[diff] [blame]299 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FASTLOCK_COUNT_LOW, 0x80),
300 UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_MULTI_LANE_CTRL1, 0x02),
Subhash Jadavani19b47dd2017-07-25 11:48:37 -0700[diff] [blame]301 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_RES_CODE_LANE_OFFSET_TX, 0x04),
302 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX1_RES_CODE_LANE_OFFSET_RX, 0x07),
303 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_00, 0x59),
Subhash Jadavanicce6fbc2016-08-11 11:35:26 -0700[diff] [blame]304};
305
306static struct ufs_qcom_phy_calibration phy_cal_table_rate_B[] = {
307 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x44),
308};
309
Subhash Jadavanicce6fbc2016-08-11 11:35:26 -0700[diff] [blame]310#endif