Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2013, Sony Mobile Communications AB. |
Archana Sathyakumar | 892c01c | 2017-10-31 13:47:20 -0600 | [diff] [blame] | 3 | * Copyright (c) 2013-2018, The Linux Foundation. All rights reserved. |
Naresh Kumar Lingagalla | ff508b4 | 2023-05-23 12:23:33 +0530 | [diff] [blame] | 4 | * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 and |
| 8 | * only version 2 as published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
Pramod Gurav | 3274558 | 2014-08-29 20:00:59 +0530 | [diff] [blame] | 16 | #include <linux/delay.h> |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 17 | #include <linux/err.h> |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 18 | #include <linux/io.h> |
Archana Sathyakumar | 8ff3ba6 | 2017-10-06 11:58:46 -0600 | [diff] [blame] | 19 | #include <linux/irq.h> |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 20 | #include <linux/module.h> |
| 21 | #include <linux/of.h> |
Mahesh Sivasubramanian | fcc313e | 2017-04-10 09:05:59 -0600 | [diff] [blame] | 22 | #include <linux/of_irq.h> |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 23 | #include <linux/platform_device.h> |
| 24 | #include <linux/pinctrl/machine.h> |
| 25 | #include <linux/pinctrl/pinctrl.h> |
| 26 | #include <linux/pinctrl/pinmux.h> |
| 27 | #include <linux/pinctrl/pinconf.h> |
| 28 | #include <linux/pinctrl/pinconf-generic.h> |
Raju P.L.S.S.S.N | cdcd769 | 2017-11-30 19:06:30 +0530 | [diff] [blame] | 29 | #include <linux/of_irq.h> |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 30 | #include <linux/slab.h> |
| 31 | #include <linux/gpio.h> |
| 32 | #include <linux/interrupt.h> |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 33 | #include <linux/spinlock.h> |
Maria Yu | 2af63b2 | 2018-03-29 17:34:28 +0800 | [diff] [blame] | 34 | #include <linux/syscore_ops.h> |
Josh Cartwright | cf1fc18 | 2014-09-23 15:59:53 -0500 | [diff] [blame] | 35 | #include <linux/reboot.h> |
Stephen Boyd | ad64498 | 2015-07-06 18:09:30 -0700 | [diff] [blame] | 36 | #include <linux/pm.h> |
Stephen Boyd | 47a01ee | 2016-06-25 22:21:31 -0700 | [diff] [blame] | 37 | #include <linux/log2.h> |
Mahesh Sivasubramanian | fcc313e | 2017-04-10 09:05:59 -0600 | [diff] [blame] | 38 | #include <linux/irq.h> |
Srinivas Rao L | d630298 | 2018-07-31 12:36:56 +0530 | [diff] [blame] | 39 | #include <soc/qcom/scm.h> |
Linus Walleij | 69b78b8 | 2014-07-09 13:55:12 +0200 | [diff] [blame] | 40 | #include "../core.h" |
| 41 | #include "../pinconf.h" |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 42 | #include "pinctrl-msm.h" |
Linus Walleij | 69b78b8 | 2014-07-09 13:55:12 +0200 | [diff] [blame] | 43 | #include "../pinctrl-utils.h" |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 44 | |
Bjorn Andersson | 408e3c6 | 2013-12-14 23:01:53 -0800 | [diff] [blame] | 45 | #define MAX_NR_GPIO 300 |
Pramod Gurav | 3274558 | 2014-08-29 20:00:59 +0530 | [diff] [blame] | 46 | #define PS_HOLD_OFFSET 0x820 |
Bjorn Andersson | 408e3c6 | 2013-12-14 23:01:53 -0800 | [diff] [blame] | 47 | |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 48 | /** |
| 49 | * struct msm_pinctrl - state for a pinctrl-msm device |
| 50 | * @dev: device handle. |
| 51 | * @pctrl: pinctrl handle. |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 52 | * @chip: gpiochip handle. |
Josh Cartwright | cf1fc18 | 2014-09-23 15:59:53 -0500 | [diff] [blame] | 53 | * @restart_nb: restart notifier block. |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 54 | * @irq: parent irq for the TLMM irq_chip. |
| 55 | * @lock: Spinlock to protect register resources as well |
| 56 | * as msm_pinctrl data structures. |
| 57 | * @enabled_irqs: Bitmap of currently enabled irqs. |
| 58 | * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge |
| 59 | * detection. |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 60 | * @soc; Reference to soc_data of platform specific data. |
| 61 | * @regs: Base address for the TLMM register map. |
| 62 | */ |
| 63 | struct msm_pinctrl { |
| 64 | struct device *dev; |
| 65 | struct pinctrl_dev *pctrl; |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 66 | struct gpio_chip chip; |
Josh Cartwright | cf1fc18 | 2014-09-23 15:59:53 -0500 | [diff] [blame] | 67 | struct notifier_block restart_nb; |
Bjorn Andersson | f393e48 | 2013-12-14 23:01:52 -0800 | [diff] [blame] | 68 | int irq; |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 69 | |
| 70 | spinlock_t lock; |
| 71 | |
Bjorn Andersson | 408e3c6 | 2013-12-14 23:01:53 -0800 | [diff] [blame] | 72 | DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO); |
| 73 | DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 74 | |
| 75 | const struct msm_pinctrl_soc_data *soc; |
| 76 | void __iomem *regs; |
Archana Sathyakumar | 892c01c | 2017-10-31 13:47:20 -0600 | [diff] [blame] | 77 | void __iomem *pdc_regs; |
Naresh Kumar Lingagalla | ff508b4 | 2023-05-23 12:23:33 +0530 | [diff] [blame] | 78 | void __iomem *spi_base; |
Srinivas Rao L | d630298 | 2018-07-31 12:36:56 +0530 | [diff] [blame] | 79 | phys_addr_t spi_cfg_regs; |
| 80 | phys_addr_t spi_cfg_end; |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 81 | }; |
| 82 | |
Maria Yu | 2af63b2 | 2018-03-29 17:34:28 +0800 | [diff] [blame] | 83 | static struct msm_pinctrl *msm_pinctrl_data; |
| 84 | |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 85 | static int msm_get_groups_count(struct pinctrl_dev *pctldev) |
| 86 | { |
| 87 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); |
| 88 | |
| 89 | return pctrl->soc->ngroups; |
| 90 | } |
| 91 | |
| 92 | static const char *msm_get_group_name(struct pinctrl_dev *pctldev, |
| 93 | unsigned group) |
| 94 | { |
| 95 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); |
| 96 | |
| 97 | return pctrl->soc->groups[group].name; |
| 98 | } |
| 99 | |
| 100 | static int msm_get_group_pins(struct pinctrl_dev *pctldev, |
| 101 | unsigned group, |
| 102 | const unsigned **pins, |
| 103 | unsigned *num_pins) |
| 104 | { |
| 105 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); |
| 106 | |
| 107 | *pins = pctrl->soc->groups[group].pins; |
| 108 | *num_pins = pctrl->soc->groups[group].npins; |
| 109 | return 0; |
| 110 | } |
| 111 | |
Bjorn Andersson | 1f2b239 | 2013-12-14 23:01:51 -0800 | [diff] [blame] | 112 | static const struct pinctrl_ops msm_pinctrl_ops = { |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 113 | .get_groups_count = msm_get_groups_count, |
| 114 | .get_group_name = msm_get_group_name, |
| 115 | .get_group_pins = msm_get_group_pins, |
| 116 | .dt_node_to_map = pinconf_generic_dt_node_to_map_group, |
Irina Tirdea | d32f7fd | 2016-03-31 14:44:42 +0300 | [diff] [blame] | 117 | .dt_free_map = pinctrl_utils_free_map, |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 118 | }; |
| 119 | |
| 120 | static int msm_get_functions_count(struct pinctrl_dev *pctldev) |
| 121 | { |
| 122 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); |
| 123 | |
| 124 | return pctrl->soc->nfunctions; |
| 125 | } |
| 126 | |
| 127 | static const char *msm_get_function_name(struct pinctrl_dev *pctldev, |
| 128 | unsigned function) |
| 129 | { |
| 130 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); |
| 131 | |
| 132 | return pctrl->soc->functions[function].name; |
| 133 | } |
| 134 | |
| 135 | static int msm_get_function_groups(struct pinctrl_dev *pctldev, |
| 136 | unsigned function, |
| 137 | const char * const **groups, |
| 138 | unsigned * const num_groups) |
| 139 | { |
| 140 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); |
| 141 | |
| 142 | *groups = pctrl->soc->functions[function].groups; |
| 143 | *num_groups = pctrl->soc->functions[function].ngroups; |
| 144 | return 0; |
| 145 | } |
| 146 | |
Linus Walleij | 03e9f0c | 2014-09-03 13:02:56 +0200 | [diff] [blame] | 147 | static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev, |
| 148 | unsigned function, |
| 149 | unsigned group) |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 150 | { |
| 151 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); |
| 152 | const struct msm_pingroup *g; |
| 153 | unsigned long flags; |
Kyle Yan | 6c2752f | 2017-09-27 16:29:45 -0700 | [diff] [blame] | 154 | u32 val, mask; |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 155 | int i; |
| 156 | |
| 157 | g = &pctrl->soc->groups[group]; |
Stephen Boyd | 47a01ee | 2016-06-25 22:21:31 -0700 | [diff] [blame] | 158 | mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 159 | |
Bjorn Andersson | 3c25381 | 2014-03-31 14:49:55 -0700 | [diff] [blame] | 160 | for (i = 0; i < g->nfuncs; i++) { |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 161 | if (g->funcs[i] == function) |
| 162 | break; |
| 163 | } |
| 164 | |
Bjorn Andersson | 3c25381 | 2014-03-31 14:49:55 -0700 | [diff] [blame] | 165 | if (WARN_ON(i == g->nfuncs)) |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 166 | return -EINVAL; |
| 167 | |
| 168 | spin_lock_irqsave(&pctrl->lock, flags); |
| 169 | |
Kyle Yan | 6c2752f | 2017-09-27 16:29:45 -0700 | [diff] [blame] | 170 | val = readl(pctrl->regs + g->ctl_reg); |
John Crispin | 6bcf3f6 | 2016-09-12 11:36:55 +0200 | [diff] [blame] | 171 | val &= ~mask; |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 172 | val |= i << g->mux_bit; |
Kyle Yan | 6c2752f | 2017-09-27 16:29:45 -0700 | [diff] [blame] | 173 | writel(val, pctrl->regs + g->ctl_reg); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 174 | |
| 175 | spin_unlock_irqrestore(&pctrl->lock, flags); |
| 176 | |
| 177 | return 0; |
| 178 | } |
| 179 | |
Bjorn Andersson | 1f2b239 | 2013-12-14 23:01:51 -0800 | [diff] [blame] | 180 | static const struct pinmux_ops msm_pinmux_ops = { |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 181 | .get_functions_count = msm_get_functions_count, |
| 182 | .get_function_name = msm_get_function_name, |
| 183 | .get_function_groups = msm_get_function_groups, |
Linus Walleij | 03e9f0c | 2014-09-03 13:02:56 +0200 | [diff] [blame] | 184 | .set_mux = msm_pinmux_set_mux, |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 185 | }; |
| 186 | |
| 187 | static int msm_config_reg(struct msm_pinctrl *pctrl, |
| 188 | const struct msm_pingroup *g, |
| 189 | unsigned param, |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 190 | unsigned *mask, |
| 191 | unsigned *bit) |
| 192 | { |
| 193 | switch (param) { |
| 194 | case PIN_CONFIG_BIAS_DISABLE: |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 195 | case PIN_CONFIG_BIAS_PULL_DOWN: |
Andy Gross | b831a15 | 2014-06-17 23:49:11 -0500 | [diff] [blame] | 196 | case PIN_CONFIG_BIAS_BUS_HOLD: |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 197 | case PIN_CONFIG_BIAS_PULL_UP: |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 198 | *bit = g->pull_bit; |
| 199 | *mask = 3; |
| 200 | break; |
| 201 | case PIN_CONFIG_DRIVE_STRENGTH: |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 202 | *bit = g->drv_bit; |
| 203 | *mask = 7; |
| 204 | break; |
Bjorn Andersson | ed118a5 | 2014-02-04 19:55:31 -0800 | [diff] [blame] | 205 | case PIN_CONFIG_OUTPUT: |
Stanimir Varbanov | 407f5e3 | 2015-03-04 12:41:57 +0200 | [diff] [blame] | 206 | case PIN_CONFIG_INPUT_ENABLE: |
Bjorn Andersson | ed118a5 | 2014-02-04 19:55:31 -0800 | [diff] [blame] | 207 | *bit = g->oe_bit; |
| 208 | *mask = 1; |
| 209 | break; |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 210 | default: |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 211 | return -ENOTSUPP; |
| 212 | } |
| 213 | |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 214 | return 0; |
| 215 | } |
| 216 | |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 217 | #define MSM_NO_PULL 0 |
| 218 | #define MSM_PULL_DOWN 1 |
Andy Gross | b831a15 | 2014-06-17 23:49:11 -0500 | [diff] [blame] | 219 | #define MSM_KEEPER 2 |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 220 | #define MSM_PULL_UP 3 |
| 221 | |
Stephen Boyd | 7cc34e2 | 2014-03-06 22:44:44 -0800 | [diff] [blame] | 222 | static unsigned msm_regval_to_drive(u32 val) |
| 223 | { |
| 224 | return (val + 1) * 2; |
| 225 | } |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 226 | |
| 227 | static int msm_config_group_get(struct pinctrl_dev *pctldev, |
| 228 | unsigned int group, |
| 229 | unsigned long *config) |
| 230 | { |
| 231 | const struct msm_pingroup *g; |
| 232 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); |
| 233 | unsigned param = pinconf_to_config_param(*config); |
| 234 | unsigned mask; |
| 235 | unsigned arg; |
| 236 | unsigned bit; |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 237 | int ret; |
Kyle Yan | 6c2752f | 2017-09-27 16:29:45 -0700 | [diff] [blame] | 238 | u32 val; |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 239 | |
| 240 | g = &pctrl->soc->groups[group]; |
| 241 | |
Stephen Boyd | 051a58b | 2014-03-06 22:44:46 -0800 | [diff] [blame] | 242 | ret = msm_config_reg(pctrl, g, param, &mask, &bit); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 243 | if (ret < 0) |
| 244 | return ret; |
| 245 | |
Kyle Yan | 6c2752f | 2017-09-27 16:29:45 -0700 | [diff] [blame] | 246 | val = readl(pctrl->regs + g->ctl_reg); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 247 | arg = (val >> bit) & mask; |
| 248 | |
| 249 | /* Convert register value to pinconf value */ |
| 250 | switch (param) { |
| 251 | case PIN_CONFIG_BIAS_DISABLE: |
| 252 | arg = arg == MSM_NO_PULL; |
| 253 | break; |
| 254 | case PIN_CONFIG_BIAS_PULL_DOWN: |
| 255 | arg = arg == MSM_PULL_DOWN; |
| 256 | break; |
Andy Gross | b831a15 | 2014-06-17 23:49:11 -0500 | [diff] [blame] | 257 | case PIN_CONFIG_BIAS_BUS_HOLD: |
| 258 | arg = arg == MSM_KEEPER; |
| 259 | break; |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 260 | case PIN_CONFIG_BIAS_PULL_UP: |
| 261 | arg = arg == MSM_PULL_UP; |
| 262 | break; |
| 263 | case PIN_CONFIG_DRIVE_STRENGTH: |
Stephen Boyd | 7cc34e2 | 2014-03-06 22:44:44 -0800 | [diff] [blame] | 264 | arg = msm_regval_to_drive(arg); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 265 | break; |
Bjorn Andersson | ed118a5 | 2014-02-04 19:55:31 -0800 | [diff] [blame] | 266 | case PIN_CONFIG_OUTPUT: |
| 267 | /* Pin is not output */ |
| 268 | if (!arg) |
| 269 | return -EINVAL; |
| 270 | |
Kyle Yan | 6c2752f | 2017-09-27 16:29:45 -0700 | [diff] [blame] | 271 | val = readl(pctrl->regs + g->io_reg); |
Bjorn Andersson | ed118a5 | 2014-02-04 19:55:31 -0800 | [diff] [blame] | 272 | arg = !!(val & BIT(g->in_bit)); |
| 273 | break; |
Stanimir Varbanov | 407f5e3 | 2015-03-04 12:41:57 +0200 | [diff] [blame] | 274 | case PIN_CONFIG_INPUT_ENABLE: |
| 275 | /* Pin is output */ |
| 276 | if (arg) |
| 277 | return -EINVAL; |
| 278 | arg = 1; |
| 279 | break; |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 280 | default: |
Stanimir Varbanov | 38d756a | 2015-03-04 12:41:56 +0200 | [diff] [blame] | 281 | return -ENOTSUPP; |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 282 | } |
| 283 | |
| 284 | *config = pinconf_to_config_packed(param, arg); |
| 285 | |
| 286 | return 0; |
| 287 | } |
| 288 | |
| 289 | static int msm_config_group_set(struct pinctrl_dev *pctldev, |
| 290 | unsigned group, |
| 291 | unsigned long *configs, |
| 292 | unsigned num_configs) |
| 293 | { |
| 294 | const struct msm_pingroup *g; |
| 295 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); |
| 296 | unsigned long flags; |
| 297 | unsigned param; |
| 298 | unsigned mask; |
| 299 | unsigned arg; |
| 300 | unsigned bit; |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 301 | int ret; |
Kyle Yan | 6c2752f | 2017-09-27 16:29:45 -0700 | [diff] [blame] | 302 | u32 val; |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 303 | int i; |
| 304 | |
| 305 | g = &pctrl->soc->groups[group]; |
| 306 | |
| 307 | for (i = 0; i < num_configs; i++) { |
| 308 | param = pinconf_to_config_param(configs[i]); |
| 309 | arg = pinconf_to_config_argument(configs[i]); |
| 310 | |
Stephen Boyd | 051a58b | 2014-03-06 22:44:46 -0800 | [diff] [blame] | 311 | ret = msm_config_reg(pctrl, g, param, &mask, &bit); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 312 | if (ret < 0) |
| 313 | return ret; |
| 314 | |
| 315 | /* Convert pinconf values to register values */ |
| 316 | switch (param) { |
| 317 | case PIN_CONFIG_BIAS_DISABLE: |
| 318 | arg = MSM_NO_PULL; |
| 319 | break; |
| 320 | case PIN_CONFIG_BIAS_PULL_DOWN: |
| 321 | arg = MSM_PULL_DOWN; |
| 322 | break; |
Andy Gross | b831a15 | 2014-06-17 23:49:11 -0500 | [diff] [blame] | 323 | case PIN_CONFIG_BIAS_BUS_HOLD: |
| 324 | arg = MSM_KEEPER; |
| 325 | break; |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 326 | case PIN_CONFIG_BIAS_PULL_UP: |
| 327 | arg = MSM_PULL_UP; |
| 328 | break; |
| 329 | case PIN_CONFIG_DRIVE_STRENGTH: |
| 330 | /* Check for invalid values */ |
Stephen Boyd | 7cc34e2 | 2014-03-06 22:44:44 -0800 | [diff] [blame] | 331 | if (arg > 16 || arg < 2 || (arg % 2) != 0) |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 332 | arg = -1; |
| 333 | else |
Stephen Boyd | 7cc34e2 | 2014-03-06 22:44:44 -0800 | [diff] [blame] | 334 | arg = (arg / 2) - 1; |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 335 | break; |
Bjorn Andersson | ed118a5 | 2014-02-04 19:55:31 -0800 | [diff] [blame] | 336 | case PIN_CONFIG_OUTPUT: |
| 337 | /* set output value */ |
| 338 | spin_lock_irqsave(&pctrl->lock, flags); |
Kyle Yan | 6c2752f | 2017-09-27 16:29:45 -0700 | [diff] [blame] | 339 | val = readl(pctrl->regs + g->io_reg); |
Bjorn Andersson | ed118a5 | 2014-02-04 19:55:31 -0800 | [diff] [blame] | 340 | if (arg) |
| 341 | val |= BIT(g->out_bit); |
| 342 | else |
| 343 | val &= ~BIT(g->out_bit); |
Kyle Yan | 6c2752f | 2017-09-27 16:29:45 -0700 | [diff] [blame] | 344 | writel(val, pctrl->regs + g->io_reg); |
Bjorn Andersson | ed118a5 | 2014-02-04 19:55:31 -0800 | [diff] [blame] | 345 | spin_unlock_irqrestore(&pctrl->lock, flags); |
| 346 | |
| 347 | /* enable output */ |
| 348 | arg = 1; |
| 349 | break; |
Stanimir Varbanov | 407f5e3 | 2015-03-04 12:41:57 +0200 | [diff] [blame] | 350 | case PIN_CONFIG_INPUT_ENABLE: |
| 351 | /* disable output */ |
| 352 | arg = 0; |
| 353 | break; |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 354 | default: |
| 355 | dev_err(pctrl->dev, "Unsupported config parameter: %x\n", |
| 356 | param); |
| 357 | return -EINVAL; |
| 358 | } |
| 359 | |
| 360 | /* Range-check user-supplied value */ |
| 361 | if (arg & ~mask) { |
| 362 | dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg); |
| 363 | return -EINVAL; |
| 364 | } |
| 365 | |
| 366 | spin_lock_irqsave(&pctrl->lock, flags); |
Kyle Yan | 6c2752f | 2017-09-27 16:29:45 -0700 | [diff] [blame] | 367 | val = readl(pctrl->regs + g->ctl_reg); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 368 | val &= ~(mask << bit); |
| 369 | val |= arg << bit; |
Kyle Yan | 6c2752f | 2017-09-27 16:29:45 -0700 | [diff] [blame] | 370 | writel(val, pctrl->regs + g->ctl_reg); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 371 | spin_unlock_irqrestore(&pctrl->lock, flags); |
| 372 | } |
| 373 | |
| 374 | return 0; |
| 375 | } |
| 376 | |
Bjorn Andersson | 1f2b239 | 2013-12-14 23:01:51 -0800 | [diff] [blame] | 377 | static const struct pinconf_ops msm_pinconf_ops = { |
Stanimir Varbanov | 38d756a | 2015-03-04 12:41:56 +0200 | [diff] [blame] | 378 | .is_generic = true, |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 379 | .pin_config_group_get = msm_config_group_get, |
| 380 | .pin_config_group_set = msm_config_group_set, |
| 381 | }; |
| 382 | |
| 383 | static struct pinctrl_desc msm_pinctrl_desc = { |
| 384 | .pctlops = &msm_pinctrl_ops, |
| 385 | .pmxops = &msm_pinmux_ops, |
| 386 | .confops = &msm_pinconf_ops, |
| 387 | .owner = THIS_MODULE, |
| 388 | }; |
| 389 | |
| 390 | static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
| 391 | { |
| 392 | const struct msm_pingroup *g; |
Linus Walleij | fded3f4 | 2015-12-08 09:49:18 +0100 | [diff] [blame] | 393 | struct msm_pinctrl *pctrl = gpiochip_get_data(chip); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 394 | unsigned long flags; |
Kyle Yan | 6c2752f | 2017-09-27 16:29:45 -0700 | [diff] [blame] | 395 | u32 val; |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 396 | |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 397 | g = &pctrl->soc->groups[offset]; |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 398 | |
| 399 | spin_lock_irqsave(&pctrl->lock, flags); |
| 400 | |
Kyle Yan | 6c2752f | 2017-09-27 16:29:45 -0700 | [diff] [blame] | 401 | val = readl(pctrl->regs + g->ctl_reg); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 402 | val &= ~BIT(g->oe_bit); |
Kyle Yan | 6c2752f | 2017-09-27 16:29:45 -0700 | [diff] [blame] | 403 | writel(val, pctrl->regs + g->ctl_reg); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 404 | |
| 405 | spin_unlock_irqrestore(&pctrl->lock, flags); |
| 406 | |
| 407 | return 0; |
| 408 | } |
| 409 | |
| 410 | static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value) |
| 411 | { |
| 412 | const struct msm_pingroup *g; |
Linus Walleij | fded3f4 | 2015-12-08 09:49:18 +0100 | [diff] [blame] | 413 | struct msm_pinctrl *pctrl = gpiochip_get_data(chip); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 414 | unsigned long flags; |
Kyle Yan | 6c2752f | 2017-09-27 16:29:45 -0700 | [diff] [blame] | 415 | u32 val; |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 416 | |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 417 | g = &pctrl->soc->groups[offset]; |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 418 | |
| 419 | spin_lock_irqsave(&pctrl->lock, flags); |
| 420 | |
Kyle Yan | 6c2752f | 2017-09-27 16:29:45 -0700 | [diff] [blame] | 421 | val = readl(pctrl->regs + g->io_reg); |
Axel Lin | e476e77 | 2013-12-13 21:35:55 +0800 | [diff] [blame] | 422 | if (value) |
| 423 | val |= BIT(g->out_bit); |
| 424 | else |
| 425 | val &= ~BIT(g->out_bit); |
Kyle Yan | 6c2752f | 2017-09-27 16:29:45 -0700 | [diff] [blame] | 426 | writel(val, pctrl->regs + g->io_reg); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 427 | |
Kyle Yan | 6c2752f | 2017-09-27 16:29:45 -0700 | [diff] [blame] | 428 | val = readl(pctrl->regs + g->ctl_reg); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 429 | val |= BIT(g->oe_bit); |
Kyle Yan | 6c2752f | 2017-09-27 16:29:45 -0700 | [diff] [blame] | 430 | writel(val, pctrl->regs + g->ctl_reg); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 431 | |
| 432 | spin_unlock_irqrestore(&pctrl->lock, flags); |
| 433 | |
| 434 | return 0; |
| 435 | } |
| 436 | |
| 437 | static int msm_gpio_get(struct gpio_chip *chip, unsigned offset) |
| 438 | { |
| 439 | const struct msm_pingroup *g; |
Linus Walleij | fded3f4 | 2015-12-08 09:49:18 +0100 | [diff] [blame] | 440 | struct msm_pinctrl *pctrl = gpiochip_get_data(chip); |
Kyle Yan | 6c2752f | 2017-09-27 16:29:45 -0700 | [diff] [blame] | 441 | u32 val; |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 442 | |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 443 | g = &pctrl->soc->groups[offset]; |
| 444 | |
Kyle Yan | 6c2752f | 2017-09-27 16:29:45 -0700 | [diff] [blame] | 445 | val = readl(pctrl->regs + g->io_reg); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 446 | return !!(val & BIT(g->in_bit)); |
| 447 | } |
| 448 | |
| 449 | static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
| 450 | { |
| 451 | const struct msm_pingroup *g; |
Linus Walleij | fded3f4 | 2015-12-08 09:49:18 +0100 | [diff] [blame] | 452 | struct msm_pinctrl *pctrl = gpiochip_get_data(chip); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 453 | unsigned long flags; |
Kyle Yan | 6c2752f | 2017-09-27 16:29:45 -0700 | [diff] [blame] | 454 | u32 val; |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 455 | |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 456 | g = &pctrl->soc->groups[offset]; |
| 457 | |
| 458 | spin_lock_irqsave(&pctrl->lock, flags); |
| 459 | |
Kyle Yan | 6c2752f | 2017-09-27 16:29:45 -0700 | [diff] [blame] | 460 | val = readl(pctrl->regs + g->io_reg); |
Axel Lin | e476e77 | 2013-12-13 21:35:55 +0800 | [diff] [blame] | 461 | if (value) |
| 462 | val |= BIT(g->out_bit); |
| 463 | else |
| 464 | val &= ~BIT(g->out_bit); |
Kyle Yan | 6c2752f | 2017-09-27 16:29:45 -0700 | [diff] [blame] | 465 | writel(val, pctrl->regs + g->io_reg); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 466 | |
| 467 | spin_unlock_irqrestore(&pctrl->lock, flags); |
| 468 | } |
| 469 | |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 470 | #ifdef CONFIG_DEBUG_FS |
| 471 | #include <linux/seq_file.h> |
| 472 | |
| 473 | static void msm_gpio_dbg_show_one(struct seq_file *s, |
| 474 | struct pinctrl_dev *pctldev, |
| 475 | struct gpio_chip *chip, |
| 476 | unsigned offset, |
| 477 | unsigned gpio) |
| 478 | { |
| 479 | const struct msm_pingroup *g; |
Linus Walleij | fded3f4 | 2015-12-08 09:49:18 +0100 | [diff] [blame] | 480 | struct msm_pinctrl *pctrl = gpiochip_get_data(chip); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 481 | unsigned func; |
| 482 | int is_out; |
| 483 | int drive; |
| 484 | int pull; |
Kyle Yan | 6c2752f | 2017-09-27 16:29:45 -0700 | [diff] [blame] | 485 | u32 ctl_reg; |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 486 | |
Bjorn Andersson | 1f2b239 | 2013-12-14 23:01:51 -0800 | [diff] [blame] | 487 | static const char * const pulls[] = { |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 488 | "no pull", |
| 489 | "pull down", |
| 490 | "keeper", |
| 491 | "pull up" |
| 492 | }; |
| 493 | |
| 494 | g = &pctrl->soc->groups[offset]; |
Kyle Yan | 6c2752f | 2017-09-27 16:29:45 -0700 | [diff] [blame] | 495 | ctl_reg = readl(pctrl->regs + g->ctl_reg); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 496 | |
| 497 | is_out = !!(ctl_reg & BIT(g->oe_bit)); |
| 498 | func = (ctl_reg >> g->mux_bit) & 7; |
| 499 | drive = (ctl_reg >> g->drv_bit) & 7; |
| 500 | pull = (ctl_reg >> g->pull_bit) & 3; |
| 501 | |
| 502 | seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func); |
Stephen Boyd | 7cc34e2 | 2014-03-06 22:44:44 -0800 | [diff] [blame] | 503 | seq_printf(s, " %dmA", msm_regval_to_drive(drive)); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 504 | seq_printf(s, " %s", pulls[pull]); |
| 505 | } |
| 506 | |
| 507 | static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) |
| 508 | { |
| 509 | unsigned gpio = chip->base; |
| 510 | unsigned i; |
| 511 | |
| 512 | for (i = 0; i < chip->ngpio; i++, gpio++) { |
| 513 | msm_gpio_dbg_show_one(s, NULL, chip, i, gpio); |
Bjorn Andersson | 1f2b239 | 2013-12-14 23:01:51 -0800 | [diff] [blame] | 514 | seq_puts(s, "\n"); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 515 | } |
| 516 | } |
| 517 | |
| 518 | #else |
| 519 | #define msm_gpio_dbg_show NULL |
| 520 | #endif |
| 521 | |
| 522 | static struct gpio_chip msm_gpio_template = { |
| 523 | .direction_input = msm_gpio_direction_input, |
| 524 | .direction_output = msm_gpio_direction_output, |
| 525 | .get = msm_gpio_get, |
| 526 | .set = msm_gpio_set, |
Jonas Gorski | 98c85d5 | 2015-10-11 17:34:19 +0200 | [diff] [blame] | 527 | .request = gpiochip_generic_request, |
| 528 | .free = gpiochip_generic_free, |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 529 | .dbg_show = msm_gpio_dbg_show, |
| 530 | }; |
| 531 | |
| 532 | /* For dual-edge interrupts in software, since some hardware has no |
| 533 | * such support: |
| 534 | * |
| 535 | * At appropriate moments, this function may be called to flip the polarity |
| 536 | * settings of both-edge irq lines to try and catch the next edge. |
| 537 | * |
| 538 | * The attempt is considered successful if: |
| 539 | * - the status bit goes high, indicating that an edge was caught, or |
| 540 | * - the input value of the gpio doesn't change during the attempt. |
| 541 | * If the value changes twice during the process, that would cause the first |
| 542 | * test to fail but would force the second, as two opposite |
| 543 | * transitions would cause a detection no matter the polarity setting. |
| 544 | * |
| 545 | * The do-loop tries to sledge-hammer closed the timing hole between |
| 546 | * the initial value-read and the polarity-write - if the line value changes |
| 547 | * during that window, an interrupt is lost, the new polarity setting is |
| 548 | * incorrect, and the first success test will fail, causing a retry. |
| 549 | * |
| 550 | * Algorithm comes from Google's msmgpio driver. |
| 551 | */ |
| 552 | static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl, |
| 553 | const struct msm_pingroup *g, |
Kyle Yan | 6c2752f | 2017-09-27 16:29:45 -0700 | [diff] [blame] | 554 | struct irq_data *d) |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 555 | { |
| 556 | int loop_limit = 100; |
| 557 | unsigned val, val2, intstat; |
| 558 | unsigned pol; |
| 559 | |
| 560 | do { |
Kyle Yan | 6c2752f | 2017-09-27 16:29:45 -0700 | [diff] [blame] | 561 | val = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 562 | |
Kyle Yan | 6c2752f | 2017-09-27 16:29:45 -0700 | [diff] [blame] | 563 | pol = readl(pctrl->regs + g->intr_cfg_reg); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 564 | pol ^= BIT(g->intr_polarity_bit); |
Kyle Yan | 6c2752f | 2017-09-27 16:29:45 -0700 | [diff] [blame] | 565 | writel(pol, pctrl->regs + g->intr_cfg_reg); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 566 | |
Kyle Yan | 6c2752f | 2017-09-27 16:29:45 -0700 | [diff] [blame] | 567 | val2 = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit); |
| 568 | intstat = readl(pctrl->regs + g->intr_status_reg); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 569 | if (intstat || (val == val2)) |
| 570 | return; |
| 571 | } while (loop_limit-- > 0); |
| 572 | dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n", |
| 573 | val, val2); |
| 574 | } |
| 575 | |
| 576 | static void msm_gpio_irq_mask(struct irq_data *d) |
| 577 | { |
Linus Walleij | cdcb0ab | 2014-04-29 11:00:40 -0700 | [diff] [blame] | 578 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
Linus Walleij | fded3f4 | 2015-12-08 09:49:18 +0100 | [diff] [blame] | 579 | struct msm_pinctrl *pctrl = gpiochip_get_data(gc); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 580 | const struct msm_pingroup *g; |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 581 | unsigned long flags; |
Kyle Yan | 6c2752f | 2017-09-27 16:29:45 -0700 | [diff] [blame] | 582 | u32 val; |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 583 | |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 584 | g = &pctrl->soc->groups[d->hwirq]; |
| 585 | |
| 586 | spin_lock_irqsave(&pctrl->lock, flags); |
| 587 | |
Kyle Yan | 6c2752f | 2017-09-27 16:29:45 -0700 | [diff] [blame] | 588 | val = readl(pctrl->regs + g->intr_cfg_reg); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 589 | val &= ~BIT(g->intr_enable_bit); |
Kyle Yan | 6c2752f | 2017-09-27 16:29:45 -0700 | [diff] [blame] | 590 | writel(val, pctrl->regs + g->intr_cfg_reg); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 591 | |
| 592 | clear_bit(d->hwirq, pctrl->enabled_irqs); |
| 593 | |
| 594 | spin_unlock_irqrestore(&pctrl->lock, flags); |
Raghavendra Kakarla | 0e77a9e | 2018-03-07 21:30:45 +0530 | [diff] [blame] | 595 | |
| 596 | if (d->parent_data) |
| 597 | irq_chip_mask_parent(d); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 598 | } |
| 599 | |
Srinivas Ramana | 6952139 | 2017-11-14 11:36:23 +0530 | [diff] [blame] | 600 | static void msm_gpio_irq_enable(struct irq_data *d) |
| 601 | { |
| 602 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
| 603 | struct msm_pinctrl *pctrl = gpiochip_get_data(gc); |
| 604 | const struct msm_pingroup *g; |
| 605 | unsigned long flags; |
| 606 | u32 val; |
| 607 | |
| 608 | g = &pctrl->soc->groups[d->hwirq]; |
| 609 | |
| 610 | spin_lock_irqsave(&pctrl->lock, flags); |
| 611 | /* clear the interrupt status bit before unmask to avoid |
| 612 | * any erraneous interrupts that would have got latched |
| 613 | * when the intterupt is not in use. |
| 614 | */ |
| 615 | val = readl(pctrl->regs + g->intr_status_reg); |
| 616 | val &= ~BIT(g->intr_status_bit); |
| 617 | writel(val, pctrl->regs + g->intr_status_reg); |
| 618 | |
| 619 | val = readl(pctrl->regs + g->intr_cfg_reg); |
| 620 | val |= BIT(g->intr_enable_bit); |
| 621 | writel(val, pctrl->regs + g->intr_cfg_reg); |
| 622 | |
| 623 | set_bit(d->hwirq, pctrl->enabled_irqs); |
| 624 | |
| 625 | spin_unlock_irqrestore(&pctrl->lock, flags); |
Raghavendra Kakarla | 0e77a9e | 2018-03-07 21:30:45 +0530 | [diff] [blame] | 626 | |
| 627 | if (d->parent_data) |
| 628 | irq_chip_enable_parent(d); |
Srinivas Ramana | 6952139 | 2017-11-14 11:36:23 +0530 | [diff] [blame] | 629 | } |
| 630 | |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 631 | static void msm_gpio_irq_unmask(struct irq_data *d) |
| 632 | { |
Linus Walleij | cdcb0ab | 2014-04-29 11:00:40 -0700 | [diff] [blame] | 633 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
Tengfei Fan | d36f745 | 2018-11-19 13:45:29 +0800 | [diff] [blame] | 634 | uint32_t irqtype = irqd_get_trigger_type(d); |
Linus Walleij | fded3f4 | 2015-12-08 09:49:18 +0100 | [diff] [blame] | 635 | struct msm_pinctrl *pctrl = gpiochip_get_data(gc); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 636 | const struct msm_pingroup *g; |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 637 | unsigned long flags; |
Kyle Yan | 6c2752f | 2017-09-27 16:29:45 -0700 | [diff] [blame] | 638 | u32 val; |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 639 | |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 640 | g = &pctrl->soc->groups[d->hwirq]; |
| 641 | |
| 642 | spin_lock_irqsave(&pctrl->lock, flags); |
| 643 | |
Tengfei Fan | d36f745 | 2018-11-19 13:45:29 +0800 | [diff] [blame] | 644 | if (irqtype & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) { |
| 645 | val = readl_relaxed(pctrl->regs + g->intr_status_reg); |
| 646 | val &= ~BIT(g->intr_status_bit); |
| 647 | writel_relaxed(val, pctrl->regs + g->intr_status_reg); |
| 648 | } |
| 649 | |
Kyle Yan | 6c2752f | 2017-09-27 16:29:45 -0700 | [diff] [blame] | 650 | val = readl(pctrl->regs + g->intr_cfg_reg); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 651 | val |= BIT(g->intr_enable_bit); |
Kyle Yan | 6c2752f | 2017-09-27 16:29:45 -0700 | [diff] [blame] | 652 | writel(val, pctrl->regs + g->intr_cfg_reg); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 653 | |
| 654 | set_bit(d->hwirq, pctrl->enabled_irqs); |
| 655 | |
| 656 | spin_unlock_irqrestore(&pctrl->lock, flags); |
Raghavendra Kakarla | 0e77a9e | 2018-03-07 21:30:45 +0530 | [diff] [blame] | 657 | |
| 658 | if (d->parent_data) |
| 659 | irq_chip_unmask_parent(d); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 660 | } |
| 661 | |
| 662 | static void msm_gpio_irq_ack(struct irq_data *d) |
| 663 | { |
Linus Walleij | cdcb0ab | 2014-04-29 11:00:40 -0700 | [diff] [blame] | 664 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
Linus Walleij | fded3f4 | 2015-12-08 09:49:18 +0100 | [diff] [blame] | 665 | struct msm_pinctrl *pctrl = gpiochip_get_data(gc); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 666 | const struct msm_pingroup *g; |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 667 | unsigned long flags; |
Kyle Yan | 6c2752f | 2017-09-27 16:29:45 -0700 | [diff] [blame] | 668 | u32 val; |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 669 | |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 670 | g = &pctrl->soc->groups[d->hwirq]; |
| 671 | |
| 672 | spin_lock_irqsave(&pctrl->lock, flags); |
| 673 | |
Kyle Yan | 6c2752f | 2017-09-27 16:29:45 -0700 | [diff] [blame] | 674 | val = readl(pctrl->regs + g->intr_status_reg); |
Bjorn Andersson | 48f15e9 | 2014-03-31 14:49:54 -0700 | [diff] [blame] | 675 | if (g->intr_ack_high) |
| 676 | val |= BIT(g->intr_status_bit); |
| 677 | else |
| 678 | val &= ~BIT(g->intr_status_bit); |
Kyle Yan | 6c2752f | 2017-09-27 16:29:45 -0700 | [diff] [blame] | 679 | writel(val, pctrl->regs + g->intr_status_reg); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 680 | |
| 681 | if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) |
Kyle Yan | 6c2752f | 2017-09-27 16:29:45 -0700 | [diff] [blame] | 682 | msm_gpio_update_dual_edge_pos(pctrl, g, d); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 683 | |
| 684 | spin_unlock_irqrestore(&pctrl->lock, flags); |
| 685 | } |
| 686 | |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 687 | static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) |
| 688 | { |
Linus Walleij | cdcb0ab | 2014-04-29 11:00:40 -0700 | [diff] [blame] | 689 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
Linus Walleij | fded3f4 | 2015-12-08 09:49:18 +0100 | [diff] [blame] | 690 | struct msm_pinctrl *pctrl = gpiochip_get_data(gc); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 691 | const struct msm_pingroup *g; |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 692 | unsigned long flags; |
Kyle Yan | 6c2752f | 2017-09-27 16:29:45 -0700 | [diff] [blame] | 693 | u32 val; |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 694 | |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 695 | g = &pctrl->soc->groups[d->hwirq]; |
Kyle Yan | 6c2752f | 2017-09-27 16:29:45 -0700 | [diff] [blame] | 696 | |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 697 | spin_lock_irqsave(&pctrl->lock, flags); |
| 698 | |
| 699 | /* |
| 700 | * For hw without possibility of detecting both edges |
| 701 | */ |
| 702 | if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH) |
| 703 | set_bit(d->hwirq, pctrl->dual_edge_irqs); |
| 704 | else |
| 705 | clear_bit(d->hwirq, pctrl->dual_edge_irqs); |
| 706 | |
| 707 | /* Route interrupts to application cpu */ |
Kyle Yan | 6c2752f | 2017-09-27 16:29:45 -0700 | [diff] [blame] | 708 | val = readl(pctrl->regs + g->intr_target_reg); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 709 | val &= ~(7 << g->intr_target_bit); |
Georgi Djakov | f712c55 | 2014-09-03 19:28:16 +0300 | [diff] [blame] | 710 | val |= g->intr_target_kpss_val << g->intr_target_bit; |
Kyle Yan | 6c2752f | 2017-09-27 16:29:45 -0700 | [diff] [blame] | 711 | writel(val, pctrl->regs + g->intr_target_reg); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 712 | |
| 713 | /* Update configuration for gpio. |
| 714 | * RAW_STATUS_EN is left on for all gpio irqs. Due to the |
| 715 | * internal circuitry of TLMM, toggling the RAW_STATUS |
| 716 | * could cause the INTR_STATUS to be set for EDGE interrupts. |
| 717 | */ |
Kyle Yan | 6c2752f | 2017-09-27 16:29:45 -0700 | [diff] [blame] | 718 | val = readl(pctrl->regs + g->intr_cfg_reg); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 719 | val |= BIT(g->intr_raw_status_bit); |
| 720 | if (g->intr_detection_width == 2) { |
| 721 | val &= ~(3 << g->intr_detection_bit); |
| 722 | val &= ~(1 << g->intr_polarity_bit); |
| 723 | switch (type) { |
| 724 | case IRQ_TYPE_EDGE_RISING: |
| 725 | val |= 1 << g->intr_detection_bit; |
| 726 | val |= BIT(g->intr_polarity_bit); |
| 727 | break; |
| 728 | case IRQ_TYPE_EDGE_FALLING: |
| 729 | val |= 2 << g->intr_detection_bit; |
| 730 | val |= BIT(g->intr_polarity_bit); |
| 731 | break; |
| 732 | case IRQ_TYPE_EDGE_BOTH: |
| 733 | val |= 3 << g->intr_detection_bit; |
| 734 | val |= BIT(g->intr_polarity_bit); |
| 735 | break; |
| 736 | case IRQ_TYPE_LEVEL_LOW: |
| 737 | break; |
| 738 | case IRQ_TYPE_LEVEL_HIGH: |
| 739 | val |= BIT(g->intr_polarity_bit); |
| 740 | break; |
| 741 | } |
| 742 | } else if (g->intr_detection_width == 1) { |
| 743 | val &= ~(1 << g->intr_detection_bit); |
| 744 | val &= ~(1 << g->intr_polarity_bit); |
| 745 | switch (type) { |
| 746 | case IRQ_TYPE_EDGE_RISING: |
| 747 | val |= BIT(g->intr_detection_bit); |
| 748 | val |= BIT(g->intr_polarity_bit); |
| 749 | break; |
| 750 | case IRQ_TYPE_EDGE_FALLING: |
| 751 | val |= BIT(g->intr_detection_bit); |
| 752 | break; |
| 753 | case IRQ_TYPE_EDGE_BOTH: |
| 754 | val |= BIT(g->intr_detection_bit); |
Bjorn Andersson | 48f15e9 | 2014-03-31 14:49:54 -0700 | [diff] [blame] | 755 | val |= BIT(g->intr_polarity_bit); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 756 | break; |
| 757 | case IRQ_TYPE_LEVEL_LOW: |
| 758 | break; |
| 759 | case IRQ_TYPE_LEVEL_HIGH: |
| 760 | val |= BIT(g->intr_polarity_bit); |
| 761 | break; |
| 762 | } |
| 763 | } else { |
| 764 | BUG(); |
| 765 | } |
Kyle Yan | 6c2752f | 2017-09-27 16:29:45 -0700 | [diff] [blame] | 766 | writel(val, pctrl->regs + g->intr_cfg_reg); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 767 | |
| 768 | if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) |
Kyle Yan | 6c2752f | 2017-09-27 16:29:45 -0700 | [diff] [blame] | 769 | msm_gpio_update_dual_edge_pos(pctrl, g, d); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 770 | |
| 771 | spin_unlock_irqrestore(&pctrl->lock, flags); |
| 772 | |
Raghavendra Kakarla | 0e77a9e | 2018-03-07 21:30:45 +0530 | [diff] [blame] | 773 | if (d->parent_data) |
| 774 | irq_chip_set_type_parent(d, type); |
| 775 | |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 776 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) |
Thomas Gleixner | 34c0ad8 | 2015-06-23 15:52:51 +0200 | [diff] [blame] | 777 | irq_set_handler_locked(d, handle_level_irq); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 778 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
Thomas Gleixner | 34c0ad8 | 2015-06-23 15:52:51 +0200 | [diff] [blame] | 779 | irq_set_handler_locked(d, handle_edge_irq); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 780 | |
| 781 | return 0; |
| 782 | } |
| 783 | |
| 784 | static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) |
| 785 | { |
Linus Walleij | cdcb0ab | 2014-04-29 11:00:40 -0700 | [diff] [blame] | 786 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
Linus Walleij | fded3f4 | 2015-12-08 09:49:18 +0100 | [diff] [blame] | 787 | struct msm_pinctrl *pctrl = gpiochip_get_data(gc); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 788 | unsigned long flags; |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 789 | |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 790 | spin_lock_irqsave(&pctrl->lock, flags); |
| 791 | |
Josh Cartwright | 6aced33 | 2014-03-05 13:33:08 -0600 | [diff] [blame] | 792 | irq_set_irq_wake(pctrl->irq, on); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 793 | |
| 794 | spin_unlock_irqrestore(&pctrl->lock, flags); |
| 795 | |
Raghavendra Kakarla | 0e77a9e | 2018-03-07 21:30:45 +0530 | [diff] [blame] | 796 | if (d->parent_data) |
| 797 | irq_chip_set_wake_parent(d, on); |
| 798 | |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 799 | return 0; |
| 800 | } |
| 801 | |
Raju P.L.S.S.S.N | cdcd769 | 2017-11-30 19:06:30 +0530 | [diff] [blame] | 802 | static int msm_gpiochip_irq_reqres(struct irq_data *d) |
| 803 | { |
| 804 | struct gpio_chip *chip = irq_data_get_irq_chip_data(d); |
| 805 | |
| 806 | if (!try_module_get(chip->owner)) |
| 807 | return -ENODEV; |
| 808 | |
| 809 | if (gpiochip_lock_as_irq(chip, d->hwirq)) { |
| 810 | pr_err("unable to lock HW IRQ %lu for IRQ\n", d->hwirq); |
| 811 | module_put(chip->owner); |
| 812 | return -EINVAL; |
| 813 | } |
| 814 | return 0; |
| 815 | } |
| 816 | |
| 817 | static void msm_gpiochip_irq_relres(struct irq_data *d) |
| 818 | { |
| 819 | struct gpio_chip *chip = irq_data_get_irq_chip_data(d); |
| 820 | |
| 821 | gpiochip_unlock_as_irq(chip, d->hwirq); |
| 822 | module_put(chip->owner); |
| 823 | } |
| 824 | |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 825 | static struct irq_chip msm_gpio_irq_chip = { |
| 826 | .name = "msmgpio", |
Srinivas Ramana | 6952139 | 2017-11-14 11:36:23 +0530 | [diff] [blame] | 827 | .irq_enable = msm_gpio_irq_enable, |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 828 | .irq_mask = msm_gpio_irq_mask, |
| 829 | .irq_unmask = msm_gpio_irq_unmask, |
| 830 | .irq_ack = msm_gpio_irq_ack, |
| 831 | .irq_set_type = msm_gpio_irq_set_type, |
| 832 | .irq_set_wake = msm_gpio_irq_set_wake, |
Raju P.L.S.S.S.N | cdcd769 | 2017-11-30 19:06:30 +0530 | [diff] [blame] | 833 | .irq_request_resources = msm_gpiochip_irq_reqres, |
| 834 | .irq_release_resources = msm_gpiochip_irq_relres, |
| 835 | .flags = IRQCHIP_MASK_ON_SUSPEND | |
| 836 | IRQCHIP_SKIP_SET_WAKE, |
| 837 | }; |
| 838 | |
| 839 | static void msm_gpio_domain_set_info(struct irq_domain *d, unsigned int irq, |
| 840 | irq_hw_number_t hwirq) |
| 841 | { |
| 842 | struct gpio_chip *gc = d->host_data; |
| 843 | |
| 844 | irq_domain_set_info(d, irq, hwirq, gc->irqchip, d->host_data, |
| 845 | gc->irq_handler, NULL, NULL); |
| 846 | |
| 847 | if (gc->can_sleep && !gc->irq_not_threaded) |
| 848 | irq_set_nested_thread(irq, 1); |
| 849 | |
| 850 | irq_set_noprobe(irq); |
| 851 | } |
| 852 | |
| 853 | static int msm_gpio_domain_translate(struct irq_domain *d, |
| 854 | struct irq_fwspec *fwspec, unsigned long *hwirq, unsigned int *type) |
| 855 | { |
| 856 | if (is_of_node(fwspec->fwnode)) { |
| 857 | if (fwspec->param_count < 2) |
| 858 | return -EINVAL; |
| 859 | if (hwirq) |
| 860 | *hwirq = fwspec->param[0]; |
| 861 | if (type) |
| 862 | *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK; |
| 863 | return 0; |
| 864 | } |
| 865 | |
| 866 | return -EINVAL; |
| 867 | } |
| 868 | |
| 869 | static int msm_gpio_domain_alloc(struct irq_domain *domain, unsigned int virq, |
| 870 | unsigned int nr_irqs, void *arg) |
| 871 | { |
Raghavendra Kakarla | 0e77a9e | 2018-03-07 21:30:45 +0530 | [diff] [blame] | 872 | int ret = 0; |
Raju P.L.S.S.S.N | cdcd769 | 2017-11-30 19:06:30 +0530 | [diff] [blame] | 873 | irq_hw_number_t hwirq; |
Raghavendra Kakarla | 0e77a9e | 2018-03-07 21:30:45 +0530 | [diff] [blame] | 874 | struct irq_fwspec *fwspec = arg, parent_fwspec; |
Raju P.L.S.S.S.N | cdcd769 | 2017-11-30 19:06:30 +0530 | [diff] [blame] | 875 | |
| 876 | ret = msm_gpio_domain_translate(domain, fwspec, &hwirq, NULL); |
| 877 | if (ret) |
| 878 | return ret; |
| 879 | |
| 880 | msm_gpio_domain_set_info(domain, virq, hwirq); |
Raghavendra Kakarla | 0e77a9e | 2018-03-07 21:30:45 +0530 | [diff] [blame] | 881 | |
| 882 | parent_fwspec = *fwspec; |
| 883 | parent_fwspec.fwnode = domain->parent->fwnode; |
| 884 | return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, |
| 885 | &parent_fwspec); |
Raju P.L.S.S.S.N | cdcd769 | 2017-11-30 19:06:30 +0530 | [diff] [blame] | 886 | } |
| 887 | |
| 888 | static const struct irq_domain_ops msm_gpio_domain_ops = { |
| 889 | .translate = msm_gpio_domain_translate, |
| 890 | .alloc = msm_gpio_domain_alloc, |
| 891 | .free = irq_domain_free_irqs_top, |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 892 | }; |
| 893 | |
Archana Sathyakumar | 892c01c | 2017-10-31 13:47:20 -0600 | [diff] [blame] | 894 | static struct irq_chip msm_dirconn_irq_chip; |
| 895 | |
| 896 | static void msm_gpio_dirconn_handler(struct irq_desc *desc) |
| 897 | { |
| 898 | struct irq_data *irqd = irq_desc_get_handler_data(desc); |
| 899 | struct irq_chip *chip = irq_desc_get_chip(desc); |
| 900 | |
| 901 | chained_irq_enter(chip, desc); |
| 902 | generic_handle_irq(irqd->irq); |
| 903 | chained_irq_exit(chip, desc); |
| 904 | } |
| 905 | |
| 906 | static void setup_pdc_gpio(struct irq_domain *domain, |
| 907 | unsigned int parent_irq, unsigned int gpio) |
| 908 | { |
| 909 | int irq; |
| 910 | |
| 911 | if (gpio != 0) { |
Raghavendra Kakarla | 0e77a9e | 2018-03-07 21:30:45 +0530 | [diff] [blame] | 912 | irq = irq_find_mapping(domain, gpio); |
Archana Sathyakumar | 892c01c | 2017-10-31 13:47:20 -0600 | [diff] [blame] | 913 | irq_set_parent(irq, parent_irq); |
| 914 | irq_set_chip(irq, &msm_dirconn_irq_chip); |
| 915 | irq_set_handler_data(parent_irq, irq_get_irq_data(irq)); |
| 916 | } |
| 917 | |
| 918 | __irq_set_handler(parent_irq, msm_gpio_dirconn_handler, false, NULL); |
| 919 | } |
| 920 | |
| 921 | static void request_dc_interrupt(struct irq_domain *domain, |
| 922 | struct irq_domain *parent, irq_hw_number_t hwirq, |
| 923 | unsigned int gpio) |
| 924 | { |
| 925 | struct irq_fwspec fwspec; |
| 926 | unsigned int parent_irq; |
| 927 | |
| 928 | fwspec.fwnode = parent->fwnode; |
| 929 | fwspec.param[0] = 0; /* SPI */ |
| 930 | fwspec.param[1] = hwirq; |
| 931 | fwspec.param[2] = IRQ_TYPE_NONE; |
| 932 | fwspec.param_count = 3; |
| 933 | |
| 934 | parent_irq = irq_create_fwspec_mapping(&fwspec); |
| 935 | |
| 936 | setup_pdc_gpio(domain, parent_irq, gpio); |
| 937 | } |
| 938 | |
| 939 | /** |
| 940 | * gpio_muxed_to_pdc: Mux the GPIO to a PDC IRQ |
| 941 | * |
| 942 | * @pdc_domain: the PDC's domain |
| 943 | * @d: the GPIO's IRQ data |
| 944 | * |
| 945 | * Find a free PDC port for the GPIO and map the GPIO's mux information to the |
| 946 | * PDC registers; so the GPIO can be used a wakeup source. |
| 947 | */ |
| 948 | static void gpio_muxed_to_pdc(struct irq_domain *pdc_domain, struct irq_data *d) |
| 949 | { |
| 950 | int i, j; |
| 951 | unsigned int mux; |
| 952 | struct irq_desc *desc = irq_data_to_desc(d); |
| 953 | struct irq_data *parent_data = irq_get_irq_data(desc->parent_irq); |
| 954 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
| 955 | unsigned int gpio = d->hwirq; |
| 956 | struct msm_pinctrl *pctrl; |
| 957 | unsigned int irq; |
| 958 | |
| 959 | if (!gc || !parent_data) |
| 960 | return; |
| 961 | |
| 962 | pctrl = gpiochip_get_data(gc); |
| 963 | |
| 964 | for (i = 0; i < pctrl->soc->n_gpio_mux_in; i++) { |
| 965 | if (gpio != pctrl->soc->gpio_mux_in[i].gpio) |
| 966 | continue; |
| 967 | mux = pctrl->soc->gpio_mux_in[i].mux; |
| 968 | for (j = 0; j < pctrl->soc->n_pdc_mux_out; j++) { |
| 969 | struct msm_pdc_mux_output *pdc_out = |
| 970 | &pctrl->soc->pdc_mux_out[j]; |
| 971 | |
| 972 | if (pdc_out->mux == mux) |
| 973 | break; |
| 974 | if (pdc_out->mux) |
| 975 | continue; |
| 976 | pdc_out->mux = gpio; |
| 977 | irq = irq_find_mapping(pdc_domain, pdc_out->hwirq + 32); |
| 978 | /* setup the IRQ parent for the GPIO */ |
| 979 | setup_pdc_gpio(pctrl->chip.irqdomain, irq, gpio); |
| 980 | /* program pdc select grp register */ |
| 981 | writel_relaxed((mux & 0x3F), pctrl->pdc_regs + |
| 982 | (0x14 * j)); |
| 983 | break; |
| 984 | } |
| 985 | /* We have no more PDC port available */ |
| 986 | WARN_ON(j == pctrl->soc->n_pdc_mux_out); |
| 987 | } |
| 988 | } |
| 989 | |
Archana Sathyakumar | 5630a2e | 2017-11-02 15:24:20 -0600 | [diff] [blame] | 990 | static bool is_gpio_tlmm_dc(struct irq_data *d, u32 type) |
| 991 | { |
| 992 | const struct msm_pingroup *g; |
| 993 | unsigned long flags; |
| 994 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
| 995 | struct msm_pinctrl *pctrl; |
| 996 | bool ret = false; |
| 997 | unsigned int polarity = 0, offset, val; |
| 998 | int i; |
| 999 | |
| 1000 | if (!gc) |
| 1001 | return false; |
| 1002 | |
| 1003 | pctrl = gpiochip_get_data(gc); |
| 1004 | |
| 1005 | for (i = 0; i < pctrl->soc->n_dir_conns; i++) { |
| 1006 | struct msm_dir_conn *dir_conn = (struct msm_dir_conn *) |
| 1007 | &pctrl->soc->dir_conn[i]; |
| 1008 | |
| 1009 | if (dir_conn->gpio == d->hwirq && dir_conn->tlmm_dc) { |
| 1010 | ret = true; |
| 1011 | offset = pctrl->soc->dir_conn_irq_base - |
| 1012 | dir_conn->hwirq; |
| 1013 | break; |
| 1014 | } |
| 1015 | } |
| 1016 | |
| 1017 | if (!ret) |
| 1018 | return ret; |
| 1019 | |
| 1020 | if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)) |
| 1021 | return ret; |
| 1022 | |
| 1023 | /* |
| 1024 | * Since the default polarity is set to 0, change it to 1 for |
| 1025 | * Rising edge and active high interrupt type such that the line |
| 1026 | * is not inverted. |
| 1027 | */ |
| 1028 | polarity = 1; |
| 1029 | |
| 1030 | spin_lock_irqsave(&pctrl->lock, flags); |
| 1031 | g = &pctrl->soc->groups[d->hwirq]; |
| 1032 | |
| 1033 | val = readl_relaxed(pctrl->regs + g->dir_conn_reg + (offset * 4)); |
| 1034 | val |= polarity << 8; |
| 1035 | |
| 1036 | writel_relaxed(val, pctrl->regs + g->dir_conn_reg + (offset * 4)); |
| 1037 | |
| 1038 | spin_unlock_irqrestore(&pctrl->lock, flags); |
| 1039 | |
| 1040 | return ret; |
| 1041 | } |
| 1042 | |
Archana Sathyakumar | 8ff3ba6 | 2017-10-06 11:58:46 -0600 | [diff] [blame] | 1043 | static bool is_gpio_dual_edge(struct irq_data *d, irq_hw_number_t *dir_conn_irq) |
| 1044 | { |
| 1045 | struct irq_desc *desc = irq_data_to_desc(d); |
| 1046 | struct irq_data *parent_data = irq_get_irq_data(desc->parent_irq); |
| 1047 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
| 1048 | struct msm_pinctrl *pctrl = gpiochip_get_data(gc); |
| 1049 | int i; |
| 1050 | |
| 1051 | if (!parent_data) |
| 1052 | return false; |
| 1053 | |
| 1054 | for (i = 0; i < pctrl->soc->n_dir_conns; i++) { |
| 1055 | const struct msm_dir_conn *dir_conn = &pctrl->soc->dir_conn[i]; |
| 1056 | |
| 1057 | if (dir_conn->gpio == d->hwirq && (dir_conn->hwirq + 32) |
| 1058 | != parent_data->hwirq) { |
| 1059 | *dir_conn_irq = dir_conn->hwirq + 32; |
| 1060 | return true; |
| 1061 | } |
| 1062 | } |
Archana Sathyakumar | 892c01c | 2017-10-31 13:47:20 -0600 | [diff] [blame] | 1063 | |
| 1064 | for (i = 0; i < pctrl->soc->n_pdc_mux_out; i++) { |
| 1065 | struct msm_pdc_mux_output *dir_conn = |
| 1066 | &pctrl->soc->pdc_mux_out[i]; |
| 1067 | |
| 1068 | if (dir_conn->mux == d->hwirq && (dir_conn->hwirq + 32) |
| 1069 | != parent_data->hwirq) { |
| 1070 | *dir_conn_irq = dir_conn->hwirq + 32; |
| 1071 | return true; |
| 1072 | } |
| 1073 | } |
Archana Sathyakumar | 8ff3ba6 | 2017-10-06 11:58:46 -0600 | [diff] [blame] | 1074 | return false; |
| 1075 | } |
| 1076 | |
Mahesh Sivasubramanian | fcc313e | 2017-04-10 09:05:59 -0600 | [diff] [blame] | 1077 | static void msm_dirconn_irq_mask(struct irq_data *d) |
| 1078 | { |
| 1079 | struct irq_desc *desc = irq_data_to_desc(d); |
| 1080 | struct irq_data *parent_data = irq_get_irq_data(desc->parent_irq); |
Archana Sathyakumar | 8ff3ba6 | 2017-10-06 11:58:46 -0600 | [diff] [blame] | 1081 | irq_hw_number_t dir_conn_irq = 0; |
Mahesh Sivasubramanian | fcc313e | 2017-04-10 09:05:59 -0600 | [diff] [blame] | 1082 | |
Archana Sathyakumar | 8ff3ba6 | 2017-10-06 11:58:46 -0600 | [diff] [blame] | 1083 | if (!parent_data) |
| 1084 | return; |
| 1085 | |
| 1086 | if (is_gpio_dual_edge(d, &dir_conn_irq)) { |
| 1087 | struct irq_data *dir_conn_data = |
| 1088 | irq_get_irq_data(irq_find_mapping(parent_data->domain, |
| 1089 | dir_conn_irq)); |
| 1090 | |
Archana Sathyakumar | 892c01c | 2017-10-31 13:47:20 -0600 | [diff] [blame] | 1091 | if (!dir_conn_data) |
| 1092 | return; |
| 1093 | if (dir_conn_data->chip->irq_mask) |
Archana Sathyakumar | 8ff3ba6 | 2017-10-06 11:58:46 -0600 | [diff] [blame] | 1094 | dir_conn_data->chip->irq_mask(dir_conn_data); |
| 1095 | } |
Archana Sathyakumar | 892c01c | 2017-10-31 13:47:20 -0600 | [diff] [blame] | 1096 | |
Mahesh Sivasubramanian | fcc313e | 2017-04-10 09:05:59 -0600 | [diff] [blame] | 1097 | if (parent_data->chip->irq_mask) |
| 1098 | parent_data->chip->irq_mask(parent_data); |
| 1099 | } |
| 1100 | |
Maulik Shah | e0a5583 | 2018-01-23 14:24:18 +0530 | [diff] [blame] | 1101 | static void msm_dirconn_irq_enable(struct irq_data *d) |
| 1102 | { |
| 1103 | struct irq_desc *desc = irq_data_to_desc(d); |
| 1104 | struct irq_data *parent_data = irq_get_irq_data(desc->parent_irq); |
| 1105 | irq_hw_number_t dir_conn_irq = 0; |
| 1106 | |
| 1107 | if (!parent_data) |
| 1108 | return; |
| 1109 | |
| 1110 | if (is_gpio_dual_edge(d, &dir_conn_irq)) { |
| 1111 | struct irq_data *dir_conn_data = |
| 1112 | irq_get_irq_data(irq_find_mapping(parent_data->domain, |
| 1113 | dir_conn_irq)); |
| 1114 | |
| 1115 | if (dir_conn_data && |
| 1116 | dir_conn_data->chip->irq_set_irqchip_state) |
| 1117 | dir_conn_data->chip->irq_set_irqchip_state( |
| 1118 | dir_conn_data, |
| 1119 | IRQCHIP_STATE_PENDING, 0); |
| 1120 | |
| 1121 | if (dir_conn_data && dir_conn_data->chip->irq_unmask) |
| 1122 | dir_conn_data->chip->irq_unmask(dir_conn_data); |
| 1123 | } |
| 1124 | |
| 1125 | if (parent_data->chip->irq_set_irqchip_state) |
| 1126 | parent_data->chip->irq_set_irqchip_state(parent_data, |
| 1127 | IRQCHIP_STATE_PENDING, 0); |
| 1128 | |
| 1129 | if (parent_data->chip->irq_unmask) |
| 1130 | parent_data->chip->irq_unmask(parent_data); |
| 1131 | } |
| 1132 | |
Mahesh Sivasubramanian | fcc313e | 2017-04-10 09:05:59 -0600 | [diff] [blame] | 1133 | static void msm_dirconn_irq_unmask(struct irq_data *d) |
| 1134 | { |
| 1135 | struct irq_desc *desc = irq_data_to_desc(d); |
| 1136 | struct irq_data *parent_data = irq_get_irq_data(desc->parent_irq); |
Archana Sathyakumar | 8ff3ba6 | 2017-10-06 11:58:46 -0600 | [diff] [blame] | 1137 | irq_hw_number_t dir_conn_irq = 0; |
Mahesh Sivasubramanian | fcc313e | 2017-04-10 09:05:59 -0600 | [diff] [blame] | 1138 | |
Archana Sathyakumar | 8ff3ba6 | 2017-10-06 11:58:46 -0600 | [diff] [blame] | 1139 | if (!parent_data) |
| 1140 | return; |
| 1141 | |
| 1142 | if (is_gpio_dual_edge(d, &dir_conn_irq)) { |
| 1143 | struct irq_data *dir_conn_data = |
| 1144 | irq_get_irq_data(irq_find_mapping(parent_data->domain, |
| 1145 | dir_conn_irq)); |
| 1146 | |
Archana Sathyakumar | 892c01c | 2017-10-31 13:47:20 -0600 | [diff] [blame] | 1147 | if (!dir_conn_data) |
| 1148 | return; |
| 1149 | if (dir_conn_data->chip->irq_unmask) |
Archana Sathyakumar | 8ff3ba6 | 2017-10-06 11:58:46 -0600 | [diff] [blame] | 1150 | dir_conn_data->chip->irq_unmask(dir_conn_data); |
| 1151 | } |
Mahesh Sivasubramanian | fcc313e | 2017-04-10 09:05:59 -0600 | [diff] [blame] | 1152 | if (parent_data->chip->irq_unmask) |
| 1153 | parent_data->chip->irq_unmask(parent_data); |
| 1154 | } |
| 1155 | |
| 1156 | static void msm_dirconn_irq_ack(struct irq_data *d) |
| 1157 | { |
| 1158 | struct irq_desc *desc = irq_data_to_desc(d); |
| 1159 | struct irq_data *parent_data = irq_get_irq_data(desc->parent_irq); |
| 1160 | |
Maulik Shah | 9180da2 | 2017-10-31 15:23:17 +0530 | [diff] [blame] | 1161 | if (!parent_data) |
| 1162 | return; |
| 1163 | |
Mahesh Sivasubramanian | fcc313e | 2017-04-10 09:05:59 -0600 | [diff] [blame] | 1164 | if (parent_data->chip->irq_ack) |
| 1165 | parent_data->chip->irq_ack(parent_data); |
| 1166 | } |
| 1167 | |
| 1168 | static void msm_dirconn_irq_eoi(struct irq_data *d) |
| 1169 | { |
| 1170 | struct irq_desc *desc = irq_data_to_desc(d); |
| 1171 | struct irq_data *parent_data = irq_get_irq_data(desc->parent_irq); |
| 1172 | |
Maulik Shah | 9180da2 | 2017-10-31 15:23:17 +0530 | [diff] [blame] | 1173 | if (!parent_data) |
| 1174 | return; |
| 1175 | |
Mahesh Sivasubramanian | fcc313e | 2017-04-10 09:05:59 -0600 | [diff] [blame] | 1176 | if (parent_data->chip->irq_eoi) |
| 1177 | parent_data->chip->irq_eoi(parent_data); |
| 1178 | } |
| 1179 | |
| 1180 | static int msm_dirconn_irq_set_affinity(struct irq_data *d, |
| 1181 | const struct cpumask *maskval, bool force) |
| 1182 | { |
| 1183 | struct irq_desc *desc = irq_data_to_desc(d); |
| 1184 | struct irq_data *parent_data = irq_get_irq_data(desc->parent_irq); |
| 1185 | |
Archana Sathyakumar | 8ff3ba6 | 2017-10-06 11:58:46 -0600 | [diff] [blame] | 1186 | if (!parent_data) |
| 1187 | return 0; |
| 1188 | |
Mahesh Sivasubramanian | fcc313e | 2017-04-10 09:05:59 -0600 | [diff] [blame] | 1189 | if (parent_data->chip->irq_set_affinity) |
| 1190 | return parent_data->chip->irq_set_affinity(parent_data, |
| 1191 | maskval, force); |
| 1192 | return 0; |
| 1193 | } |
| 1194 | |
| 1195 | static int msm_dirconn_irq_set_vcpu_affinity(struct irq_data *d, |
| 1196 | void *vcpu_info) |
| 1197 | { |
| 1198 | struct irq_desc *desc = irq_data_to_desc(d); |
| 1199 | struct irq_data *parent_data = irq_get_irq_data(desc->parent_irq); |
| 1200 | |
Maulik Shah | 9180da2 | 2017-10-31 15:23:17 +0530 | [diff] [blame] | 1201 | if (!parent_data) |
| 1202 | return 0; |
| 1203 | |
Mahesh Sivasubramanian | fcc313e | 2017-04-10 09:05:59 -0600 | [diff] [blame] | 1204 | if (parent_data->chip->irq_set_vcpu_affinity) |
| 1205 | return parent_data->chip->irq_set_vcpu_affinity(parent_data, |
| 1206 | vcpu_info); |
| 1207 | return 0; |
| 1208 | } |
| 1209 | |
Archana Sathyakumar | 8ff3ba6 | 2017-10-06 11:58:46 -0600 | [diff] [blame] | 1210 | static void msm_dirconn_cfg_reg(struct irq_data *d, u32 offset) |
| 1211 | { |
| 1212 | u32 val = 0; |
| 1213 | const struct msm_pingroup *g; |
| 1214 | unsigned long flags; |
| 1215 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
| 1216 | struct msm_pinctrl *pctrl = gpiochip_get_data(gc); |
| 1217 | |
| 1218 | spin_lock_irqsave(&pctrl->lock, flags); |
| 1219 | g = &pctrl->soc->groups[d->hwirq]; |
| 1220 | |
| 1221 | val = readl_relaxed(pctrl->regs + g->dir_conn_reg + (offset * 4)); |
| 1222 | val = (d->hwirq) & 0xFF; |
| 1223 | |
| 1224 | writel_relaxed(val, pctrl->regs + g->dir_conn_reg + (offset * 4)); |
| 1225 | |
| 1226 | //write the dir_conn_en bit |
| 1227 | val = readl_relaxed(pctrl->regs + g->intr_cfg_reg); |
| 1228 | val |= BIT(g->dir_conn_en_bit); |
| 1229 | writel_relaxed(val, pctrl->regs + g->intr_cfg_reg); |
| 1230 | spin_unlock_irqrestore(&pctrl->lock, flags); |
| 1231 | } |
| 1232 | |
| 1233 | static void msm_dirconn_uncfg_reg(struct irq_data *d, u32 offset) |
| 1234 | { |
| 1235 | const struct msm_pingroup *g; |
| 1236 | unsigned long flags; |
| 1237 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
| 1238 | struct msm_pinctrl *pctrl = gpiochip_get_data(gc); |
| 1239 | |
| 1240 | spin_lock_irqsave(&pctrl->lock, flags); |
| 1241 | g = &pctrl->soc->groups[d->hwirq]; |
| 1242 | |
| 1243 | writel_relaxed(BIT(8), pctrl->regs + g->dir_conn_reg + (offset * 4)); |
| 1244 | spin_unlock_irqrestore(&pctrl->lock, flags); |
| 1245 | } |
| 1246 | |
| 1247 | static int select_dir_conn_mux(struct irq_data *d, irq_hw_number_t *irq) |
| 1248 | { |
| 1249 | struct msm_dir_conn *dc = NULL; |
| 1250 | struct irq_desc *desc = irq_data_to_desc(d); |
| 1251 | struct irq_data *parent_data = irq_get_irq_data(desc->parent_irq); |
| 1252 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
| 1253 | struct msm_pinctrl *pctrl = gpiochip_get_data(gc); |
| 1254 | int i; |
| 1255 | |
| 1256 | if (!parent_data) |
| 1257 | return -EINVAL; |
| 1258 | |
| 1259 | for (i = 0; i < pctrl->soc->n_dir_conns; i++) { |
| 1260 | struct msm_dir_conn *dir_conn = |
| 1261 | (struct msm_dir_conn *)&pctrl->soc->dir_conn[i]; |
| 1262 | |
| 1263 | /* Check if there is already mux assigned for this gpio */ |
| 1264 | if (dir_conn->gpio == d->hwirq && (dir_conn->hwirq + 32) != |
| 1265 | parent_data->hwirq) { |
| 1266 | *irq = dir_conn->hwirq + 32; |
| 1267 | return pctrl->soc->dir_conn_irq_base - dir_conn->hwirq; |
| 1268 | } |
| 1269 | |
| 1270 | if (dir_conn->gpio) |
| 1271 | continue; |
| 1272 | |
| 1273 | /* Use the first unused direct connect available */ |
| 1274 | dc = dir_conn; |
| 1275 | break; |
| 1276 | } |
| 1277 | |
| 1278 | if (dc) { |
| 1279 | *irq = dc->hwirq + 32; |
| 1280 | dc->gpio = (u32)d->hwirq; |
| 1281 | return pctrl->soc->dir_conn_irq_base - (u32)dc->hwirq; |
| 1282 | } |
| 1283 | |
| 1284 | pr_err("%s: No direct connects available for interrupt %lu\n", |
| 1285 | __func__, d->hwirq); |
| 1286 | return -EINVAL; |
| 1287 | } |
| 1288 | |
| 1289 | static void add_dirconn_tlmm(struct irq_data *d, irq_hw_number_t irq) |
| 1290 | { |
| 1291 | struct irq_desc *desc = irq_data_to_desc(d); |
| 1292 | struct irq_data *parent_data = irq_get_irq_data(desc->parent_irq); |
| 1293 | struct irq_data *dir_conn_data = NULL; |
Srinivas Rao L | d630298 | 2018-07-31 12:36:56 +0530 | [diff] [blame] | 1294 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
Archana Sathyakumar | 8ff3ba6 | 2017-10-06 11:58:46 -0600 | [diff] [blame] | 1295 | int offset = 0; |
Srinivas Rao L | d630298 | 2018-07-31 12:36:56 +0530 | [diff] [blame] | 1296 | unsigned int virt = 0, val = 0; |
| 1297 | struct msm_pinctrl *pctrl; |
| 1298 | phys_addr_t spi_cfg_reg = 0; |
| 1299 | unsigned long flags; |
Naresh Kumar Lingagalla | ff508b4 | 2023-05-23 12:23:33 +0530 | [diff] [blame] | 1300 | u32 offset_local; |
Archana Sathyakumar | 8ff3ba6 | 2017-10-06 11:58:46 -0600 | [diff] [blame] | 1301 | |
| 1302 | offset = select_dir_conn_mux(d, &irq); |
| 1303 | if (offset < 0 || !parent_data) |
| 1304 | return; |
| 1305 | |
| 1306 | virt = irq_find_mapping(parent_data->domain, irq); |
| 1307 | msm_dirconn_cfg_reg(d, offset); |
| 1308 | irq_set_handler_data(virt, d); |
| 1309 | desc = irq_to_desc(virt); |
| 1310 | if (!desc) |
| 1311 | return; |
| 1312 | |
| 1313 | dir_conn_data = &(desc->irq_data); |
| 1314 | |
| 1315 | if (dir_conn_data) { |
Srinivas Rao L | d630298 | 2018-07-31 12:36:56 +0530 | [diff] [blame] | 1316 | |
| 1317 | pctrl = gpiochip_get_data(gc); |
| 1318 | if (pctrl->spi_cfg_regs) { |
| 1319 | spi_cfg_reg = pctrl->spi_cfg_regs + |
Raghavendra Kakarla | cd625c3 | 2018-10-10 11:47:43 +0530 | [diff] [blame] | 1320 | ((dir_conn_data->hwirq - 32) / 32) * 4; |
Naresh Kumar Lingagalla | ff508b4 | 2023-05-23 12:23:33 +0530 | [diff] [blame] | 1321 | offset_local = ((dir_conn_data->hwirq - 32) / 32) * 4; |
Srinivas Rao L | d630298 | 2018-07-31 12:36:56 +0530 | [diff] [blame] | 1322 | if (spi_cfg_reg < pctrl->spi_cfg_end) { |
| 1323 | spin_lock_irqsave(&pctrl->lock, flags); |
Naresh Kumar Lingagalla | ff508b4 | 2023-05-23 12:23:33 +0530 | [diff] [blame] | 1324 | val = readl_relaxed(pctrl->spi_base + |
| 1325 | offset_local); |
Srinivas Rao L | d630298 | 2018-07-31 12:36:56 +0530 | [diff] [blame] | 1326 | /* |
| 1327 | * Clear the respective bit for edge type |
| 1328 | * interrupt |
| 1329 | */ |
Raghavendra Kakarla | cd625c3 | 2018-10-10 11:47:43 +0530 | [diff] [blame] | 1330 | val &= ~(1 << ((dir_conn_data->hwirq - 32) |
| 1331 | % 32)); |
Naresh Kumar Lingagalla | ff508b4 | 2023-05-23 12:23:33 +0530 | [diff] [blame] | 1332 | writel_relaxed(val, pctrl->spi_base + |
| 1333 | offset_local); |
Srinivas Rao L | d630298 | 2018-07-31 12:36:56 +0530 | [diff] [blame] | 1334 | spin_unlock_irqrestore(&pctrl->lock, flags); |
| 1335 | } else |
| 1336 | pr_err("%s: type config failed for SPI: %lu\n", |
| 1337 | __func__, irq); |
| 1338 | } else |
| 1339 | pr_debug("%s: type config for SPI is not supported\n", |
| 1340 | __func__); |
| 1341 | |
Archana Sathyakumar | 8ff3ba6 | 2017-10-06 11:58:46 -0600 | [diff] [blame] | 1342 | if (dir_conn_data->chip && dir_conn_data->chip->irq_set_type) |
| 1343 | dir_conn_data->chip->irq_set_type(dir_conn_data, |
| 1344 | IRQ_TYPE_EDGE_RISING); |
| 1345 | if (dir_conn_data->chip && dir_conn_data->chip->irq_unmask) |
| 1346 | dir_conn_data->chip->irq_unmask(dir_conn_data); |
| 1347 | } |
| 1348 | } |
| 1349 | |
| 1350 | static void remove_dirconn_tlmm(struct irq_data *d, irq_hw_number_t irq) |
| 1351 | { |
| 1352 | struct irq_desc *desc = irq_data_to_desc(d); |
| 1353 | struct irq_data *parent_data = irq_get_irq_data(desc->parent_irq); |
| 1354 | struct irq_data *dir_conn_data = NULL; |
| 1355 | int offset = 0; |
| 1356 | unsigned int virt = 0; |
| 1357 | |
| 1358 | virt = irq_find_mapping(parent_data->domain, irq); |
| 1359 | msm_dirconn_uncfg_reg(d, offset); |
| 1360 | irq_set_handler_data(virt, NULL); |
| 1361 | desc = irq_to_desc(virt); |
| 1362 | if (!desc) |
| 1363 | return; |
| 1364 | |
| 1365 | dir_conn_data = &(desc->irq_data); |
| 1366 | |
| 1367 | if (dir_conn_data) { |
| 1368 | if (dir_conn_data->chip && dir_conn_data->chip->irq_mask) |
| 1369 | dir_conn_data->chip->irq_mask(dir_conn_data); |
| 1370 | } |
| 1371 | } |
| 1372 | |
Mahesh Sivasubramanian | fcc313e | 2017-04-10 09:05:59 -0600 | [diff] [blame] | 1373 | static int msm_dirconn_irq_set_type(struct irq_data *d, unsigned int type) |
| 1374 | { |
| 1375 | struct irq_desc *desc = irq_data_to_desc(d); |
| 1376 | struct irq_data *parent_data = irq_get_irq_data(desc->parent_irq); |
Srinivas Rao L | d630298 | 2018-07-31 12:36:56 +0530 | [diff] [blame] | 1377 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
Archana Sathyakumar | 8ff3ba6 | 2017-10-06 11:58:46 -0600 | [diff] [blame] | 1378 | irq_hw_number_t irq = 0; |
Srinivas Rao L | d630298 | 2018-07-31 12:36:56 +0530 | [diff] [blame] | 1379 | struct msm_pinctrl *pctrl; |
| 1380 | phys_addr_t spi_cfg_reg = 0; |
| 1381 | unsigned int config_val = 0; |
| 1382 | unsigned int val = 0; |
| 1383 | unsigned long flags; |
Naresh Kumar Lingagalla | ff508b4 | 2023-05-23 12:23:33 +0530 | [diff] [blame] | 1384 | u32 offset_local; |
Archana Sathyakumar | 8ff3ba6 | 2017-10-06 11:58:46 -0600 | [diff] [blame] | 1385 | |
| 1386 | if (!parent_data) |
| 1387 | return 0; |
| 1388 | |
Srinivas Rao L | d630298 | 2018-07-31 12:36:56 +0530 | [diff] [blame] | 1389 | pctrl = gpiochip_get_data(gc); |
| 1390 | |
Archana Sathyakumar | 5630a2e | 2017-11-02 15:24:20 -0600 | [diff] [blame] | 1391 | if (type == IRQ_TYPE_EDGE_BOTH) |
Archana Sathyakumar | 8ff3ba6 | 2017-10-06 11:58:46 -0600 | [diff] [blame] | 1392 | add_dirconn_tlmm(d, irq); |
Archana Sathyakumar | 5630a2e | 2017-11-02 15:24:20 -0600 | [diff] [blame] | 1393 | else if (is_gpio_dual_edge(d, &irq)) |
| 1394 | remove_dirconn_tlmm(d, irq); |
| 1395 | else if (is_gpio_tlmm_dc(d, type)) |
| 1396 | type = IRQ_TYPE_EDGE_RISING; |
Archana Sathyakumar | 8ff3ba6 | 2017-10-06 11:58:46 -0600 | [diff] [blame] | 1397 | |
Srinivas Rao L | d630298 | 2018-07-31 12:36:56 +0530 | [diff] [blame] | 1398 | /* |
| 1399 | * Shared SPI config for Edge is 0 and |
| 1400 | * for Level interrupt is 1 |
| 1401 | */ |
| 1402 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) { |
Archana Sathyakumar | 8ff3ba6 | 2017-10-06 11:58:46 -0600 | [diff] [blame] | 1403 | irq_set_handler_locked(d, handle_level_irq); |
Srinivas Rao L | d630298 | 2018-07-31 12:36:56 +0530 | [diff] [blame] | 1404 | config_val = 1; |
| 1405 | } else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
Archana Sathyakumar | 8ff3ba6 | 2017-10-06 11:58:46 -0600 | [diff] [blame] | 1406 | irq_set_handler_locked(d, handle_edge_irq); |
Mahesh Sivasubramanian | fcc313e | 2017-04-10 09:05:59 -0600 | [diff] [blame] | 1407 | |
Srinivas Rao L | d630298 | 2018-07-31 12:36:56 +0530 | [diff] [blame] | 1408 | if (pctrl->spi_cfg_regs && type != IRQ_TYPE_NONE) { |
| 1409 | spi_cfg_reg = pctrl->spi_cfg_regs + |
Raghavendra Kakarla | cd625c3 | 2018-10-10 11:47:43 +0530 | [diff] [blame] | 1410 | ((parent_data->hwirq - 32) / 32) * 4; |
Naresh Kumar Lingagalla | ff508b4 | 2023-05-23 12:23:33 +0530 | [diff] [blame] | 1411 | offset_local = ((parent_data->hwirq - 32) / 32) * 4; |
Srinivas Rao L | d630298 | 2018-07-31 12:36:56 +0530 | [diff] [blame] | 1412 | if (spi_cfg_reg < pctrl->spi_cfg_end) { |
| 1413 | spin_lock_irqsave(&pctrl->lock, flags); |
Naresh Kumar Lingagalla | ff508b4 | 2023-05-23 12:23:33 +0530 | [diff] [blame] | 1414 | val = readl_relaxed(pctrl->spi_base + offset_local); |
Raghavendra Kakarla | cd625c3 | 2018-10-10 11:47:43 +0530 | [diff] [blame] | 1415 | val &= ~(1 << ((parent_data->hwirq - 32) % 32)); |
Srinivas Rao L | d630298 | 2018-07-31 12:36:56 +0530 | [diff] [blame] | 1416 | if (config_val) |
Raghavendra Kakarla | cd625c3 | 2018-10-10 11:47:43 +0530 | [diff] [blame] | 1417 | val |= (1 << ((parent_data->hwirq - 32) % 32)); |
Naresh Kumar Lingagalla | ff508b4 | 2023-05-23 12:23:33 +0530 | [diff] [blame] | 1418 | writel_relaxed(val, pctrl->spi_base + offset_local); |
Srinivas Rao L | d630298 | 2018-07-31 12:36:56 +0530 | [diff] [blame] | 1419 | spin_unlock_irqrestore(&pctrl->lock, flags); |
| 1420 | } else |
| 1421 | pr_err("%s: type config failed for SPI: %lu\n", |
| 1422 | __func__, irq); |
| 1423 | } else |
| 1424 | pr_debug("%s: SPI type config is not supported\n", __func__); |
| 1425 | |
Mahesh Sivasubramanian | fcc313e | 2017-04-10 09:05:59 -0600 | [diff] [blame] | 1426 | if (parent_data->chip->irq_set_type) |
| 1427 | return parent_data->chip->irq_set_type(parent_data, type); |
| 1428 | |
| 1429 | return 0; |
| 1430 | } |
| 1431 | |
| 1432 | static struct irq_chip msm_dirconn_irq_chip = { |
| 1433 | .name = "msmgpio-dc", |
| 1434 | .irq_mask = msm_dirconn_irq_mask, |
Maulik Shah | e0a5583 | 2018-01-23 14:24:18 +0530 | [diff] [blame] | 1435 | .irq_enable = msm_dirconn_irq_enable, |
Mahesh Sivasubramanian | fcc313e | 2017-04-10 09:05:59 -0600 | [diff] [blame] | 1436 | .irq_unmask = msm_dirconn_irq_unmask, |
| 1437 | .irq_eoi = msm_dirconn_irq_eoi, |
| 1438 | .irq_ack = msm_dirconn_irq_ack, |
| 1439 | .irq_set_type = msm_dirconn_irq_set_type, |
| 1440 | .irq_set_affinity = msm_dirconn_irq_set_affinity, |
| 1441 | .irq_set_vcpu_affinity = msm_dirconn_irq_set_vcpu_affinity, |
| 1442 | .flags = IRQCHIP_SKIP_SET_WAKE |
| 1443 | | IRQCHIP_MASK_ON_SUSPEND |
| 1444 | | IRQCHIP_SET_TYPE_MASKED, |
| 1445 | }; |
| 1446 | |
Thomas Gleixner | bd0b9ac | 2015-09-14 10:42:37 +0200 | [diff] [blame] | 1447 | static void msm_gpio_irq_handler(struct irq_desc *desc) |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 1448 | { |
Linus Walleij | cdcb0ab | 2014-04-29 11:00:40 -0700 | [diff] [blame] | 1449 | struct gpio_chip *gc = irq_desc_get_handler_data(desc); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 1450 | const struct msm_pingroup *g; |
Linus Walleij | fded3f4 | 2015-12-08 09:49:18 +0100 | [diff] [blame] | 1451 | struct msm_pinctrl *pctrl = gpiochip_get_data(gc); |
Jiang Liu | 5663bb2 | 2015-06-04 12:13:16 +0800 | [diff] [blame] | 1452 | struct irq_chip *chip = irq_desc_get_chip(desc); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 1453 | int irq_pin; |
| 1454 | int handled = 0; |
Kyle Yan | 6c2752f | 2017-09-27 16:29:45 -0700 | [diff] [blame] | 1455 | u32 val; |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 1456 | int i; |
| 1457 | |
| 1458 | chained_irq_enter(chip, desc); |
| 1459 | |
| 1460 | /* |
Bjorn Andersson | 1f2b239 | 2013-12-14 23:01:51 -0800 | [diff] [blame] | 1461 | * Each pin has it's own IRQ status register, so use |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 1462 | * enabled_irq bitmap to limit the number of reads. |
| 1463 | */ |
| 1464 | for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) { |
| 1465 | g = &pctrl->soc->groups[i]; |
Kyle Yan | 6c2752f | 2017-09-27 16:29:45 -0700 | [diff] [blame] | 1466 | val = readl(pctrl->regs + g->intr_status_reg); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 1467 | if (val & BIT(g->intr_status_bit)) { |
Linus Walleij | cdcb0ab | 2014-04-29 11:00:40 -0700 | [diff] [blame] | 1468 | irq_pin = irq_find_mapping(gc->irqdomain, i); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 1469 | generic_handle_irq(irq_pin); |
| 1470 | handled++; |
| 1471 | } |
| 1472 | } |
| 1473 | |
Bjorn Andersson | 1f2b239 | 2013-12-14 23:01:51 -0800 | [diff] [blame] | 1474 | /* No interrupts were flagged */ |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 1475 | if (handled == 0) |
Thomas Gleixner | bd0b9ac | 2015-09-14 10:42:37 +0200 | [diff] [blame] | 1476 | handle_bad_irq(desc); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 1477 | |
| 1478 | chained_irq_exit(chip, desc); |
| 1479 | } |
| 1480 | |
Mahesh Sivasubramanian | fcc313e | 2017-04-10 09:05:59 -0600 | [diff] [blame] | 1481 | static void msm_gpio_setup_dir_connects(struct msm_pinctrl *pctrl) |
| 1482 | { |
| 1483 | struct device_node *parent_node; |
Archana Sathyakumar | 892c01c | 2017-10-31 13:47:20 -0600 | [diff] [blame] | 1484 | struct irq_domain *pdc_domain; |
Mahesh Sivasubramanian | fcc313e | 2017-04-10 09:05:59 -0600 | [diff] [blame] | 1485 | unsigned int i; |
| 1486 | |
| 1487 | parent_node = of_irq_find_parent(pctrl->dev->of_node); |
Mahesh Sivasubramanian | fcc313e | 2017-04-10 09:05:59 -0600 | [diff] [blame] | 1488 | if (!parent_node) |
| 1489 | return; |
| 1490 | |
Archana Sathyakumar | 892c01c | 2017-10-31 13:47:20 -0600 | [diff] [blame] | 1491 | pdc_domain = irq_find_host(parent_node); |
| 1492 | if (!pdc_domain) |
Mahesh Sivasubramanian | fcc313e | 2017-04-10 09:05:59 -0600 | [diff] [blame] | 1493 | return; |
| 1494 | |
Mahesh Sivasubramanian | fcc313e | 2017-04-10 09:05:59 -0600 | [diff] [blame] | 1495 | for (i = 0; i < pctrl->soc->n_dir_conns; i++) { |
| 1496 | const struct msm_dir_conn *dirconn = &pctrl->soc->dir_conn[i]; |
Archana Sathyakumar | 5630a2e | 2017-11-02 15:24:20 -0600 | [diff] [blame] | 1497 | struct irq_data *d; |
Mahesh Sivasubramanian | fcc313e | 2017-04-10 09:05:59 -0600 | [diff] [blame] | 1498 | |
Archana Sathyakumar | 892c01c | 2017-10-31 13:47:20 -0600 | [diff] [blame] | 1499 | request_dc_interrupt(pctrl->chip.irqdomain, pdc_domain, |
| 1500 | dirconn->hwirq, dirconn->gpio); |
Archana Sathyakumar | 5630a2e | 2017-11-02 15:24:20 -0600 | [diff] [blame] | 1501 | |
| 1502 | if (!dirconn->gpio) |
| 1503 | continue; |
| 1504 | |
| 1505 | if (!dirconn->tlmm_dc) |
| 1506 | continue; |
| 1507 | |
| 1508 | /* |
| 1509 | * If the gpio is routed through TLMM direct connect interrupts, |
| 1510 | * program the TLMM registers for this setup. |
| 1511 | */ |
| 1512 | d = irq_get_irq_data(irq_find_mapping(pctrl->chip.irqdomain, |
| 1513 | dirconn->gpio)); |
| 1514 | if (!d) |
| 1515 | continue; |
| 1516 | |
| 1517 | msm_dirconn_cfg_reg(d, pctrl->soc->dir_conn_irq_base |
| 1518 | - (u32)dirconn->hwirq); |
Archana Sathyakumar | 892c01c | 2017-10-31 13:47:20 -0600 | [diff] [blame] | 1519 | } |
Mahesh Sivasubramanian | fcc313e | 2017-04-10 09:05:59 -0600 | [diff] [blame] | 1520 | |
Archana Sathyakumar | 892c01c | 2017-10-31 13:47:20 -0600 | [diff] [blame] | 1521 | for (i = 0; i < pctrl->soc->n_pdc_mux_out; i++) { |
| 1522 | struct msm_pdc_mux_output *pdc_out = |
| 1523 | &pctrl->soc->pdc_mux_out[i]; |
Mahesh Sivasubramanian | fcc313e | 2017-04-10 09:05:59 -0600 | [diff] [blame] | 1524 | |
Archana Sathyakumar | 892c01c | 2017-10-31 13:47:20 -0600 | [diff] [blame] | 1525 | request_dc_interrupt(pctrl->chip.irqdomain, pdc_domain, |
| 1526 | pdc_out->hwirq, 0); |
| 1527 | } |
| 1528 | |
| 1529 | /* |
| 1530 | * Statically choose the GPIOs for mapping to PDC. Dynamic mux mapping |
| 1531 | * is very difficult. |
| 1532 | */ |
Maulik Shah | f166e3f | 2018-08-06 17:27:12 +0530 | [diff] [blame] | 1533 | for (i = 0; i < pctrl->soc->n_gpio_mux_in; i++) { |
Archana Sathyakumar | 892c01c | 2017-10-31 13:47:20 -0600 | [diff] [blame] | 1534 | unsigned int irq; |
| 1535 | struct irq_data *d; |
| 1536 | struct msm_gpio_mux_input *gpio_in = |
| 1537 | &pctrl->soc->gpio_mux_in[i]; |
| 1538 | if (!gpio_in->init) |
| 1539 | continue; |
| 1540 | |
| 1541 | irq = irq_find_mapping(pctrl->chip.irqdomain, gpio_in->gpio); |
| 1542 | d = irq_get_irq_data(irq); |
| 1543 | if (!d) |
| 1544 | continue; |
| 1545 | |
| 1546 | gpio_muxed_to_pdc(pdc_domain, d); |
Mahesh Sivasubramanian | fcc313e | 2017-04-10 09:05:59 -0600 | [diff] [blame] | 1547 | } |
| 1548 | } |
| 1549 | |
Raju P.L.S.S.S.N | cdcd769 | 2017-11-30 19:06:30 +0530 | [diff] [blame] | 1550 | static int msm_gpiochip_to_irq(struct gpio_chip *chip, unsigned int offset) |
| 1551 | { |
Raghavendra Kakarla | 0e77a9e | 2018-03-07 21:30:45 +0530 | [diff] [blame] | 1552 | struct irq_fwspec fwspec; |
Raghavendra Kakarla | 882117f | 2018-08-21 16:24:01 +0530 | [diff] [blame] | 1553 | struct irq_domain *domain = chip->irqdomain; |
| 1554 | int virq; |
| 1555 | |
| 1556 | virq = irq_find_mapping(domain, offset); |
| 1557 | if (virq) |
| 1558 | return virq; |
Raghavendra Kakarla | 0e77a9e | 2018-03-07 21:30:45 +0530 | [diff] [blame] | 1559 | |
| 1560 | fwspec.fwnode = of_node_to_fwnode(chip->of_node); |
| 1561 | fwspec.param[0] = offset; |
| 1562 | fwspec.param[1] = IRQ_TYPE_NONE; |
| 1563 | fwspec.param_count = 2; |
| 1564 | |
| 1565 | return irq_create_fwspec_mapping(&fwspec); |
Raju P.L.S.S.S.N | cdcd769 | 2017-11-30 19:06:30 +0530 | [diff] [blame] | 1566 | } |
| 1567 | |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 1568 | static int msm_gpio_init(struct msm_pinctrl *pctrl) |
| 1569 | { |
| 1570 | struct gpio_chip *chip; |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 1571 | int ret; |
Stephen Boyd | dcd278b | 2014-03-06 22:44:41 -0800 | [diff] [blame] | 1572 | unsigned ngpio = pctrl->soc->ngpios; |
Raghavendra Kakarla | 0e77a9e | 2018-03-07 21:30:45 +0530 | [diff] [blame] | 1573 | struct device_node *irq_parent = NULL; |
Raju P.L.S.S.S.N | cdcd769 | 2017-11-30 19:06:30 +0530 | [diff] [blame] | 1574 | struct irq_domain *domain_parent; |
Stephen Boyd | dcd278b | 2014-03-06 22:44:41 -0800 | [diff] [blame] | 1575 | |
| 1576 | if (WARN_ON(ngpio > MAX_NR_GPIO)) |
| 1577 | return -EINVAL; |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 1578 | |
| 1579 | chip = &pctrl->chip; |
| 1580 | chip->base = 0; |
Stephen Boyd | dcd278b | 2014-03-06 22:44:41 -0800 | [diff] [blame] | 1581 | chip->ngpio = ngpio; |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 1582 | chip->label = dev_name(pctrl->dev); |
Linus Walleij | 58383c7 | 2015-11-04 09:56:26 +0100 | [diff] [blame] | 1583 | chip->parent = pctrl->dev; |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 1584 | chip->owner = THIS_MODULE; |
| 1585 | chip->of_node = pctrl->dev->of_node; |
| 1586 | |
Linus Walleij | fded3f4 | 2015-12-08 09:49:18 +0100 | [diff] [blame] | 1587 | ret = gpiochip_add_data(&pctrl->chip, pctrl); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 1588 | if (ret) { |
| 1589 | dev_err(pctrl->dev, "Failed register gpiochip\n"); |
| 1590 | return ret; |
| 1591 | } |
| 1592 | |
Christian Lamparter | 43b0861 | 2018-05-21 22:57:37 +0200 | [diff] [blame] | 1593 | /* |
| 1594 | * For DeviceTree-supported systems, the gpio core checks the |
| 1595 | * pinctrl's device node for the "gpio-ranges" property. |
| 1596 | * If it is present, it takes care of adding the pin ranges |
| 1597 | * for the driver. In this case the driver can skip ahead. |
| 1598 | * |
| 1599 | * In order to remain compatible with older, existing DeviceTree |
| 1600 | * files which don't set the "gpio-ranges" property or systems that |
| 1601 | * utilize ACPI the driver has to call gpiochip_add_pin_range(). |
| 1602 | */ |
| 1603 | if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) { |
| 1604 | ret = gpiochip_add_pin_range(&pctrl->chip, |
| 1605 | dev_name(pctrl->dev), 0, 0, chip->ngpio); |
| 1606 | if (ret) { |
| 1607 | dev_err(pctrl->dev, "Failed to add pin range\n"); |
| 1608 | gpiochip_remove(&pctrl->chip); |
| 1609 | return ret; |
| 1610 | } |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 1611 | } |
| 1612 | |
Raghavendra Kakarla | 0e77a9e | 2018-03-07 21:30:45 +0530 | [diff] [blame] | 1613 | irq_parent = of_irq_find_parent(chip->of_node); |
| 1614 | if (of_device_is_compatible(irq_parent, "qcom,mpm-gpio")) { |
| 1615 | chip->irqchip = &msm_gpio_irq_chip; |
| 1616 | chip->irq_handler = handle_fasteoi_irq; |
| 1617 | chip->irq_default_type = IRQ_TYPE_NONE; |
| 1618 | chip->to_irq = msm_gpiochip_to_irq; |
| 1619 | chip->lock_key = NULL; |
| 1620 | domain_parent = irq_find_host(irq_parent); |
| 1621 | if (!domain_parent) { |
| 1622 | pr_err("unable to find parent domain\n"); |
| 1623 | gpiochip_remove(&pctrl->chip); |
| 1624 | return -ENXIO; |
| 1625 | } |
Raju P.L.S.S.S.N | cdcd769 | 2017-11-30 19:06:30 +0530 | [diff] [blame] | 1626 | |
Raghavendra Kakarla | 0e77a9e | 2018-03-07 21:30:45 +0530 | [diff] [blame] | 1627 | chip->irqdomain = irq_domain_add_hierarchy(domain_parent, 0, |
Raju P.L.S.S.S.N | cdcd769 | 2017-11-30 19:06:30 +0530 | [diff] [blame] | 1628 | chip->ngpio, |
| 1629 | chip->of_node, |
| 1630 | &msm_gpio_domain_ops, |
| 1631 | chip); |
Raghavendra Kakarla | 0e77a9e | 2018-03-07 21:30:45 +0530 | [diff] [blame] | 1632 | if (!chip->irqdomain) { |
| 1633 | dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n"); |
| 1634 | chip->irqchip = NULL; |
| 1635 | gpiochip_remove(&pctrl->chip); |
| 1636 | return -ENXIO; |
| 1637 | } |
| 1638 | } else { |
| 1639 | ret = gpiochip_irqchip_add(chip, |
| 1640 | &msm_gpio_irq_chip, |
| 1641 | 0, |
| 1642 | handle_fasteoi_irq, |
| 1643 | IRQ_TYPE_NONE); |
| 1644 | if (ret) { |
| 1645 | dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n"); |
| 1646 | gpiochip_remove(&pctrl->chip); |
| 1647 | return ret; |
| 1648 | } |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 1649 | } |
Raju P.L.S.S.S.N | cdcd769 | 2017-11-30 19:06:30 +0530 | [diff] [blame] | 1650 | gpiochip_set_chained_irqchip(chip, &msm_gpio_irq_chip, |
| 1651 | pctrl->irq, msm_gpio_irq_handler); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 1652 | |
Mahesh Sivasubramanian | fcc313e | 2017-04-10 09:05:59 -0600 | [diff] [blame] | 1653 | msm_gpio_setup_dir_connects(pctrl); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 1654 | return 0; |
| 1655 | } |
| 1656 | |
Josh Cartwright | cf1fc18 | 2014-09-23 15:59:53 -0500 | [diff] [blame] | 1657 | static int msm_ps_hold_restart(struct notifier_block *nb, unsigned long action, |
| 1658 | void *data) |
Pramod Gurav | 3274558 | 2014-08-29 20:00:59 +0530 | [diff] [blame] | 1659 | { |
Josh Cartwright | cf1fc18 | 2014-09-23 15:59:53 -0500 | [diff] [blame] | 1660 | struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb); |
| 1661 | |
| 1662 | writel(0, pctrl->regs + PS_HOLD_OFFSET); |
| 1663 | mdelay(1000); |
| 1664 | return NOTIFY_DONE; |
Pramod Gurav | 3274558 | 2014-08-29 20:00:59 +0530 | [diff] [blame] | 1665 | } |
| 1666 | |
Stephen Boyd | ad64498 | 2015-07-06 18:09:30 -0700 | [diff] [blame] | 1667 | static struct msm_pinctrl *poweroff_pctrl; |
| 1668 | |
| 1669 | static void msm_ps_hold_poweroff(void) |
| 1670 | { |
| 1671 | msm_ps_hold_restart(&poweroff_pctrl->restart_nb, 0, NULL); |
| 1672 | } |
| 1673 | |
Pramod Gurav | 3274558 | 2014-08-29 20:00:59 +0530 | [diff] [blame] | 1674 | static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl) |
| 1675 | { |
Stephen Boyd | bcd53f8 | 2015-01-19 11:17:45 +0100 | [diff] [blame] | 1676 | int i; |
Pramod Gurav | 3274558 | 2014-08-29 20:00:59 +0530 | [diff] [blame] | 1677 | const struct msm_function *func = pctrl->soc->functions; |
| 1678 | |
Stephen Boyd | bcd53f8 | 2015-01-19 11:17:45 +0100 | [diff] [blame] | 1679 | for (i = 0; i < pctrl->soc->nfunctions; i++) |
Pramod Gurav | 3274558 | 2014-08-29 20:00:59 +0530 | [diff] [blame] | 1680 | if (!strcmp(func[i].name, "ps_hold")) { |
Josh Cartwright | cf1fc18 | 2014-09-23 15:59:53 -0500 | [diff] [blame] | 1681 | pctrl->restart_nb.notifier_call = msm_ps_hold_restart; |
| 1682 | pctrl->restart_nb.priority = 128; |
| 1683 | if (register_restart_handler(&pctrl->restart_nb)) |
| 1684 | dev_err(pctrl->dev, |
| 1685 | "failed to setup restart handler.\n"); |
Stephen Boyd | ad64498 | 2015-07-06 18:09:30 -0700 | [diff] [blame] | 1686 | poweroff_pctrl = pctrl; |
| 1687 | pm_power_off = msm_ps_hold_poweroff; |
Josh Cartwright | cf1fc18 | 2014-09-23 15:59:53 -0500 | [diff] [blame] | 1688 | break; |
Pramod Gurav | 3274558 | 2014-08-29 20:00:59 +0530 | [diff] [blame] | 1689 | } |
| 1690 | } |
Pramod Gurav | 3274558 | 2014-08-29 20:00:59 +0530 | [diff] [blame] | 1691 | |
Maria Yu | 2af63b2 | 2018-03-29 17:34:28 +0800 | [diff] [blame] | 1692 | #ifdef CONFIG_PM |
| 1693 | static int msm_pinctrl_suspend(void) |
| 1694 | { |
| 1695 | return 0; |
| 1696 | } |
| 1697 | |
| 1698 | static void msm_pinctrl_resume(void) |
| 1699 | { |
| 1700 | int i, irq; |
| 1701 | u32 val; |
| 1702 | unsigned long flags; |
| 1703 | struct irq_desc *desc; |
| 1704 | const struct msm_pingroup *g; |
| 1705 | const char *name = "null"; |
| 1706 | struct msm_pinctrl *pctrl = msm_pinctrl_data; |
| 1707 | |
| 1708 | if (!msm_show_resume_irq_mask) |
| 1709 | return; |
| 1710 | |
| 1711 | spin_lock_irqsave(&pctrl->lock, flags); |
| 1712 | for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) { |
| 1713 | g = &pctrl->soc->groups[i]; |
| 1714 | val = readl_relaxed(pctrl->regs + g->intr_status_reg); |
| 1715 | if (val & BIT(g->intr_status_bit)) { |
| 1716 | irq = irq_find_mapping(pctrl->chip.irqdomain, i); |
| 1717 | desc = irq_to_desc(irq); |
| 1718 | if (desc == NULL) |
| 1719 | name = "stray irq"; |
| 1720 | else if (desc->action && desc->action->name) |
| 1721 | name = desc->action->name; |
| 1722 | |
| 1723 | pr_warn("%s: %d triggered %s\n", __func__, irq, name); |
| 1724 | } |
| 1725 | } |
| 1726 | spin_unlock_irqrestore(&pctrl->lock, flags); |
| 1727 | } |
| 1728 | #else |
| 1729 | #define msm_pinctrl_suspend NULL |
| 1730 | #define msm_pinctrl_resume NULL |
| 1731 | #endif |
| 1732 | |
| 1733 | static struct syscore_ops msm_pinctrl_pm_ops = { |
| 1734 | .suspend = msm_pinctrl_suspend, |
| 1735 | .resume = msm_pinctrl_resume, |
| 1736 | }; |
| 1737 | |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 1738 | int msm_pinctrl_probe(struct platform_device *pdev, |
| 1739 | const struct msm_pinctrl_soc_data *soc_data) |
| 1740 | { |
| 1741 | struct msm_pinctrl *pctrl; |
| 1742 | struct resource *res; |
| 1743 | int ret; |
Srinivas Rao L | d630298 | 2018-07-31 12:36:56 +0530 | [diff] [blame] | 1744 | char *key; |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 1745 | |
Maria Yu | 2af63b2 | 2018-03-29 17:34:28 +0800 | [diff] [blame] | 1746 | msm_pinctrl_data = pctrl = devm_kzalloc(&pdev->dev, |
| 1747 | sizeof(*pctrl), GFP_KERNEL); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 1748 | if (!pctrl) { |
| 1749 | dev_err(&pdev->dev, "Can't allocate msm_pinctrl\n"); |
| 1750 | return -ENOMEM; |
| 1751 | } |
| 1752 | pctrl->dev = &pdev->dev; |
| 1753 | pctrl->soc = soc_data; |
| 1754 | pctrl->chip = msm_gpio_template; |
| 1755 | |
| 1756 | spin_lock_init(&pctrl->lock); |
| 1757 | |
Srinivas Rao L | d630298 | 2018-07-31 12:36:56 +0530 | [diff] [blame] | 1758 | key = "pinctrl_regs"; |
| 1759 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, key); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 1760 | pctrl->regs = devm_ioremap_resource(&pdev->dev, res); |
| 1761 | if (IS_ERR(pctrl->regs)) |
| 1762 | return PTR_ERR(pctrl->regs); |
| 1763 | |
Srinivas Rao L | d630298 | 2018-07-31 12:36:56 +0530 | [diff] [blame] | 1764 | key = "pdc_regs"; |
| 1765 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, key); |
Archana Sathyakumar | 892c01c | 2017-10-31 13:47:20 -0600 | [diff] [blame] | 1766 | pctrl->pdc_regs = devm_ioremap_resource(&pdev->dev, res); |
| 1767 | |
Srinivas Rao L | d630298 | 2018-07-31 12:36:56 +0530 | [diff] [blame] | 1768 | key = "spi_cfg_regs"; |
| 1769 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, key); |
| 1770 | if (res) { |
| 1771 | pctrl->spi_cfg_regs = res->start; |
| 1772 | pctrl->spi_cfg_end = res->end; |
| 1773 | } |
| 1774 | |
Pramod Gurav | 3274558 | 2014-08-29 20:00:59 +0530 | [diff] [blame] | 1775 | msm_pinctrl_setup_pm_reset(pctrl); |
| 1776 | |
Bjorn Andersson | f393e48 | 2013-12-14 23:01:52 -0800 | [diff] [blame] | 1777 | pctrl->irq = platform_get_irq(pdev, 0); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 1778 | if (pctrl->irq < 0) { |
| 1779 | dev_err(&pdev->dev, "No interrupt defined for msmgpio\n"); |
| 1780 | return pctrl->irq; |
| 1781 | } |
| 1782 | |
| 1783 | msm_pinctrl_desc.name = dev_name(&pdev->dev); |
| 1784 | msm_pinctrl_desc.pins = pctrl->soc->pins; |
| 1785 | msm_pinctrl_desc.npins = pctrl->soc->npins; |
Laxman Dewangan | fe0267f | 2016-02-24 14:44:07 +0530 | [diff] [blame] | 1786 | pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &msm_pinctrl_desc, |
| 1787 | pctrl); |
Masahiro Yamada | 323de9e | 2015-06-09 13:01:16 +0900 | [diff] [blame] | 1788 | if (IS_ERR(pctrl->pctrl)) { |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 1789 | dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); |
Masahiro Yamada | 323de9e | 2015-06-09 13:01:16 +0900 | [diff] [blame] | 1790 | return PTR_ERR(pctrl->pctrl); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 1791 | } |
| 1792 | |
| 1793 | ret = msm_gpio_init(pctrl); |
Laxman Dewangan | fe0267f | 2016-02-24 14:44:07 +0530 | [diff] [blame] | 1794 | if (ret) |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 1795 | return ret; |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 1796 | |
| 1797 | platform_set_drvdata(pdev, pctrl); |
| 1798 | |
Maria Yu | 2af63b2 | 2018-03-29 17:34:28 +0800 | [diff] [blame] | 1799 | register_syscore_ops(&msm_pinctrl_pm_ops); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 1800 | dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n"); |
| 1801 | |
| 1802 | return 0; |
| 1803 | } |
| 1804 | EXPORT_SYMBOL(msm_pinctrl_probe); |
| 1805 | |
| 1806 | int msm_pinctrl_remove(struct platform_device *pdev) |
| 1807 | { |
| 1808 | struct msm_pinctrl *pctrl = platform_get_drvdata(pdev); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 1809 | |
Linus Walleij | 2fcea6c | 2014-09-16 15:05:41 -0700 | [diff] [blame] | 1810 | gpiochip_remove(&pctrl->chip); |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 1811 | |
Josh Cartwright | cf1fc18 | 2014-09-23 15:59:53 -0500 | [diff] [blame] | 1812 | unregister_restart_handler(&pctrl->restart_nb); |
Maria Yu | 2af63b2 | 2018-03-29 17:34:28 +0800 | [diff] [blame] | 1813 | unregister_syscore_ops(&msm_pinctrl_pm_ops); |
Josh Cartwright | cf1fc18 | 2014-09-23 15:59:53 -0500 | [diff] [blame] | 1814 | |
Bjorn Andersson | f365be0 | 2013-12-05 18:10:03 -0800 | [diff] [blame] | 1815 | return 0; |
| 1816 | } |
| 1817 | EXPORT_SYMBOL(msm_pinctrl_remove); |
| 1818 | |