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gerrit-public.fairphone.software / kernel / msm-4.9 / 12d217c795071bfee483158e1397c57e8dc3cb76 / drivers / gpu / drm / i915 / i915_reg.h
  1. e3b95f1 drm/i915: Apply OCD to data/link m/n register #defines by Daniel Vetter · 11 years ago
  2. 275f01b2 drm/i915: PCH_ prefix for transcoder timings by Daniel Vetter · 11 years ago
  3. ab9412b drm/i915: s/TRANSCONF/PCH_TRANSCONF/ by Daniel Vetter · 11 years ago
  4. 17aa6be drm/i915: simplify DP/DDI port width macros by Daniel Vetter · 11 years ago
  5. 1bd1bd8 drm/i915: hw state readout support for pipe timings by Daniel Vetter · 11 years ago
  6. 7241920 drm/i915: hw state readout support for fdi m/n by Daniel Vetter · 11 years ago
  7. 627eb5a drm/i915: hw state readout support for pipe_config->fdi_lanes by Daniel Vetter · 11 years ago
  8. 35ffda4 drm/i915: hsw backlight registers need transcoder instead of pipe by Jani Nikula · 11 years ago
  9. 29a397b drm/i915: Move the CSC_MODE bits next to the register by Ville Syrjälä · 11 years ago
  10. de032bf drm/i915: print Gen5+ CPU/PCH poison interrupts by Paulo Zanoni · 11 years ago
  11. 8664281 drm/i915: report Gen5+ CPU and PCH FIFO underruns by Paulo Zanoni · 11 years ago
  12. 598fac6 drm/i915: magic VLV PLL registers in the dpio sideband by Daniel Vetter · 11 years ago
  13. 0a073b8 drm/i915: turbo & RC6 support for VLV v7 by Jesse Barnes · 11 years ago
  14. dc4bd2d drm/i915: preserve the PBC bits of TRANS_CHICKEN2 by Paulo Zanoni · 11 years ago
  15. 3f704fa drm/i915: set CPT FDI RX polarity bits based on VBT by Paulo Zanoni · 11 years ago
  16. 3ebecd0 drm/i915: Scale ring, rather than ia, frequency on Haswell by Chris Wilson · 11 years ago
  17. 3a06247 drm/i915: Increase max fence pitch limit to 256KB on IVB+ by Ville Syrjälä · 11 years ago
  18. a6f429a drm/i915: Configure GAM_ECOCHK appropriatly for Gen7 by Ville Syrjälä · 11 years ago
  19. 3b9d788 drm/i915: Add ECOBITS_SNB_BIT by Ville Syrjälä · 11 years ago
  20. 88a2b2a drm/i915: Don't wait for PCH on reset by Ben Widawsky · 11 years ago
  21. a0e4e19 drm/i915: add Punit read/write routines for VLV v2 by Jesse Barnes · 11 years ago
  22. 453c542 drm/i915: panel power sequencing for VLV eDP v2 by Jesse Barnes · 11 years ago
  23. 7f1f385 drm/i915: sprite support for ValleyView v4 by Jesse Barnes · 11 years ago
  24. 8a5c2ae drm/i915: fix ILK GPU reset for render by Jesse Barnes · 11 years ago
  25. 73c352a drm/i915: wire up SDVO hpd support on cpt/ppt by Daniel Vetter · 11 years ago
  26. e5868a3 DRM/i915: Convert HPD interrupts to make use of HPD pin assignment in encoders (v2) by Egbert Eich · 11 years ago
  27. 92bd1bf drm/i915: HSW PM Frequency bits fix by Rodrigo Vivi · 11 years ago
  28. e3dff58 drm/i915: Implement WaSwitchSolVfFArbitrationPriority by Ben Widawsky · 11 years ago
  29. 12569ad drm/i915: DSPFW and BLC regs are in the display offset range by Jesse Barnes · 11 years ago
  30. ed5de39 drm/i915: add media well to VLV force wake routines v2 by Jesse Barnes · 11 years ago
  31. 0d4a42f Merge tag 'v3.9-rc3' into drm-intel-next-queued by Daniel Vetter · 11 years ago
  32. d62b489 drm/i915: allow force wake at init time on VLV v2 by Jesse Barnes · 11 years ago
  33. 60222c0 drm/i915: Fix incorrect definition of ADPA HSYNC and VSYNC bits by Patrik Jakobsson · 11 years ago
  34. 4f3a8bc drm/i915: rename some HDMI bit definitions by Paulo Zanoni · 12 years ago
  35. dc0fa71 drm/i915: remove duplicated SDVO/HDMI bit definitions by Paulo Zanoni · 12 years ago
  36. c20cd31 drm/i915: unify the definitions of the HDMI/SDVO register by Paulo Zanoni · 12 years ago
  37. e2debe9 drm/i915: clarify confusion between SDVO and HDMI registers by Paulo Zanoni · 12 years ago
  38. 7d9bceb drm/i915: Use cpu_transcoder for HSW_TVIDEO_DIP_* instead of pipe by Rodrigo Vivi · 11 years ago
  39. 90a72f8 drm/i915: Refactor gen2 to gen4 vblank interrupt handling by Ville Syrjälä · 12 years ago
  40. 3f1e109 drm/i915: use FPGA_DBG for the "unclaimed register" checks by Paulo Zanoni · 12 years ago
  41. 86d3efc drm/i915: Implement pipe CSC based limited range RGB output by Ville Syrjälä · 12 years ago
  42. b9e1faa drm/i915: Fix PIPE_CONTROL DW/QW write through global GTT on IVB+ by Ville Syrjälä · 12 years ago
  43. 876a8cd drm/i915: Preserve the DDI link reversal configuration by Damien Lespiau · 12 years ago
  44. 3e68320 drm/i915: Preserve the FDI line reversal override bit on CPT by Damien Lespiau · 12 years ago
  45. 1d7aaa0 drm/i915: detect wrong MCH watermark values by Daniel Vetter · 12 years ago
  46. 26739f1 drm/i915: unify HDMI/DP hpd definitions by Daniel Vetter · 12 years ago
  47. 7083e05 drm/i915: Fix RC6VIDS encode/decode by Ben Widawsky · 12 years ago
  48. 6dc1c49 Merge branch 'fbcon-locking-fixes' of ssh://people.freedesktop.org/~airlied/linux into drm-next by Dave Airlie · 12 years ago
  49. 766aa1c drm/i915: Introduce i915_vgacntrl_reg() by Ville Syrjälä · 12 years ago
  50. f82855d drm/i915: Fix CAGF for HSW by Ben Widawsky · 12 years ago
  51. 41c0b3a drm/i915: Implement WaVSRefCountFullforceMissDisable by Ben Widawsky · 12 years ago
  52. fa42e23 drm/i915: fix intel_init_power_wells by Paulo Zanoni · 12 years ago
  53. 80a75f7 drm/i915: SWF screatch registers need an offset on VLV by Ville Syrjälä · 12 years ago
  54. 56a12a5 drm/i915: Include display_mmio_offset in sequencer index/data registers by Ville Syrjälä · 12 years ago
  55. fc2de40 drm/i915: PLL registers need an offset on VLV by Ville Syrjälä · 12 years ago
  56. 54d9d49 drm/i915: DPIO registers are VLV only and need an offset by Ville Syrjälä · 12 years ago
  57. ff76301 drm/i915: Spell out VLV_DISPLAY_BASE for interrupt registers by Ville Syrjälä · 12 years ago
  58. 07ec7ec drm/i915: Make VLV_GUNIT_CLOCK_GATE register value more readable by Ville Syrjälä · 12 years ago
  59. d88b227 drm/i915: FB_BLC_SELF_VLV is VLV only and needs an offset by Ville Syrjälä · 12 years ago
  60. 4b05998 drm/i915: Pipe palette registers need an offset on VLV by Ville Syrjälä · 12 years ago
  61. 4e8e7eb drm/i915: Pipe timing registers need an offset on VLV by Ville Syrjälä · 12 years ago
  62. 67d62c5 drm/i915: PORT_HOTPLUG registers need an offset on VLV by Ville Syrjälä · 12 years ago
  63. 7e470ab drm/i915: Panel fitter registers need an offset on VLV by Ville Syrjälä · 12 years ago
  64. b41fbda drm/i915: DPFLIPSTAT and DPINVGTT registers are VLV only and need an offset by Ville Syrjälä · 12 years ago
  65. 90f7da3 drm/i915: DSPFW registers need an offset on VLV by Ville Syrjälä · 12 years ago
  66. 8f6d8ee drm/i915: VLV_DDL is VLV only and needs an offset by Ville Syrjälä · 12 years ago
  67. 9dc33f3 drm/i915: Cursor registers need an offset on VLV by Ville Syrjälä · 12 years ago
  68. 0c3870e drm/i915: Pipe registers need an offset on VLV by Ville Syrjälä · 12 years ago
  69. 895abf0 drm/i915: Primary plane registers need an offset on VLV by Ville Syrjälä · 12 years ago
  70. aab1713 drm/i915: PIPE M/N registers need an offset on VLV by Ville Syrjälä · 12 years ago
  71. b906487 drm/i915: VLV_VIDEO_DIP_CTL is for VLV only by Ville Syrjälä · 12 years ago
  72. f12c47b drm/i915: Per-pipe PP registers are for VLV only by Ville Syrjälä · 12 years ago
  73. f4ba9f8 drm/i915: AUD_VID_DID needs an offset on VLV by Ville Syrjälä · 12 years ago
  74. 1c8c38c drm/i915: Disable AsyncFlip performance optimisations by Chris Wilson · 12 years ago
  75. 3685a8f drm/i915: Fix RGB color range property for PCH platforms by Ville Syrjälä · 12 years ago
  76. c70af1e drm/i915: Fix SPRITE0_FLIP_DONE_INT_EN_VLV and SPRITE0_FLIPDONE_INT_STATUS_VLV by Ville Syrjälä · 12 years ago
  77. b5cc6c0 Merge tag 'drm-intel-next-2012-12-21' of git://people.freedesktop.org/~danvet/drm-intel into drm-next by Dave Airlie · 12 years ago
  78. 0f3b684 drm/i915: Record DERRMR, FORCEWAKE and RING_CTL in error-state by Chris Wilson · 12 years ago
  79. 6547fbd drm/i915: Implement WaSetupGtModeTdRowDispatch by Daniel Vetter · 12 years ago
  80. 4283908 drm/i915: Implement WaDisableHiZPlanesWhenMSAAEnabled by Daniel Vetter · 12 years ago
  81. dfd07d7 drm/i915: clean up PIPECONF bpc #defines by Daniel Vetter · 12 years ago
  82. b696519 drm/i915: Cleanup SHOTPLUG_CTL status bits definitions by Damien Lespiau · 12 years ago
  83. 68d18ad drm/i915: set the LPT FDI RX polarity reversal bit when needed by Paulo Zanoni · 12 years ago
  84. dde86e2 drm/i915: add lpt_init_pch_refclk by Paulo Zanoni · 12 years ago
  85. 988d6ee drm/i915: add support for mPHY destination on intel_sbi_{read, write} by Paulo Zanoni · 12 years ago
  86. 6ef6a45 drm/i915: Remove duplicate and unused register #defines in i915_reg.h by Dexuan Cui · 12 years ago
  87. f930ddd drm/i915: remove duplicate register #defines by Daniel Vetter · 12 years ago
  88. 13888d7 drm/i915: make the panel fitter work on pipes B and C on IVB by Paulo Zanoni · 12 years ago
  89. 79935fc drm/i915: don't intel_crt_init if DDI A has 4 lanes by Paulo Zanoni · 12 years ago
  90. 17a303e drm/i915: make DP work on LPT-LP machines by Paulo Zanoni · 12 years ago
  91. 26b1ff3 drm/i915: Move the remaining gtt code by Ben Widawsky · 12 years ago
  92. 0f9b91c drm/i915: flush system agent TLBs on SNB by Ben Widawsky · 12 years ago
  93. 03752f5 drm/i915: Calculate correct stolen size for GEN7+ by Ben Widawsky · 12 years ago
  94. e76e9ae drm/i915: Stop using AGP layer for GEN6+ by Ben Widawsky · 12 years ago
  95. 9a28977 drm/i915: TLB invalidation with MI_FLUSH_DW requires a post-sync op v3 by Jesse Barnes · 12 years ago
  96. 12f3382 drm/i915: implement WaDisablePSDDualDispatchEnable on IVB & VLV by Jesse Barnes · 12 years ago
  97. 2d80957 drm/i915: implement WaDisableVLVClockGating_VBIIssue on VLV by Jesse Barnes · 12 years ago
  98. 8ab4397 drm/i915: implement WaDisableDopClockGatingisable on VLV and IVB by Jesse Barnes · 12 years ago
  99. d0cf5ea drm/i915: implement WaDisableL3CacheAging on VLV by Jesse Barnes · 12 years ago
  100. 0494564 drm/i915: fix Haswell FDI link training code by Paulo Zanoni · 12 years ago