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gerrit-public.fairphone.software / kernel / msm-4.9 / f0f59a00a1c9be11038bef5aa735ed7dd985f9cf / drivers
  1. f0f59a0 drm/i915: Type safe register read/write by Ville Syrjälä · 9 years ago
  2. 9bca5d0 drm/i915: Add missing ')' to SKL_PS_ECC_STAT define by Ville Syrjälä · 9 years ago
  3. 0670c5a drm/i915: Add 'offset' to uncore funcs by Ville Syrjälä · 9 years ago
  4. 8a74db7 drm/i915: Pull the vgpu uncore funcs apart from the rest of gen6+ by Ville Syrjälä · 9 years ago
  5. ab75bb5 drm/i915: Turn vgpu pdps into an array by Ville Syrjälä · 9 years ago
  6. 0d925ea drm/i915: Wrap context LRI init in a macro by Ville Syrjälä · 9 years ago
  7. 35dc3f9 drm/i915: Give names to more ring registers by Ville Syrjälä · 9 years ago
  8. 9244a81 drm/i915: Wrap ASSIGN_CTX_{PDP,PM4L} in do {} while(0) by Ville Syrjälä · 9 years ago
  9. 8f40db7 drm/i915: Add wa_ctx_emit_reg() by Ville Syrjälä · 9 years ago
  10. f92a916 drm/i915: Add functions to emit register offsets to the ring by Ville Syrjälä · 9 years ago
  11. e597ef4 drm/i915: Make the cmd parser 64bit regs explicit by Ville Syrjälä · 9 years ago
  12. 8697600 drm/i915: Make the high dword offset more explicit in i915_reg_read_ioctl by Ville Syrjälä · 9 years ago
  13. 3613cf1 drm/i915: s/0x50/RING_PSMI_CTL/ by Ville Syrjälä · 9 years ago
  14. e6c4c76 drm/i915: Parametrize MOCS registers by Ville Syrjälä · 9 years ago
  15. 6fa1c5f drm/i915: Parametrize L3 error registers by Ville Syrjälä · 9 years ago
  16. 086f8e8 drm/i915: Prefix raw register defines with underscore by Ville Syrjälä · 9 years ago
  17. b2e8c6c drm/i915: Streamline gpio_mmio_base deduction by Ville Syrjälä · 9 years ago
  18. 78e0d2e drm/i915: Store DVO SRCDIM register offset under intel_dvo_device by Ville Syrjälä · 9 years ago
  19. 2a5c083 drm/i915: s/is_sdvob/enum port/ by Ville Syrjälä · 9 years ago
  20. c48b530 drm/i915: s/PCH_DP_/PORT_/ in intel_trans_dp_port_sel() and move it next to its only user by Ville Syrjälä · 9 years ago
  21. aba72dd pci: Decouple quirks.c from i915_reg.h by Ville Syrjälä · 9 years ago
  22. 6d8175d drm/i915: Rely on TEST_SINK_START instead of tracking Sink CRC state on dev_priv. by Rodrigo Vivi · 9 years ago
  23. 7e38eef drm/i915: Stop tracking last calculated Sink CRC. by Rodrigo Vivi · 9 years ago
  24. c629784 drm/i915: Make Sink crc calculation waiting for counter to reset. by Rodrigo Vivi · 9 years ago
  25. d72f9d9 drm/i915: Allow 1 vblank to let Sink CRC calculation to start or stop. by Rodrigo Vivi · 9 years ago
  26. a03bc7c drm/i915/skl: Remove unused suspend and resume callbacks by Patrik Jakobsson · 9 years ago
  27. 443646c drm/i915/gen9: Add boot parameter for disabling DC6 by Patrik Jakobsson · 9 years ago
  28. 9f836f9 drm/i915/gen9: Turn DC handling into a power well by Patrik Jakobsson · 9 years ago
  29. cd02ac5 drm/i915: Explain usage of power well IDs vs bit groups by Patrik Jakobsson · 9 years ago
  30. b450e17 drm/i915: Do not warn on PG2 enabled in gen9_disable_dc5() by Patrik Jakobsson · 9 years ago
  31. dfa5762 drm/i915: Add a modeset power domain by Patrik Jakobsson · 9 years ago
  32. 6331a70 drm/i915: Remove distinction between DDI 2 vs 4 lanes by Patrik Jakobsson · 9 years ago
  33. edd993f drm/i915: Remove DDI power domain exclusion SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS by Ville Syrjälä · 9 years ago
  34. f0ab43e drm/i915: Introduce a gmbus power domain by Ville Syrjälä · 9 years ago
  35. 25f78f5 drm/i915: Clean up AUX power domain handling by Ville Syrjälä · 9 years ago
  36. 4deccbb drm/i915/gen9: Always set mask memory up when enabling DC5 or DC6 by Patrik Jakobsson · 9 years ago
  37. fc131bf drm/i915: Don't trust CSR program memory contents by Patrik Jakobsson · 9 years ago
  38. d314cd4 drm/i915: fix handling of the disable_power_well module option by Imre Deak · 9 years ago
  39. c2b1615 drm/i915/skl: remove redundant DDI/IRQ reinitialization during PW1 enabling by Imre Deak · 9 years ago
  40. ab96c1ee drm/i915/skl: make sure LCPLL is disabled when uniniting CDCLK by Imre Deak · 9 years ago
  41. d26fa1d drm/i915/skl: disable DC states before display core init/uninit by Imre Deak · 9 years ago
  42. 13ae3a0 drm/i915/gen9: simplify DC toggling code by Imre Deak · 9 years ago
  43. 4a76f29 drm/i915/skl: don't toggle PW1 and MISC power wells on-demand by Imre Deak · 9 years ago
  44. 73dfc22 drm/i915/skl: init/uninit display core as part of the HW power domain state by Imre Deak · 9 years ago
  45. 30eade1 drm/i915: rename intel_power_domains_resume to *_sync_hw by Imre Deak · 9 years ago
  46. 2f693e2 drm/i915: Make turning on/off PW1 and Misc I/O part of the init/fini sequences by Damien Lespiau · 9 years ago
  47. fc17f22 drm/i915: fix lookup_power_well for power wells without any domain by Imre Deak · 9 years ago
  48. 56fcfd6 drm/i915: fix the power well ID for always on wells by Imre Deak · 9 years ago
  49. e64e6bd drm/i915: get runtime PM reference around GEM set_tiling IOCTL by Imre Deak · 9 years ago
  50. 5bab6f6 drm/i915: Serialise updates to GGTT with access through GGTT on Braswell by Chris Wilson · 9 years ago
  51. 14631e9 drm/i915: force link training when requested by Sink by Shubhangi Shrivastava · 9 years ago
  52. 4df6960 drm/i915: Cleanup test data during long/short hotplug by Shubhangi Shrivastava · 9 years ago
  53. e6d9002 drm/i915/skl: Correct other-pipe watermark update condition check (v2) by Kumar, Mahesh · 9 years ago
  54. 1f38089 drm/i915: Model PSR AUX register selection more like the normal AUX code by Ville Syrjälä · 9 years ago
  55. 443a389 drm/i915: Add dev_priv->psr_mmio_base by Ville Syrjälä · 9 years ago
  56. 330e20e drm/i915: Store aux data reg offsets in intel_dp->aux_ch_data_reg[] by Ville Syrjälä · 9 years ago
  57. da00bdc drm/i915: Remove the magic AUX_CTL is at DP + foo tricks by Ville Syrjälä · 9 years ago
  58. 750a951 drm/i915: Parametrize AUX registers by Ville Syrjälä · 9 years ago
  59. a121f4e drm/i915: Replace the aux ddc name switch statement with kasprintf() by Ville Syrjälä · 9 years ago
  60. f3c6a3a drm/i915: Replace aux_ch_ctl_reg check with port check by Ville Syrjälä · 9 years ago
  61. d1c0a00 drm/i915/skl: Update DDI translation tables for SKL by jim.bride@linux.intel.com · 9 years ago
  62. e4d4c05 drm/i915: Fix SKL i_boost level by Ander Conselvan de Oliveira · 9 years ago
  63. ca1283d drm/i915/skl: Removed assert for csr-fw-loading check during disabling dc6 by Animesh Manna · 9 years ago
  64. f514c2d drm/i915/gen9: flush DMC fw loading work during system suspend by Imre Deak · 9 years ago
  65. 15e72c1 drm/i915/gen9: Use flush_work to synchronize with dmc loader by Animesh Manna · 9 years ago
  66. 8144ac5 drm/i915: Use request_firmware and our own async work by Daniel Vetter · 9 years ago
  67. 6a6582b drm/i915/gen9: extract parse_csr_fw by Daniel Vetter · 9 years ago
  68. f444837 drm/i915/gen9: Use dev_priv in csr functions by Daniel Vetter · 9 years ago
  69. bffbcd9 drm/i915/gen9: Don't try to load garbage dmc firmware on resume by Daniel Vetter · 9 years ago
  70. c729ed8 drm/i915/gen9: Simplify csr loading failure printing. by Daniel Vetter · 9 years ago
  71. f98f70d drm/i915/gen9: Align line continuations in intel_csr.c. by Daniel Vetter · 9 years ago
  72. 414b799 drm/i915/gen9: Remove csr.state, csr_lock and related code. by Daniel Vetter · 9 years ago
  73. af5fead drm/i915/gen9: move assert_csr_loaded into intel_rpm.c by Daniel Vetter · 9 years ago
  74. 01a6908 drm/i915: use correct power domain for csr loading by Daniel Vetter · 9 years ago
  75. ebae38d drm/i915/gen9: csr_init after runtime pm enable by Animesh Manna · 9 years ago
  76. b1a14c6 drm/i915: refactor stepping info retrieval by Jani Nikula · 9 years ago
  77. b9cd5bf drm/i915: constify bxt stepping info by Jani Nikula · 9 years ago
  78. 84cb00e drm/i915: fix indentation on skl stepping info by Jani Nikula · 9 years ago
  79. 1b68372 drm/i915: Remove redundant check in i915_gem_obj_to_vma by Tvrtko Ursulin · 9 years ago
  80. af9b9c1 drm/i915: Clean up LVDS register handling harder by Lukas Wunner · 9 years ago
  81. e00bf69 drm/i915: Move the fbdev async_schedule() into intel_fbdev.c by Ville Syrjälä · 9 years ago
  82. 2013bfc drm/i915: Do fbdev fini first during unload by Ville Syrjälä · 9 years ago
  83. 18a04a7 drm/i915: Kill intel_runtime_pm_disable() by Ville Syrjälä · 9 years ago
  84. e404ba8 drm/i915: Setup DDI clk for MST on SKL by Ville Syrjälä · 9 years ago
  85. abfce94 drm/i915: Configure eDP PLL freq from ironlake_edp_pll_on() by Ville Syrjälä · 9 years ago
  86. 6fec766 drm/i915: Use intel_dp->DP in eDP PLL setup by Ville Syrjälä · 9 years ago
  87. 64e1077 drm/i915: Clean up eDP PLL state asserts by Ville Syrjälä · 9 years ago
  88. 9ece1de drm/i915: Remove ILK-A eDP PLL workaround notes by Ville Syrjälä · 9 years ago
  89. b377e0d drm/i915: s/DP_PLL_FREQ_160MHZ/DP_PLL_FREQ_162MHZ/ by Ville Syrjälä · 9 years ago
  90. d6fbdd1 drm/i915: Hide underruns from eDP PLL and port enable on ILK by Ville Syrjälä · 9 years ago
  91. 0c241d5 drm/i915: Disable FIFO underrun reporting around IBX transcoder B workaround by Ville Syrjälä · 9 years ago
  92. c465613 drm/i915: Check for CPT and not !IBX in ironlake_disable_pch_transcoder() by Ville Syrjälä · 9 years ago
  93. aca7b68 drm/i915: Check for FIFO underruns after modeset on IVB/HSW and CPT/PPT by Ville Syrjälä · 9 years ago
  94. 81b088c drm/i915: Re-enable PCH FIO underrun reporting after pipe has been disabled by Ville Syrjälä · 9 years ago
  95. d2d6540 drm/i915: Enable PCH FIFO underruns later on HSW+ by Ville Syrjälä · 9 years ago
  96. 37ca8d4 drm/i915: Enable PCH FIFO underruns later on ILK/SNB/IVB by Ville Syrjälä · 9 years ago
  97. 9c4edae drm/i915: Set sync polarity from adjusted mode for TRANS_DP_CTL by Ville Syrjälä · 9 years ago
  98. 1a70a728 drm/i915: Don't use intel_pipe_to_cpu_transcoder() when there's a pipe config around by Ville Syrjälä · 9 years ago
  99. 5205bbe drm/i915: remove in_dbg_master check from intel_fbc.c by Paulo Zanoni · 9 years ago
  100. 850bfaa drm/i915: clarify that checking the FB stride for CFB is intentional by Paulo Zanoni · 9 years ago