blob: 60343b58364db77c95a9762c9b838b71d767f44f [file] [log] [blame]
Auke Kok9d5c8242008-01-24 02:22:38 -08001/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
Alexander Duyck86d5d382009-02-06 23:23:12 +00004 Copyright(c) 2007-2009 Intel Corporation.
Auke Kok9d5c8242008-01-24 02:22:38 -08005
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/if_ether.h>
29#include <linux/delay.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32
33#include "e1000_mac.h"
34
35#include "igb.h"
36
37static s32 igb_set_default_fc(struct e1000_hw *hw);
38static s32 igb_set_fc_watermarks(struct e1000_hw *hw);
Auke Kok9d5c8242008-01-24 02:22:38 -080039
Auke Kok9d5c8242008-01-24 02:22:38 -080040/**
Jeff Kirsher733596b2008-06-27 10:59:59 -070041 * igb_get_bus_info_pcie - Get PCIe bus information
Auke Kok9d5c8242008-01-24 02:22:38 -080042 * @hw: pointer to the HW structure
43 *
44 * Determines and stores the system bus information for a particular
45 * network interface. The following bus information is determined and stored:
46 * bus speed, bus width, type (PCIe), and PCIe function.
47 **/
48s32 igb_get_bus_info_pcie(struct e1000_hw *hw)
49{
50 struct e1000_bus_info *bus = &hw->bus;
51 s32 ret_val;
Alexander Duyck5e8427e2008-12-10 01:09:53 -080052 u32 reg;
53 u16 pcie_link_status;
Auke Kok9d5c8242008-01-24 02:22:38 -080054
55 bus->type = e1000_bus_type_pci_express;
56 bus->speed = e1000_bus_speed_2500;
57
58 ret_val = igb_read_pcie_cap_reg(hw,
59 PCIE_LINK_STATUS,
60 &pcie_link_status);
61 if (ret_val)
62 bus->width = e1000_bus_width_unknown;
63 else
64 bus->width = (enum e1000_bus_width)((pcie_link_status &
65 PCIE_LINK_WIDTH_MASK) >>
66 PCIE_LINK_WIDTH_SHIFT);
67
Alexander Duyck5e8427e2008-12-10 01:09:53 -080068 reg = rd32(E1000_STATUS);
69 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;
Auke Kok9d5c8242008-01-24 02:22:38 -080070
71 return 0;
72}
73
74/**
Jeff Kirsher733596b2008-06-27 10:59:59 -070075 * igb_clear_vfta - Clear VLAN filter table
Auke Kok9d5c8242008-01-24 02:22:38 -080076 * @hw: pointer to the HW structure
77 *
78 * Clears the register array which contains the VLAN filter table by
79 * setting all the values to 0.
80 **/
81void igb_clear_vfta(struct e1000_hw *hw)
82{
83 u32 offset;
84
85 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
86 array_wr32(E1000_VFTA, offset, 0);
87 wrfl();
88 }
89}
90
91/**
Jeff Kirsher733596b2008-06-27 10:59:59 -070092 * igb_write_vfta - Write value to VLAN filter table
Auke Kok9d5c8242008-01-24 02:22:38 -080093 * @hw: pointer to the HW structure
94 * @offset: register offset in VLAN filter table
95 * @value: register value written to VLAN filter table
96 *
97 * Writes value at the given offset in the register array which stores
98 * the VLAN filter table.
99 **/
Alexander Duyckff6f63d2009-04-09 22:49:02 +0000100static void igb_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)
Auke Kok9d5c8242008-01-24 02:22:38 -0800101{
102 array_wr32(E1000_VFTA, offset, value);
103 wrfl();
104}
105
106/**
Alexander Duyck4ae196d2009-02-19 20:40:07 -0800107 * igb_vfta_set - enable or disable vlan in VLAN filter table
108 * @hw: pointer to the HW structure
109 * @vid: VLAN id to add or remove
110 * @add: if true add filter, if false remove
111 *
112 * Sets or clears a bit in the VLAN filter table array based on VLAN id
113 * and if we are adding or removing the filter
114 **/
Alexander Duyckcad6d052009-03-13 20:41:37 +0000115s32 igb_vfta_set(struct e1000_hw *hw, u32 vid, bool add)
Alexander Duyck4ae196d2009-02-19 20:40:07 -0800116{
117 u32 index = (vid >> E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK;
Alexander Duyck75f4f382009-03-13 20:41:55 +0000118 u32 mask = 1 << (vid & E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
Alexander Duyckcad6d052009-03-13 20:41:37 +0000119 u32 vfta = array_rd32(E1000_VFTA, index);
120 s32 ret_val = 0;
Alexander Duyck4ae196d2009-02-19 20:40:07 -0800121
Alexander Duyckcad6d052009-03-13 20:41:37 +0000122 /* bit was set/cleared before we started */
123 if ((!!(vfta & mask)) == add) {
124 ret_val = -E1000_ERR_CONFIG;
125 } else {
126 if (add)
127 vfta |= mask;
128 else
129 vfta &= ~mask;
130 }
Alexander Duyck4ae196d2009-02-19 20:40:07 -0800131
132 igb_write_vfta(hw, index, vfta);
Alexander Duyckcad6d052009-03-13 20:41:37 +0000133
134 return ret_val;
Alexander Duyck4ae196d2009-02-19 20:40:07 -0800135}
136
137/**
Jeff Kirsher733596b2008-06-27 10:59:59 -0700138 * igb_check_alt_mac_addr - Check for alternate MAC addr
Auke Kok9d5c8242008-01-24 02:22:38 -0800139 * @hw: pointer to the HW structure
140 *
141 * Checks the nvm for an alternate MAC address. An alternate MAC address
142 * can be setup by pre-boot software and must be treated like a permanent
143 * address and must override the actual permanent MAC address. If an
144 * alternate MAC address is fopund it is saved in the hw struct and
145 * prgrammed into RAR0 and the cuntion returns success, otherwise the
146 * fucntion returns an error.
147 **/
148s32 igb_check_alt_mac_addr(struct e1000_hw *hw)
149{
150 u32 i;
151 s32 ret_val = 0;
152 u16 offset, nvm_alt_mac_addr_offset, nvm_data;
153 u8 alt_mac_addr[ETH_ALEN];
154
Alexander Duyck312c75a2009-02-06 23:17:47 +0000155 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
Auke Kok9d5c8242008-01-24 02:22:38 -0800156 &nvm_alt_mac_addr_offset);
157 if (ret_val) {
Auke Kok652fff32008-06-27 11:00:18 -0700158 hw_dbg("NVM Read Error\n");
Auke Kok9d5c8242008-01-24 02:22:38 -0800159 goto out;
160 }
161
162 if (nvm_alt_mac_addr_offset == 0xFFFF) {
163 ret_val = -(E1000_NOT_IMPLEMENTED);
164 goto out;
165 }
166
167 if (hw->bus.func == E1000_FUNC_1)
168 nvm_alt_mac_addr_offset += ETH_ALEN/sizeof(u16);
169
170 for (i = 0; i < ETH_ALEN; i += 2) {
171 offset = nvm_alt_mac_addr_offset + (i >> 1);
Alexander Duyck312c75a2009-02-06 23:17:47 +0000172 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
Auke Kok9d5c8242008-01-24 02:22:38 -0800173 if (ret_val) {
Auke Kok652fff32008-06-27 11:00:18 -0700174 hw_dbg("NVM Read Error\n");
Auke Kok9d5c8242008-01-24 02:22:38 -0800175 goto out;
176 }
177
178 alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
179 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
180 }
181
182 /* if multicast bit is set, the alternate address will not be used */
183 if (alt_mac_addr[0] & 0x01) {
184 ret_val = -(E1000_NOT_IMPLEMENTED);
185 goto out;
186 }
187
188 for (i = 0; i < ETH_ALEN; i++)
189 hw->mac.addr[i] = hw->mac.perm_addr[i] = alt_mac_addr[i];
190
191 hw->mac.ops.rar_set(hw, hw->mac.perm_addr, 0);
192
193out:
194 return ret_val;
195}
196
197/**
Jeff Kirsher733596b2008-06-27 10:59:59 -0700198 * igb_rar_set - Set receive address register
Auke Kok9d5c8242008-01-24 02:22:38 -0800199 * @hw: pointer to the HW structure
200 * @addr: pointer to the receive address
201 * @index: receive address array register
202 *
203 * Sets the receive address array register at index to the address passed
204 * in by addr.
205 **/
206void igb_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
207{
208 u32 rar_low, rar_high;
209
210 /*
211 * HW expects these in little endian so we reverse the byte order
212 * from network order (big endian) to little endian
213 */
214 rar_low = ((u32) addr[0] |
215 ((u32) addr[1] << 8) |
216 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
217
218 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
219
Alexander Duyck86757372009-02-06 23:21:51 +0000220 /* If MAC address zero, no need to set the AV bit */
221 if (rar_low || rar_high)
Auke Kok9d5c8242008-01-24 02:22:38 -0800222 rar_high |= E1000_RAH_AV;
223
Alexander Duyck5e8427e2008-12-10 01:09:53 -0800224 wr32(E1000_RAL(index), rar_low);
225 wr32(E1000_RAH(index), rar_high);
Auke Kok9d5c8242008-01-24 02:22:38 -0800226}
227
228/**
Jeff Kirsher733596b2008-06-27 10:59:59 -0700229 * igb_mta_set - Set multicast filter table address
Auke Kok9d5c8242008-01-24 02:22:38 -0800230 * @hw: pointer to the HW structure
231 * @hash_value: determines the MTA register and bit to set
232 *
233 * The multicast table address is a register array of 32-bit registers.
234 * The hash_value is used to determine what register the bit is in, the
235 * current value is read, the new bit is OR'd in and the new value is
236 * written back into the register.
237 **/
Alexander Duyck549bdd82008-08-04 15:00:06 -0700238void igb_mta_set(struct e1000_hw *hw, u32 hash_value)
Auke Kok9d5c8242008-01-24 02:22:38 -0800239{
240 u32 hash_bit, hash_reg, mta;
241
242 /*
243 * The MTA is a register array of 32-bit registers. It is
244 * treated like an array of (32*mta_reg_count) bits. We want to
245 * set bit BitArray[hash_value]. So we figure out what register
246 * the bit is in, read it, OR in the new bit, then write
247 * back the new value. The (hw->mac.mta_reg_count - 1) serves as a
248 * mask to bits 31:5 of the hash value which gives us the
249 * register we're modifying. The hash bit within that register
250 * is determined by the lower 5 bits of the hash value.
251 */
252 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
253 hash_bit = hash_value & 0x1F;
254
255 mta = array_rd32(E1000_MTA, hash_reg);
256
257 mta |= (1 << hash_bit);
258
259 array_wr32(E1000_MTA, hash_reg, mta);
260 wrfl();
261}
262
263/**
Jeff Kirsher733596b2008-06-27 10:59:59 -0700264 * igb_hash_mc_addr - Generate a multicast hash value
Auke Kok9d5c8242008-01-24 02:22:38 -0800265 * @hw: pointer to the HW structure
266 * @mc_addr: pointer to a multicast address
267 *
268 * Generates a multicast address hash value which is used to determine
269 * the multicast filter table array address and new table value. See
270 * igb_mta_set()
271 **/
Alexander Duyck2d064c02008-07-08 15:10:12 -0700272u32 igb_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
Auke Kok9d5c8242008-01-24 02:22:38 -0800273{
274 u32 hash_value, hash_mask;
275 u8 bit_shift = 0;
276
277 /* Register count multiplied by bits per register */
278 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
279
280 /*
281 * For a mc_filter_type of 0, bit_shift is the number of left-shifts
282 * where 0xFF would still fall within the hash mask.
283 */
284 while (hash_mask >> bit_shift != 0xFF)
285 bit_shift++;
286
287 /*
288 * The portion of the address that is used for the hash table
289 * is determined by the mc_filter_type setting.
290 * The algorithm is such that there is a total of 8 bits of shifting.
291 * The bit_shift for a mc_filter_type of 0 represents the number of
292 * left-shifts where the MSB of mc_addr[5] would still fall within
293 * the hash_mask. Case 0 does this exactly. Since there are a total
294 * of 8 bits of shifting, then mc_addr[4] will shift right the
295 * remaining number of bits. Thus 8 - bit_shift. The rest of the
296 * cases are a variation of this algorithm...essentially raising the
297 * number of bits to shift mc_addr[5] left, while still keeping the
298 * 8-bit shifting total.
299 *
300 * For example, given the following Destination MAC Address and an
301 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
302 * we can see that the bit_shift for case 0 is 4. These are the hash
303 * values resulting from each mc_filter_type...
304 * [0] [1] [2] [3] [4] [5]
305 * 01 AA 00 12 34 56
306 * LSB MSB
307 *
308 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
309 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
310 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
311 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
312 */
313 switch (hw->mac.mc_filter_type) {
314 default:
315 case 0:
316 break;
317 case 1:
318 bit_shift += 1;
319 break;
320 case 2:
321 bit_shift += 2;
322 break;
323 case 3:
324 bit_shift += 4;
325 break;
326 }
327
328 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
329 (((u16) mc_addr[5]) << bit_shift)));
330
331 return hash_value;
332}
333
334/**
Jeff Kirsher733596b2008-06-27 10:59:59 -0700335 * igb_clear_hw_cntrs_base - Clear base hardware counters
Auke Kok9d5c8242008-01-24 02:22:38 -0800336 * @hw: pointer to the HW structure
337 *
338 * Clears the base hardware counters by reading the counter registers.
339 **/
340void igb_clear_hw_cntrs_base(struct e1000_hw *hw)
341{
342 u32 temp;
343
344 temp = rd32(E1000_CRCERRS);
345 temp = rd32(E1000_SYMERRS);
346 temp = rd32(E1000_MPC);
347 temp = rd32(E1000_SCC);
348 temp = rd32(E1000_ECOL);
349 temp = rd32(E1000_MCC);
350 temp = rd32(E1000_LATECOL);
351 temp = rd32(E1000_COLC);
352 temp = rd32(E1000_DC);
353 temp = rd32(E1000_SEC);
354 temp = rd32(E1000_RLEC);
355 temp = rd32(E1000_XONRXC);
356 temp = rd32(E1000_XONTXC);
357 temp = rd32(E1000_XOFFRXC);
358 temp = rd32(E1000_XOFFTXC);
359 temp = rd32(E1000_FCRUC);
360 temp = rd32(E1000_GPRC);
361 temp = rd32(E1000_BPRC);
362 temp = rd32(E1000_MPRC);
363 temp = rd32(E1000_GPTC);
364 temp = rd32(E1000_GORCL);
365 temp = rd32(E1000_GORCH);
366 temp = rd32(E1000_GOTCL);
367 temp = rd32(E1000_GOTCH);
368 temp = rd32(E1000_RNBC);
369 temp = rd32(E1000_RUC);
370 temp = rd32(E1000_RFC);
371 temp = rd32(E1000_ROC);
372 temp = rd32(E1000_RJC);
373 temp = rd32(E1000_TORL);
374 temp = rd32(E1000_TORH);
375 temp = rd32(E1000_TOTL);
376 temp = rd32(E1000_TOTH);
377 temp = rd32(E1000_TPR);
378 temp = rd32(E1000_TPT);
379 temp = rd32(E1000_MPTC);
380 temp = rd32(E1000_BPTC);
381}
382
383/**
Jeff Kirsher733596b2008-06-27 10:59:59 -0700384 * igb_check_for_copper_link - Check for link (Copper)
Auke Kok9d5c8242008-01-24 02:22:38 -0800385 * @hw: pointer to the HW structure
386 *
387 * Checks to see of the link status of the hardware has changed. If a
388 * change in link status has been detected, then we read the PHY registers
389 * to get the current speed/duplex if link exists.
390 **/
391s32 igb_check_for_copper_link(struct e1000_hw *hw)
392{
393 struct e1000_mac_info *mac = &hw->mac;
394 s32 ret_val;
395 bool link;
396
397 /*
398 * We only want to go out to the PHY registers to see if Auto-Neg
399 * has completed and/or if our link status has changed. The
400 * get_link_status flag is set upon receiving a Link Status
401 * Change or Rx Sequence Error interrupt.
402 */
403 if (!mac->get_link_status) {
404 ret_val = 0;
405 goto out;
406 }
407
408 /*
409 * First we want to see if the MII Status Register reports
410 * link. If so, then we want to get the current speed/duplex
411 * of the PHY.
412 */
413 ret_val = igb_phy_has_link(hw, 1, 0, &link);
414 if (ret_val)
415 goto out;
416
417 if (!link)
418 goto out; /* No link detected */
419
420 mac->get_link_status = false;
421
422 /*
423 * Check if there was DownShift, must be checked
424 * immediately after link-up
425 */
426 igb_check_downshift(hw);
427
428 /*
429 * If we are forcing speed/duplex, then we simply return since
430 * we have already determined whether we have link or not.
431 */
432 if (!mac->autoneg) {
433 ret_val = -E1000_ERR_CONFIG;
434 goto out;
435 }
436
437 /*
438 * Auto-Neg is enabled. Auto Speed Detection takes care
439 * of MAC speed/duplex configuration. So we only need to
440 * configure Collision Distance in the MAC.
441 */
442 igb_config_collision_dist(hw);
443
444 /*
445 * Configure Flow Control now that Auto-Neg has completed.
446 * First, we need to restore the desired flow control
447 * settings because we may have had to re-autoneg with a
448 * different link partner.
449 */
450 ret_val = igb_config_fc_after_link_up(hw);
451 if (ret_val)
Auke Kok652fff32008-06-27 11:00:18 -0700452 hw_dbg("Error configuring flow control\n");
Auke Kok9d5c8242008-01-24 02:22:38 -0800453
454out:
455 return ret_val;
456}
457
458/**
Jeff Kirsher733596b2008-06-27 10:59:59 -0700459 * igb_setup_link - Setup flow control and link settings
Auke Kok9d5c8242008-01-24 02:22:38 -0800460 * @hw: pointer to the HW structure
461 *
462 * Determines which flow control settings to use, then configures flow
463 * control. Calls the appropriate media-specific link configuration
464 * function. Assuming the adapter has a valid link partner, a valid link
465 * should be established. Assumes the hardware has previously been reset
466 * and the transmitter and receiver are not enabled.
467 **/
468s32 igb_setup_link(struct e1000_hw *hw)
469{
470 s32 ret_val = 0;
471
472 /*
473 * In the case of the phy reset being blocked, we already have a link.
474 * We do not need to set it up again.
475 */
476 if (igb_check_reset_block(hw))
477 goto out;
478
479 ret_val = igb_set_default_fc(hw);
480 if (ret_val)
481 goto out;
482
483 /*
484 * We want to save off the original Flow Control configuration just
485 * in case we get disconnected and then reconnected into a different
486 * hub or switch with different Flow Control capabilities.
487 */
488 hw->fc.original_type = hw->fc.type;
489
Auke Kok652fff32008-06-27 11:00:18 -0700490 hw_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.type);
Auke Kok9d5c8242008-01-24 02:22:38 -0800491
492 /* Call the necessary media_type subroutine to configure the link. */
493 ret_val = hw->mac.ops.setup_physical_interface(hw);
494 if (ret_val)
495 goto out;
496
497 /*
498 * Initialize the flow control address, type, and PAUSE timer
499 * registers to their default values. This is done even if flow
500 * control is disabled, because it does not hurt anything to
501 * initialize these registers.
502 */
Auke Kok652fff32008-06-27 11:00:18 -0700503 hw_dbg("Initializing the Flow Control address, type and timer regs\n");
Auke Kok9d5c8242008-01-24 02:22:38 -0800504 wr32(E1000_FCT, FLOW_CONTROL_TYPE);
505 wr32(E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
506 wr32(E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
507
508 wr32(E1000_FCTTV, hw->fc.pause_time);
509
510 ret_val = igb_set_fc_watermarks(hw);
511
512out:
513 return ret_val;
514}
515
516/**
Jeff Kirsher733596b2008-06-27 10:59:59 -0700517 * igb_config_collision_dist - Configure collision distance
Auke Kok9d5c8242008-01-24 02:22:38 -0800518 * @hw: pointer to the HW structure
519 *
520 * Configures the collision distance to the default value and is used
521 * during link setup. Currently no func pointer exists and all
522 * implementations are handled in the generic version of this function.
523 **/
524void igb_config_collision_dist(struct e1000_hw *hw)
525{
526 u32 tctl;
527
528 tctl = rd32(E1000_TCTL);
529
530 tctl &= ~E1000_TCTL_COLD;
531 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
532
533 wr32(E1000_TCTL, tctl);
534 wrfl();
535}
536
537/**
Jeff Kirsher733596b2008-06-27 10:59:59 -0700538 * igb_set_fc_watermarks - Set flow control high/low watermarks
Auke Kok9d5c8242008-01-24 02:22:38 -0800539 * @hw: pointer to the HW structure
540 *
541 * Sets the flow control high/low threshold (watermark) registers. If
542 * flow control XON frame transmission is enabled, then set XON frame
543 * tansmission as well.
544 **/
545static s32 igb_set_fc_watermarks(struct e1000_hw *hw)
546{
547 s32 ret_val = 0;
548 u32 fcrtl = 0, fcrth = 0;
549
550 /*
551 * Set the flow control receive threshold registers. Normally,
552 * these registers will be set to a default threshold that may be
553 * adjusted later by the driver's runtime code. However, if the
554 * ability to transmit pause frames is not enabled, then these
555 * registers will be set to 0.
556 */
557 if (hw->fc.type & e1000_fc_tx_pause) {
558 /*
559 * We need to set up the Receive Threshold high and low water
560 * marks as well as (optionally) enabling the transmission of
561 * XON frames.
562 */
563 fcrtl = hw->fc.low_water;
564 if (hw->fc.send_xon)
565 fcrtl |= E1000_FCRTL_XONE;
566
567 fcrth = hw->fc.high_water;
568 }
569 wr32(E1000_FCRTL, fcrtl);
570 wr32(E1000_FCRTH, fcrth);
571
572 return ret_val;
573}
574
575/**
Jeff Kirsher733596b2008-06-27 10:59:59 -0700576 * igb_set_default_fc - Set flow control default values
Auke Kok9d5c8242008-01-24 02:22:38 -0800577 * @hw: pointer to the HW structure
578 *
579 * Read the EEPROM for the default values for flow control and store the
580 * values.
581 **/
582static s32 igb_set_default_fc(struct e1000_hw *hw)
583{
584 s32 ret_val = 0;
585 u16 nvm_data;
586
587 /*
588 * Read and store word 0x0F of the EEPROM. This word contains bits
589 * that determine the hardware's default PAUSE (flow control) mode,
590 * a bit that determines whether the HW defaults to enabling or
591 * disabling auto-negotiation, and the direction of the
592 * SW defined pins. If there is no SW over-ride of the flow
593 * control setting, then the variable hw->fc will
594 * be initialized based on a value in the EEPROM.
595 */
Alexander Duyck312c75a2009-02-06 23:17:47 +0000596 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
Auke Kok9d5c8242008-01-24 02:22:38 -0800597
598 if (ret_val) {
Auke Kok652fff32008-06-27 11:00:18 -0700599 hw_dbg("NVM Read Error\n");
Auke Kok9d5c8242008-01-24 02:22:38 -0800600 goto out;
601 }
602
603 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0)
604 hw->fc.type = e1000_fc_none;
605 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
606 NVM_WORD0F_ASM_DIR)
607 hw->fc.type = e1000_fc_tx_pause;
608 else
609 hw->fc.type = e1000_fc_full;
610
611out:
612 return ret_val;
613}
614
615/**
Jeff Kirsher733596b2008-06-27 10:59:59 -0700616 * igb_force_mac_fc - Force the MAC's flow control settings
Auke Kok9d5c8242008-01-24 02:22:38 -0800617 * @hw: pointer to the HW structure
618 *
619 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
620 * device control register to reflect the adapter settings. TFCE and RFCE
621 * need to be explicitly set by software when a copper PHY is used because
622 * autonegotiation is managed by the PHY rather than the MAC. Software must
623 * also configure these bits when link is forced on a fiber connection.
624 **/
625s32 igb_force_mac_fc(struct e1000_hw *hw)
626{
627 u32 ctrl;
628 s32 ret_val = 0;
629
630 ctrl = rd32(E1000_CTRL);
631
632 /*
633 * Because we didn't get link via the internal auto-negotiation
634 * mechanism (we either forced link or we got link via PHY
635 * auto-neg), we have to manually enable/disable transmit an
636 * receive flow control.
637 *
638 * The "Case" statement below enables/disable flow control
639 * according to the "hw->fc.type" parameter.
640 *
641 * The possible values of the "fc" parameter are:
642 * 0: Flow control is completely disabled
643 * 1: Rx flow control is enabled (we can receive pause
644 * frames but not send pause frames).
645 * 2: Tx flow control is enabled (we can send pause frames
646 * frames but we do not receive pause frames).
647 * 3: Both Rx and TX flow control (symmetric) is enabled.
648 * other: No other values should be possible at this point.
649 */
Auke Kok652fff32008-06-27 11:00:18 -0700650 hw_dbg("hw->fc.type = %u\n", hw->fc.type);
Auke Kok9d5c8242008-01-24 02:22:38 -0800651
652 switch (hw->fc.type) {
653 case e1000_fc_none:
654 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
655 break;
656 case e1000_fc_rx_pause:
657 ctrl &= (~E1000_CTRL_TFCE);
658 ctrl |= E1000_CTRL_RFCE;
659 break;
660 case e1000_fc_tx_pause:
661 ctrl &= (~E1000_CTRL_RFCE);
662 ctrl |= E1000_CTRL_TFCE;
663 break;
664 case e1000_fc_full:
665 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
666 break;
667 default:
Auke Kok652fff32008-06-27 11:00:18 -0700668 hw_dbg("Flow control param set incorrectly\n");
Auke Kok9d5c8242008-01-24 02:22:38 -0800669 ret_val = -E1000_ERR_CONFIG;
670 goto out;
671 }
672
673 wr32(E1000_CTRL, ctrl);
674
675out:
676 return ret_val;
677}
678
679/**
Jeff Kirsher733596b2008-06-27 10:59:59 -0700680 * igb_config_fc_after_link_up - Configures flow control after link
Auke Kok9d5c8242008-01-24 02:22:38 -0800681 * @hw: pointer to the HW structure
682 *
683 * Checks the status of auto-negotiation after link up to ensure that the
684 * speed and duplex were not forced. If the link needed to be forced, then
685 * flow control needs to be forced also. If auto-negotiation is enabled
686 * and did not fail, then we configure flow control based on our link
687 * partner.
688 **/
689s32 igb_config_fc_after_link_up(struct e1000_hw *hw)
690{
691 struct e1000_mac_info *mac = &hw->mac;
692 s32 ret_val = 0;
693 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
694 u16 speed, duplex;
695
696 /*
697 * Check for the case where we have fiber media and auto-neg failed
698 * so we had to force link. In this case, we need to force the
699 * configuration of the MAC to match the "fc" parameter.
700 */
701 if (mac->autoneg_failed) {
Alexander Duyckdcc3ae92009-07-23 18:07:20 +0000702 if (hw->phy.media_type == e1000_media_type_internal_serdes)
Auke Kok9d5c8242008-01-24 02:22:38 -0800703 ret_val = igb_force_mac_fc(hw);
704 } else {
705 if (hw->phy.media_type == e1000_media_type_copper)
706 ret_val = igb_force_mac_fc(hw);
707 }
708
709 if (ret_val) {
Auke Kok652fff32008-06-27 11:00:18 -0700710 hw_dbg("Error forcing flow control settings\n");
Auke Kok9d5c8242008-01-24 02:22:38 -0800711 goto out;
712 }
713
714 /*
715 * Check for the case where we have copper media and auto-neg is
716 * enabled. In this case, we need to check and see if Auto-Neg
717 * has completed, and if so, how the PHY and link partner has
718 * flow control configured.
719 */
720 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
721 /*
722 * Read the MII Status Register and check to see if AutoNeg
723 * has completed. We read this twice because this reg has
724 * some "sticky" (latched) bits.
725 */
Alexander Duycka8d2a0c2009-02-06 23:17:26 +0000726 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS,
Auke Kok9d5c8242008-01-24 02:22:38 -0800727 &mii_status_reg);
728 if (ret_val)
729 goto out;
Alexander Duycka8d2a0c2009-02-06 23:17:26 +0000730 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS,
Auke Kok9d5c8242008-01-24 02:22:38 -0800731 &mii_status_reg);
732 if (ret_val)
733 goto out;
734
735 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
Auke Kok652fff32008-06-27 11:00:18 -0700736 hw_dbg("Copper PHY and Auto Neg "
Auke Kok9d5c8242008-01-24 02:22:38 -0800737 "has not completed.\n");
738 goto out;
739 }
740
741 /*
742 * The AutoNeg process has completed, so we now need to
743 * read both the Auto Negotiation Advertisement
744 * Register (Address 4) and the Auto_Negotiation Base
745 * Page Ability Register (Address 5) to determine how
746 * flow control was negotiated.
747 */
Alexander Duycka8d2a0c2009-02-06 23:17:26 +0000748 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
Auke Kok9d5c8242008-01-24 02:22:38 -0800749 &mii_nway_adv_reg);
750 if (ret_val)
751 goto out;
Alexander Duycka8d2a0c2009-02-06 23:17:26 +0000752 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
Auke Kok9d5c8242008-01-24 02:22:38 -0800753 &mii_nway_lp_ability_reg);
754 if (ret_val)
755 goto out;
756
757 /*
758 * Two bits in the Auto Negotiation Advertisement Register
759 * (Address 4) and two bits in the Auto Negotiation Base
760 * Page Ability Register (Address 5) determine flow control
761 * for both the PHY and the link partner. The following
762 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
763 * 1999, describes these PAUSE resolution bits and how flow
764 * control is determined based upon these settings.
765 * NOTE: DC = Don't Care
766 *
767 * LOCAL DEVICE | LINK PARTNER
768 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
769 *-------|---------|-------|---------|--------------------
770 * 0 | 0 | DC | DC | e1000_fc_none
771 * 0 | 1 | 0 | DC | e1000_fc_none
772 * 0 | 1 | 1 | 0 | e1000_fc_none
773 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
774 * 1 | 0 | 0 | DC | e1000_fc_none
775 * 1 | DC | 1 | DC | e1000_fc_full
776 * 1 | 1 | 0 | 0 | e1000_fc_none
777 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
778 *
779 * Are both PAUSE bits set to 1? If so, this implies
780 * Symmetric Flow Control is enabled at both ends. The
781 * ASM_DIR bits are irrelevant per the spec.
782 *
783 * For Symmetric Flow Control:
784 *
785 * LOCAL DEVICE | LINK PARTNER
786 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
787 *-------|---------|-------|---------|--------------------
788 * 1 | DC | 1 | DC | E1000_fc_full
789 *
790 */
791 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
792 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
793 /*
794 * Now we need to check if the user selected RX ONLY
795 * of pause frames. In this case, we had to advertise
796 * FULL flow control because we could not advertise RX
797 * ONLY. Hence, we must now check to see if we need to
798 * turn OFF the TRANSMISSION of PAUSE frames.
799 */
800 if (hw->fc.original_type == e1000_fc_full) {
801 hw->fc.type = e1000_fc_full;
Auke Kok652fff32008-06-27 11:00:18 -0700802 hw_dbg("Flow Control = FULL.\r\n");
Auke Kok9d5c8242008-01-24 02:22:38 -0800803 } else {
804 hw->fc.type = e1000_fc_rx_pause;
Auke Kok652fff32008-06-27 11:00:18 -0700805 hw_dbg("Flow Control = "
806 "RX PAUSE frames only.\r\n");
Auke Kok9d5c8242008-01-24 02:22:38 -0800807 }
808 }
809 /*
810 * For receiving PAUSE frames ONLY.
811 *
812 * LOCAL DEVICE | LINK PARTNER
813 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
814 *-------|---------|-------|---------|--------------------
815 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
816 */
817 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
818 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
819 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
820 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
821 hw->fc.type = e1000_fc_tx_pause;
Auke Kok652fff32008-06-27 11:00:18 -0700822 hw_dbg("Flow Control = TX PAUSE frames only.\r\n");
Auke Kok9d5c8242008-01-24 02:22:38 -0800823 }
824 /*
825 * For transmitting PAUSE frames ONLY.
826 *
827 * LOCAL DEVICE | LINK PARTNER
828 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
829 *-------|---------|-------|---------|--------------------
830 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
831 */
832 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
833 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
834 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
835 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
836 hw->fc.type = e1000_fc_rx_pause;
Auke Kok652fff32008-06-27 11:00:18 -0700837 hw_dbg("Flow Control = RX PAUSE frames only.\r\n");
Auke Kok9d5c8242008-01-24 02:22:38 -0800838 }
839 /*
840 * Per the IEEE spec, at this point flow control should be
841 * disabled. However, we want to consider that we could
842 * be connected to a legacy switch that doesn't advertise
843 * desired flow control, but can be forced on the link
844 * partner. So if we advertised no flow control, that is
845 * what we will resolve to. If we advertised some kind of
846 * receive capability (Rx Pause Only or Full Flow Control)
847 * and the link partner advertised none, we will configure
848 * ourselves to enable Rx Flow Control only. We can do
849 * this safely for two reasons: If the link partner really
850 * didn't want flow control enabled, and we enable Rx, no
851 * harm done since we won't be receiving any PAUSE frames
852 * anyway. If the intent on the link partner was to have
853 * flow control enabled, then by us enabling RX only, we
854 * can at least receive pause frames and process them.
855 * This is a good idea because in most cases, since we are
856 * predominantly a server NIC, more times than not we will
857 * be asked to delay transmission of packets than asking
858 * our link partner to pause transmission of frames.
859 */
860 else if ((hw->fc.original_type == e1000_fc_none ||
861 hw->fc.original_type == e1000_fc_tx_pause) ||
862 hw->fc.strict_ieee) {
863 hw->fc.type = e1000_fc_none;
Auke Kok652fff32008-06-27 11:00:18 -0700864 hw_dbg("Flow Control = NONE.\r\n");
Auke Kok9d5c8242008-01-24 02:22:38 -0800865 } else {
866 hw->fc.type = e1000_fc_rx_pause;
Auke Kok652fff32008-06-27 11:00:18 -0700867 hw_dbg("Flow Control = RX PAUSE frames only.\r\n");
Auke Kok9d5c8242008-01-24 02:22:38 -0800868 }
869
870 /*
871 * Now we need to do one last check... If we auto-
872 * negotiated to HALF DUPLEX, flow control should not be
873 * enabled per IEEE 802.3 spec.
874 */
875 ret_val = hw->mac.ops.get_speed_and_duplex(hw, &speed, &duplex);
876 if (ret_val) {
Auke Kok652fff32008-06-27 11:00:18 -0700877 hw_dbg("Error getting link speed and duplex\n");
Auke Kok9d5c8242008-01-24 02:22:38 -0800878 goto out;
879 }
880
881 if (duplex == HALF_DUPLEX)
882 hw->fc.type = e1000_fc_none;
883
884 /*
885 * Now we call a subroutine to actually force the MAC
886 * controller to use the correct flow control settings.
887 */
888 ret_val = igb_force_mac_fc(hw);
889 if (ret_val) {
Auke Kok652fff32008-06-27 11:00:18 -0700890 hw_dbg("Error forcing flow control settings\n");
Auke Kok9d5c8242008-01-24 02:22:38 -0800891 goto out;
892 }
893 }
894
895out:
896 return ret_val;
897}
898
899/**
Jeff Kirsher733596b2008-06-27 10:59:59 -0700900 * igb_get_speed_and_duplex_copper - Retreive current speed/duplex
Auke Kok9d5c8242008-01-24 02:22:38 -0800901 * @hw: pointer to the HW structure
902 * @speed: stores the current speed
903 * @duplex: stores the current duplex
904 *
905 * Read the status register for the current speed/duplex and store the current
906 * speed and duplex for copper connections.
907 **/
908s32 igb_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed,
909 u16 *duplex)
910{
911 u32 status;
912
913 status = rd32(E1000_STATUS);
914 if (status & E1000_STATUS_SPEED_1000) {
915 *speed = SPEED_1000;
Auke Kok652fff32008-06-27 11:00:18 -0700916 hw_dbg("1000 Mbs, ");
Auke Kok9d5c8242008-01-24 02:22:38 -0800917 } else if (status & E1000_STATUS_SPEED_100) {
918 *speed = SPEED_100;
Auke Kok652fff32008-06-27 11:00:18 -0700919 hw_dbg("100 Mbs, ");
Auke Kok9d5c8242008-01-24 02:22:38 -0800920 } else {
921 *speed = SPEED_10;
Auke Kok652fff32008-06-27 11:00:18 -0700922 hw_dbg("10 Mbs, ");
Auke Kok9d5c8242008-01-24 02:22:38 -0800923 }
924
925 if (status & E1000_STATUS_FD) {
926 *duplex = FULL_DUPLEX;
Auke Kok652fff32008-06-27 11:00:18 -0700927 hw_dbg("Full Duplex\n");
Auke Kok9d5c8242008-01-24 02:22:38 -0800928 } else {
929 *duplex = HALF_DUPLEX;
Auke Kok652fff32008-06-27 11:00:18 -0700930 hw_dbg("Half Duplex\n");
Auke Kok9d5c8242008-01-24 02:22:38 -0800931 }
932
933 return 0;
934}
935
936/**
Jeff Kirsher733596b2008-06-27 10:59:59 -0700937 * igb_get_hw_semaphore - Acquire hardware semaphore
Auke Kok9d5c8242008-01-24 02:22:38 -0800938 * @hw: pointer to the HW structure
939 *
940 * Acquire the HW semaphore to access the PHY or NVM
941 **/
942s32 igb_get_hw_semaphore(struct e1000_hw *hw)
943{
944 u32 swsm;
945 s32 ret_val = 0;
946 s32 timeout = hw->nvm.word_size + 1;
947 s32 i = 0;
948
949 /* Get the SW semaphore */
950 while (i < timeout) {
951 swsm = rd32(E1000_SWSM);
952 if (!(swsm & E1000_SWSM_SMBI))
953 break;
954
955 udelay(50);
956 i++;
957 }
958
959 if (i == timeout) {
Auke Kok652fff32008-06-27 11:00:18 -0700960 hw_dbg("Driver can't access device - SMBI bit is set.\n");
Auke Kok9d5c8242008-01-24 02:22:38 -0800961 ret_val = -E1000_ERR_NVM;
962 goto out;
963 }
964
965 /* Get the FW semaphore. */
966 for (i = 0; i < timeout; i++) {
967 swsm = rd32(E1000_SWSM);
968 wr32(E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
969
970 /* Semaphore acquired if bit latched */
971 if (rd32(E1000_SWSM) & E1000_SWSM_SWESMBI)
972 break;
973
974 udelay(50);
975 }
976
977 if (i == timeout) {
978 /* Release semaphores */
979 igb_put_hw_semaphore(hw);
Auke Kok652fff32008-06-27 11:00:18 -0700980 hw_dbg("Driver can't access the NVM\n");
Auke Kok9d5c8242008-01-24 02:22:38 -0800981 ret_val = -E1000_ERR_NVM;
982 goto out;
983 }
984
985out:
986 return ret_val;
987}
988
989/**
Jeff Kirsher733596b2008-06-27 10:59:59 -0700990 * igb_put_hw_semaphore - Release hardware semaphore
Auke Kok9d5c8242008-01-24 02:22:38 -0800991 * @hw: pointer to the HW structure
992 *
993 * Release hardware semaphore used to access the PHY or NVM
994 **/
995void igb_put_hw_semaphore(struct e1000_hw *hw)
996{
997 u32 swsm;
998
999 swsm = rd32(E1000_SWSM);
1000
1001 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1002
1003 wr32(E1000_SWSM, swsm);
1004}
1005
1006/**
Jeff Kirsher733596b2008-06-27 10:59:59 -07001007 * igb_get_auto_rd_done - Check for auto read completion
Auke Kok9d5c8242008-01-24 02:22:38 -08001008 * @hw: pointer to the HW structure
1009 *
1010 * Check EEPROM for Auto Read done bit.
1011 **/
1012s32 igb_get_auto_rd_done(struct e1000_hw *hw)
1013{
1014 s32 i = 0;
1015 s32 ret_val = 0;
1016
1017
1018 while (i < AUTO_READ_DONE_TIMEOUT) {
1019 if (rd32(E1000_EECD) & E1000_EECD_AUTO_RD)
1020 break;
1021 msleep(1);
1022 i++;
1023 }
1024
1025 if (i == AUTO_READ_DONE_TIMEOUT) {
Auke Kok652fff32008-06-27 11:00:18 -07001026 hw_dbg("Auto read by HW from NVM has not completed.\n");
Auke Kok9d5c8242008-01-24 02:22:38 -08001027 ret_val = -E1000_ERR_RESET;
1028 goto out;
1029 }
1030
1031out:
1032 return ret_val;
1033}
1034
1035/**
Jeff Kirsher733596b2008-06-27 10:59:59 -07001036 * igb_valid_led_default - Verify a valid default LED config
Auke Kok9d5c8242008-01-24 02:22:38 -08001037 * @hw: pointer to the HW structure
1038 * @data: pointer to the NVM (EEPROM)
1039 *
1040 * Read the EEPROM for the current default LED configuration. If the
1041 * LED configuration is not valid, set to a valid LED configuration.
1042 **/
1043static s32 igb_valid_led_default(struct e1000_hw *hw, u16 *data)
1044{
1045 s32 ret_val;
1046
Alexander Duyck312c75a2009-02-06 23:17:47 +00001047 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
Auke Kok9d5c8242008-01-24 02:22:38 -08001048 if (ret_val) {
Auke Kok652fff32008-06-27 11:00:18 -07001049 hw_dbg("NVM Read Error\n");
Auke Kok9d5c8242008-01-24 02:22:38 -08001050 goto out;
1051 }
1052
Alexander Duyck099e1cb2009-07-23 18:07:40 +00001053 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1054 switch(hw->phy.media_type) {
1055 case e1000_media_type_internal_serdes:
1056 *data = ID_LED_DEFAULT_82575_SERDES;
1057 break;
1058 case e1000_media_type_copper:
1059 default:
1060 *data = ID_LED_DEFAULT;
1061 break;
1062 }
1063 }
Auke Kok9d5c8242008-01-24 02:22:38 -08001064out:
1065 return ret_val;
1066}
1067
1068/**
Jeff Kirsher733596b2008-06-27 10:59:59 -07001069 * igb_id_led_init -
Auke Kok9d5c8242008-01-24 02:22:38 -08001070 * @hw: pointer to the HW structure
1071 *
1072 **/
1073s32 igb_id_led_init(struct e1000_hw *hw)
1074{
1075 struct e1000_mac_info *mac = &hw->mac;
1076 s32 ret_val;
1077 const u32 ledctl_mask = 0x000000FF;
1078 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1079 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1080 u16 data, i, temp;
1081 const u16 led_mask = 0x0F;
1082
1083 ret_val = igb_valid_led_default(hw, &data);
1084 if (ret_val)
1085 goto out;
1086
1087 mac->ledctl_default = rd32(E1000_LEDCTL);
1088 mac->ledctl_mode1 = mac->ledctl_default;
1089 mac->ledctl_mode2 = mac->ledctl_default;
1090
1091 for (i = 0; i < 4; i++) {
1092 temp = (data >> (i << 2)) & led_mask;
1093 switch (temp) {
1094 case ID_LED_ON1_DEF2:
1095 case ID_LED_ON1_ON2:
1096 case ID_LED_ON1_OFF2:
1097 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1098 mac->ledctl_mode1 |= ledctl_on << (i << 3);
1099 break;
1100 case ID_LED_OFF1_DEF2:
1101 case ID_LED_OFF1_ON2:
1102 case ID_LED_OFF1_OFF2:
1103 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1104 mac->ledctl_mode1 |= ledctl_off << (i << 3);
1105 break;
1106 default:
1107 /* Do nothing */
1108 break;
1109 }
1110 switch (temp) {
1111 case ID_LED_DEF1_ON2:
1112 case ID_LED_ON1_ON2:
1113 case ID_LED_OFF1_ON2:
1114 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1115 mac->ledctl_mode2 |= ledctl_on << (i << 3);
1116 break;
1117 case ID_LED_DEF1_OFF2:
1118 case ID_LED_ON1_OFF2:
1119 case ID_LED_OFF1_OFF2:
1120 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1121 mac->ledctl_mode2 |= ledctl_off << (i << 3);
1122 break;
1123 default:
1124 /* Do nothing */
1125 break;
1126 }
1127 }
1128
1129out:
1130 return ret_val;
1131}
1132
1133/**
Jeff Kirsher733596b2008-06-27 10:59:59 -07001134 * igb_cleanup_led - Set LED config to default operation
Auke Kok9d5c8242008-01-24 02:22:38 -08001135 * @hw: pointer to the HW structure
1136 *
1137 * Remove the current LED configuration and set the LED configuration
1138 * to the default value, saved from the EEPROM.
1139 **/
1140s32 igb_cleanup_led(struct e1000_hw *hw)
1141{
1142 wr32(E1000_LEDCTL, hw->mac.ledctl_default);
1143 return 0;
1144}
1145
1146/**
Jeff Kirsher733596b2008-06-27 10:59:59 -07001147 * igb_blink_led - Blink LED
Auke Kok9d5c8242008-01-24 02:22:38 -08001148 * @hw: pointer to the HW structure
1149 *
1150 * Blink the led's which are set to be on.
1151 **/
1152s32 igb_blink_led(struct e1000_hw *hw)
1153{
1154 u32 ledctl_blink = 0;
1155 u32 i;
1156
Alexander Duyckdcc3ae92009-07-23 18:07:20 +00001157 /*
1158 * set the blink bit for each LED that's "on" (0x0E)
1159 * in ledctl_mode2
1160 */
1161 ledctl_blink = hw->mac.ledctl_mode2;
1162 for (i = 0; i < 4; i++)
1163 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1164 E1000_LEDCTL_MODE_LED_ON)
1165 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK <<
1166 (i * 8));
Auke Kok9d5c8242008-01-24 02:22:38 -08001167
1168 wr32(E1000_LEDCTL, ledctl_blink);
1169
1170 return 0;
1171}
1172
1173/**
Jeff Kirsher733596b2008-06-27 10:59:59 -07001174 * igb_led_off - Turn LED off
Auke Kok9d5c8242008-01-24 02:22:38 -08001175 * @hw: pointer to the HW structure
1176 *
1177 * Turn LED off.
1178 **/
1179s32 igb_led_off(struct e1000_hw *hw)
1180{
Auke Kok9d5c8242008-01-24 02:22:38 -08001181 switch (hw->phy.media_type) {
Auke Kok9d5c8242008-01-24 02:22:38 -08001182 case e1000_media_type_copper:
1183 wr32(E1000_LEDCTL, hw->mac.ledctl_mode1);
1184 break;
1185 default:
1186 break;
1187 }
1188
1189 return 0;
1190}
1191
1192/**
Jeff Kirsher733596b2008-06-27 10:59:59 -07001193 * igb_disable_pcie_master - Disables PCI-express master access
Auke Kok9d5c8242008-01-24 02:22:38 -08001194 * @hw: pointer to the HW structure
1195 *
1196 * Returns 0 (0) if successful, else returns -10
1197 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not casued
1198 * the master requests to be disabled.
1199 *
1200 * Disables PCI-Express master access and verifies there are no pending
1201 * requests.
1202 **/
1203s32 igb_disable_pcie_master(struct e1000_hw *hw)
1204{
1205 u32 ctrl;
1206 s32 timeout = MASTER_DISABLE_TIMEOUT;
1207 s32 ret_val = 0;
1208
1209 if (hw->bus.type != e1000_bus_type_pci_express)
1210 goto out;
1211
1212 ctrl = rd32(E1000_CTRL);
1213 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
1214 wr32(E1000_CTRL, ctrl);
1215
1216 while (timeout) {
1217 if (!(rd32(E1000_STATUS) &
1218 E1000_STATUS_GIO_MASTER_ENABLE))
1219 break;
1220 udelay(100);
1221 timeout--;
1222 }
1223
1224 if (!timeout) {
Auke Kok652fff32008-06-27 11:00:18 -07001225 hw_dbg("Master requests are pending.\n");
Auke Kok9d5c8242008-01-24 02:22:38 -08001226 ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING;
1227 goto out;
1228 }
1229
1230out:
1231 return ret_val;
1232}
1233
1234/**
Jeff Kirsher733596b2008-06-27 10:59:59 -07001235 * igb_reset_adaptive - Reset Adaptive Interframe Spacing
Auke Kok9d5c8242008-01-24 02:22:38 -08001236 * @hw: pointer to the HW structure
1237 *
1238 * Reset the Adaptive Interframe Spacing throttle to default values.
1239 **/
1240void igb_reset_adaptive(struct e1000_hw *hw)
1241{
1242 struct e1000_mac_info *mac = &hw->mac;
1243
1244 if (!mac->adaptive_ifs) {
Auke Kok652fff32008-06-27 11:00:18 -07001245 hw_dbg("Not in Adaptive IFS mode!\n");
Auke Kok9d5c8242008-01-24 02:22:38 -08001246 goto out;
1247 }
1248
1249 if (!mac->ifs_params_forced) {
1250 mac->current_ifs_val = 0;
1251 mac->ifs_min_val = IFS_MIN;
1252 mac->ifs_max_val = IFS_MAX;
1253 mac->ifs_step_size = IFS_STEP;
1254 mac->ifs_ratio = IFS_RATIO;
1255 }
1256
1257 mac->in_ifs_mode = false;
1258 wr32(E1000_AIT, 0);
1259out:
1260 return;
1261}
1262
1263/**
Jeff Kirsher733596b2008-06-27 10:59:59 -07001264 * igb_update_adaptive - Update Adaptive Interframe Spacing
Auke Kok9d5c8242008-01-24 02:22:38 -08001265 * @hw: pointer to the HW structure
1266 *
1267 * Update the Adaptive Interframe Spacing Throttle value based on the
1268 * time between transmitted packets and time between collisions.
1269 **/
1270void igb_update_adaptive(struct e1000_hw *hw)
1271{
1272 struct e1000_mac_info *mac = &hw->mac;
1273
1274 if (!mac->adaptive_ifs) {
Auke Kok652fff32008-06-27 11:00:18 -07001275 hw_dbg("Not in Adaptive IFS mode!\n");
Auke Kok9d5c8242008-01-24 02:22:38 -08001276 goto out;
1277 }
1278
1279 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
1280 if (mac->tx_packet_delta > MIN_NUM_XMITS) {
1281 mac->in_ifs_mode = true;
1282 if (mac->current_ifs_val < mac->ifs_max_val) {
1283 if (!mac->current_ifs_val)
1284 mac->current_ifs_val = mac->ifs_min_val;
1285 else
1286 mac->current_ifs_val +=
1287 mac->ifs_step_size;
1288 wr32(E1000_AIT,
1289 mac->current_ifs_val);
1290 }
1291 }
1292 } else {
1293 if (mac->in_ifs_mode &&
1294 (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
1295 mac->current_ifs_val = 0;
1296 mac->in_ifs_mode = false;
1297 wr32(E1000_AIT, 0);
1298 }
1299 }
1300out:
1301 return;
1302}
1303
1304/**
Jeff Kirsher733596b2008-06-27 10:59:59 -07001305 * igb_validate_mdi_setting - Verify MDI/MDIx settings
Auke Kok9d5c8242008-01-24 02:22:38 -08001306 * @hw: pointer to the HW structure
1307 *
1308 * Verify that when not using auto-negotitation that MDI/MDIx is correctly
1309 * set, which is forced to MDI mode only.
1310 **/
1311s32 igb_validate_mdi_setting(struct e1000_hw *hw)
1312{
1313 s32 ret_val = 0;
1314
1315 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) {
Auke Kok652fff32008-06-27 11:00:18 -07001316 hw_dbg("Invalid MDI setting detected\n");
Auke Kok9d5c8242008-01-24 02:22:38 -08001317 hw->phy.mdix = 1;
1318 ret_val = -E1000_ERR_CONFIG;
1319 goto out;
1320 }
1321
1322out:
1323 return ret_val;
1324}
1325
1326/**
Jeff Kirsher733596b2008-06-27 10:59:59 -07001327 * igb_write_8bit_ctrl_reg - Write a 8bit CTRL register
Auke Kok9d5c8242008-01-24 02:22:38 -08001328 * @hw: pointer to the HW structure
1329 * @reg: 32bit register offset such as E1000_SCTL
1330 * @offset: register offset to write to
1331 * @data: data to write at register offset
1332 *
1333 * Writes an address/data control type register. There are several of these
1334 * and they all have the format address << 8 | data and bit 31 is polled for
1335 * completion.
1336 **/
1337s32 igb_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg,
1338 u32 offset, u8 data)
1339{
1340 u32 i, regvalue = 0;
1341 s32 ret_val = 0;
1342
1343 /* Set up the address and data */
1344 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT);
1345 wr32(reg, regvalue);
1346
1347 /* Poll the ready bit to see if the MDI read completed */
1348 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) {
1349 udelay(5);
1350 regvalue = rd32(reg);
1351 if (regvalue & E1000_GEN_CTL_READY)
1352 break;
1353 }
1354 if (!(regvalue & E1000_GEN_CTL_READY)) {
Auke Kok652fff32008-06-27 11:00:18 -07001355 hw_dbg("Reg %08x did not indicate ready\n", reg);
Auke Kok9d5c8242008-01-24 02:22:38 -08001356 ret_val = -E1000_ERR_PHY;
1357 goto out;
1358 }
1359
1360out:
1361 return ret_val;
1362}
1363
1364/**
Jeff Kirsher733596b2008-06-27 10:59:59 -07001365 * igb_enable_mng_pass_thru - Enable processing of ARP's
Auke Kok9d5c8242008-01-24 02:22:38 -08001366 * @hw: pointer to the HW structure
1367 *
1368 * Verifies the hardware needs to allow ARPs to be processed by the host.
1369 **/
1370bool igb_enable_mng_pass_thru(struct e1000_hw *hw)
1371{
1372 u32 manc;
1373 u32 fwsm, factps;
1374 bool ret_val = false;
1375
1376 if (!hw->mac.asf_firmware_present)
1377 goto out;
1378
1379 manc = rd32(E1000_MANC);
1380
1381 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
1382 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
1383 goto out;
1384
1385 if (hw->mac.arc_subsystem_valid) {
1386 fwsm = rd32(E1000_FWSM);
1387 factps = rd32(E1000_FACTPS);
1388
1389 if (!(factps & E1000_FACTPS_MNGCG) &&
1390 ((fwsm & E1000_FWSM_MODE_MASK) ==
1391 (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) {
1392 ret_val = true;
1393 goto out;
1394 }
1395 } else {
1396 if ((manc & E1000_MANC_SMBUS_EN) &&
1397 !(manc & E1000_MANC_ASF_EN)) {
1398 ret_val = true;
1399 goto out;
1400 }
1401 }
1402
1403out:
1404 return ret_val;
1405}