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gerrit-public.fairphone.software / kernel / msm-5.4 / 027bdc85ee74f8f456a47dc53154252ef7d1792f / . / drivers / video / omap2 / dss / ti_hdmi.h
blob: 88fdc1cda364f118c85a130b7e50255c2ebe9005 [file] [log] [blame]
Mythri P K94c52982011-09-08 19:06:21 +0530[diff] [blame]1/*
2 * ti_hdmi.h
3 *
4 * HDMI driver definition for TI OMAP4, DM81xx, DM38xx Processor.
5 *
6 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published by
10 * the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#ifndef _TI_HDMI_H
22#define _TI_HDMI_H
23
Mythri P K60634a22011-09-08 19:06:26 +0530[diff] [blame]24struct hdmi_ip_data;
25
Mythri P K94c52982011-09-08 19:06:21 +0530[diff] [blame]26enum hdmi_pll_pwr {
27 HDMI_PLLPWRCMD_ALLOFF = 0,
28 HDMI_PLLPWRCMD_PLLONLY = 1,
29 HDMI_PLLPWRCMD_BOTHON_ALLCLKS = 2,
30 HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 3
31};
32
33enum hdmi_core_hdmi_dvi {
34 HDMI_DVI = 0,
35 HDMI_HDMI = 1
36};
37
38enum hdmi_clk_refsel {
39 HDMI_REFSEL_PCLK = 0,
40 HDMI_REFSEL_REF1 = 1,
41 HDMI_REFSEL_REF2 = 2,
42 HDMI_REFSEL_SYSCLK = 3
43};
44
Mythri P Ka05ce782012-01-06 17:52:08 +0530[diff] [blame]45/* HDMI timing structure */
Mythri P K94c52982011-09-08 19:06:21 +0530[diff] [blame]46struct hdmi_video_timings {
47 u16 x_res;
48 u16 y_res;
49 /* Unit: KHz */
50 u32 pixel_clock;
51 u16 hsw;
52 u16 hfp;
53 u16 hbp;
54 u16 vsw;
55 u16 vfp;
56 u16 vbp;
Mythri P Ka05ce782012-01-06 17:52:08 +0530[diff] [blame]57 bool vsync_pol;
58 bool hsync_pol;
59 bool interlace;
Mythri P K94c52982011-09-08 19:06:21 +0530[diff] [blame]60};
61
62struct hdmi_cm {
63 int code;
64 int mode;
65};
66
67struct hdmi_config {
Mythri P Ka05ce782012-01-06 17:52:08 +0530[diff] [blame]68 struct hdmi_video_timings timings;
Mythri P K94c52982011-09-08 19:06:21 +0530[diff] [blame]69 struct hdmi_cm cm;
70};
71
72/* HDMI PLL structure */
73struct hdmi_pll_info {
74 u16 regn;
75 u16 regm;
76 u32 regmf;
77 u16 regm2;
78 u16 regsd;
79 u16 dcofreq;
80 enum hdmi_clk_refsel refsel;
81};
82
Mythri P K60634a22011-09-08 19:06:26 +0530[diff] [blame]83struct ti_hdmi_ip_ops {
84
85 void (*video_configure)(struct hdmi_ip_data *ip_data);
86
87 int (*phy_enable)(struct hdmi_ip_data *ip_data);
88
89 void (*phy_disable)(struct hdmi_ip_data *ip_data);
90
Tomi Valkeinen937fce12011-08-31 11:12:40 +0300[diff] [blame]91 int (*read_edid)(struct hdmi_ip_data *ip_data, u8 *edid, int len);
Mythri P K60634a22011-09-08 19:06:26 +0530[diff] [blame]92
Tomi Valkeinen759593f2011-08-29 18:10:20 +0300[diff] [blame]93 bool (*detect)(struct hdmi_ip_data *ip_data);
94
Mythri P K60634a22011-09-08 19:06:26 +0530[diff] [blame]95 int (*pll_enable)(struct hdmi_ip_data *ip_data);
96
97 void (*pll_disable)(struct hdmi_ip_data *ip_data);
98
99 void (*video_enable)(struct hdmi_ip_data *ip_data, bool start);
Mythri P K162874d2011-09-22 13:37:45 +0530[diff] [blame]100
101 void (*dump_wrapper)(struct hdmi_ip_data *ip_data, struct seq_file *s);
102
103 void (*dump_core)(struct hdmi_ip_data *ip_data, struct seq_file *s);
104
105 void (*dump_pll)(struct hdmi_ip_data *ip_data, struct seq_file *s);
106
107 void (*dump_phy)(struct hdmi_ip_data *ip_data, struct seq_file *s);
108
Ricardo Neri80a48592011-11-27 16:09:58 -0600[diff] [blame]109#if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
110 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
Ricardo Neri027bdc82012-04-20 17:17:46 -0500[diff] [blame^]111 int (*audio_enable)(struct hdmi_ip_data *ip_data);
112
113 void (*audio_disable)(struct hdmi_ip_data *ip_data);
Ricardo Neri80a48592011-11-27 16:09:58 -0600[diff] [blame]114#endif
115
Mythri P K60634a22011-09-08 19:06:26 +0530[diff] [blame]116};
117
Mythri P Kda8f14f2012-02-08 11:54:19 +0530[diff] [blame]118/*
119 * Refer to section 8.2 in HDMI 1.3 specification for
120 * details about infoframe databytes
121 */
122struct hdmi_core_infoframe_avi {
123 /* Y0, Y1 rgb,yCbCr */
124 u8 db1_format;
125 /* A0 Active information Present */
126 u8 db1_active_info;
127 /* B0, B1 Bar info data valid */
128 u8 db1_bar_info_dv;
129 /* S0, S1 scan information */
130 u8 db1_scan_info;
131 /* C0, C1 colorimetry */
132 u8 db2_colorimetry;
133 /* M0, M1 Aspect ratio (4:3, 16:9) */
134 u8 db2_aspect_ratio;
135 /* R0...R3 Active format aspect ratio */
136 u8 db2_active_fmt_ar;
137 /* ITC IT content. */
138 u8 db3_itc;
139 /* EC0, EC1, EC2 Extended colorimetry */
140 u8 db3_ec;
141 /* Q1, Q0 Quantization range */
142 u8 db3_q_range;
143 /* SC1, SC0 Non-uniform picture scaling */
144 u8 db3_nup_scaling;
145 /* VIC0..6 Video format identification */
146 u8 db4_videocode;
147 /* PR0..PR3 Pixel repetition factor */
148 u8 db5_pixel_repeat;
149 /* Line number end of top bar */
150 u16 db6_7_line_eoftop;
151 /* Line number start of bottom bar */
152 u16 db8_9_line_sofbottom;
153 /* Pixel number end of left bar */
154 u16 db10_11_pixel_eofleft;
155 /* Pixel number start of right bar */
156 u16 db12_13_pixel_sofright;
157};
158
Mythri P K94c52982011-09-08 19:06:21 +0530[diff] [blame]159struct hdmi_ip_data {
160 void __iomem *base_wp; /* HDMI wrapper */
161 unsigned long core_sys_offset;
162 unsigned long core_av_offset;
163 unsigned long pll_offset;
164 unsigned long phy_offset;
Mythri P K60634a22011-09-08 19:06:26 +0530[diff] [blame]165 const struct ti_hdmi_ip_ops *ops;
Mythri P K94c52982011-09-08 19:06:21 +0530[diff] [blame]166 struct hdmi_config cfg;
167 struct hdmi_pll_info pll_data;
Mythri P Kda8f14f2012-02-08 11:54:19 +0530[diff] [blame]168 struct hdmi_core_infoframe_avi avi_cfg;
Tomi Valkeinenc49d0052012-01-17 11:09:57 +0200[diff] [blame]169
170 /* ti_hdmi_4xxx_ip private data. These should be in a separate struct */
171 int hpd_gpio;
172 bool phy_tx_enabled;
Mythri P K94c52982011-09-08 19:06:21 +0530[diff] [blame]173};
Mythri P K176b5782011-09-08 19:06:25 +0530[diff] [blame]174int ti_hdmi_4xxx_phy_enable(struct hdmi_ip_data *ip_data);
175void ti_hdmi_4xxx_phy_disable(struct hdmi_ip_data *ip_data);
Tomi Valkeinen937fce12011-08-31 11:12:40 +0300[diff] [blame]176int ti_hdmi_4xxx_read_edid(struct hdmi_ip_data *ip_data, u8 *edid, int len);
Tomi Valkeinen759593f2011-08-29 18:10:20 +0300[diff] [blame]177bool ti_hdmi_4xxx_detect(struct hdmi_ip_data *ip_data);
Mythri P K176b5782011-09-08 19:06:25 +0530[diff] [blame]178void ti_hdmi_4xxx_wp_video_start(struct hdmi_ip_data *ip_data, bool start);
179int ti_hdmi_4xxx_pll_enable(struct hdmi_ip_data *ip_data);
180void ti_hdmi_4xxx_pll_disable(struct hdmi_ip_data *ip_data);
181void ti_hdmi_4xxx_basic_configure(struct hdmi_ip_data *ip_data);
Mythri P K162874d2011-09-22 13:37:45 +0530[diff] [blame]182void ti_hdmi_4xxx_wp_dump(struct hdmi_ip_data *ip_data, struct seq_file *s);
183void ti_hdmi_4xxx_pll_dump(struct hdmi_ip_data *ip_data, struct seq_file *s);
184void ti_hdmi_4xxx_core_dump(struct hdmi_ip_data *ip_data, struct seq_file *s);
185void ti_hdmi_4xxx_phy_dump(struct hdmi_ip_data *ip_data, struct seq_file *s);
Ricardo Neri80a48592011-11-27 16:09:58 -0600[diff] [blame]186#if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
187 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
Ricardo Neri027bdc82012-04-20 17:17:46 -0500[diff] [blame^]188int ti_hdmi_4xxx_wp_audio_enable(struct hdmi_ip_data *ip_data);
189void ti_hdmi_4xxx_wp_audio_disable(struct hdmi_ip_data *ip_data);
Ricardo Neri80a48592011-11-27 16:09:58 -0600[diff] [blame]190#endif
Mythri P K94c52982011-09-08 19:06:21 +0530[diff] [blame]191#endif