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gerrit-public.fairphone.software / kernel / msm-5.4 / 041627790b02af1f68c003018ecfa868b02f4191 / . / arch / arm / boot / dts / am33xx.dtsi
blob: d37f95025807708a9c486d1e6f6365f9960286b5 [file] [log] [blame]
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]1/*
2 * Device Tree Source for AM33XX SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
Florian Vaussarde94233c2013-06-03 16:12:23 +0200[diff] [blame]11#include <dt-bindings/gpio/gpio.h>
Florian Vaussard6a8a6b62013-06-03 16:12:25 +0200[diff] [blame]12#include <dt-bindings/pinctrl/am33xx.h>
Florian Vaussarde94233c2013-06-03 16:12:23 +0200[diff] [blame]13
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]14/ {
15 compatible = "ti,am33xx";
Benoit Cousson4c94ac22012-10-24 10:47:52 +0200[diff] [blame]16 interrupt-parent = <&intc>;
Javier Martinez Canillasf8bf0162016-08-31 12:35:21 +0200[diff] [blame]17 #address-cells = <1>;
18 #size-cells = <1>;
Javier Martinez Canillas1d8d6d32016-12-19 11:44:37 -0300[diff] [blame]19 chosen { };
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]20
21 aliases {
Nishanth Menon6a968672013-10-16 15:21:04 -0500[diff] [blame]22 i2c0 = &i2c0;
23 i2c1 = &i2c1;
24 i2c2 = &i2c2;
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]25 serial0 = &uart0;
26 serial1 = &uart1;
27 serial2 = &uart2;
28 serial3 = &uart3;
29 serial4 = &uart4;
30 serial5 = &uart5;
AnilKumar Ch7a57ee82012-11-14 23:38:24 +0530[diff] [blame]31 d_can0 = &dcan0;
32 d_can1 = &dcan1;
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]33 usb0 = &usb0;
34 usb1 = &usb1;
35 phy0 = &usb0_phy;
36 phy1 = &usb1_phy;
Dan Murphy81700562013-10-02 12:58:33 -0500[diff] [blame]37 ethernet0 = &cpsw_emac0;
38 ethernet1 = &cpsw_emac1;
Suniel Maheshcddfae22017-09-11 12:00:16 +0530[diff] [blame]39 spi0 = &spi0;
40 spi1 = &spi1;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]41 };
42
43 cpus {
Lorenzo Pieralisi2e0d5132013-04-18 18:35:59 +0100[diff] [blame]44 #address-cells = <1>;
45 #size-cells = <0>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]46 cpu@0 {
47 compatible = "arm,cortex-a8";
Lorenzo Pieralisi2e0d5132013-04-18 18:35:59 +0100[diff] [blame]48 device_type = "cpu";
49 reg = <0>;
AnilKumar Chefeedcf2012-08-31 15:07:20 +0530[diff] [blame]50
Dave Gerlach72ac40f2017-03-06 09:23:38 -0600[diff] [blame]51 operating-points-v2 = <&cpu0_opp_table>;
Nishanth Menon8d766fa2014-01-29 12:19:17 -0600[diff] [blame]52
53 clocks = <&dpll_mpu_ck>;
54 clock-names = "cpu";
55
AnilKumar Chefeedcf2012-08-31 15:07:20 +0530[diff] [blame]56 clock-latency = <300000>; /* From omap-cpufreq driver */
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]57 };
58 };
59
Dave Gerlach72ac40f2017-03-06 09:23:38 -0600[diff] [blame]60 cpu0_opp_table: opp-table {
61 compatible = "operating-points-v2-ti-cpu";
62 syscon = <&scm_conf>;
63
64 /*
65 * The three following nodes are marked with opp-suspend
66 * because the can not be enabled simultaneously on a
67 * single SoC.
68 */
Viresh Kumarb9cb2ba2017-04-20 16:25:06 +0530[diff] [blame]69 opp50-300000000 {
Dave Gerlach72ac40f2017-03-06 09:23:38 -0600[diff] [blame]70 opp-hz = /bits/ 64 <300000000>;
71 opp-microvolt = <950000 931000 969000>;
72 opp-supported-hw = <0x06 0x0010>;
73 opp-suspend;
74 };
75
Viresh Kumarb9cb2ba2017-04-20 16:25:06 +0530[diff] [blame]76 opp100-275000000 {
Dave Gerlach72ac40f2017-03-06 09:23:38 -0600[diff] [blame]77 opp-hz = /bits/ 64 <275000000>;
78 opp-microvolt = <1100000 1078000 1122000>;
79 opp-supported-hw = <0x01 0x00FF>;
80 opp-suspend;
81 };
82
Viresh Kumarb9cb2ba2017-04-20 16:25:06 +0530[diff] [blame]83 opp100-300000000 {
Dave Gerlach72ac40f2017-03-06 09:23:38 -0600[diff] [blame]84 opp-hz = /bits/ 64 <300000000>;
85 opp-microvolt = <1100000 1078000 1122000>;
86 opp-supported-hw = <0x06 0x0020>;
87 opp-suspend;
88 };
89
Viresh Kumarb9cb2ba2017-04-20 16:25:06 +0530[diff] [blame]90 opp100-500000000 {
Dave Gerlach72ac40f2017-03-06 09:23:38 -0600[diff] [blame]91 opp-hz = /bits/ 64 <500000000>;
92 opp-microvolt = <1100000 1078000 1122000>;
93 opp-supported-hw = <0x01 0xFFFF>;
94 };
95
Viresh Kumarb9cb2ba2017-04-20 16:25:06 +0530[diff] [blame]96 opp100-600000000 {
Dave Gerlach72ac40f2017-03-06 09:23:38 -0600[diff] [blame]97 opp-hz = /bits/ 64 <600000000>;
98 opp-microvolt = <1100000 1078000 1122000>;
99 opp-supported-hw = <0x06 0x0040>;
100 };
101
Viresh Kumarb9cb2ba2017-04-20 16:25:06 +0530[diff] [blame]102 opp120-600000000 {
Dave Gerlach72ac40f2017-03-06 09:23:38 -0600[diff] [blame]103 opp-hz = /bits/ 64 <600000000>;
104 opp-microvolt = <1200000 1176000 1224000>;
105 opp-supported-hw = <0x01 0xFFFF>;
106 };
107
Viresh Kumarb9cb2ba2017-04-20 16:25:06 +0530[diff] [blame]108 opp120-720000000 {
Dave Gerlach72ac40f2017-03-06 09:23:38 -0600[diff] [blame]109 opp-hz = /bits/ 64 <720000000>;
110 opp-microvolt = <1200000 1176000 1224000>;
111 opp-supported-hw = <0x06 0x0080>;
112 };
113
Viresh Kumarb9cb2ba2017-04-20 16:25:06 +0530[diff] [blame]114 oppturbo-720000000 {
Dave Gerlach72ac40f2017-03-06 09:23:38 -0600[diff] [blame]115 opp-hz = /bits/ 64 <720000000>;
116 opp-microvolt = <1260000 1234800 1285200>;
117 opp-supported-hw = <0x01 0xFFFF>;
118 };
119
Viresh Kumarb9cb2ba2017-04-20 16:25:06 +0530[diff] [blame]120 oppturbo-800000000 {
Dave Gerlach72ac40f2017-03-06 09:23:38 -0600[diff] [blame]121 opp-hz = /bits/ 64 <800000000>;
122 opp-microvolt = <1260000 1234800 1285200>;
123 opp-supported-hw = <0x06 0x0100>;
124 };
125
Viresh Kumarb9cb2ba2017-04-20 16:25:06 +0530[diff] [blame]126 oppnitro-1000000000 {
Dave Gerlach72ac40f2017-03-06 09:23:38 -0600[diff] [blame]127 opp-hz = /bits/ 64 <1000000000>;
128 opp-microvolt = <1325000 1298500 1351500>;
129 opp-supported-hw = <0x04 0x0200>;
130 };
131 };
132
Tony Lindgrencd57dc52017-08-30 08:19:52 -0700[diff] [blame]133 pmu@4b000000 {
Alexandre Belloni6797cdb2013-08-03 20:00:54 +0200[diff] [blame]134 compatible = "arm,cortex-a8-pmu";
135 interrupts = <3>;
Tony Lindgrencd57dc52017-08-30 08:19:52 -0700[diff] [blame]136 reg = <0x4b000000 0x1000000>;
137 ti,hwmods = "debugss";
Alexandre Belloni6797cdb2013-08-03 20:00:54 +0200[diff] [blame]138 };
139
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]140 /*
Geert Uytterhoeven5c5be9d2014-03-28 11:11:37 +0100[diff] [blame]141 * The soc node represents the soc top level view. It is used for IPs
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]142 * that are not memory mapped in the MPU view or for the MPU itself.
143 */
144 soc {
145 compatible = "ti,omap-infra";
146 mpu {
147 compatible = "ti,omap3-mpu";
148 ti,hwmods = "mpu";
149 };
150 };
151
152 /*
153 * XXX: Use a flat representation of the AM33XX interconnect.
Geert Uytterhoevenb7ab5242014-03-28 11:11:39 +0100[diff] [blame]154 * The real AM33XX interconnect network is quite complex. Since
155 * it will not bring real advantage to represent that in DT
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]156 * for the moment, just use a fake OCP bus entry to represent
157 * the whole bus hierarchy.
158 */
159 ocp {
160 compatible = "simple-bus";
161 #address-cells = <1>;
162 #size-cells = <1>;
163 ranges;
164 ti,hwmods = "l3_main";
165
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]166 l4_wkup: l4_wkup@44c00000 {
167 compatible = "ti,am3-l4-wkup", "simple-bus";
168 #address-cells = <1>;
169 #size-cells = <1>;
170 ranges = <0 0x44c00000 0x280000>;
Tero Kristoea291c92013-07-18 18:15:35 +0300[diff] [blame]171
Suman Annad129be22015-07-13 12:34:54 -0500[diff] [blame]172 wkup_m3: wkup_m3@100000 {
173 compatible = "ti,am3352-wkup-m3";
174 reg = <0x100000 0x4000>,
175 <0x180000 0x2000>;
176 reg-names = "umem", "dmem";
177 ti,hwmods = "wkup_m3";
178 ti,pm-firmware = "am335x-pm-firmware.elf";
179 };
180
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]181 prcm: prcm@200000 {
182 compatible = "ti,am3-prcm";
183 reg = <0x200000 0x4000>;
184
185 prcm_clocks: clocks {
186 #address-cells = <1>;
187 #size-cells = <0>;
188 };
189
190 prcm_clockdomains: clockdomains {
191 };
192 };
193
194 scm: scm@210000 {
195 compatible = "ti,am3-scm", "simple-bus";
196 reg = <0x210000 0x2000>;
Tero Kristoea291c92013-07-18 18:15:35 +0300[diff] [blame]197 #address-cells = <1>;
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]198 #size-cells = <1>;
Tony Lindgrenbe76fd32016-11-07 08:27:49 -0700[diff] [blame]199 #pinctrl-cells = <1>;
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]200 ranges = <0 0x210000 0x2000>;
201
202 am33xx_pinmux: pinmux@800 {
203 compatible = "pinctrl-single";
204 reg = <0x800 0x238>;
205 #address-cells = <1>;
206 #size-cells = <0>;
Tony Lindgrenbe76fd32016-11-07 08:27:49 -0700[diff] [blame]207 #pinctrl-cells = <1>;
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]208 pinctrl-single,register-width = <32>;
209 pinctrl-single,function-mask = <0x7f>;
210 };
211
212 scm_conf: scm_conf@0 {
Tony Lindgren1aa09df2017-01-05 11:10:40 -0800[diff] [blame]213 compatible = "syscon", "simple-bus";
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]214 reg = <0x0 0x800>;
215 #address-cells = <1>;
216 #size-cells = <1>;
Tony Lindgren1aa09df2017-01-05 11:10:40 -0800[diff] [blame]217 ranges = <0 0 0x800>;
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]218
219 scm_clocks: clocks {
220 #address-cells = <1>;
221 #size-cells = <0>;
222 };
223 };
224
Suman Anna99937122015-07-17 16:08:03 -0500[diff] [blame]225 wkup_m3_ipc: wkup_m3_ipc@1324 {
226 compatible = "ti,am3352-wkup-m3-ipc";
227 reg = <0x1324 0x24>;
228 interrupts = <78>;
229 ti,rproc = <&wkup_m3>;
230 mboxes = <&mailbox &mbox_wkupm3>;
231 };
232
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]233 edma_xbar: dma-router@f90 {
234 compatible = "ti,am335x-edma-crossbar";
235 reg = <0xf90 0x40>;
236 #dma-cells = <3>;
237 dma-requests = <32>;
238 dma-masters = <&edma>;
239 };
240
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]241 scm_clockdomains: clockdomains {
242 };
Tero Kristoea291c92013-07-18 18:15:35 +0300[diff] [blame]243 };
Markus Pargmannc9aaf872014-09-29 08:53:18 +0200[diff] [blame]244 };
245
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]246 intc: interrupt-controller@48200000 {
Felipe Balbicab82b72014-09-08 17:54:48 -0700[diff] [blame]247 compatible = "ti,am33xx-intc";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]248 interrupt-controller;
249 #interrupt-cells = <1>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]250 reg = <0x48200000 0x1000>;
251 };
252
Matt Porter505975d2013-09-10 14:24:37 -0500[diff] [blame]253 edma: edma@49000000 {
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]254 compatible = "ti,edma3-tpcc";
255 ti,hwmods = "tpcc";
256 reg = <0x49000000 0x10000>;
257 reg-names = "edma3_cc";
Matt Porter505975d2013-09-10 14:24:37 -0500[diff] [blame]258 interrupts = <12 13 14>;
Robert P. J. Daya5206552016-05-24 17:20:28 -0400[diff] [blame]259 interrupt-names = "edma3_ccint", "edma3_mperr",
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]260 "edma3_ccerrint";
261 dma-requests = <64>;
262 #dma-cells = <2>;
263
264 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
265 <&edma_tptc2 0>;
266
267 ti,edma-memcpy-channels = <20 21>;
268 };
269
270 edma_tptc0: tptc@49800000 {
271 compatible = "ti,edma3-tptc";
272 ti,hwmods = "tptc0";
273 reg = <0x49800000 0x100000>;
274 interrupts = <112>;
275 interrupt-names = "edma3_tcerrint";
276 };
277
278 edma_tptc1: tptc@49900000 {
279 compatible = "ti,edma3-tptc";
280 ti,hwmods = "tptc1";
281 reg = <0x49900000 0x100000>;
282 interrupts = <113>;
283 interrupt-names = "edma3_tcerrint";
284 };
285
286 edma_tptc2: tptc@49a00000 {
287 compatible = "ti,edma3-tptc";
288 ti,hwmods = "tptc2";
289 reg = <0x49a00000 0x100000>;
290 interrupts = <114>;
291 interrupt-names = "edma3_tcerrint";
Matt Porter505975d2013-09-10 14:24:37 -0500[diff] [blame]292 };
293
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]294 gpio0: gpio@44e07000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]295 compatible = "ti,omap4-gpio";
296 ti,hwmods = "gpio1";
297 gpio-controller;
298 #gpio-cells = <2>;
299 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]300 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]301 reg = <0x44e07000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]302 interrupts = <96>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]303 };
304
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]305 gpio1: gpio@4804c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]306 compatible = "ti,omap4-gpio";
307 ti,hwmods = "gpio2";
308 gpio-controller;
309 #gpio-cells = <2>;
310 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]311 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]312 reg = <0x4804c000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]313 interrupts = <98>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]314 };
315
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]316 gpio2: gpio@481ac000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]317 compatible = "ti,omap4-gpio";
318 ti,hwmods = "gpio3";
319 gpio-controller;
320 #gpio-cells = <2>;
321 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]322 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]323 reg = <0x481ac000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]324 interrupts = <32>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]325 };
326
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]327 gpio3: gpio@481ae000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]328 compatible = "ti,omap4-gpio";
329 ti,hwmods = "gpio4";
330 gpio-controller;
331 #gpio-cells = <2>;
332 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]333 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]334 reg = <0x481ae000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]335 interrupts = <62>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]336 };
337
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]338 uart0: serial@44e09000 {
Sekhar Nori4fcdff92015-07-14 13:32:06 +0530[diff] [blame]339 compatible = "ti,am3352-uart", "ti,omap3-uart";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]340 ti,hwmods = "uart1";
341 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]342 reg = <0x44e09000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]343 interrupts = <72>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]344 status = "disabled";
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]345 dmas = <&edma 26 0>, <&edma 27 0>;
Sebastian Andrzej Siewior13fd3d52014-09-29 20:06:46 +0200[diff] [blame]346 dma-names = "tx", "rx";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]347 };
348
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]349 uart1: serial@48022000 {
Sekhar Nori4fcdff92015-07-14 13:32:06 +0530[diff] [blame]350 compatible = "ti,am3352-uart", "ti,omap3-uart";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]351 ti,hwmods = "uart2";
352 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]353 reg = <0x48022000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]354 interrupts = <73>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]355 status = "disabled";
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]356 dmas = <&edma 28 0>, <&edma 29 0>;
Sebastian Andrzej Siewior13fd3d52014-09-29 20:06:46 +0200[diff] [blame]357 dma-names = "tx", "rx";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]358 };
359
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]360 uart2: serial@48024000 {
Sekhar Nori4fcdff92015-07-14 13:32:06 +0530[diff] [blame]361 compatible = "ti,am3352-uart", "ti,omap3-uart";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]362 ti,hwmods = "uart3";
363 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]364 reg = <0x48024000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]365 interrupts = <74>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]366 status = "disabled";
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]367 dmas = <&edma 30 0>, <&edma 31 0>;
Sebastian Andrzej Siewior13fd3d52014-09-29 20:06:46 +0200[diff] [blame]368 dma-names = "tx", "rx";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]369 };
370
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]371 uart3: serial@481a6000 {
Sekhar Nori4fcdff92015-07-14 13:32:06 +0530[diff] [blame]372 compatible = "ti,am3352-uart", "ti,omap3-uart";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]373 ti,hwmods = "uart4";
374 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]375 reg = <0x481a6000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]376 interrupts = <44>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]377 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]378 };
379
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]380 uart4: serial@481a8000 {
Sekhar Nori4fcdff92015-07-14 13:32:06 +0530[diff] [blame]381 compatible = "ti,am3352-uart", "ti,omap3-uart";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]382 ti,hwmods = "uart5";
383 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]384 reg = <0x481a8000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]385 interrupts = <45>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]386 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]387 };
388
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]389 uart5: serial@481aa000 {
Sekhar Nori4fcdff92015-07-14 13:32:06 +0530[diff] [blame]390 compatible = "ti,am3352-uart", "ti,omap3-uart";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]391 ti,hwmods = "uart6";
392 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]393 reg = <0x481aa000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]394 interrupts = <46>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]395 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]396 };
397
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]398 i2c0: i2c@44e0b000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]399 compatible = "ti,omap4-i2c";
400 #address-cells = <1>;
401 #size-cells = <0>;
402 ti,hwmods = "i2c1";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]403 reg = <0x44e0b000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]404 interrupts = <70>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]405 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]406 };
407
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]408 i2c1: i2c@4802a000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]409 compatible = "ti,omap4-i2c";
410 #address-cells = <1>;
411 #size-cells = <0>;
412 ti,hwmods = "i2c2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]413 reg = <0x4802a000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]414 interrupts = <71>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]415 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]416 };
417
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]418 i2c2: i2c@4819c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]419 compatible = "ti,omap4-i2c";
420 #address-cells = <1>;
421 #size-cells = <0>;
422 ti,hwmods = "i2c3";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]423 reg = <0x4819c000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]424 interrupts = <30>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]425 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]426 };
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]427
Matt Porter55b44522013-09-10 14:24:39 -0500[diff] [blame]428 mmc1: mmc@48060000 {
429 compatible = "ti,omap4-hsmmc";
430 ti,hwmods = "mmc1";
431 ti,dual-volt;
432 ti,needs-special-reset;
433 ti,needs-special-hs-handling;
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]434 dmas = <&edma_xbar 24 0 0
435 &edma_xbar 25 0 0>;
Matt Porter55b44522013-09-10 14:24:39 -0500[diff] [blame]436 dma-names = "tx", "rx";
437 interrupts = <64>;
Matt Porter55b44522013-09-10 14:24:39 -0500[diff] [blame]438 reg = <0x48060000 0x1000>;
439 status = "disabled";
440 };
441
442 mmc2: mmc@481d8000 {
443 compatible = "ti,omap4-hsmmc";
444 ti,hwmods = "mmc2";
445 ti,needs-special-reset;
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]446 dmas = <&edma 2 0
447 &edma 3 0>;
Matt Porter55b44522013-09-10 14:24:39 -0500[diff] [blame]448 dma-names = "tx", "rx";
449 interrupts = <28>;
Matt Porter55b44522013-09-10 14:24:39 -0500[diff] [blame]450 reg = <0x481d8000 0x1000>;
451 status = "disabled";
452 };
453
454 mmc3: mmc@47810000 {
455 compatible = "ti,omap4-hsmmc";
456 ti,hwmods = "mmc3";
457 ti,needs-special-reset;
458 interrupts = <29>;
Matt Porter55b44522013-09-10 14:24:39 -0500[diff] [blame]459 reg = <0x47810000 0x1000>;
460 status = "disabled";
461 };
462
Suman Annad4cbe802013-10-10 16:15:35 -0500[diff] [blame]463 hwspinlock: spinlock@480ca000 {
464 compatible = "ti,omap4-hwspinlock";
465 reg = <0x480ca000 0x1000>;
466 ti,hwmods = "spinlock";
Suman Anna34054212014-01-13 18:26:45 -0600[diff] [blame]467 #hwlock-cells = <1>;
Suman Annad4cbe802013-10-10 16:15:35 -0500[diff] [blame]468 };
469
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]470 wdt2: wdt@44e35000 {
471 compatible = "ti,omap3-wdt";
472 ti,hwmods = "wd_timer2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]473 reg = <0x44e35000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]474 interrupts = <91>;
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]475 };
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]476
Roger Quadrose23aabc2014-09-09 16:15:35 +0300[diff] [blame]477 dcan0: can@481cc000 {
478 compatible = "ti,am3352-d_can";
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]479 ti,hwmods = "d_can0";
Roger Quadrose23aabc2014-09-09 16:15:35 +0300[diff] [blame]480 reg = <0x481cc000 0x2000>;
481 clocks = <&dcan0_fck>;
482 clock-names = "fck";
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]483 syscon-raminit = <&scm_conf 0x644 0>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]484 interrupts = <52>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]485 status = "disabled";
486 };
487
Roger Quadrose23aabc2014-09-09 16:15:35 +0300[diff] [blame]488 dcan1: can@481d0000 {
489 compatible = "ti,am3352-d_can";
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]490 ti,hwmods = "d_can1";
Roger Quadrose23aabc2014-09-09 16:15:35 +0300[diff] [blame]491 reg = <0x481d0000 0x2000>;
492 clocks = <&dcan1_fck>;
493 clock-names = "fck";
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]494 syscon-raminit = <&scm_conf 0x644 1>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]495 interrupts = <55>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]496 status = "disabled";
497 };
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]498
Suman Anna40242302014-07-11 16:44:36 -0500[diff] [blame]499 mailbox: mailbox@480C8000 {
500 compatible = "ti,omap4-mailbox";
501 reg = <0x480C8000 0x200>;
502 interrupts = <77>;
503 ti,hwmods = "mailbox";
Suman Anna24df0452014-11-03 17:07:35 -0600[diff] [blame]504 #mbox-cells = <1>;
Suman Anna40242302014-07-11 16:44:36 -0500[diff] [blame]505 ti,mbox-num-users = <4>;
506 ti,mbox-num-fifos = <8>;
Suman Annad27704d2014-09-10 14:27:23 -0500[diff] [blame]507 mbox_wkupm3: wkup_m3 {
Dave Gerlach2800971f2015-07-17 16:08:01 -0500[diff] [blame]508 ti,mbox-send-noirq;
Suman Annad27704d2014-09-10 14:27:23 -0500[diff] [blame]509 ti,mbox-tx = <0 0 0>;
510 ti,mbox-rx = <0 0 3>;
511 };
Suman Anna40242302014-07-11 16:44:36 -0500[diff] [blame]512 };
513
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]514 timer1: timer@44e31000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]515 compatible = "ti,am335x-timer-1ms";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]516 reg = <0x44e31000 0x400>;
517 interrupts = <67>;
518 ti,hwmods = "timer1";
519 ti,timer-alwon;
520 };
521
522 timer2: timer@48040000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]523 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]524 reg = <0x48040000 0x400>;
525 interrupts = <68>;
526 ti,hwmods = "timer2";
527 };
528
529 timer3: timer@48042000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]530 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]531 reg = <0x48042000 0x400>;
532 interrupts = <69>;
533 ti,hwmods = "timer3";
534 };
535
536 timer4: timer@48044000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]537 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]538 reg = <0x48044000 0x400>;
539 interrupts = <92>;
540 ti,hwmods = "timer4";
541 ti,timer-pwm;
542 };
543
544 timer5: timer@48046000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]545 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]546 reg = <0x48046000 0x400>;
547 interrupts = <93>;
548 ti,hwmods = "timer5";
549 ti,timer-pwm;
550 };
551
552 timer6: timer@48048000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]553 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]554 reg = <0x48048000 0x400>;
555 interrupts = <94>;
556 ti,hwmods = "timer6";
557 ti,timer-pwm;
558 };
559
560 timer7: timer@4804a000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]561 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]562 reg = <0x4804a000 0x400>;
563 interrupts = <95>;
564 ti,hwmods = "timer7";
565 ti,timer-pwm;
566 };
Afzal Mohammed0d935c12012-10-30 15:04:01 +0530[diff] [blame]567
Stefan Roeseccd8b9e2014-02-05 13:12:39 +0100[diff] [blame]568 rtc: rtc@44e3e000 {
Johan Hovold6ac7b4a2014-12-10 15:53:25 -0800[diff] [blame]569 compatible = "ti,am3352-rtc", "ti,da830-rtc";
Afzal Mohammed0d935c12012-10-30 15:04:01 +0530[diff] [blame]570 reg = <0x44e3e000 0x1000>;
571 interrupts = <75
572 76>;
573 ti,hwmods = "rtc";
Keerthy17fad5f2016-10-27 11:18:06 +0530[diff] [blame]574 clocks = <&clkdiv32k_ick>;
575 clock-names = "int-clk";
Afzal Mohammed0d935c12012-10-30 15:04:01 +0530[diff] [blame]576 };
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]577
578 spi0: spi@48030000 {
579 compatible = "ti,omap4-mcspi";
580 #address-cells = <1>;
581 #size-cells = <0>;
582 reg = <0x48030000 0x400>;
Philip Avinash7b3754c2013-02-01 11:07:27 +0530[diff] [blame]583 interrupts = <65>;
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]584 ti,spi-num-cs = <2>;
585 ti,hwmods = "spi0";
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]586 dmas = <&edma 16 0
587 &edma 17 0
588 &edma 18 0
589 &edma 19 0>;
Matt Porterf5e2f802013-09-10 14:24:38 -0500[diff] [blame]590 dma-names = "tx0", "rx0", "tx1", "rx1";
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]591 status = "disabled";
592 };
593
594 spi1: spi@481a0000 {
595 compatible = "ti,omap4-mcspi";
596 #address-cells = <1>;
597 #size-cells = <0>;
598 reg = <0x481a0000 0x400>;
Philip Avinash7b3754c2013-02-01 11:07:27 +0530[diff] [blame]599 interrupts = <125>;
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]600 ti,spi-num-cs = <2>;
601 ti,hwmods = "spi1";
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]602 dmas = <&edma 42 0
603 &edma 43 0
604 &edma 44 0
605 &edma 45 0>;
Matt Porterf5e2f802013-09-10 14:24:38 -0500[diff] [blame]606 dma-names = "tx0", "rx0", "tx1", "rx1";
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]607 status = "disabled";
608 };
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]609
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]610 usb: usb@47400000 {
611 compatible = "ti,am33xx-usb";
612 reg = <0x47400000 0x1000>;
613 ranges;
614 #address-cells = <1>;
615 #size-cells = <1>;
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]616 ti,hwmods = "usb_otg_hs";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]617 status = "disabled";
618
Mugunthan V N8abcdd62014-03-06 18:01:34 +0530[diff] [blame]619 usb_ctrl_mod: control@44e10620 {
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]620 compatible = "ti,am335x-usb-ctrl-module";
621 reg = <0x44e10620 0x10
622 0x44e10648 0x4>;
623 reg-names = "phy_ctrl", "wakeup";
624 status = "disabled";
625 };
626
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]627 usb0_phy: usb-phy@47401300 {
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]628 compatible = "ti,am335x-usb-phy";
629 reg = <0x47401300 0x100>;
630 reg-names = "phy";
631 status = "disabled";
Markus Pargmanne7243b72013-10-14 14:49:21 +0200[diff] [blame]632 ti,ctrl_mod = <&usb_ctrl_mod>;
Rob Herringf0e11ff82017-11-09 16:26:14 -0600[diff] [blame]633 #phy-cells = <0>;
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]634 };
635
636 usb0: usb@47401000 {
637 compatible = "ti,musb-am33xx";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]638 status = "disabled";
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]639 reg = <0x47401400 0x400
640 0x47401000 0x200>;
641 reg-names = "mc", "control";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]642
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]643 interrupts = <18>;
644 interrupt-names = "mc";
645 dr_mode = "otg";
646 mentor,multipoint = <1>;
647 mentor,num-eps = <16>;
648 mentor,ram-bits = <12>;
649 mentor,power = <500>;
650 phys = <&usb0_phy>;
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]651
652 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
653 &cppi41dma 2 0 &cppi41dma 3 0
654 &cppi41dma 4 0 &cppi41dma 5 0
655 &cppi41dma 6 0 &cppi41dma 7 0
656 &cppi41dma 8 0 &cppi41dma 9 0
657 &cppi41dma 10 0 &cppi41dma 11 0
658 &cppi41dma 12 0 &cppi41dma 13 0
659 &cppi41dma 14 0 &cppi41dma 0 1
660 &cppi41dma 1 1 &cppi41dma 2 1
661 &cppi41dma 3 1 &cppi41dma 4 1
662 &cppi41dma 5 1 &cppi41dma 6 1
663 &cppi41dma 7 1 &cppi41dma 8 1
664 &cppi41dma 9 1 &cppi41dma 10 1
665 &cppi41dma 11 1 &cppi41dma 12 1
666 &cppi41dma 13 1 &cppi41dma 14 1>;
667 dma-names =
668 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
669 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
670 "rx14", "rx15",
671 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
672 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
673 "tx14", "tx15";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]674 };
675
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]676 usb1_phy: usb-phy@47401b00 {
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]677 compatible = "ti,am335x-usb-phy";
678 reg = <0x47401b00 0x100>;
679 reg-names = "phy";
680 status = "disabled";
Markus Pargmanne7243b72013-10-14 14:49:21 +0200[diff] [blame]681 ti,ctrl_mod = <&usb_ctrl_mod>;
Rob Herringf0e11ff82017-11-09 16:26:14 -0600[diff] [blame]682 #phy-cells = <0>;
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]683 };
684
685 usb1: usb@47401800 {
686 compatible = "ti,musb-am33xx";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]687 status = "disabled";
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]688 reg = <0x47401c00 0x400
689 0x47401800 0x200>;
690 reg-names = "mc", "control";
691 interrupts = <19>;
692 interrupt-names = "mc";
693 dr_mode = "otg";
694 mentor,multipoint = <1>;
695 mentor,num-eps = <16>;
696 mentor,ram-bits = <12>;
697 mentor,power = <500>;
698 phys = <&usb1_phy>;
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]699
700 dmas = <&cppi41dma 15 0 &cppi41dma 16 0
701 &cppi41dma 17 0 &cppi41dma 18 0
702 &cppi41dma 19 0 &cppi41dma 20 0
703 &cppi41dma 21 0 &cppi41dma 22 0
704 &cppi41dma 23 0 &cppi41dma 24 0
705 &cppi41dma 25 0 &cppi41dma 26 0
706 &cppi41dma 27 0 &cppi41dma 28 0
707 &cppi41dma 29 0 &cppi41dma 15 1
708 &cppi41dma 16 1 &cppi41dma 17 1
709 &cppi41dma 18 1 &cppi41dma 19 1
710 &cppi41dma 20 1 &cppi41dma 21 1
711 &cppi41dma 22 1 &cppi41dma 23 1
712 &cppi41dma 24 1 &cppi41dma 25 1
713 &cppi41dma 26 1 &cppi41dma 27 1
714 &cppi41dma 28 1 &cppi41dma 29 1>;
715 dma-names =
716 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
717 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
718 "rx14", "rx15",
719 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
720 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
721 "tx14", "tx15";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]722 };
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]723
Mugunthan V N8abcdd62014-03-06 18:01:34 +0530[diff] [blame]724 cppi41dma: dma-controller@47402000 {
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]725 compatible = "ti,am3359-cppi41";
726 reg = <0x47400000 0x1000
727 0x47402000 0x1000
728 0x47403000 0x1000
729 0x47404000 0x4000>;
Sebastian Andrzej Siewior3b6394b2013-08-20 18:35:45 +0200[diff] [blame]730 reg-names = "glue", "controller", "scheduler", "queuemgr";
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]731 interrupts = <17>;
732 interrupt-names = "glue";
733 #dma-cells = <2>;
734 #dma-channels = <30>;
735 #dma-requests = <256>;
736 status = "disabled";
737 };
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]738 };
Linus Torvalds6be35c72012-12-12 18:07:07 -0800[diff] [blame]739
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]740 epwmss0: epwmss@48300000 {
741 compatible = "ti,am33xx-pwmss";
742 reg = <0x48300000 0x10>;
743 ti,hwmods = "epwmss0";
744 #address-cells = <1>;
745 #size-cells = <1>;
746 status = "disabled";
747 ranges = <0x48300100 0x48300100 0x80 /* ECAP */
748 0x48300180 0x48300180 0x80 /* EQEP */
749 0x48300200 0x48300200 0x80>; /* EHRPWM */
750
751 ecap0: ecap@48300100 {
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]752 compatible = "ti,am3352-ecap",
753 "ti,am33xx-ecap";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]754 #pwm-cells = <3>;
755 reg = <0x48300100 0x80>;
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]756 clocks = <&l4ls_gclk>;
757 clock-names = "fck";
Matt Portere8c85a32014-01-29 15:59:59 -0500[diff] [blame]758 interrupts = <31>;
759 interrupt-names = "ecap0";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]760 status = "disabled";
761 };
762
Franklin S Cooper Jrdce2a652016-03-17 20:15:22 -0500[diff] [blame]763 ehrpwm0: pwm@48300200 {
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]764 compatible = "ti,am3352-ehrpwm",
765 "ti,am33xx-ehrpwm";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]766 #pwm-cells = <3>;
767 reg = <0x48300200 0x80>;
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]768 clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
769 clock-names = "tbclk", "fck";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]770 status = "disabled";
771 };
772 };
773
774 epwmss1: epwmss@48302000 {
775 compatible = "ti,am33xx-pwmss";
776 reg = <0x48302000 0x10>;
777 ti,hwmods = "epwmss1";
778 #address-cells = <1>;
779 #size-cells = <1>;
780 status = "disabled";
781 ranges = <0x48302100 0x48302100 0x80 /* ECAP */
782 0x48302180 0x48302180 0x80 /* EQEP */
783 0x48302200 0x48302200 0x80>; /* EHRPWM */
784
785 ecap1: ecap@48302100 {
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]786 compatible = "ti,am3352-ecap",
787 "ti,am33xx-ecap";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]788 #pwm-cells = <3>;
789 reg = <0x48302100 0x80>;
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]790 clocks = <&l4ls_gclk>;
791 clock-names = "fck";
Matt Portere8c85a32014-01-29 15:59:59 -0500[diff] [blame]792 interrupts = <47>;
793 interrupt-names = "ecap1";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]794 status = "disabled";
795 };
796
Franklin S Cooper Jrdce2a652016-03-17 20:15:22 -0500[diff] [blame]797 ehrpwm1: pwm@48302200 {
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]798 compatible = "ti,am3352-ehrpwm",
799 "ti,am33xx-ehrpwm";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]800 #pwm-cells = <3>;
801 reg = <0x48302200 0x80>;
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]802 clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>;
803 clock-names = "tbclk", "fck";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]804 status = "disabled";
805 };
806 };
807
808 epwmss2: epwmss@48304000 {
809 compatible = "ti,am33xx-pwmss";
810 reg = <0x48304000 0x10>;
811 ti,hwmods = "epwmss2";
812 #address-cells = <1>;
813 #size-cells = <1>;
814 status = "disabled";
815 ranges = <0x48304100 0x48304100 0x80 /* ECAP */
816 0x48304180 0x48304180 0x80 /* EQEP */
817 0x48304200 0x48304200 0x80>; /* EHRPWM */
818
819 ecap2: ecap@48304100 {
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]820 compatible = "ti,am3352-ecap",
821 "ti,am33xx-ecap";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]822 #pwm-cells = <3>;
823 reg = <0x48304100 0x80>;
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]824 clocks = <&l4ls_gclk>;
825 clock-names = "fck";
Matt Portere8c85a32014-01-29 15:59:59 -0500[diff] [blame]826 interrupts = <61>;
827 interrupt-names = "ecap2";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]828 status = "disabled";
829 };
830
Franklin S Cooper Jrdce2a652016-03-17 20:15:22 -0500[diff] [blame]831 ehrpwm2: pwm@48304200 {
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]832 compatible = "ti,am3352-ehrpwm",
833 "ti,am33xx-ehrpwm";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]834 #pwm-cells = <3>;
835 reg = <0x48304200 0x80>;
Franklin S Cooper Jr229110c2016-05-03 10:56:51 -0500[diff] [blame]836 clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>;
837 clock-names = "tbclk", "fck";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]838 status = "disabled";
839 };
840 };
841
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]842 mac: ethernet@4a100000 {
Mugunthan V N21696f72015-08-12 15:22:55 +0530[diff] [blame]843 compatible = "ti,am335x-cpsw","ti,cpsw";
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]844 ti,hwmods = "cpgmac0";
George Cherian0987a6e2014-05-02 12:01:59 +0530[diff] [blame]845 clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
846 clock-names = "fck", "cpts";
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]847 cpdma_channels = <8>;
848 ale_entries = <1024>;
849 bd_ram_size = <0x2000>;
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]850 mac_control = <0x20>;
851 slaves = <2>;
Mugunthan V Ne86ac132013-03-11 23:16:35 +0000[diff] [blame]852 active_slave = <0>;
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]853 cpts_clock_mult = <0x80000000>;
854 cpts_clock_shift = <29>;
855 reg = <0x4a100000 0x800
856 0x4a101200 0x100>;
857 #address-cells = <1>;
858 #size-cells = <1>;
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]859 /*
860 * c0_rx_thresh_pend
861 * c0_rx_pend
862 * c0_tx_pend
863 * c0_misc_pend
864 */
865 interrupts = <40 41 42 43>;
866 ranges;
Tero Kristoe3bc5352015-03-20 13:08:29 +0200[diff] [blame]867 syscon = <&scm_conf>;
Johan Hovold16c75a12014-05-08 10:57:36 +0200[diff] [blame]868 status = "disabled";
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]869
870 davinci_mdio: mdio@4a101000 {
Grygorii Strashko9efd1a62016-06-24 21:23:55 +0300[diff] [blame]871 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]872 #address-cells = <1>;
873 #size-cells = <0>;
874 ti,hwmods = "davinci_mdio";
875 bus_freq = <1000000>;
876 reg = <0x4a101000 0x100>;
Johan Hovold16c75a12014-05-08 10:57:36 +0200[diff] [blame]877 status = "disabled";
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]878 };
879
880 cpsw_emac0: slave@4a100200 {
881 /* Filled in by U-Boot */
882 mac-address = [ 00 00 00 00 00 00 ];
883 };
884
885 cpsw_emac1: slave@4a100300 {
886 /* Filled in by U-Boot */
887 mac-address = [ 00 00 00 00 00 00 ];
888 };
Mugunthan V N39ffbd92013-09-21 00:50:41 +0530[diff] [blame]889
890 phy_sel: cpsw-phy-sel@44e10650 {
891 compatible = "ti,am3352-cpsw-phy-sel";
892 reg= <0x44e10650 0x4>;
893 reg-names = "gmii-sel";
894 };
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]895 };
Vaibhav Bediaf6575c92013-01-29 16:45:07 +0530[diff] [blame]896
897 ocmcram: ocmcram@40300000 {
Rajendra Nayak8b9a2812014-09-10 11:04:03 -0500[diff] [blame]898 compatible = "mmio-sram";
899 reg = <0x40300000 0x10000>; /* 64k */
Vaibhav Bediaf6575c92013-01-29 16:45:07 +0530[diff] [blame]900 };
901
Philip, Avinash15e82462013-05-31 13:19:03 +0530[diff] [blame]902 elm: elm@48080000 {
903 compatible = "ti,am3352-elm";
904 reg = <0x48080000 0x2000>;
905 interrupts = <4>;
906 ti,hwmods = "elm";
907 status = "disabled";
908 };
909
Benoit Parrotd6cfc1e2013-08-08 18:28:14 -0500[diff] [blame]910 lcdc: lcdc@4830e000 {
911 compatible = "ti,am33xx-tilcdc";
912 reg = <0x4830e000 0x1000>;
Benoit Parrotd6cfc1e2013-08-08 18:28:14 -0500[diff] [blame]913 interrupts = <36>;
914 ti,hwmods = "lcdc";
915 status = "disabled";
916 };
917
Patil, Rachnaa82279d2013-01-24 03:45:12 +0000[diff] [blame]918 tscadc: tscadc@44e0d000 {
919 compatible = "ti,am3359-tscadc";
920 reg = <0x44e0d000 0x1000>;
Patil, Rachnaa82279d2013-01-24 03:45:12 +0000[diff] [blame]921 interrupts = <16>;
922 ti,hwmods = "adc_tsc";
923 status = "disabled";
Mugunthan V N55e871f2016-10-05 14:34:42 +0530[diff] [blame]924 dmas = <&edma 53 0>, <&edma 57 0>;
925 dma-names = "fifo0", "fifo1";
Patil, Rachnaa82279d2013-01-24 03:45:12 +0000[diff] [blame]926
927 tsc {
928 compatible = "ti,am3359-tsc";
929 };
930 am335x_adc: adc {
931 #io-channel-cells = <1>;
932 compatible = "ti,am3359-adc";
933 };
Patil, Rachnaa82279d2013-01-24 03:45:12 +0000[diff] [blame]934 };
935
Tony Lindgrencd57dc52017-08-30 08:19:52 -0700[diff] [blame]936 emif: emif@4c000000 {
937 compatible = "ti,emif-am3352";
938 reg = <0x4c000000 0x1000000>;
939 ti,hwmods = "emif";
940 };
941
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]942 gpmc: gpmc@50000000 {
943 compatible = "ti,am3352-gpmc";
944 ti,hwmods = "gpmc";
Rajendra Nayakf12ecbe22013-10-15 12:37:50 +0530[diff] [blame]945 ti,no-idle-on-init;
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]946 reg = <0x50000000 0x2000>;
947 interrupts = <100>;
Franklin S Cooper Jra2abf902016-03-10 17:56:38 -0600[diff] [blame]948 dmas = <&edma 52 0>;
Franklin S Cooper Jr201c7e32015-10-15 12:37:27 -0500[diff] [blame]949 dma-names = "rxtx";
Lars Poeschel00dddca2013-05-28 10:24:57 +0200[diff] [blame]950 gpmc,num-cs = <7>;
951 gpmc,num-waitpins = <2>;
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]952 #address-cells = <2>;
953 #size-cells = <1>;
Roger Quadros03752142016-02-23 18:37:21 +0200[diff] [blame]954 interrupt-controller;
955 #interrupt-cells = <2>;
Roger Quadros4eb4dd52016-04-07 13:25:32 +0300[diff] [blame]956 gpio-controller;
957 #gpio-cells = <2>;
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]958 status = "disabled";
959 };
Mark A. Greerf8302e12013-08-23 14:12:35 -0700[diff] [blame]960
961 sham: sham@53100000 {
962 compatible = "ti,omap4-sham";
963 ti,hwmods = "sham";
964 reg = <0x53100000 0x200>;
965 interrupts = <109>;
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]966 dmas = <&edma 36 0>;
Mark A. Greerf8302e12013-08-23 14:12:35 -0700[diff] [blame]967 dma-names = "rx";
968 };
Mark A. Greer99919e5e2013-08-23 14:12:36 -0700[diff] [blame]969
970 aes: aes@53500000 {
971 compatible = "ti,omap4-aes";
972 ti,hwmods = "aes";
973 reg = <0x53500000 0xa0>;
Joel Fernandes7af88842013-07-17 19:07:52 -0500[diff] [blame]974 interrupts = <103>;
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]975 dmas = <&edma 6 0>,
976 <&edma 5 0>;
Mark A. Greer99919e5e2013-08-23 14:12:36 -0700[diff] [blame]977 dma-names = "tx", "rx";
978 };
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]979
980 mcasp0: mcasp@48038000 {
981 compatible = "ti,am33xx-mcasp-audio";
982 ti,hwmods = "mcasp0";
Jyri Sarha0bee55a2013-10-20 20:04:09 +0300[diff] [blame]983 reg = <0x48038000 0x2000>,
984 <0x46000000 0x400000>;
985 reg-names = "mpu", "dat";
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]986 interrupts = <80>, <81>;
Geert Uytterhoevenae107d02014-04-22 20:40:25 +0200[diff] [blame]987 interrupt-names = "tx", "rx";
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]988 status = "disabled";
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]989 dmas = <&edma 8 2>,
990 <&edma 9 2>;
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]991 dma-names = "tx", "rx";
992 };
993
994 mcasp1: mcasp@4803C000 {
995 compatible = "ti,am33xx-mcasp-audio";
996 ti,hwmods = "mcasp1";
Jyri Sarha0bee55a2013-10-20 20:04:09 +0300[diff] [blame]997 reg = <0x4803C000 0x2000>,
998 <0x46400000 0x400000>;
999 reg-names = "mpu", "dat";
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]1000 interrupts = <82>, <83>;
Geert Uytterhoevenae107d02014-04-22 20:40:25 +0200[diff] [blame]1001 interrupt-names = "tx", "rx";
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]1002 status = "disabled";
Peter Ujfalusib5e50902015-12-17 15:33:36 +0200[diff] [blame]1003 dmas = <&edma 10 2>,
1004 <&edma 11 2>;
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]1005 dma-names = "tx", "rx";
1006 };
Lokesh Vutlaed845d62013-08-29 18:22:09 +0530[diff] [blame]1007
1008 rng: rng@48310000 {
1009 compatible = "ti,omap4-rng";
1010 ti,hwmods = "rng";
1011 reg = <0x48310000 0x2000>;
1012 interrupts = <111>;
1013 };
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]1014 };
1015};
Tero Kristoea291c92013-07-18 18:15:35 +0300[diff] [blame]1016
1017/include/ "am33xx-clocks.dtsi"