blob: ed7e1009326cd748628c5422849bfffad2a3b21e [file] [log] [blame]
Marc Dietrichcc2afa42011-11-01 10:37:05 +00001/dts-v1/;
2
Laxman Dewangan6bccbd52013-12-02 18:39:57 +05303#include <dt-bindings/input/input.h>
Stephen Warren1bd0bd42012-10-17 16:38:21 -06004#include "tegra20.dtsi"
Marc Dietrichcc2afa42011-11-01 10:37:05 +00005
6/ {
7 model = "Toshiba AC100 / Dynabook AZ";
8 compatible = "compal,paz00", "nvidia,tegra20";
9
Stephen Warren553c0a22013-12-09 14:43:59 -070010 aliases {
11 rtc0 = "/i2c@7000d000/tps6586x@34";
12 rtc1 = "/rtc@7000e000";
Olof Johanssonc4574aa2014-11-11 12:49:30 -080013 serial0 = &uarta;
14 serial1 = &uartc;
Stephen Warren553c0a22013-12-09 14:43:59 -070015 };
16
Stephen Warrenf9eb26a2012-05-11 16:17:47 -060017 memory {
Marc Dietrichcc2afa42011-11-01 10:37:05 +000018 reg = <0x00000000 0x20000000>;
19 };
20
Stephen Warren58ecb232013-11-25 17:53:16 -070021 host1x@50000000 {
Marc Dietrich58168982013-12-21 21:38:13 +010022 dc@54200000 {
23 rgb {
24 status = "okay";
25
26 nvidia,panel = <&panel>;
27 };
28 };
29
Stephen Warren58ecb232013-11-25 17:53:16 -070030 hdmi@54280000 {
Stephen Warren11a3c862013-01-02 14:53:22 -070031 status = "okay";
32
33 vdd-supply = <&hdmi_vdd_reg>;
34 pll-supply = <&hdmi_pll_reg>;
35
36 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
Stephen Warren3325f1b2013-02-12 17:25:15 -070037 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
38 GPIO_ACTIVE_HIGH>;
Stephen Warren11a3c862013-01-02 14:53:22 -070039 };
40 };
41
Stephen Warren58ecb232013-11-25 17:53:16 -070042 pinmux@70000014 {
Stephen Warrenecc295b2012-03-15 16:27:36 -060043 pinctrl-names = "default";
44 pinctrl-0 = <&state_default>;
45
46 state_default: pinmux {
47 ata {
48 nvidia,pins = "ata", "atc", "atd", "ate",
49 "dap2", "gmb", "gmc", "gmd", "spia",
50 "spib", "spic", "spid", "spie";
51 nvidia,function = "gmi";
52 };
53 atb {
54 nvidia,pins = "atb", "gma", "gme";
55 nvidia,function = "sdio4";
56 };
57 cdev1 {
58 nvidia,pins = "cdev1";
59 nvidia,function = "plla_out";
60 };
61 cdev2 {
62 nvidia,pins = "cdev2";
63 nvidia,function = "pllp_out4";
64 };
65 crtp {
66 nvidia,pins = "crtp";
67 nvidia,function = "crt";
68 };
69 csus {
70 nvidia,pins = "csus";
71 nvidia,function = "pllc_out1";
72 };
73 dap1 {
74 nvidia,pins = "dap1";
75 nvidia,function = "dap1";
76 };
77 dap3 {
78 nvidia,pins = "dap3";
79 nvidia,function = "dap3";
80 };
81 dap4 {
82 nvidia,pins = "dap4";
83 nvidia,function = "dap4";
84 };
85 ddc {
86 nvidia,pins = "ddc";
87 nvidia,function = "i2c2";
88 };
89 dta {
90 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
91 nvidia,function = "rsvd1";
92 };
93 dtf {
94 nvidia,pins = "dtf";
95 nvidia,function = "i2c3";
96 };
97 gpu {
98 nvidia,pins = "gpu", "sdb", "sdd";
99 nvidia,function = "pwm";
100 };
101 gpu7 {
102 nvidia,pins = "gpu7";
103 nvidia,function = "rtck";
104 };
105 gpv {
106 nvidia,pins = "gpv", "slxa", "slxk";
107 nvidia,function = "pcie";
108 };
109 hdint {
110 nvidia,pins = "hdint", "pta";
111 nvidia,function = "hdmi";
112 };
113 i2cp {
114 nvidia,pins = "i2cp";
115 nvidia,function = "i2cp";
116 };
117 irrx {
118 nvidia,pins = "irrx", "irtx";
119 nvidia,function = "uarta";
120 };
121 kbca {
122 nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
123 nvidia,function = "kbc";
124 };
125 kbcb {
126 nvidia,pins = "kbcb", "kbcd";
127 nvidia,function = "sdio2";
128 };
129 lcsn {
130 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
131 "ld3", "ld4", "ld5", "ld6", "ld7",
132 "ld8", "ld9", "ld10", "ld11", "ld12",
133 "ld13", "ld14", "ld15", "ld16", "ld17",
134 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
135 "lhs", "lm0", "lm1", "lpp", "lpw0",
136 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
137 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
138 "lvs";
139 nvidia,function = "displaya";
140 };
141 owc {
142 nvidia,pins = "owc";
143 nvidia,function = "owr";
144 };
145 pmc {
146 nvidia,pins = "pmc";
147 nvidia,function = "pwr_on";
148 };
149 rm {
150 nvidia,pins = "rm";
151 nvidia,function = "i2c1";
152 };
153 sdc {
154 nvidia,pins = "sdc";
155 nvidia,function = "twc";
156 };
157 sdio1 {
158 nvidia,pins = "sdio1";
159 nvidia,function = "sdio1";
160 };
161 slxc {
162 nvidia,pins = "slxc", "slxd";
163 nvidia,function = "spi4";
164 };
165 spdi {
166 nvidia,pins = "spdi", "spdo";
167 nvidia,function = "rsvd2";
168 };
169 spif {
170 nvidia,pins = "spif", "uac";
171 nvidia,function = "rsvd4";
172 };
173 spig {
174 nvidia,pins = "spig", "spih";
175 nvidia,function = "spi2_alt";
176 };
177 uaa {
178 nvidia,pins = "uaa", "uab", "uda";
179 nvidia,function = "ulpi";
180 };
181 uad {
182 nvidia,pins = "uad";
183 nvidia,function = "spdif";
184 };
185 uca {
186 nvidia,pins = "uca", "ucb";
187 nvidia,function = "uartc";
188 };
189 conf_ata {
190 nvidia,pins = "ata", "atb", "atc", "atd", "ate",
Stephen Warren563da212012-04-13 16:35:20 -0600191 "cdev1", "cdev2", "dap1", "dap2", "dtf",
192 "gma", "gmb", "gmc", "gmd", "gme",
193 "gpu", "gpu7", "gpv", "i2cp", "pta",
194 "rm", "sdio1", "slxk", "spdo", "uac",
195 "uda";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530196 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
197 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600198 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600199 conf_ck32 {
200 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
201 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530202 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600203 };
204 conf_crtp {
205 nvidia,pins = "crtp", "dap3", "dap4", "dtb",
206 "dtc", "dte", "slxa", "slxc", "slxd",
207 "spdi";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530208 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
209 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600210 };
211 conf_csus {
212 nvidia,pins = "csus", "spia", "spib", "spid",
213 "spif";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530214 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
215 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600216 };
217 conf_ddc {
218 nvidia,pins = "ddc", "irrx", "irtx", "kbca",
219 "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
220 "spic", "spig", "uaa", "uab";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530221 nvidia,pull = <TEGRA_PIN_PULL_UP>;
222 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600223 };
224 conf_dta {
225 nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd",
226 "spie", "spih", "uad", "uca", "ucb";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530227 nvidia,pull = <TEGRA_PIN_PULL_UP>;
228 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600229 };
230 conf_hdint {
231 nvidia,pins = "hdint", "ld0", "ld1", "ld2",
232 "ld3", "ld4", "ld5", "ld6", "ld7",
233 "ld8", "ld9", "ld10", "ld11", "ld12",
234 "ld13", "ld14", "ld15", "ld16", "ld17",
235 "ldc", "ldi", "lhs", "lsc0", "lspi",
236 "lvs", "pmc";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530237 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600238 };
239 conf_lc {
240 nvidia,pins = "lc", "ls";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530241 nvidia,pull = <TEGRA_PIN_PULL_UP>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600242 };
243 conf_lcsn {
244 nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2",
245 "lm0", "lm1", "lpp", "lpw0", "lpw1",
246 "lpw2", "lsc1", "lsck", "lsda", "lsdi",
247 "lvp0", "lvp1", "sdb";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530248 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600249 };
250 conf_ld17_0 {
251 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
252 "ld23_22";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530253 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600254 };
255 };
256 };
257
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600258 i2s@70002800 {
259 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600260 };
261
262 serial@70006000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600263 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600264 };
265
Stephen Warrenc04abb32012-05-11 17:03:26 -0600266 serial@70006200 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600267 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600268 };
269
Marc Dietrich58168982013-12-21 21:38:13 +0100270 pwm: pwm@7000a000 {
271 status = "okay";
272 };
273
274 lvds_ddc: i2c@7000c000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600275 status = "okay";
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000276 clock-frequency = <400000>;
Leon Romanovsky613e9652012-02-02 22:13:35 +0200277
278 alc5632: alc5632@1e {
279 compatible = "realtek,alc5632";
280 reg = <0x1e>;
281 gpio-controller;
282 #gpio-cells = <2>;
283 };
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000284 };
285
Stephen Warren11a3c862013-01-02 14:53:22 -0700286 hdmi_ddc: i2c@7000c400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600287 status = "okay";
Stephen Warren11a3c862013-01-02 14:53:22 -0700288 clock-frequency = <100000>;
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000289 };
290
Stephen Warren58ecb232013-11-25 17:53:16 -0700291 nvec@7000c500 {
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000292 compatible = "nvidia,nvec";
Stephen Warrenba04c282012-05-11 16:28:59 -0600293 reg = <0x7000c500 0x100>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700294 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600295 #address-cells = <1>;
296 #size-cells = <0>;
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000297 clock-frequency = <80000>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700298 request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000299 slave-addr = <138>;
Hiroshi Doyu885a8cf2013-05-22 19:45:32 +0300300 clocks = <&tegra_car TEGRA20_CLK_I2C3>,
Thierry Reding067cc282014-07-25 12:40:02 -0600301 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
Prashant Gaikwadd409b3a2013-01-11 13:31:23 +0530302 clock-names = "div-clk", "fast-clk";
Stephen Warren3393d422013-11-06 14:01:16 -0700303 resets = <&tegra_car 67>;
304 reset-names = "i2c";
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000305 };
306
307 i2c@7000d000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600308 status = "okay";
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000309 clock-frequency = <400000>;
Marc Dietrich1266f892012-01-31 19:53:21 +0100310
Stephen Warren217b8f02012-06-21 14:24:57 -0600311 pmic: tps6586x@34 {
312 compatible = "ti,tps6586x";
313 reg = <0x34>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700314 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
Stephen Warren217b8f02012-06-21 14:24:57 -0600315
316 #gpio-cells = <2>;
317 gpio-controller;
318
319 sys-supply = <&p5valw_reg>;
320 vin-sm0-supply = <&sys_reg>;
321 vin-sm1-supply = <&sys_reg>;
322 vin-sm2-supply = <&sys_reg>;
323 vinldo01-supply = <&sm2_reg>;
324 vinldo23-supply = <&sm2_reg>;
325 vinldo4-supply = <&sm2_reg>;
326 vinldo678-supply = <&sm2_reg>;
327 vinldo9-supply = <&sm2_reg>;
328
329 regulators {
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600330 sys_reg: sys {
Stephen Warren217b8f02012-06-21 14:24:57 -0600331 regulator-name = "vdd_sys";
332 regulator-always-on;
333 };
334
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600335 sm0 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600336 regulator-name = "+1.2vs_sm0,vdd_core";
337 regulator-min-microvolt = <1200000>;
338 regulator-max-microvolt = <1200000>;
339 regulator-always-on;
340 };
341
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600342 sm1 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600343 regulator-name = "+1.0vs_sm1,vdd_cpu";
344 regulator-min-microvolt = <1000000>;
345 regulator-max-microvolt = <1000000>;
346 regulator-always-on;
347 };
348
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600349 sm2_reg: sm2 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600350 regulator-name = "+3.7vs_sm2,vin_ldo*";
351 regulator-min-microvolt = <3700000>;
352 regulator-max-microvolt = <3700000>;
353 regulator-always-on;
354 };
355
356 /* LDO0 is not connected to anything */
357
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600358 ldo1 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600359 regulator-name = "+1.1vs_ldo1,avdd_pll*";
360 regulator-min-microvolt = <1100000>;
361 regulator-max-microvolt = <1100000>;
362 regulator-always-on;
363 };
364
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600365 ldo2 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600366 regulator-name = "+1.2vs_ldo2,vdd_rtc";
367 regulator-min-microvolt = <1200000>;
368 regulator-max-microvolt = <1200000>;
369 };
370
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600371 ldo3 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600372 regulator-name = "+3.3vs_ldo3,avdd_usb*";
373 regulator-min-microvolt = <3300000>;
374 regulator-max-microvolt = <3300000>;
375 regulator-always-on;
376 };
377
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600378 ldo4 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600379 regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys";
380 regulator-min-microvolt = <1800000>;
381 regulator-max-microvolt = <1800000>;
382 regulator-always-on;
383 };
384
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600385 ldo5 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600386 regulator-name = "+2.85vs_ldo5,vcore_mmc";
387 regulator-min-microvolt = <2850000>;
388 regulator-max-microvolt = <2850000>;
389 regulator-always-on;
390 };
391
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600392 ldo6 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600393 /*
394 * Research indicates this should be
395 * 1.8v; other boards that use this
396 * rail for the same purpose need it
397 * set to 1.8v. The schematic signal
398 * name is incorrect; perhaps copied
399 * from an incorrect NVIDIA reference.
400 */
401 regulator-name = "+2.85vs_ldo6,avdd_vdac";
402 regulator-min-microvolt = <1800000>;
403 regulator-max-microvolt = <1800000>;
404 };
405
Stephen Warren11a3c862013-01-02 14:53:22 -0700406 hdmi_vdd_reg: ldo7 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600407 regulator-name = "+3.3vs_ldo7,avdd_hdmi";
408 regulator-min-microvolt = <3300000>;
409 regulator-max-microvolt = <3300000>;
410 };
411
Stephen Warren11a3c862013-01-02 14:53:22 -0700412 hdmi_pll_reg: ldo8 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600413 regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll";
414 regulator-min-microvolt = <1800000>;
415 regulator-max-microvolt = <1800000>;
416 };
417
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600418 ldo9 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600419 regulator-name = "+2.85vs_ldo9,vdd_ddr_rx";
420 regulator-min-microvolt = <2850000>;
421 regulator-max-microvolt = <2850000>;
422 regulator-always-on;
423 };
424
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600425 ldo_rtc {
Stephen Warren217b8f02012-06-21 14:24:57 -0600426 regulator-name = "+3.3vs_rtc";
427 regulator-min-microvolt = <3300000>;
428 regulator-max-microvolt = <3300000>;
429 regulator-always-on;
430 };
431 };
432 };
433
Marc Dietrich1266f892012-01-31 19:53:21 +0100434 adt7461@4c {
435 compatible = "adi,adt7461";
436 reg = <0x4c>;
437 };
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000438 };
439
Stephen Warren58ecb232013-11-25 17:53:16 -0700440 pmc@7000e400 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600441 nvidia,invert-interrupt;
Joseph Lo47d2d632013-08-12 17:40:07 +0800442 nvidia,suspend-mode = <1>;
Joseph Loa44a0192013-04-03 19:31:52 +0800443 nvidia,cpu-pwr-good-time = <2000>;
444 nvidia,cpu-pwr-off-time = <0>;
445 nvidia,core-pwr-good-time = <3845 3845>;
446 nvidia,core-pwr-off-time = <0>;
447 nvidia,sys-clock-req-active-high;
Stephen Warren217b8f02012-06-21 14:24:57 -0600448 };
449
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600450 usb@c5000000 {
451 status = "okay";
452 };
453
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530454 usb-phy@c5000000 {
455 status = "okay";
456 };
457
Stephen Warrenc04abb32012-05-11 17:03:26 -0600458 usb@c5004000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600459 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700460 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
461 GPIO_ACTIVE_LOW>;
Venu Byravarasu9dffe3b2013-05-16 19:42:56 +0530462 };
463
464 usb-phy@c5004000 {
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530465 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700466 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
467 GPIO_ACTIVE_LOW>;
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000468 };
469
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600470 usb@c5008000 {
471 status = "okay";
472 };
473
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530474 usb-phy@c5008000 {
475 status = "okay";
476 };
477
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000478 sdhci@c8000000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600479 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700480 cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>;
481 wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
482 power-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
Arnd Bergmann7f217792012-05-13 00:14:24 -0400483 bus-width = <4>;
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000484 };
485
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000486 sdhci@c8000600 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600487 status = "okay";
Arnd Bergmann7f217792012-05-13 00:14:24 -0400488 bus-width = <8>;
Joseph Lo7a2617a2013-04-03 14:34:39 -0600489 non-removable;
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000490 };
Marc Dietrichd8d56c82012-01-28 20:03:07 +0100491
Marc Dietrich58168982013-12-21 21:38:13 +0100492 backlight: backlight {
493 compatible = "pwm-backlight";
494
495 enable-gpios = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
496 pwms = <&pwm 0 5000000>;
497
498 brightness-levels = <0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 255>;
499 default-brightness-level = <10>;
500
501 backlight-boot-off;
502 };
503
Joseph Lo7021d122013-04-03 19:31:27 +0800504 clocks {
505 compatible = "simple-bus";
506 #address-cells = <1>;
507 #size-cells = <0>;
508
Stephen Warren58ecb232013-11-25 17:53:16 -0700509 clk32k_in: clock@0 {
Joseph Lo7021d122013-04-03 19:31:27 +0800510 compatible = "fixed-clock";
511 reg=<0>;
512 #clock-cells = <0>;
513 clock-frequency = <32768>;
514 };
515 };
516
Marc Dietrichd8d56c82012-01-28 20:03:07 +0100517 gpio-keys {
518 compatible = "gpio-keys";
519
520 power {
521 label = "Power";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700522 gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>;
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530523 linux,code = <KEY_POWER>;
Marc Dietrichd8d56c82012-01-28 20:03:07 +0100524 gpio-key,wakeup;
525 };
526 };
Marc Dietrich80c94732012-01-28 20:03:08 +0100527
528 gpio-leds {
529 compatible = "gpio-leds";
530
531 wifi {
532 label = "wifi-led";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700533 gpios = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
Marc Dietrich80c94732012-01-28 20:03:08 +0100534 linux,default-trigger = "rfkill0";
535 };
536 };
Stephen Warrenaa607eb2012-04-12 15:46:49 -0600537
Marc Dietrich58168982013-12-21 21:38:13 +0100538 panel: panel {
539 compatible = "samsung,ltn101nt05", "simple-panel";
540
541 ddc-i2c-bus = <&lvds_ddc>;
542 power-supply = <&vdd_pnl_reg>;
543 enable-gpios = <&gpio TEGRA_GPIO(M, 6) GPIO_ACTIVE_HIGH>;
544
545 backlight = <&backlight>;
546 };
547
Stephen Warren217b8f02012-06-21 14:24:57 -0600548 regulators {
549 compatible = "simple-bus";
550 #address-cells = <1>;
551 #size-cells = <0>;
552
553 p5valw_reg: regulator@0 {
554 compatible = "regulator-fixed";
555 reg = <0>;
556 regulator-name = "+5valw";
557 regulator-min-microvolt = <5000000>;
558 regulator-max-microvolt = <5000000>;
559 regulator-always-on;
560 };
Marc Dietrich58168982013-12-21 21:38:13 +0100561
562 vdd_pnl_reg: regulator@1 {
563 compatible = "regulator-fixed";
564 reg = <1>;
565 regulator-name = "+3VS,vdd_pnl";
566 regulator-min-microvolt = <3300000>;
567 regulator-max-microvolt = <3300000>;
568 gpio = <&gpio TEGRA_GPIO(A, 4) GPIO_ACTIVE_HIGH>;
569 enable-active-high;
570 };
Stephen Warren217b8f02012-06-21 14:24:57 -0600571 };
572
Stephen Warrenc04abb32012-05-11 17:03:26 -0600573 sound {
574 compatible = "nvidia,tegra-audio-alc5632-paz00",
575 "nvidia,tegra-audio-alc5632";
576
577 nvidia,model = "Compal PAZ00";
578
579 nvidia,audio-routing =
580 "Int Spk", "SPKOUT",
581 "Int Spk", "SPKOUTN",
582 "Headset Mic", "MICBIAS1",
583 "MIC1", "Headset Mic",
584 "Headset Stereophone", "HPR",
585 "Headset Stereophone", "HPL",
586 "DMICDAT", "Digital Mic";
587
588 nvidia,audio-codec = <&alc5632>;
589 nvidia,i2s-controller = <&tegra_i2s1>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700590 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
591 GPIO_ACTIVE_HIGH>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600592
Hiroshi Doyu885a8cf2013-05-22 19:45:32 +0300593 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
Thierry Reding067cc282014-07-25 12:40:02 -0600594 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
595 <&tegra_car TEGRA20_CLK_CDEV1>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600596 clock-names = "pll_a", "pll_a_out0", "mclk";
Stephen Warrenaa607eb2012-04-12 15:46:49 -0600597 };
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000598};