Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2015 Cavium, Inc. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify it |
| 5 | * under the terms of version 2 of the GNU General Public License |
| 6 | * as published by the Free Software Foundation. |
| 7 | */ |
| 8 | |
| 9 | #ifndef NIC_H |
| 10 | #define NIC_H |
| 11 | |
| 12 | #include <linux/netdevice.h> |
| 13 | #include <linux/interrupt.h> |
Robert Richter | d768b67 | 2015-06-02 11:00:18 -0700 | [diff] [blame] | 14 | #include <linux/pci.h> |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 15 | #include "thunder_bgx.h" |
| 16 | |
| 17 | /* PCI device IDs */ |
| 18 | #define PCI_DEVICE_ID_THUNDER_NIC_PF 0xA01E |
| 19 | #define PCI_DEVICE_ID_THUNDER_PASS1_NIC_VF 0x0011 |
| 20 | #define PCI_DEVICE_ID_THUNDER_NIC_VF 0xA034 |
| 21 | #define PCI_DEVICE_ID_THUNDER_BGX 0xA026 |
| 22 | |
Sunil Goutham | a5c3d49 | 2016-08-12 16:51:24 +0530 | [diff] [blame] | 23 | /* Subsystem device IDs */ |
Sunil Goutham | f7ff0ae | 2016-08-12 16:51:25 +0530 | [diff] [blame] | 24 | #define PCI_SUBSYS_DEVID_88XX_NIC_PF 0xA11E |
| 25 | #define PCI_SUBSYS_DEVID_81XX_NIC_PF 0xA21E |
| 26 | #define PCI_SUBSYS_DEVID_83XX_NIC_PF 0xA31E |
| 27 | |
| 28 | #define PCI_SUBSYS_DEVID_88XX_PASS1_NIC_VF 0xA11E |
| 29 | #define PCI_SUBSYS_DEVID_88XX_NIC_VF 0xA134 |
| 30 | #define PCI_SUBSYS_DEVID_81XX_NIC_VF 0xA234 |
| 31 | #define PCI_SUBSYS_DEVID_83XX_NIC_VF 0xA334 |
| 32 | |
Sunil Goutham | a5c3d49 | 2016-08-12 16:51:24 +0530 | [diff] [blame] | 33 | |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 34 | /* PCI BAR nos */ |
| 35 | #define PCI_CFG_REG_BAR_NUM 0 |
| 36 | #define PCI_MSIX_REG_BAR_NUM 4 |
| 37 | |
| 38 | /* NIC SRIOV VF count */ |
| 39 | #define MAX_NUM_VFS_SUPPORTED 128 |
| 40 | #define DEFAULT_NUM_VF_ENABLED 8 |
| 41 | |
| 42 | #define NIC_TNS_BYPASS_MODE 0 |
| 43 | #define NIC_TNS_MODE 1 |
| 44 | |
| 45 | /* NIC priv flags */ |
| 46 | #define NIC_SRIOV_ENABLED BIT(0) |
| 47 | |
| 48 | /* Min/Max packet size */ |
| 49 | #define NIC_HW_MIN_FRS 64 |
Sunil Goutham | 712c318 | 2016-11-15 17:37:36 +0530 | [diff] [blame] | 50 | #define NIC_HW_MAX_FRS 9190 /* Excluding L2 header and FCS */ |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 51 | |
| 52 | /* Max pkinds */ |
| 53 | #define NIC_MAX_PKIND 16 |
| 54 | |
Sunil Goutham | a5c3d49 | 2016-08-12 16:51:24 +0530 | [diff] [blame] | 55 | /* Max when CPI_ALG is IP diffserv */ |
| 56 | #define NIC_MAX_CPI_PER_LMAC 64 |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 57 | |
| 58 | /* NIC VF Interrupts */ |
| 59 | #define NICVF_INTR_CQ 0 |
| 60 | #define NICVF_INTR_SQ 1 |
| 61 | #define NICVF_INTR_RBDR 2 |
| 62 | #define NICVF_INTR_PKT_DROP 3 |
| 63 | #define NICVF_INTR_TCP_TIMER 4 |
| 64 | #define NICVF_INTR_MBOX 5 |
| 65 | #define NICVF_INTR_QS_ERR 6 |
| 66 | |
| 67 | #define NICVF_INTR_CQ_SHIFT 0 |
| 68 | #define NICVF_INTR_SQ_SHIFT 8 |
| 69 | #define NICVF_INTR_RBDR_SHIFT 16 |
| 70 | #define NICVF_INTR_PKT_DROP_SHIFT 20 |
| 71 | #define NICVF_INTR_TCP_TIMER_SHIFT 21 |
| 72 | #define NICVF_INTR_MBOX_SHIFT 22 |
| 73 | #define NICVF_INTR_QS_ERR_SHIFT 23 |
| 74 | |
| 75 | #define NICVF_INTR_CQ_MASK (0xFF << NICVF_INTR_CQ_SHIFT) |
| 76 | #define NICVF_INTR_SQ_MASK (0xFF << NICVF_INTR_SQ_SHIFT) |
| 77 | #define NICVF_INTR_RBDR_MASK (0x03 << NICVF_INTR_RBDR_SHIFT) |
| 78 | #define NICVF_INTR_PKT_DROP_MASK BIT(NICVF_INTR_PKT_DROP_SHIFT) |
| 79 | #define NICVF_INTR_TCP_TIMER_MASK BIT(NICVF_INTR_TCP_TIMER_SHIFT) |
| 80 | #define NICVF_INTR_MBOX_MASK BIT(NICVF_INTR_MBOX_SHIFT) |
| 81 | #define NICVF_INTR_QS_ERR_MASK BIT(NICVF_INTR_QS_ERR_SHIFT) |
| 82 | |
| 83 | /* MSI-X interrupts */ |
| 84 | #define NIC_PF_MSIX_VECTORS 10 |
| 85 | #define NIC_VF_MSIX_VECTORS 20 |
| 86 | |
| 87 | #define NIC_PF_INTR_ID_ECC0_SBE 0 |
| 88 | #define NIC_PF_INTR_ID_ECC0_DBE 1 |
| 89 | #define NIC_PF_INTR_ID_ECC1_SBE 2 |
| 90 | #define NIC_PF_INTR_ID_ECC1_DBE 3 |
| 91 | #define NIC_PF_INTR_ID_ECC2_SBE 4 |
| 92 | #define NIC_PF_INTR_ID_ECC2_DBE 5 |
| 93 | #define NIC_PF_INTR_ID_ECC3_SBE 6 |
| 94 | #define NIC_PF_INTR_ID_ECC3_DBE 7 |
| 95 | #define NIC_PF_INTR_ID_MBOX0 8 |
| 96 | #define NIC_PF_INTR_ID_MBOX1 9 |
| 97 | |
Sunil Goutham | 4c0b6eaf | 2016-02-24 16:40:50 +0530 | [diff] [blame] | 98 | /* Minimum FIFO level before all packets for the CQ are dropped |
| 99 | * |
| 100 | * This value ensures that once a packet has been "accepted" |
| 101 | * for reception it will not get dropped due to non-availability |
| 102 | * of CQ descriptor. An errata in HW mandates this value to be |
| 103 | * atleast 0x100. |
| 104 | */ |
| 105 | #define NICPF_CQM_MIN_DROP_LEVEL 0x100 |
| 106 | |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 107 | /* Global timer for CQ timer thresh interrupts |
| 108 | * Calculated for SCLK of 700Mhz |
| 109 | * value written should be a 1/16th of what is expected |
| 110 | * |
Sunil Goutham | 006394a | 2015-12-02 15:36:15 +0530 | [diff] [blame] | 111 | * 1 tick per 0.025usec |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 112 | */ |
Sunil Goutham | 006394a | 2015-12-02 15:36:15 +0530 | [diff] [blame] | 113 | #define NICPF_CLK_PER_INT_TICK 1 |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 114 | |
Sunil Goutham | 3d7a8aa | 2015-07-29 16:49:43 +0300 | [diff] [blame] | 115 | /* Time to wait before we decide that a SQ is stuck. |
| 116 | * |
| 117 | * Since both pkt rx and tx notifications are done with same CQ, |
| 118 | * when packets are being received at very high rate (eg: L2 forwarding) |
| 119 | * then freeing transmitted skbs will be delayed and watchdog |
| 120 | * will kick in, resetting interface. Hence keeping this value high. |
| 121 | */ |
| 122 | #define NICVF_TX_TIMEOUT (50 * HZ) |
| 123 | |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 124 | struct nicvf_cq_poll { |
Sunil Goutham | 39ad6ee | 2015-08-30 12:29:14 +0300 | [diff] [blame] | 125 | struct nicvf *nicvf; |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 126 | u8 cq_idx; /* Completion queue index */ |
| 127 | struct napi_struct napi; |
| 128 | }; |
| 129 | |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 130 | #define NIC_MAX_RSS_HASH_BITS 8 |
| 131 | #define NIC_MAX_RSS_IDR_TBL_SIZE (1 << NIC_MAX_RSS_HASH_BITS) |
| 132 | #define RSS_HASH_KEY_SIZE 5 /* 320 bit key */ |
| 133 | |
| 134 | struct nicvf_rss_info { |
| 135 | bool enable; |
| 136 | #define RSS_L2_EXTENDED_HASH_ENA BIT(0) |
| 137 | #define RSS_IP_HASH_ENA BIT(1) |
| 138 | #define RSS_TCP_HASH_ENA BIT(2) |
| 139 | #define RSS_TCP_SYN_DIS BIT(3) |
| 140 | #define RSS_UDP_HASH_ENA BIT(4) |
| 141 | #define RSS_L4_EXTENDED_HASH_ENA BIT(5) |
| 142 | #define RSS_ROCE_ENA BIT(6) |
| 143 | #define RSS_L3_BI_DIRECTION_ENA BIT(7) |
| 144 | #define RSS_L4_BI_DIRECTION_ENA BIT(8) |
| 145 | u64 cfg; |
| 146 | u8 hash_bits; |
| 147 | u16 rss_size; |
| 148 | u8 ind_tbl[NIC_MAX_RSS_IDR_TBL_SIZE]; |
| 149 | u64 key[RSS_HASH_KEY_SIZE]; |
| 150 | } ____cacheline_aligned_in_smp; |
| 151 | |
Sunil Goutham | 430da20 | 2016-11-24 14:48:03 +0530 | [diff] [blame] | 152 | struct nicvf_pfc { |
| 153 | u8 autoneg; |
| 154 | u8 fc_rx; |
| 155 | u8 fc_tx; |
| 156 | }; |
| 157 | |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 158 | enum rx_stats_reg_offset { |
| 159 | RX_OCTS = 0x0, |
| 160 | RX_UCAST = 0x1, |
| 161 | RX_BCAST = 0x2, |
| 162 | RX_MCAST = 0x3, |
| 163 | RX_RED = 0x4, |
| 164 | RX_RED_OCTS = 0x5, |
| 165 | RX_ORUN = 0x6, |
| 166 | RX_ORUN_OCTS = 0x7, |
| 167 | RX_FCS = 0x8, |
| 168 | RX_L2ERR = 0x9, |
| 169 | RX_DRP_BCAST = 0xa, |
| 170 | RX_DRP_MCAST = 0xb, |
| 171 | RX_DRP_L3BCAST = 0xc, |
| 172 | RX_DRP_L3MCAST = 0xd, |
| 173 | RX_STATS_ENUM_LAST, |
| 174 | }; |
| 175 | |
| 176 | enum tx_stats_reg_offset { |
| 177 | TX_OCTS = 0x0, |
| 178 | TX_UCAST = 0x1, |
| 179 | TX_BCAST = 0x2, |
| 180 | TX_MCAST = 0x3, |
| 181 | TX_DROP = 0x4, |
| 182 | TX_STATS_ENUM_LAST, |
| 183 | }; |
| 184 | |
| 185 | struct nicvf_hw_stats { |
Sunil Goutham | a2dc5de | 2015-08-30 12:29:10 +0300 | [diff] [blame] | 186 | u64 rx_bytes; |
Sunil Goutham | 964cb69 | 2016-11-15 17:38:16 +0530 | [diff] [blame] | 187 | u64 rx_frames; |
Sunil Goutham | a2dc5de | 2015-08-30 12:29:10 +0300 | [diff] [blame] | 188 | u64 rx_ucast_frames; |
| 189 | u64 rx_bcast_frames; |
| 190 | u64 rx_mcast_frames; |
Sunil Goutham | 964cb69 | 2016-11-15 17:38:16 +0530 | [diff] [blame] | 191 | u64 rx_drops; |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 192 | u64 rx_drop_red; |
| 193 | u64 rx_drop_red_bytes; |
| 194 | u64 rx_drop_overrun; |
| 195 | u64 rx_drop_overrun_bytes; |
| 196 | u64 rx_drop_bcast; |
| 197 | u64 rx_drop_mcast; |
| 198 | u64 rx_drop_l3_bcast; |
| 199 | u64 rx_drop_l3_mcast; |
Sunil Goutham | 964cb69 | 2016-11-15 17:38:16 +0530 | [diff] [blame] | 200 | u64 rx_fcs_errors; |
| 201 | u64 rx_l2_errors; |
| 202 | |
| 203 | u64 tx_bytes; |
| 204 | u64 tx_frames; |
| 205 | u64 tx_ucast_frames; |
| 206 | u64 tx_bcast_frames; |
| 207 | u64 tx_mcast_frames; |
| 208 | u64 tx_drops; |
| 209 | }; |
| 210 | |
| 211 | struct nicvf_drv_stats { |
| 212 | /* CQE Rx errs */ |
Sunil Goutham | a2dc5de | 2015-08-30 12:29:10 +0300 | [diff] [blame] | 213 | u64 rx_bgx_truncated_pkts; |
| 214 | u64 rx_jabber_errs; |
| 215 | u64 rx_fcs_errs; |
| 216 | u64 rx_bgx_errs; |
| 217 | u64 rx_prel2_errs; |
| 218 | u64 rx_l2_hdr_malformed; |
| 219 | u64 rx_oversize; |
| 220 | u64 rx_undersize; |
| 221 | u64 rx_l2_len_mismatch; |
| 222 | u64 rx_l2_pclp; |
| 223 | u64 rx_ip_ver_errs; |
| 224 | u64 rx_ip_csum_errs; |
| 225 | u64 rx_ip_hdr_malformed; |
| 226 | u64 rx_ip_payload_malformed; |
| 227 | u64 rx_ip_ttl_errs; |
| 228 | u64 rx_l3_pclp; |
| 229 | u64 rx_l4_malformed; |
| 230 | u64 rx_l4_csum_errs; |
| 231 | u64 rx_udp_len_errs; |
| 232 | u64 rx_l4_port_errs; |
| 233 | u64 rx_tcp_flag_errs; |
| 234 | u64 rx_tcp_offset_errs; |
| 235 | u64 rx_l4_pclp; |
| 236 | u64 rx_truncated_pkts; |
| 237 | |
Sunil Goutham | 964cb69 | 2016-11-15 17:38:16 +0530 | [diff] [blame] | 238 | /* CQE Tx errs */ |
| 239 | u64 tx_desc_fault; |
| 240 | u64 tx_hdr_cons_err; |
| 241 | u64 tx_subdesc_err; |
| 242 | u64 tx_max_size_exceeded; |
| 243 | u64 tx_imm_size_oflow; |
| 244 | u64 tx_data_seq_err; |
| 245 | u64 tx_mem_seq_err; |
| 246 | u64 tx_lock_viol; |
| 247 | u64 tx_data_fault; |
| 248 | u64 tx_tstmp_conflict; |
| 249 | u64 tx_tstmp_timeout; |
| 250 | u64 tx_mem_fault; |
| 251 | u64 tx_csum_overlap; |
| 252 | u64 tx_csum_overflow; |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 253 | |
Sunil Goutham | 964cb69 | 2016-11-15 17:38:16 +0530 | [diff] [blame] | 254 | /* driver debug stats */ |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 255 | u64 tx_tso; |
Thanneeru Srinivasulu | a05d484 | 2016-02-11 21:50:21 +0530 | [diff] [blame] | 256 | u64 tx_timeout; |
Sunil Goutham | 74840b8 | 2015-07-29 16:49:42 +0300 | [diff] [blame] | 257 | u64 txq_stop; |
| 258 | u64 txq_wake; |
Sunil Goutham | 964cb69 | 2016-11-15 17:38:16 +0530 | [diff] [blame] | 259 | |
Sunil Goutham | 5836b44 | 2017-05-02 18:36:50 +0530 | [diff] [blame] | 260 | u64 rcv_buffer_alloc_failures; |
| 261 | u64 page_alloc; |
| 262 | |
Sunil Goutham | 964cb69 | 2016-11-15 17:38:16 +0530 | [diff] [blame] | 263 | struct u64_stats_sync syncp; |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 264 | }; |
| 265 | |
Sunil Goutham | 4a87550 | 2018-01-15 18:44:57 +0600 | [diff] [blame] | 266 | struct cavium_ptp; |
| 267 | |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 268 | struct nicvf { |
Sunil Goutham | 92dc876 | 2015-08-30 12:29:15 +0300 | [diff] [blame] | 269 | struct nicvf *pnicvf; |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 270 | struct net_device *netdev; |
| 271 | struct pci_dev *pdev; |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 272 | void __iomem *reg_base; |
Sunil Goutham | 05c773f | 2017-05-02 18:36:54 +0530 | [diff] [blame] | 273 | struct bpf_prog *xdp_prog; |
Sunil Goutham | a5c3d49 | 2016-08-12 16:51:24 +0530 | [diff] [blame] | 274 | #define MAX_QUEUES_PER_QSET 8 |
Sunil Goutham | 1d36879 | 2016-03-14 16:36:15 +0530 | [diff] [blame] | 275 | struct queue_set *qs; |
Sunil Goutham | 83abb7d | 2017-03-07 18:09:08 +0530 | [diff] [blame] | 276 | void *iommu_domain; |
Sunil Goutham | 1d36879 | 2016-03-14 16:36:15 +0530 | [diff] [blame] | 277 | u8 vf_id; |
| 278 | u8 sqs_id; |
| 279 | bool sqs_mode; |
| 280 | bool hw_tso; |
Sunil Goutham | 7ceb8a1 | 2016-08-30 11:36:27 +0530 | [diff] [blame] | 281 | bool t88; |
Sunil Goutham | 1d36879 | 2016-03-14 16:36:15 +0530 | [diff] [blame] | 282 | |
| 283 | /* Receive buffer alloc */ |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 284 | u32 rb_page_offset; |
Sunil Goutham | 5c2e26f | 2016-03-14 16:36:14 +0530 | [diff] [blame] | 285 | u16 rb_pageref; |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 286 | bool rb_alloc_fail; |
| 287 | bool rb_work_scheduled; |
Sunil Goutham | 1d36879 | 2016-03-14 16:36:15 +0530 | [diff] [blame] | 288 | struct page *rb_page; |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 289 | struct delayed_work rbdr_work; |
| 290 | struct tasklet_struct rbdr_task; |
Sunil Goutham | 1d36879 | 2016-03-14 16:36:15 +0530 | [diff] [blame] | 291 | |
| 292 | /* Secondary Qset */ |
| 293 | u8 sqs_count; |
| 294 | #define MAX_SQS_PER_VF_SINGLE_NODE 5 |
| 295 | #define MAX_SQS_PER_VF 11 |
| 296 | struct nicvf *snicvf[MAX_SQS_PER_VF]; |
| 297 | |
| 298 | /* Queue count */ |
| 299 | u8 rx_queues; |
| 300 | u8 tx_queues; |
Sunil Goutham | 05c773f | 2017-05-02 18:36:54 +0530 | [diff] [blame] | 301 | u8 xdp_tx_queues; |
Sunil Goutham | 1d36879 | 2016-03-14 16:36:15 +0530 | [diff] [blame] | 302 | u8 max_queues; |
| 303 | |
| 304 | u8 node; |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 305 | u8 cpi_alg; |
Sunil Goutham | 1d36879 | 2016-03-14 16:36:15 +0530 | [diff] [blame] | 306 | bool link_up; |
Thanneeru Srinivasulu | 1cc7025 | 2016-11-24 14:48:01 +0530 | [diff] [blame] | 307 | u8 mac_type; |
Sunil Goutham | 1d36879 | 2016-03-14 16:36:15 +0530 | [diff] [blame] | 308 | u8 duplex; |
| 309 | u32 speed; |
| 310 | bool tns_mode; |
| 311 | bool loopback_supported; |
| 312 | struct nicvf_rss_info rss_info; |
Sunil Goutham | 430da20 | 2016-11-24 14:48:03 +0530 | [diff] [blame] | 313 | struct nicvf_pfc pfc; |
Sunil Goutham | 1d36879 | 2016-03-14 16:36:15 +0530 | [diff] [blame] | 314 | struct tasklet_struct qs_err_task; |
| 315 | struct work_struct reset_task; |
| 316 | |
Sunil Goutham | 4a87550 | 2018-01-15 18:44:57 +0600 | [diff] [blame] | 317 | /* PTP timestamp */ |
| 318 | struct cavium_ptp *ptp_clock; |
| 319 | /* Inbound timestamping is on */ |
| 320 | bool hw_rx_tstamp; |
| 321 | /* When the packet that requires timestamping is sent, hardware inserts |
| 322 | * two entries to the completion queue. First is the regular |
| 323 | * CQE_TYPE_SEND entry that signals that the packet was sent. |
| 324 | * The second is CQE_TYPE_SEND_PTP that contains the actual timestamp |
| 325 | * for that packet. |
| 326 | * `ptp_skb` is initialized in the handler for the CQE_TYPE_SEND |
| 327 | * entry and is used and zeroed in the handler for the CQE_TYPE_SEND_PTP |
| 328 | * entry. |
| 329 | * So `ptp_skb` is used to hold the pointer to the packet between |
| 330 | * the calls to CQE_TYPE_SEND and CQE_TYPE_SEND_PTP handlers. |
| 331 | */ |
| 332 | struct sk_buff *ptp_skb; |
| 333 | /* `tx_ptp_skbs` is set when the hardware is sending a packet that |
| 334 | * requires timestamping. Cavium hardware can not process more than one |
| 335 | * such packet at once so this is set each time the driver submits |
| 336 | * a packet that requires timestamping to the send queue and clears |
| 337 | * each time it receives the entry on the completion queue saying |
| 338 | * that such packet was sent. |
| 339 | * So `tx_ptp_skbs` prevents driver from submitting more than one |
| 340 | * packet that requires timestamping to the hardware for transmitting. |
| 341 | */ |
| 342 | atomic_t tx_ptp_skbs; |
| 343 | |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 344 | /* Interrupt coalescing settings */ |
| 345 | u32 cq_coalesce_usecs; |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 346 | u32 msg_enable; |
Sunil Goutham | 1d36879 | 2016-03-14 16:36:15 +0530 | [diff] [blame] | 347 | |
| 348 | /* Stats */ |
Sunil Goutham | a2dc5de | 2015-08-30 12:29:10 +0300 | [diff] [blame] | 349 | struct nicvf_hw_stats hw_stats; |
Sunil Goutham | 964cb69 | 2016-11-15 17:38:16 +0530 | [diff] [blame] | 350 | struct nicvf_drv_stats __percpu *drv_stats; |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 351 | struct bgx_stats bgx_stats; |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 352 | |
Sunil Goutham | 05c773f | 2017-05-02 18:36:54 +0530 | [diff] [blame] | 353 | /* Napi */ |
| 354 | struct nicvf_cq_poll *napi[8]; |
| 355 | |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 356 | /* MSI-X */ |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 357 | u8 num_vec; |
Sunil Goutham | b4e28c1 | 2016-09-23 14:42:27 +0530 | [diff] [blame] | 358 | char irq_name[NIC_VF_MSIX_VECTORS][IFNAMSIZ + 15]; |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 359 | bool irq_allocated[NIC_VF_MSIX_VECTORS]; |
Sunil Goutham | fb4b7d9 | 2016-02-11 21:50:23 +0530 | [diff] [blame] | 360 | cpumask_var_t affinity_mask[NIC_VF_MSIX_VECTORS]; |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 361 | |
Sunil Goutham | 6051cba | 2015-08-30 12:29:11 +0300 | [diff] [blame] | 362 | /* VF <-> PF mailbox communication */ |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 363 | bool pf_acked; |
| 364 | bool pf_nacked; |
Pavel Fedin | bd049a9 | 2015-06-23 17:51:06 +0300 | [diff] [blame] | 365 | bool set_mac_pending; |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 366 | } ____cacheline_aligned_in_smp; |
| 367 | |
| 368 | /* PF <--> VF Mailbox communication |
| 369 | * Eight 64bit registers are shared between PF and VF. |
| 370 | * Separate set for each VF. |
| 371 | * Writing '1' into last register mbx7 means end of message. |
| 372 | */ |
| 373 | |
| 374 | /* PF <--> VF mailbox communication */ |
| 375 | #define NIC_PF_VF_MAILBOX_SIZE 2 |
| 376 | #define NIC_MBOX_MSG_TIMEOUT 2000 /* ms */ |
| 377 | |
| 378 | /* Mailbox message types */ |
| 379 | #define NIC_MBOX_MSG_READY 0x01 /* Is PF ready to rcv msgs */ |
| 380 | #define NIC_MBOX_MSG_ACK 0x02 /* ACK the message received */ |
| 381 | #define NIC_MBOX_MSG_NACK 0x03 /* NACK the message received */ |
| 382 | #define NIC_MBOX_MSG_QS_CFG 0x04 /* Configure Qset */ |
| 383 | #define NIC_MBOX_MSG_RQ_CFG 0x05 /* Configure receive queue */ |
| 384 | #define NIC_MBOX_MSG_SQ_CFG 0x06 /* Configure Send queue */ |
| 385 | #define NIC_MBOX_MSG_RQ_DROP_CFG 0x07 /* Configure receive queue */ |
| 386 | #define NIC_MBOX_MSG_SET_MAC 0x08 /* Add MAC ID to DMAC filter */ |
| 387 | #define NIC_MBOX_MSG_SET_MAX_FRS 0x09 /* Set max frame size */ |
| 388 | #define NIC_MBOX_MSG_CPI_CFG 0x0A /* Config CPI, RSSI */ |
| 389 | #define NIC_MBOX_MSG_RSS_SIZE 0x0B /* Get RSS indir_tbl size */ |
| 390 | #define NIC_MBOX_MSG_RSS_CFG 0x0C /* Config RSS table */ |
| 391 | #define NIC_MBOX_MSG_RSS_CFG_CONT 0x0D /* RSS config continuation */ |
| 392 | #define NIC_MBOX_MSG_RQ_BP_CFG 0x0E /* RQ backpressure config */ |
| 393 | #define NIC_MBOX_MSG_RQ_SW_SYNC 0x0F /* Flush inflight pkts to RQ */ |
| 394 | #define NIC_MBOX_MSG_BGX_STATS 0x10 /* Get stats from BGX */ |
| 395 | #define NIC_MBOX_MSG_BGX_LINK_CHANGE 0x11 /* BGX:LMAC link status */ |
Sunil Goutham | 92dc876 | 2015-08-30 12:29:15 +0300 | [diff] [blame] | 396 | #define NIC_MBOX_MSG_ALLOC_SQS 0x12 /* Allocate secondary Qset */ |
| 397 | #define NIC_MBOX_MSG_NICVF_PTR 0x13 /* Send nicvf ptr to PF */ |
| 398 | #define NIC_MBOX_MSG_PNICVF_PTR 0x14 /* Get primary qset nicvf ptr */ |
| 399 | #define NIC_MBOX_MSG_SNICVF_PTR 0x15 /* Send sqet nicvf ptr to PVF */ |
Sunil Goutham | d77a238 | 2015-08-30 12:29:16 +0300 | [diff] [blame] | 400 | #define NIC_MBOX_MSG_LOOPBACK 0x16 /* Set interface in loopback */ |
Jerin Jacob | 3458c40 | 2016-08-12 16:51:39 +0530 | [diff] [blame] | 401 | #define NIC_MBOX_MSG_RESET_STAT_COUNTER 0x17 /* Reset statistics counters */ |
Sunil Goutham | 430da20 | 2016-11-24 14:48:03 +0530 | [diff] [blame] | 402 | #define NIC_MBOX_MSG_PFC 0x18 /* Pause frame control */ |
Sunil Goutham | 4a87550 | 2018-01-15 18:44:57 +0600 | [diff] [blame] | 403 | #define NIC_MBOX_MSG_PTP_CFG 0x19 /* HW packet timestamp */ |
Sunil Goutham | 92dc876 | 2015-08-30 12:29:15 +0300 | [diff] [blame] | 404 | #define NIC_MBOX_MSG_CFG_DONE 0xF0 /* VF configuration done */ |
| 405 | #define NIC_MBOX_MSG_SHUTDOWN 0xF1 /* VF is being shutdown */ |
Vadim Lomovtsev | 0b849f5 | 2018-03-30 04:59:50 -0700 | [diff] [blame^] | 406 | #define NIC_MBOX_MSG_RESET_XCAST 0xF2 /* Reset DCAM filtering mode */ |
| 407 | #define NIC_MBOX_MSG_ADD_MCAST 0xF3 /* Add MAC to DCAM filters */ |
| 408 | #define NIC_MBOX_MSG_SET_XCAST 0xF4 /* Set MCAST/BCAST RX mode */ |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 409 | |
| 410 | struct nic_cfg_msg { |
| 411 | u8 msg; |
| 412 | u8 vf_id; |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 413 | u8 node_id; |
Sunil Goutham | 92dc876 | 2015-08-30 12:29:15 +0300 | [diff] [blame] | 414 | u8 tns_mode:1; |
| 415 | u8 sqs_mode:1; |
Sunil Goutham | d77a238 | 2015-08-30 12:29:16 +0300 | [diff] [blame] | 416 | u8 loopback_supported:1; |
Aleksey Makarov | e610cb3 | 2015-06-02 11:00:21 -0700 | [diff] [blame] | 417 | u8 mac_addr[ETH_ALEN]; |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 418 | }; |
| 419 | |
| 420 | /* Qset configuration */ |
| 421 | struct qs_cfg_msg { |
| 422 | u8 msg; |
| 423 | u8 num; |
Sunil Goutham | 92dc876 | 2015-08-30 12:29:15 +0300 | [diff] [blame] | 424 | u8 sqs_count; |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 425 | u64 cfg; |
| 426 | }; |
| 427 | |
| 428 | /* Receive queue configuration */ |
| 429 | struct rq_cfg_msg { |
| 430 | u8 msg; |
| 431 | u8 qs_num; |
| 432 | u8 rq_num; |
| 433 | u64 cfg; |
| 434 | }; |
| 435 | |
| 436 | /* Send queue configuration */ |
| 437 | struct sq_cfg_msg { |
| 438 | u8 msg; |
| 439 | u8 qs_num; |
| 440 | u8 sq_num; |
Sunil Goutham | 92dc876 | 2015-08-30 12:29:15 +0300 | [diff] [blame] | 441 | bool sqs_mode; |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 442 | u64 cfg; |
| 443 | }; |
| 444 | |
| 445 | /* Set VF's MAC address */ |
| 446 | struct set_mac_msg { |
| 447 | u8 msg; |
| 448 | u8 vf_id; |
Aleksey Makarov | e610cb3 | 2015-06-02 11:00:21 -0700 | [diff] [blame] | 449 | u8 mac_addr[ETH_ALEN]; |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 450 | }; |
| 451 | |
| 452 | /* Set Maximum frame size */ |
| 453 | struct set_frs_msg { |
| 454 | u8 msg; |
| 455 | u8 vf_id; |
| 456 | u16 max_frs; |
| 457 | }; |
| 458 | |
| 459 | /* Set CPI algorithm type */ |
| 460 | struct cpi_cfg_msg { |
| 461 | u8 msg; |
| 462 | u8 vf_id; |
| 463 | u8 rq_cnt; |
| 464 | u8 cpi_alg; |
| 465 | }; |
| 466 | |
| 467 | /* Get RSS table size */ |
| 468 | struct rss_sz_msg { |
| 469 | u8 msg; |
| 470 | u8 vf_id; |
| 471 | u16 ind_tbl_size; |
| 472 | }; |
| 473 | |
| 474 | /* Set RSS configuration */ |
| 475 | struct rss_cfg_msg { |
| 476 | u8 msg; |
| 477 | u8 vf_id; |
| 478 | u8 hash_bits; |
| 479 | u8 tbl_len; |
| 480 | u8 tbl_offset; |
| 481 | #define RSS_IND_TBL_LEN_PER_MBX_MSG 8 |
| 482 | u8 ind_tbl[RSS_IND_TBL_LEN_PER_MBX_MSG]; |
| 483 | }; |
| 484 | |
| 485 | struct bgx_stats_msg { |
| 486 | u8 msg; |
| 487 | u8 vf_id; |
| 488 | u8 rx; |
| 489 | u8 idx; |
| 490 | u64 stats; |
| 491 | }; |
| 492 | |
| 493 | /* Physical interface link status */ |
| 494 | struct bgx_link_status { |
| 495 | u8 msg; |
Thanneeru Srinivasulu | 1cc7025 | 2016-11-24 14:48:01 +0530 | [diff] [blame] | 496 | u8 mac_type; |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 497 | u8 link_up; |
| 498 | u8 duplex; |
| 499 | u32 speed; |
| 500 | }; |
| 501 | |
Sunil Goutham | 92dc876 | 2015-08-30 12:29:15 +0300 | [diff] [blame] | 502 | /* Get Extra Qset IDs */ |
| 503 | struct sqs_alloc { |
| 504 | u8 msg; |
| 505 | u8 vf_id; |
| 506 | u8 qs_count; |
| 507 | }; |
| 508 | |
| 509 | struct nicvf_ptr { |
| 510 | u8 msg; |
| 511 | u8 vf_id; |
| 512 | bool sqs_mode; |
| 513 | u8 sqs_id; |
| 514 | u64 nicvf; |
| 515 | }; |
| 516 | |
Sunil Goutham | d77a238 | 2015-08-30 12:29:16 +0300 | [diff] [blame] | 517 | /* Set interface in loopback mode */ |
| 518 | struct set_loopback { |
| 519 | u8 msg; |
| 520 | u8 vf_id; |
| 521 | bool enable; |
| 522 | }; |
| 523 | |
Jerin Jacob | 3458c40 | 2016-08-12 16:51:39 +0530 | [diff] [blame] | 524 | /* Reset statistics counters */ |
| 525 | struct reset_stat_cfg { |
| 526 | u8 msg; |
| 527 | /* Bitmap to select NIC_PF_VNIC(vf_id)_RX_STAT(0..13) */ |
| 528 | u16 rx_stat_mask; |
| 529 | /* Bitmap to select NIC_PF_VNIC(vf_id)_TX_STAT(0..4) */ |
| 530 | u8 tx_stat_mask; |
| 531 | /* Bitmap to select NIC_PF_QS(0..127)_RQ(0..7)_STAT(0..1) |
| 532 | * bit14, bit15 NIC_PF_QS(vf_id)_RQ7_STAT(0..1) |
| 533 | * bit12, bit13 NIC_PF_QS(vf_id)_RQ6_STAT(0..1) |
| 534 | * .. |
| 535 | * bit2, bit3 NIC_PF_QS(vf_id)_RQ1_STAT(0..1) |
| 536 | * bit0, bit1 NIC_PF_QS(vf_id)_RQ0_STAT(0..1) |
| 537 | */ |
| 538 | u16 rq_stat_mask; |
| 539 | /* Bitmap to select NIC_PF_QS(0..127)_SQ(0..7)_STAT(0..1) |
| 540 | * bit14, bit15 NIC_PF_QS(vf_id)_SQ7_STAT(0..1) |
| 541 | * bit12, bit13 NIC_PF_QS(vf_id)_SQ6_STAT(0..1) |
| 542 | * .. |
| 543 | * bit2, bit3 NIC_PF_QS(vf_id)_SQ1_STAT(0..1) |
| 544 | * bit0, bit1 NIC_PF_QS(vf_id)_SQ0_STAT(0..1) |
| 545 | */ |
| 546 | u16 sq_stat_mask; |
| 547 | }; |
| 548 | |
Sunil Goutham | 430da20 | 2016-11-24 14:48:03 +0530 | [diff] [blame] | 549 | struct pfc { |
| 550 | u8 msg; |
| 551 | u8 get; /* Get or set PFC settings */ |
| 552 | u8 autoneg; |
| 553 | u8 fc_rx; |
| 554 | u8 fc_tx; |
| 555 | }; |
| 556 | |
Sunil Goutham | 4a87550 | 2018-01-15 18:44:57 +0600 | [diff] [blame] | 557 | struct set_ptp { |
| 558 | u8 msg; |
| 559 | bool enable; |
| 560 | }; |
| 561 | |
Vadim Lomovtsev | 0b849f5 | 2018-03-30 04:59:50 -0700 | [diff] [blame^] | 562 | struct xcast { |
| 563 | u8 msg; |
| 564 | union { |
| 565 | u8 mode; |
| 566 | u64 mac; |
| 567 | } data; |
| 568 | }; |
| 569 | |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 570 | /* 128 bit shared memory between PF and each VF */ |
| 571 | union nic_mbx { |
| 572 | struct { u8 msg; } msg; |
| 573 | struct nic_cfg_msg nic_cfg; |
| 574 | struct qs_cfg_msg qs; |
| 575 | struct rq_cfg_msg rq; |
| 576 | struct sq_cfg_msg sq; |
| 577 | struct set_mac_msg mac; |
| 578 | struct set_frs_msg frs; |
| 579 | struct cpi_cfg_msg cpi_cfg; |
| 580 | struct rss_sz_msg rss_size; |
| 581 | struct rss_cfg_msg rss_cfg; |
| 582 | struct bgx_stats_msg bgx_stats; |
| 583 | struct bgx_link_status link_status; |
Sunil Goutham | 92dc876 | 2015-08-30 12:29:15 +0300 | [diff] [blame] | 584 | struct sqs_alloc sqs_alloc; |
| 585 | struct nicvf_ptr nicvf; |
Sunil Goutham | d77a238 | 2015-08-30 12:29:16 +0300 | [diff] [blame] | 586 | struct set_loopback lbk; |
Jerin Jacob | 3458c40 | 2016-08-12 16:51:39 +0530 | [diff] [blame] | 587 | struct reset_stat_cfg reset_stat; |
Sunil Goutham | 430da20 | 2016-11-24 14:48:03 +0530 | [diff] [blame] | 588 | struct pfc pfc; |
Sunil Goutham | 4a87550 | 2018-01-15 18:44:57 +0600 | [diff] [blame] | 589 | struct set_ptp ptp; |
Vadim Lomovtsev | 0b849f5 | 2018-03-30 04:59:50 -0700 | [diff] [blame^] | 590 | struct xcast xcast; |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 591 | }; |
| 592 | |
Robert Richter | d768b67 | 2015-06-02 11:00:18 -0700 | [diff] [blame] | 593 | #define NIC_NODE_ID_MASK 0x03 |
| 594 | #define NIC_NODE_ID_SHIFT 44 |
| 595 | |
| 596 | static inline int nic_get_node_id(struct pci_dev *pdev) |
| 597 | { |
| 598 | u64 addr = pci_resource_start(pdev, PCI_CFG_REG_BAR_NUM); |
| 599 | return ((addr >> NIC_NODE_ID_SHIFT) & NIC_NODE_ID_MASK); |
| 600 | } |
| 601 | |
Sunil Goutham | 40fb5f8 | 2015-12-10 13:25:19 +0530 | [diff] [blame] | 602 | static inline bool pass1_silicon(struct pci_dev *pdev) |
| 603 | { |
Sunil Goutham | 02a72bd | 2016-08-12 16:51:28 +0530 | [diff] [blame] | 604 | return (pdev->revision < 8) && |
| 605 | (pdev->subsystem_device == PCI_SUBSYS_DEVID_88XX_NIC_PF); |
| 606 | } |
| 607 | |
| 608 | static inline bool pass2_silicon(struct pci_dev *pdev) |
| 609 | { |
| 610 | return (pdev->revision >= 8) && |
| 611 | (pdev->subsystem_device == PCI_SUBSYS_DEVID_88XX_NIC_PF); |
Sunil Goutham | 40fb5f8 | 2015-12-10 13:25:19 +0530 | [diff] [blame] | 612 | } |
| 613 | |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 614 | int nicvf_set_real_num_queues(struct net_device *netdev, |
| 615 | int tx_queues, int rx_queues); |
| 616 | int nicvf_open(struct net_device *netdev); |
| 617 | int nicvf_stop(struct net_device *netdev); |
| 618 | int nicvf_send_msg_to_pf(struct nicvf *vf, union nic_mbx *mbx); |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 619 | void nicvf_config_rss(struct nicvf *nic); |
| 620 | void nicvf_set_rss_key(struct nicvf *nic); |
Sunil Goutham | 4863dea | 2015-05-26 19:20:15 -0700 | [diff] [blame] | 621 | void nicvf_set_ethtool_ops(struct net_device *netdev); |
| 622 | void nicvf_update_stats(struct nicvf *nic); |
| 623 | void nicvf_update_lmac_stats(struct nicvf *nic); |
| 624 | |
| 625 | #endif /* NIC_H */ |