blob: f5900f04ff5c77b2fb352bf95f6c2c66a194b3c2 [file] [log] [blame]
Michael Buesch424047e2008-01-09 16:13:56 +01001/*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11n PHY support
5
6 Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING. If not, write to
20 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
21 Boston, MA 02110-1301, USA.
22
23*/
24
John W. Linville819d7722008-01-17 16:57:10 -050025#include <linux/delay.h>
26#include <linux/types.h>
27
Michael Buesch424047e2008-01-09 16:13:56 +010028#include "b43.h"
Michael Buesch3d0da752008-08-30 02:27:19 +020029#include "phy_n.h"
Michael Buesch53a6e232008-01-13 21:23:44 +010030#include "tables_nphy.h"
Rafał Miłeckibbec3982010-01-15 14:31:39 +010031#include "main.h"
Michael Buesch424047e2008-01-09 16:13:56 +010032
Rafał Miłeckif8187b52010-01-15 12:34:21 +010033struct nphy_txgains {
34 u16 txgm[2];
35 u16 pga[2];
36 u16 pad[2];
37 u16 ipa[2];
38};
39
40struct nphy_iqcal_params {
41 u16 txgm;
42 u16 pga;
43 u16 pad;
44 u16 ipa;
45 u16 cal_gain;
46 u16 ncorr[5];
47};
48
49struct nphy_iq_est {
50 s32 iq0_prod;
51 u32 i0_pwr;
52 u32 q0_pwr;
53 s32 iq1_prod;
54 u32 i1_pwr;
55 u32 q1_pwr;
56};
Michael Buesch424047e2008-01-09 16:13:56 +010057
Rafał Miłecki67c0d6e2010-01-17 13:04:02 +010058enum b43_nphy_rf_sequence {
59 B43_RFSEQ_RX2TX,
60 B43_RFSEQ_TX2RX,
61 B43_RFSEQ_RESET2RX,
62 B43_RFSEQ_UPDATE_GAINH,
63 B43_RFSEQ_UPDATE_GAINL,
64 B43_RFSEQ_UPDATE_GAINU,
65};
66
67static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
68 enum b43_nphy_rf_sequence seq);
69
Michael Buesch53a6e232008-01-13 21:23:44 +010070void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
71{//TODO
72}
73
Michael Buesch18c8ade2008-08-28 19:33:40 +020074static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
Michael Buesch53a6e232008-01-13 21:23:44 +010075{//TODO
76}
77
Michael Buesch18c8ade2008-08-28 19:33:40 +020078static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
79 bool ignore_tssi)
80{//TODO
81 return B43_TXPWR_RES_DONE;
82}
83
Michael Bueschd1591312008-01-14 00:05:57 +010084static void b43_chantab_radio_upload(struct b43_wldev *dev,
85 const struct b43_nphy_channeltab_entry *e)
86{
87 b43_radio_write16(dev, B2055_PLL_REF, e->radio_pll_ref);
88 b43_radio_write16(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
89 b43_radio_write16(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
90 b43_radio_write16(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
91 b43_radio_write16(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
92 b43_radio_write16(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
93 b43_radio_write16(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
94 b43_radio_write16(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
95 b43_radio_write16(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
96 b43_radio_write16(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
97 b43_radio_write16(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
98 b43_radio_write16(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
99 b43_radio_write16(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
100 b43_radio_write16(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
101 b43_radio_write16(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
102 b43_radio_write16(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
103 b43_radio_write16(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
104 b43_radio_write16(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
105 b43_radio_write16(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
106 b43_radio_write16(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
107 b43_radio_write16(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
108 b43_radio_write16(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
109}
110
111static void b43_chantab_phy_upload(struct b43_wldev *dev,
112 const struct b43_nphy_channeltab_entry *e)
113{
114 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
115 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
116 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
117 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
118 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
119 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
120}
121
122static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
123{
124 //TODO
125}
126
Michael Bueschef1a6282008-08-27 18:53:02 +0200127/* Tune the hardware to a new channel. */
128static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel)
Michael Buesch53a6e232008-01-13 21:23:44 +0100129{
Michael Bueschd1591312008-01-14 00:05:57 +0100130 const struct b43_nphy_channeltab_entry *tabent;
Michael Buesch53a6e232008-01-13 21:23:44 +0100131
Michael Bueschd1591312008-01-14 00:05:57 +0100132 tabent = b43_nphy_get_chantabent(dev, channel);
133 if (!tabent)
134 return -ESRCH;
135
136 //FIXME enable/disable band select upper20 in RXCTL
137 if (0 /*FIXME 5Ghz*/)
138 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x20);
139 else
140 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x50);
141 b43_chantab_radio_upload(dev, tabent);
142 udelay(50);
143 b43_radio_write16(dev, B2055_VCO_CAL10, 5);
144 b43_radio_write16(dev, B2055_VCO_CAL10, 45);
145 b43_radio_write16(dev, B2055_VCO_CAL10, 65);
146 udelay(300);
147 if (0 /*FIXME 5Ghz*/)
148 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
149 else
150 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
151 b43_chantab_phy_upload(dev, tabent);
152 b43_nphy_tx_power_fix(dev);
153
154 return 0;
Michael Buesch53a6e232008-01-13 21:23:44 +0100155}
156
157static void b43_radio_init2055_pre(struct b43_wldev *dev)
158{
159 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
160 ~B43_NPHY_RFCTL_CMD_PORFORCE);
161 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
162 B43_NPHY_RFCTL_CMD_CHIP0PU |
163 B43_NPHY_RFCTL_CMD_OEPORFORCE);
164 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
165 B43_NPHY_RFCTL_CMD_PORFORCE);
166}
167
168static void b43_radio_init2055_post(struct b43_wldev *dev)
169{
170 struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
171 struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo);
172 int i;
173 u16 val;
174
175 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
176 msleep(1);
Gábor Stefanik738f0f42009-08-03 01:28:12 +0200177 if ((sprom->revision != 4) ||
178 !(sprom->boardflags_hi & B43_BFH_RSSIINV)) {
Michael Buesch53a6e232008-01-13 21:23:44 +0100179 if ((binfo->vendor != PCI_VENDOR_ID_BROADCOM) ||
180 (binfo->type != 0x46D) ||
181 (binfo->rev < 0x41)) {
182 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
183 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
184 msleep(1);
185 }
186 }
187 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0x3F, 0x2C);
188 msleep(1);
189 b43_radio_write16(dev, B2055_CAL_MISC, 0x3C);
190 msleep(1);
191 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
192 msleep(1);
193 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
194 msleep(1);
195 b43_radio_set(dev, B2055_CAL_MISC, 0x1);
196 msleep(1);
197 b43_radio_set(dev, B2055_CAL_MISC, 0x40);
198 msleep(1);
199 for (i = 0; i < 100; i++) {
200 val = b43_radio_read16(dev, B2055_CAL_COUT2);
201 if (val & 0x80)
202 break;
203 udelay(10);
204 }
205 msleep(1);
206 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
207 msleep(1);
Michael Bueschef1a6282008-08-27 18:53:02 +0200208 nphy_channel_switch(dev, dev->phy.channel);
Michael Buesch53a6e232008-01-13 21:23:44 +0100209 b43_radio_write16(dev, B2055_C1_RX_BB_LPF, 0x9);
210 b43_radio_write16(dev, B2055_C2_RX_BB_LPF, 0x9);
211 b43_radio_write16(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
212 b43_radio_write16(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
213}
214
215/* Initialize a Broadcom 2055 N-radio */
216static void b43_radio_init2055(struct b43_wldev *dev)
217{
218 b43_radio_init2055_pre(dev);
219 if (b43_status(dev) < B43_STAT_INITIALIZED)
220 b2055_upload_inittab(dev, 0, 1);
221 else
222 b2055_upload_inittab(dev, 0/*FIXME on 5ghz band*/, 0);
223 b43_radio_init2055_post(dev);
224}
225
226void b43_nphy_radio_turn_on(struct b43_wldev *dev)
227{
228 b43_radio_init2055(dev);
229}
230
231void b43_nphy_radio_turn_off(struct b43_wldev *dev)
232{
233 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
234 ~B43_NPHY_RFCTL_CMD_EN);
235}
236
Rafał Miłecki4772ae12010-01-15 12:18:21 +0100237/*
238 * Upload the N-PHY tables.
239 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
240 */
Michael Buesch95b66ba2008-01-18 01:09:25 +0100241static void b43_nphy_tables_init(struct b43_wldev *dev)
242{
Rafał Miłecki4772ae12010-01-15 12:18:21 +0100243 if (dev->phy.rev < 3)
244 b43_nphy_rev0_1_2_tables_init(dev);
245 else
246 b43_nphy_rev3plus_tables_init(dev);
Michael Buesch95b66ba2008-01-18 01:09:25 +0100247}
248
249static void b43_nphy_workarounds(struct b43_wldev *dev)
250{
251 struct b43_phy *phy = &dev->phy;
252 unsigned int i;
253
254 b43_phy_set(dev, B43_NPHY_IQFLIP,
255 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
Michael Buesch95b66ba2008-01-18 01:09:25 +0100256 if (1 /* FIXME band is 2.4GHz */) {
257 b43_phy_set(dev, B43_NPHY_CLASSCTL,
258 B43_NPHY_CLASSCTL_CCKEN);
259 } else {
260 b43_phy_mask(dev, B43_NPHY_CLASSCTL,
261 ~B43_NPHY_CLASSCTL_CCKEN);
262 }
263 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
264 b43_phy_write(dev, B43_NPHY_TXFRAMEDELAY, 8);
265
266 /* Fixup some tables */
267 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0xA);
268 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0xA);
269 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
270 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
271 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0);
272 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0);
273 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
274 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
275 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x800);
276 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x800);
277
278 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
279 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
280 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
281 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
282
283 //TODO set RF sequence
284
285 /* Set narrowband clip threshold */
286 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 66);
287 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 66);
288
289 /* Set wideband clip 2 threshold */
290 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
291 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
292 21 << B43_NPHY_C1_CLIPWBTHRES_CLIP2_SHIFT);
293 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
294 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
295 21 << B43_NPHY_C2_CLIPWBTHRES_CLIP2_SHIFT);
296
297 /* Set Clip 2 detect */
298 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
299 B43_NPHY_C1_CGAINI_CL2DETECT);
300 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
301 B43_NPHY_C2_CGAINI_CL2DETECT);
302
303 if (0 /*FIXME*/) {
304 /* Set dwell lengths */
305 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 43);
306 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 43);
307 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 9);
308 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 9);
309
310 /* Set gain backoff */
311 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
312 ~B43_NPHY_C1_CGAINI_GAINBKOFF,
313 1 << B43_NPHY_C1_CGAINI_GAINBKOFF_SHIFT);
314 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
315 ~B43_NPHY_C2_CGAINI_GAINBKOFF,
316 1 << B43_NPHY_C2_CGAINI_GAINBKOFF_SHIFT);
317
318 /* Set HPVGA2 index */
319 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
320 ~B43_NPHY_C1_INITGAIN_HPVGA2,
321 6 << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
322 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
323 ~B43_NPHY_C2_INITGAIN_HPVGA2,
324 6 << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
325
326 //FIXME verify that the specs really mean to use autoinc here.
327 for (i = 0; i < 3; i++)
328 b43_ntab_write(dev, B43_NTAB16(7, 0x106) + i, 0x673);
329 }
330
331 /* Set minimum gain value */
332 b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN,
333 ~B43_NPHY_C1_MINGAIN,
334 23 << B43_NPHY_C1_MINGAIN_SHIFT);
335 b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN,
336 ~B43_NPHY_C2_MINGAIN,
337 23 << B43_NPHY_C2_MINGAIN_SHIFT);
338
339 if (phy->rev < 2) {
340 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
341 ~B43_NPHY_SCRAM_SIGCTL_SCM);
342 }
343
344 /* Set phase track alpha and beta */
345 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
346 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
347 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
348 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
349 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
350 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
351}
352
Rafał Miłeckie50cbcf2010-01-15 15:02:38 +0100353/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
354static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
355{
356 struct b43_phy_n *nphy = dev->phy.n;
357 enum ieee80211_band band;
358 u16 tmp;
359
360 if (!enable) {
361 nphy->rfctrl_intc1_save = b43_phy_read(dev,
362 B43_NPHY_RFCTL_INTC1);
363 nphy->rfctrl_intc2_save = b43_phy_read(dev,
364 B43_NPHY_RFCTL_INTC2);
365 band = b43_current_band(dev->wl);
366 if (dev->phy.rev >= 3) {
367 if (band == IEEE80211_BAND_5GHZ)
368 tmp = 0x600;
369 else
370 tmp = 0x480;
371 } else {
372 if (band == IEEE80211_BAND_5GHZ)
373 tmp = 0x180;
374 else
375 tmp = 0x120;
376 }
377 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
378 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
379 } else {
380 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
381 nphy->rfctrl_intc1_save);
382 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
383 nphy->rfctrl_intc2_save);
384 }
385}
386
Rafał Miłeckife3e46e2010-01-15 15:51:55 +0100387/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
388static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
389{
390 struct b43_phy_n *nphy = dev->phy.n;
391 u16 tmp;
392 enum ieee80211_band band = b43_current_band(dev->wl);
393 bool ipa = (nphy->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
394 (nphy->ipa5g_on && band == IEEE80211_BAND_5GHZ);
395
396 if (dev->phy.rev >= 3) {
397 if (ipa) {
398 tmp = 4;
399 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
400 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
401 }
402
403 tmp = 1;
404 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
405 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
406 }
407}
408
Rafał Miłecki4a933c82010-01-15 13:36:43 +0100409/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
410static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force)
411{
412 u32 tmslow;
413
414 if (dev->phy.type != B43_PHYTYPE_N)
415 return;
416
417 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
418 if (force)
419 tmslow |= SSB_TMSLOW_FGC;
420 else
421 tmslow &= ~SSB_TMSLOW_FGC;
422 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
423}
424
425/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
Michael Buesch95b66ba2008-01-18 01:09:25 +0100426static void b43_nphy_reset_cca(struct b43_wldev *dev)
427{
428 u16 bbcfg;
429
Rafał Miłecki4a933c82010-01-15 13:36:43 +0100430 b43_nphy_bmac_clock_fgc(dev, 1);
Michael Buesch95b66ba2008-01-18 01:09:25 +0100431 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
Rafał Miłecki4a933c82010-01-15 13:36:43 +0100432 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
433 udelay(1);
434 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
435 b43_nphy_bmac_clock_fgc(dev, 0);
Rafał Miłecki67c0d6e2010-01-17 13:04:02 +0100436 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
Michael Buesch95b66ba2008-01-18 01:09:25 +0100437}
438
Rafał Miłeckiad9716e2010-01-17 13:03:40 +0100439/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
440static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
441{
442 u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
443
444 mimocfg |= B43_NPHY_MIMOCFG_AUTO;
445 if (preamble == 1)
446 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
447 else
448 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
449
450 b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
451}
452
Rafał Miłecki4f4ab6c2010-01-17 13:03:55 +0100453/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
454static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
455{
456 struct b43_phy_n *nphy = dev->phy.n;
457
458 bool override = false;
459 u16 chain = 0x33;
460
461 if (nphy->txrx_chain == 0) {
462 chain = 0x11;
463 override = true;
464 } else if (nphy->txrx_chain == 1) {
465 chain = 0x22;
466 override = true;
467 }
468
469 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
470 ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
471 chain);
472
473 if (override)
474 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
475 B43_NPHY_RFSEQMODE_CAOVER);
476 else
477 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
478 ~B43_NPHY_RFSEQMODE_CAOVER);
479}
480
Rafał Miłecki2faa6b82010-01-15 15:26:12 +0100481/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
482static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
483 u16 samps, u8 time, bool wait)
484{
485 int i;
486 u16 tmp;
487
488 b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
489 b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
490 if (wait)
491 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
492 else
493 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
494
495 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
496
497 for (i = 1000; i; i--) {
498 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
499 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
500 est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
501 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
502 est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
503 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
504 est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
505 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
506
507 est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
508 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
509 est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
510 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
511 est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
512 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
513 return;
514 }
515 udelay(10);
516 }
517 memset(est, 0, sizeof(*est));
518}
519
Rafał Miłeckia67162a2010-01-15 15:16:25 +0100520/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
521static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
522 struct b43_phy_n_iq_comp *pcomp)
523{
524 if (write) {
525 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
526 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
527 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
528 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
529 } else {
530 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
531 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
532 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
533 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
534 }
535}
536
Rafał Miłecki026816f2010-01-17 13:03:28 +0100537/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
538static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
539{
540 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
541
542 b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
543 if (core == 0) {
544 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
545 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
546 } else {
547 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
548 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
549 }
550 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
551 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
552 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
553 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
554 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
555 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
556 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
557 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
558}
559
560/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
561static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
562{
563 u8 rxval, txval;
564 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
565
566 regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
567 if (core == 0) {
568 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
569 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
570 } else {
571 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
572 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
573 }
574 regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
575 regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
576 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
577 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
578 regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
579 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
580 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
581 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
582
583 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
584 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
585
586 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, (u16)~B43_NPHY_RFSEQCA_RXDIS,
587 ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
588 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
589 ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
590 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
591 (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
592 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
593 (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
594
595 if (core == 0) {
596 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
597 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
598 } else {
599 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
600 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
601 }
602
603 /* TODO: Call N PHY RF Ctrl Intc Override with 2, 0, 3 as arguments */
604 /* TODO: Call N PHY RF Intc Override with 8, 0, 3, 0 as arguments */
Rafał Miłecki67c0d6e2010-01-17 13:04:02 +0100605 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
Rafał Miłecki026816f2010-01-17 13:03:28 +0100606
607 if (core == 0) {
608 rxval = 1;
609 txval = 8;
610 } else {
611 rxval = 4;
612 txval = 2;
613 }
614
615 /* TODO: Call N PHY RF Ctrl Intc Override with 1, rxval, (core + 1) */
616 /* TODO: Call N PHY RF Ctrl Intc Override with 1, txval, (2 - core) */
617}
618
Rafał Miłecki34a56f22010-01-15 15:29:05 +0100619/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
620static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
621{
622 int i;
623 s32 iq;
624 u32 ii;
625 u32 qq;
626 int iq_nbits, qq_nbits;
627 int arsh, brsh;
628 u16 tmp, a, b;
629
630 struct nphy_iq_est est;
631 struct b43_phy_n_iq_comp old;
632 struct b43_phy_n_iq_comp new = { };
633 bool error = false;
634
635 if (mask == 0)
636 return;
637
638 b43_nphy_rx_iq_coeffs(dev, false, &old);
639 b43_nphy_rx_iq_coeffs(dev, true, &new);
640 b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
641 new = old;
642
643 for (i = 0; i < 2; i++) {
644 if (i == 0 && (mask & 1)) {
645 iq = est.iq0_prod;
646 ii = est.i0_pwr;
647 qq = est.q0_pwr;
648 } else if (i == 1 && (mask & 2)) {
649 iq = est.iq1_prod;
650 ii = est.i1_pwr;
651 qq = est.q1_pwr;
652 } else {
653 B43_WARN_ON(1);
654 continue;
655 }
656
657 if (ii + qq < 2) {
658 error = true;
659 break;
660 }
661
662 iq_nbits = fls(abs(iq));
663 qq_nbits = fls(qq);
664
665 arsh = iq_nbits - 20;
666 if (arsh >= 0) {
667 a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
668 tmp = ii >> arsh;
669 } else {
670 a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
671 tmp = ii << -arsh;
672 }
673 if (tmp == 0) {
674 error = true;
675 break;
676 }
677 a /= tmp;
678
679 brsh = qq_nbits - 11;
680 if (brsh >= 0) {
681 b = (qq << (31 - qq_nbits));
682 tmp = ii >> brsh;
683 } else {
684 b = (qq << (31 - qq_nbits));
685 tmp = ii << -brsh;
686 }
687 if (tmp == 0) {
688 error = true;
689 break;
690 }
691 b = int_sqrt(b / tmp - a * a) - (1 << 10);
692
693 if (i == 0 && (mask & 0x1)) {
694 if (dev->phy.rev >= 3) {
695 new.a0 = a & 0x3FF;
696 new.b0 = b & 0x3FF;
697 } else {
698 new.a0 = b & 0x3FF;
699 new.b0 = a & 0x3FF;
700 }
701 } else if (i == 1 && (mask & 0x2)) {
702 if (dev->phy.rev >= 3) {
703 new.a1 = a & 0x3FF;
704 new.b1 = b & 0x3FF;
705 } else {
706 new.a1 = b & 0x3FF;
707 new.b1 = a & 0x3FF;
708 }
709 }
710 }
711
712 if (error)
713 new = old;
714
715 b43_nphy_rx_iq_coeffs(dev, true, &new);
716}
717
Rafał Miłecki09146402010-01-15 15:17:10 +0100718/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
719static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
720{
721 u16 array[4];
722 int i;
723
724 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C50);
725 for (i = 0; i < 4; i++)
726 array[i] = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
727
728 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
729 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
730 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
731 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
732}
733
Rafał Miłeckibbec3982010-01-15 14:31:39 +0100734/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
735static void b43_nphy_write_clip_detection(struct b43_wldev *dev, u16 *clip_st)
736{
737 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
738 b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
739}
740
741/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
742static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
743{
744 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
745 clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
746}
747
748/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
749static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
750{
751 u16 tmp;
752
753 if (dev->dev->id.revision == 16)
754 b43_mac_suspend(dev);
755
756 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
757 tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
758 B43_NPHY_CLASSCTL_WAITEDEN);
759 tmp &= ~mask;
760 tmp |= (val & mask);
761 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
762
763 if (dev->dev->id.revision == 16)
764 b43_mac_enable(dev);
765
766 return tmp;
767}
768
Rafał Miłecki5c1a1402010-01-15 15:10:54 +0100769/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
770static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
771{
772 struct b43_phy *phy = &dev->phy;
773 struct b43_phy_n *nphy = phy->n;
774
775 if (enable) {
776 u16 clip[] = { 0xFFFF, 0xFFFF };
777 if (nphy->deaf_count++ == 0) {
778 nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
779 b43_nphy_classifier(dev, 0x7, 0);
780 b43_nphy_read_clip_detection(dev, nphy->clip_state);
781 b43_nphy_write_clip_detection(dev, clip);
782 }
783 b43_nphy_reset_cca(dev);
784 } else {
785 if (--nphy->deaf_count == 0) {
786 b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
787 b43_nphy_write_clip_detection(dev, nphy->clip_state);
788 }
789 }
790}
791
Rafał Miłecki53ae8e82010-01-17 13:03:48 +0100792/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
793static void b43_nphy_stop_playback(struct b43_wldev *dev)
794{
795 struct b43_phy_n *nphy = dev->phy.n;
796 u16 tmp;
797
798 if (nphy->hang_avoid)
799 b43_nphy_stay_in_carrier_search(dev, 1);
800
801 tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
802 if (tmp & 0x1)
803 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
804 else if (tmp & 0x2)
805 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, (u16)~0x8000);
806
807 b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
808
809 if (nphy->bb_mult_save & 0x80000000) {
810 tmp = nphy->bb_mult_save & 0xFFFF;
Rafał Miłeckid41a3552010-01-18 00:21:17 +0100811 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
Rafał Miłecki53ae8e82010-01-17 13:03:48 +0100812 nphy->bb_mult_save = 0;
813 }
814
815 if (nphy->hang_avoid)
816 b43_nphy_stay_in_carrier_search(dev, 0);
817}
818
Rafał Miłecki10a79872010-01-22 01:53:14 +0100819/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
820static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
821 u16 wait, bool iqmode, bool dac_test)
822{
823 struct b43_phy_n *nphy = dev->phy.n;
824 int i;
825 u16 seq_mode;
826 u32 tmp;
827
828 if (nphy->hang_avoid)
829 b43_nphy_stay_in_carrier_search(dev, true);
830
831 if ((nphy->bb_mult_save & 0x80000000) == 0) {
832 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
833 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
834 }
835
836 if (!dev->phy.is_40mhz)
837 tmp = 0x6464;
838 else
839 tmp = 0x4747;
840 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
841
842 if (nphy->hang_avoid)
843 b43_nphy_stay_in_carrier_search(dev, false);
844
845 b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
846
847 if (loops != 0xFFFF)
848 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
849 else
850 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
851
852 b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
853
854 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
855
856 b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
857 if (iqmode) {
858 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
859 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
860 } else {
861 if (dac_test)
862 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
863 else
864 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
865 }
866 for (i = 0; i < 100; i++) {
867 if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) {
868 i = 0;
869 break;
870 }
871 udelay(10);
872 }
873 if (i)
874 b43err(dev->wl, "run samples timeout\n");
875
876 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
877}
878
Rafał Miłecki6dcd9d92010-01-15 16:24:57 +0100879/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
880static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
881{
882 struct b43_phy_n *nphy = dev->phy.n;
883 int i, j;
884 u32 tmp;
885 u32 cur_real, cur_imag, real_part, imag_part;
886
887 u16 buffer[7];
888
889 if (nphy->hang_avoid)
890 b43_nphy_stay_in_carrier_search(dev, true);
891
Rafał Miłecki91458342010-01-18 00:21:35 +0100892 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
Rafał Miłecki6dcd9d92010-01-15 16:24:57 +0100893
894 for (i = 0; i < 2; i++) {
895 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
896 (buffer[i * 2 + 1] & 0x3FF);
897 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
898 (((i + 26) << 10) | 320));
899 for (j = 0; j < 128; j++) {
900 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
901 ((tmp >> 16) & 0xFFFF));
902 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
903 (tmp & 0xFFFF));
904 }
905 }
906
907 for (i = 0; i < 2; i++) {
908 tmp = buffer[5 + i];
909 real_part = (tmp >> 8) & 0xFF;
910 imag_part = (tmp & 0xFF);
911 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
912 (((i + 26) << 10) | 448));
913
914 if (dev->phy.rev >= 3) {
915 cur_real = real_part;
916 cur_imag = imag_part;
917 tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
918 }
919
920 for (j = 0; j < 128; j++) {
921 if (dev->phy.rev < 3) {
922 cur_real = (real_part * loscale[j] + 128) >> 8;
923 cur_imag = (imag_part * loscale[j] + 128) >> 8;
924 tmp = ((cur_real & 0xFF) << 8) |
925 (cur_imag & 0xFF);
926 }
927 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
928 ((tmp >> 16) & 0xFFFF));
929 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
930 (tmp & 0xFFFF));
931 }
932 }
933
934 if (dev->phy.rev >= 3) {
935 b43_shm_write16(dev, B43_SHM_SHARED,
936 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
937 b43_shm_write16(dev, B43_SHM_SHARED,
938 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
939 }
940
941 if (nphy->hang_avoid)
942 b43_nphy_stay_in_carrier_search(dev, false);
943}
944
Rafał Miłecki67c0d6e2010-01-17 13:04:02 +0100945/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
Michael Buesch95b66ba2008-01-18 01:09:25 +0100946static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
947 enum b43_nphy_rf_sequence seq)
948{
949 static const u16 trigger[] = {
950 [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
951 [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
952 [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
953 [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
954 [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
955 [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
956 };
957 int i;
Rafał Miłeckic57199b2010-01-17 13:04:08 +0100958 u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
Michael Buesch95b66ba2008-01-18 01:09:25 +0100959
960 B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
961
962 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
963 B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
964 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
965 for (i = 0; i < 200; i++) {
966 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
967 goto ok;
968 msleep(1);
969 }
970 b43err(dev->wl, "RF sequence status timeout\n");
971ok:
Rafał Miłeckic57199b2010-01-17 13:04:08 +0100972 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
Michael Buesch95b66ba2008-01-18 01:09:25 +0100973}
974
Rafał Miłecki75377b22010-01-22 01:53:13 +0100975/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
976static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
977 u16 value, u8 core, bool off)
978{
979 int i;
980 u8 index = fls(field);
981 u8 addr, en_addr, val_addr;
982 /* we expect only one bit set */
983 B43_WARN_ON(field & (~(1 << index)));
984
985 if (dev->phy.rev >= 3) {
986 const struct nphy_rf_control_override_rev3 *rf_ctrl;
987 for (i = 0; i < 2; i++) {
988 if (index == 0 || index == 16) {
989 b43err(dev->wl,
990 "Unsupported RF Ctrl Override call\n");
991 return;
992 }
993
994 rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
995 en_addr = B43_PHY_N((i == 0) ?
996 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
997 val_addr = B43_PHY_N((i == 0) ?
998 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
999
1000 if (off) {
1001 b43_phy_mask(dev, en_addr, ~(field));
1002 b43_phy_mask(dev, val_addr,
1003 ~(rf_ctrl->val_mask));
1004 } else {
1005 if (core == 0 || ((1 << core) & i) != 0) {
1006 b43_phy_set(dev, en_addr, field);
1007 b43_phy_maskset(dev, val_addr,
1008 ~(rf_ctrl->val_mask),
1009 (value << rf_ctrl->val_shift));
1010 }
1011 }
1012 }
1013 } else {
1014 const struct nphy_rf_control_override_rev2 *rf_ctrl;
1015 if (off) {
1016 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
1017 value = 0;
1018 } else {
1019 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
1020 }
1021
1022 for (i = 0; i < 2; i++) {
1023 if (index <= 1 || index == 16) {
1024 b43err(dev->wl,
1025 "Unsupported RF Ctrl Override call\n");
1026 return;
1027 }
1028
1029 if (index == 2 || index == 10 ||
1030 (index >= 13 && index <= 15)) {
1031 core = 1;
1032 }
1033
1034 rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
1035 addr = B43_PHY_N((i == 0) ?
1036 rf_ctrl->addr0 : rf_ctrl->addr1);
1037
1038 if ((core & (1 << i)) != 0)
1039 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
1040 (value << rf_ctrl->shift));
1041
1042 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1043 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1044 B43_NPHY_RFCTL_CMD_START);
1045 udelay(1);
1046 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
1047 }
1048 }
1049}
1050
Michael Buesch95b66ba2008-01-18 01:09:25 +01001051static void b43_nphy_bphy_init(struct b43_wldev *dev)
1052{
1053 unsigned int i;
1054 u16 val;
1055
1056 val = 0x1E1F;
1057 for (i = 0; i < 14; i++) {
1058 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
1059 val -= 0x202;
1060 }
1061 val = 0x3E3F;
1062 for (i = 0; i < 16; i++) {
1063 b43_phy_write(dev, B43_PHY_N_BMODE(0x97 + i), val);
1064 val -= 0x202;
1065 }
1066 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
1067}
1068
Rafał Miłecki3c956272010-01-15 14:38:32 +01001069/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
1070static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
1071 s8 offset, u8 core, u8 rail, u8 type)
1072{
1073 u16 tmp;
1074 bool core1or5 = (core == 1) || (core == 5);
1075 bool core2or5 = (core == 2) || (core == 5);
1076
1077 offset = clamp_val(offset, -32, 31);
1078 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
1079
1080 if (core1or5 && (rail == 0) && (type == 2))
1081 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
1082 if (core1or5 && (rail == 1) && (type == 2))
1083 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
1084 if (core2or5 && (rail == 0) && (type == 2))
1085 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
1086 if (core2or5 && (rail == 1) && (type == 2))
1087 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
1088 if (core1or5 && (rail == 0) && (type == 0))
1089 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
1090 if (core1or5 && (rail == 1) && (type == 0))
1091 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1092 if (core2or5 && (rail == 0) && (type == 0))
1093 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
1094 if (core2or5 && (rail == 1) && (type == 0))
1095 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
1096 if (core1or5 && (rail == 0) && (type == 1))
1097 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1098 if (core1or5 && (rail == 1) && (type == 1))
1099 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1100 if (core2or5 && (rail == 0) && (type == 1))
1101 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1102 if (core2or5 && (rail == 1) && (type == 1))
1103 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1104 if (core1or5 && (rail == 0) && (type == 6))
1105 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1106 if (core1or5 && (rail == 1) && (type == 6))
1107 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1108 if (core2or5 && (rail == 0) && (type == 6))
1109 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1110 if (core2or5 && (rail == 1) && (type == 6))
1111 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
1112 if (core1or5 && (rail == 0) && (type == 3))
1113 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1114 if (core1or5 && (rail == 1) && (type == 3))
1115 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1116 if (core2or5 && (rail == 0) && (type == 3))
1117 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1118 if (core2or5 && (rail == 1) && (type == 3))
1119 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
1120 if (core1or5 && (type == 4))
1121 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1122 if (core2or5 && (type == 4))
1123 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1124 if (core1or5 && (type == 5))
1125 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1126 if (core2or5 && (type == 5))
1127 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1128}
1129
1130/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
1131static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1132{
1133 u16 val;
1134
1135 if (dev->phy.rev >= 3) {
1136 /* TODO */
1137 } else {
1138 if (type < 3)
1139 val = 0;
1140 else if (type == 6)
1141 val = 1;
1142 else if (type == 3)
1143 val = 2;
1144 else
1145 val = 3;
1146
1147 val = (val << 12) | (val << 14);
1148 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1149 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
1150
1151 if (type < 3) {
1152 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
1153 (type + 1) << 4);
1154 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
1155 (type + 1) << 4);
1156 }
1157
1158 /* TODO use some definitions */
1159 if (code == 0) {
1160 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF, 0);
1161 if (type < 3) {
1162 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1163 0xFEC7, 0);
1164 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1165 0xEFDC, 0);
1166 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1167 0xFFFE, 0);
1168 udelay(20);
1169 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1170 0xFFFE, 0);
1171 }
1172 } else {
1173 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF,
1174 0x3000);
1175 if (type < 3) {
1176 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1177 0xFEC7, 0x0180);
1178 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1179 0xEFDC, (code << 1 | 0x1021));
1180 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1181 0xFFFE, 0x0001);
1182 udelay(20);
1183 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1184 0xFFFE, 0);
1185 }
1186 }
1187 }
1188}
1189
Rafał Miłeckidfb4aa52010-01-15 14:45:13 +01001190/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
1191static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
1192{
1193 int i;
1194 for (i = 0; i < 2; i++) {
1195 if (type == 2) {
1196 if (i == 0) {
1197 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1198 0xFC, buf[0]);
1199 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1200 0xFC, buf[1]);
1201 } else {
1202 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
1203 0xFC, buf[2 * i]);
1204 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1205 0xFC, buf[2 * i + 1]);
1206 }
1207 } else {
1208 if (i == 0)
1209 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1210 0xF3, buf[0] << 2);
1211 else
1212 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1213 0xF3, buf[2 * i + 1] << 2);
1214 }
1215 }
1216}
1217
1218/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
1219static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
1220 u8 nsamp)
1221{
1222 int i;
1223 int out;
1224 u16 save_regs_phy[9];
1225 u16 s[2];
1226
1227 if (dev->phy.rev >= 3) {
1228 save_regs_phy[0] = b43_phy_read(dev,
1229 B43_NPHY_RFCTL_LUT_TRSW_UP1);
1230 save_regs_phy[1] = b43_phy_read(dev,
1231 B43_NPHY_RFCTL_LUT_TRSW_UP2);
1232 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1233 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1234 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1235 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1236 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
1237 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
1238 }
1239
1240 b43_nphy_rssi_select(dev, 5, type);
1241
1242 if (dev->phy.rev < 2) {
1243 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
1244 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
1245 }
1246
1247 for (i = 0; i < 4; i++)
1248 buf[i] = 0;
1249
1250 for (i = 0; i < nsamp; i++) {
1251 if (dev->phy.rev < 2) {
1252 s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
1253 s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
1254 } else {
1255 s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
1256 s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
1257 }
1258
1259 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
1260 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
1261 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
1262 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
1263 }
1264 out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
1265 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
1266
1267 if (dev->phy.rev < 2)
1268 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
1269
1270 if (dev->phy.rev >= 3) {
1271 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
1272 save_regs_phy[0]);
1273 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1274 save_regs_phy[1]);
1275 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
1276 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
1277 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
1278 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
1279 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
1280 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
1281 }
1282
1283 return out;
1284}
1285
Rafał Miłecki4cb99772010-01-15 13:40:58 +01001286/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
1287static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
Michael Buesch95b66ba2008-01-18 01:09:25 +01001288{
Rafał Miłecki90b97382010-01-15 14:48:21 +01001289 int i, j;
1290 u8 state[4];
1291 u8 code, val;
1292 u16 class, override;
1293 u8 regs_save_radio[2];
1294 u16 regs_save_phy[2];
1295 s8 offset[4];
1296
1297 u16 clip_state[2];
1298 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1299 s32 results_min[4] = { };
1300 u8 vcm_final[4] = { };
1301 s32 results[4][4] = { };
1302 s32 miniq[4][2] = { };
1303
1304 if (type == 2) {
1305 code = 0;
1306 val = 6;
1307 } else if (type < 2) {
1308 code = 25;
1309 val = 4;
1310 } else {
1311 B43_WARN_ON(1);
1312 return;
1313 }
1314
1315 class = b43_nphy_classifier(dev, 0, 0);
1316 b43_nphy_classifier(dev, 7, 4);
1317 b43_nphy_read_clip_detection(dev, clip_state);
1318 b43_nphy_write_clip_detection(dev, clip_off);
1319
1320 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1321 override = 0x140;
1322 else
1323 override = 0x110;
1324
1325 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1326 regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
1327 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
1328 b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
1329
1330 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1331 regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
1332 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
1333 b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
1334
1335 state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
1336 state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
1337 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
1338 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
1339 state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
1340 state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
1341
1342 b43_nphy_rssi_select(dev, 5, type);
1343 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
1344 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
1345
1346 for (i = 0; i < 4; i++) {
1347 u8 tmp[4];
1348 for (j = 0; j < 4; j++)
1349 tmp[j] = i;
1350 if (type != 1)
1351 b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
1352 b43_nphy_poll_rssi(dev, type, results[i], 8);
1353 if (type < 2)
1354 for (j = 0; j < 2; j++)
1355 miniq[i][j] = min(results[i][2 * j],
1356 results[i][2 * j + 1]);
1357 }
1358
1359 for (i = 0; i < 4; i++) {
1360 s32 mind = 40;
1361 u8 minvcm = 0;
1362 s32 minpoll = 249;
1363 s32 curr;
1364 for (j = 0; j < 4; j++) {
1365 if (type == 2)
1366 curr = abs(results[j][i]);
1367 else
1368 curr = abs(miniq[j][i / 2] - code * 8);
1369
1370 if (curr < mind) {
1371 mind = curr;
1372 minvcm = j;
1373 }
1374
1375 if (results[j][i] < minpoll)
1376 minpoll = results[j][i];
1377 }
1378 results_min[i] = minpoll;
1379 vcm_final[i] = minvcm;
1380 }
1381
1382 if (type != 1)
1383 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
1384
1385 for (i = 0; i < 4; i++) {
1386 offset[i] = (code * 8) - results[vcm_final[i]][i];
1387
1388 if (offset[i] < 0)
1389 offset[i] = -((abs(offset[i]) + 4) / 8);
1390 else
1391 offset[i] = (offset[i] + 4) / 8;
1392
1393 if (results_min[i] == 248)
1394 offset[i] = code - 32;
1395
1396 if (i % 2 == 0)
1397 b43_nphy_scale_offset_rssi(dev, 0, offset[i], 1, 0,
1398 type);
1399 else
1400 b43_nphy_scale_offset_rssi(dev, 0, offset[i], 2, 1,
1401 type);
1402 }
1403
1404 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
1405 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[1]);
1406
1407 switch (state[2]) {
1408 case 1:
1409 b43_nphy_rssi_select(dev, 1, 2);
1410 break;
1411 case 4:
1412 b43_nphy_rssi_select(dev, 1, 0);
1413 break;
1414 case 2:
1415 b43_nphy_rssi_select(dev, 1, 1);
1416 break;
1417 default:
1418 b43_nphy_rssi_select(dev, 1, 1);
1419 break;
1420 }
1421
1422 switch (state[3]) {
1423 case 1:
1424 b43_nphy_rssi_select(dev, 2, 2);
1425 break;
1426 case 4:
1427 b43_nphy_rssi_select(dev, 2, 0);
1428 break;
1429 default:
1430 b43_nphy_rssi_select(dev, 2, 1);
1431 break;
1432 }
1433
1434 b43_nphy_rssi_select(dev, 0, type);
1435
1436 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
1437 b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
1438 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
1439 b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
1440
1441 b43_nphy_classifier(dev, 7, class);
1442 b43_nphy_write_clip_detection(dev, clip_state);
Rafał Miłecki4cb99772010-01-15 13:40:58 +01001443}
1444
1445/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
1446static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1447{
1448 /* TODO */
1449}
1450
1451/*
1452 * RSSI Calibration
1453 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
1454 */
1455static void b43_nphy_rssi_cal(struct b43_wldev *dev)
1456{
1457 if (dev->phy.rev >= 3) {
1458 b43_nphy_rev3_rssi_cal(dev);
1459 } else {
1460 b43_nphy_rev2_rssi_cal(dev, 2);
1461 b43_nphy_rev2_rssi_cal(dev, 0);
1462 b43_nphy_rev2_rssi_cal(dev, 1);
1463 }
Michael Buesch95b66ba2008-01-18 01:09:25 +01001464}
1465
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01001466/*
Rafał Miłecki42e15472010-01-15 15:06:47 +01001467 * Restore RSSI Calibration
1468 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
1469 */
1470static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
1471{
1472 struct b43_phy_n *nphy = dev->phy.n;
1473
1474 u16 *rssical_radio_regs = NULL;
1475 u16 *rssical_phy_regs = NULL;
1476
1477 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1478 if (!nphy->rssical_chanspec_2G)
1479 return;
1480 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
1481 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
1482 } else {
1483 if (!nphy->rssical_chanspec_5G)
1484 return;
1485 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
1486 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
1487 }
1488
1489 /* TODO use some definitions */
1490 b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
1491 b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
1492
1493 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
1494 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
1495 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
1496 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
1497
1498 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
1499 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
1500 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
1501 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
1502
1503 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
1504 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
1505 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
1506 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
1507}
1508
Rafał Miłecki2f258b72010-01-15 15:18:35 +01001509/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
1510static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
1511{
1512 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1513 if (dev->phy.rev >= 6) {
1514 /* TODO If the chip is 47162
1515 return txpwrctrl_tx_gain_ipa_rev5 */
1516 return txpwrctrl_tx_gain_ipa_rev6;
1517 } else if (dev->phy.rev >= 5) {
1518 return txpwrctrl_tx_gain_ipa_rev5;
1519 } else {
1520 return txpwrctrl_tx_gain_ipa;
1521 }
1522 } else {
1523 return txpwrctrl_tx_gain_ipa_5g;
1524 }
1525}
1526
Rafał Miłeckic4a92002010-01-15 15:55:18 +01001527/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
1528static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
1529{
1530 struct b43_phy_n *nphy = dev->phy.n;
1531 u16 *save = nphy->tx_rx_cal_radio_saveregs;
1532
1533 if (dev->phy.rev >= 3) {
1534 /* TODO */
1535 } else {
1536 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
1537 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
1538
1539 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
1540 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
1541
1542 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
1543 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
1544
1545 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
1546 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
1547
1548 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
1549 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
1550
1551 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
1552 B43_NPHY_BANDCTL_5GHZ)) {
1553 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
1554 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
1555 } else {
1556 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
1557 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
1558 }
1559
1560 if (dev->phy.rev < 2) {
1561 b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
1562 b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
1563 } else {
1564 b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
1565 b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
1566 }
1567 }
1568}
1569
Rafał Miłeckie9762492010-01-15 16:08:25 +01001570/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
1571static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
1572 struct nphy_txgains target,
1573 struct nphy_iqcal_params *params)
1574{
1575 int i, j, indx;
1576 u16 gain;
1577
1578 if (dev->phy.rev >= 3) {
1579 params->txgm = target.txgm[core];
1580 params->pga = target.pga[core];
1581 params->pad = target.pad[core];
1582 params->ipa = target.ipa[core];
1583 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
1584 (params->pad << 4) | (params->ipa);
1585 for (j = 0; j < 5; j++)
1586 params->ncorr[j] = 0x79;
1587 } else {
1588 gain = (target.pad[core]) | (target.pga[core] << 4) |
1589 (target.txgm[core] << 8);
1590
1591 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
1592 1 : 0;
1593 for (i = 0; i < 9; i++)
1594 if (tbl_iqcal_gainparams[indx][i][0] == gain)
1595 break;
1596 i = min(i, 8);
1597
1598 params->txgm = tbl_iqcal_gainparams[indx][i][1];
1599 params->pga = tbl_iqcal_gainparams[indx][i][2];
1600 params->pad = tbl_iqcal_gainparams[indx][i][3];
1601 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
1602 (params->pad << 2);
1603 for (j = 0; j < 4; j++)
1604 params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
1605 }
1606}
1607
Rafał Miłeckide7ed0c2010-01-15 16:06:35 +01001608/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
1609static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
1610{
1611 struct b43_phy_n *nphy = dev->phy.n;
1612 int i;
1613 u16 scale, entry;
1614
1615 u16 tmp = nphy->txcal_bbmult;
1616 if (core == 0)
1617 tmp >>= 8;
1618 tmp &= 0xff;
1619
1620 for (i = 0; i < 18; i++) {
1621 scale = (ladder_lo[i].percent * tmp) / 100;
1622 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
Rafał Miłeckid41a3552010-01-18 00:21:17 +01001623 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
Rafał Miłeckide7ed0c2010-01-15 16:06:35 +01001624
1625 scale = (ladder_iq[i].percent * tmp) / 100;
1626 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
Rafał Miłeckid41a3552010-01-18 00:21:17 +01001627 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
Rafał Miłeckide7ed0c2010-01-15 16:06:35 +01001628 }
1629}
1630
Rafał Miłeckib0022e12010-01-15 15:40:50 +01001631/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
1632static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
1633{
1634 struct b43_phy_n *nphy = dev->phy.n;
1635
1636 u16 curr_gain[2];
1637 struct nphy_txgains target;
1638 const u32 *table = NULL;
1639
1640 if (nphy->txpwrctrl == 0) {
1641 int i;
1642
1643 if (nphy->hang_avoid)
1644 b43_nphy_stay_in_carrier_search(dev, true);
Rafał Miłecki91458342010-01-18 00:21:35 +01001645 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
Rafał Miłeckib0022e12010-01-15 15:40:50 +01001646 if (nphy->hang_avoid)
1647 b43_nphy_stay_in_carrier_search(dev, false);
1648
1649 for (i = 0; i < 2; ++i) {
1650 if (dev->phy.rev >= 3) {
1651 target.ipa[i] = curr_gain[i] & 0x000F;
1652 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
1653 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
1654 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
1655 } else {
1656 target.ipa[i] = curr_gain[i] & 0x0003;
1657 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
1658 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
1659 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
1660 }
1661 }
1662 } else {
1663 int i;
1664 u16 index[2];
1665 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
1666 B43_NPHY_TXPCTL_STAT_BIDX) >>
1667 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
1668 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
1669 B43_NPHY_TXPCTL_STAT_BIDX) >>
1670 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
1671
1672 for (i = 0; i < 2; ++i) {
1673 if (dev->phy.rev >= 3) {
1674 enum ieee80211_band band =
1675 b43_current_band(dev->wl);
1676
1677 if ((nphy->ipa2g_on &&
1678 band == IEEE80211_BAND_2GHZ) ||
1679 (nphy->ipa5g_on &&
1680 band == IEEE80211_BAND_5GHZ)) {
1681 table = b43_nphy_get_ipa_gain_table(dev);
1682 } else {
1683 if (band == IEEE80211_BAND_5GHZ) {
1684 if (dev->phy.rev == 3)
1685 table = b43_ntab_tx_gain_rev3_5ghz;
1686 else if (dev->phy.rev == 4)
1687 table = b43_ntab_tx_gain_rev4_5ghz;
1688 else
1689 table = b43_ntab_tx_gain_rev5plus_5ghz;
1690 } else {
1691 table = b43_ntab_tx_gain_rev3plus_2ghz;
1692 }
1693 }
1694
1695 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
1696 target.pad[i] = (table[index[i]] >> 20) & 0xF;
1697 target.pga[i] = (table[index[i]] >> 24) & 0xF;
1698 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
1699 } else {
1700 table = b43_ntab_tx_gain_rev0_1_2;
1701
1702 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
1703 target.pad[i] = (table[index[i]] >> 18) & 0x3;
1704 target.pga[i] = (table[index[i]] >> 20) & 0x7;
1705 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
1706 }
1707 }
1708 }
1709
1710 return target;
1711}
1712
Rafał Miłeckie53de672010-01-17 13:03:32 +01001713/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
1714static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
1715{
1716 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
1717
1718 if (dev->phy.rev >= 3) {
1719 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
1720 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
1721 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
1722 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
1723 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
Rafał Miłeckid41a3552010-01-18 00:21:17 +01001724 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
1725 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
Rafał Miłeckie53de672010-01-17 13:03:32 +01001726 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
1727 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
1728 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
1729 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
1730 b43_nphy_reset_cca(dev);
1731 } else {
1732 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
1733 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
1734 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
Rafał Miłeckid41a3552010-01-18 00:21:17 +01001735 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
1736 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
Rafał Miłeckie53de672010-01-17 13:03:32 +01001737 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
1738 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
1739 }
1740}
1741
1742/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
1743static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
1744{
1745 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
1746 u16 tmp;
1747
1748 regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1749 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1750 if (dev->phy.rev >= 3) {
1751 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
1752 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
1753
1754 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1755 regs[2] = tmp;
1756 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
1757
1758 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1759 regs[3] = tmp;
1760 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
1761
1762 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
Rafał Miłeckide9a47f2010-01-18 00:21:49 +01001763 b43_phy_mask(dev, B43_NPHY_BBCFG, (u16)~B43_NPHY_BBCFG_RSTRX);
Rafał Miłeckie53de672010-01-17 13:03:32 +01001764
Rafał Miłeckic643a662010-01-18 00:21:27 +01001765 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
Rafał Miłeckie53de672010-01-17 13:03:32 +01001766 regs[5] = tmp;
Rafał Miłeckid41a3552010-01-18 00:21:17 +01001767 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
Rafał Miłeckic643a662010-01-18 00:21:27 +01001768
1769 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
Rafał Miłeckie53de672010-01-17 13:03:32 +01001770 regs[6] = tmp;
Rafał Miłeckid41a3552010-01-18 00:21:17 +01001771 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
Rafał Miłeckie53de672010-01-17 13:03:32 +01001772 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1773 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1774
1775 /* TODO: Call N PHY RF Ctrl Intc Override with 2, 1, 3 */
1776 /* TODO: Call N PHY RF Ctrl Intc Override with 1, 2, 1 */
1777 /* TODO: Call N PHY RF Ctrl Intc Override with 1, 8, 2 */
1778
1779 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
1780 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
1781 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
1782 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
1783 } else {
1784 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
1785 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
1786 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1787 regs[2] = tmp;
1788 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
Rafał Miłeckic643a662010-01-18 00:21:27 +01001789 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
Rafał Miłeckie53de672010-01-17 13:03:32 +01001790 regs[3] = tmp;
1791 tmp |= 0x2000;
Rafał Miłeckid41a3552010-01-18 00:21:17 +01001792 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
Rafał Miłeckic643a662010-01-18 00:21:27 +01001793 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
Rafał Miłeckie53de672010-01-17 13:03:32 +01001794 regs[4] = tmp;
1795 tmp |= 0x2000;
Rafał Miłeckid41a3552010-01-18 00:21:17 +01001796 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
Rafał Miłeckie53de672010-01-17 13:03:32 +01001797 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1798 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1799 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1800 tmp = 0x0180;
1801 else
1802 tmp = 0x0120;
1803 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
1804 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
1805 }
1806}
1807
Rafał Miłecki2f258b72010-01-15 15:18:35 +01001808/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
1809static void b43_nphy_restore_cal(struct b43_wldev *dev)
1810{
1811 struct b43_phy_n *nphy = dev->phy.n;
1812
1813 u16 coef[4];
1814 u16 *loft = NULL;
1815 u16 *table = NULL;
1816
1817 int i;
1818 u16 *txcal_radio_regs = NULL;
1819 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
1820
1821 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1822 if (nphy->iqcal_chanspec_2G == 0)
1823 return;
1824 table = nphy->cal_cache.txcal_coeffs_2G;
1825 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
1826 } else {
1827 if (nphy->iqcal_chanspec_5G == 0)
1828 return;
1829 table = nphy->cal_cache.txcal_coeffs_5G;
1830 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
1831 }
1832
Rafał Miłecki2581b142010-01-18 00:21:21 +01001833 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
Rafał Miłecki2f258b72010-01-15 15:18:35 +01001834
1835 for (i = 0; i < 4; i++) {
1836 if (dev->phy.rev >= 3)
1837 table[i] = coef[i];
1838 else
1839 coef[i] = 0;
1840 }
1841
Rafał Miłecki2581b142010-01-18 00:21:21 +01001842 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
1843 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
1844 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
Rafał Miłecki2f258b72010-01-15 15:18:35 +01001845
1846 if (dev->phy.rev < 2)
1847 b43_nphy_tx_iq_workaround(dev);
1848
1849 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1850 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
1851 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
1852 } else {
1853 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
1854 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
1855 }
1856
1857 /* TODO use some definitions */
1858 if (dev->phy.rev >= 3) {
1859 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
1860 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
1861 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
1862 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
1863 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
1864 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
1865 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
1866 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
1867 } else {
1868 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
1869 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
1870 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
1871 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
1872 }
1873 b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
1874}
1875
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +01001876/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
1877static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
1878 struct nphy_txgains target,
1879 bool full, bool mphase)
1880{
1881 struct b43_phy_n *nphy = dev->phy.n;
1882 int i;
1883 int error = 0;
1884 int freq;
1885 bool avoid = false;
1886 u8 length;
1887 u16 tmp, core, type, count, max, numb, last, cmd;
1888 const u16 *table;
1889 bool phy6or5x;
1890
1891 u16 buffer[11];
1892 u16 diq_start = 0;
1893 u16 save[2];
1894 u16 gain[2];
1895 struct nphy_iqcal_params params[2];
1896 bool updated[2] = { };
1897
1898 b43_nphy_stay_in_carrier_search(dev, true);
1899
1900 if (dev->phy.rev >= 4) {
1901 avoid = nphy->hang_avoid;
1902 nphy->hang_avoid = 0;
1903 }
1904
Rafał Miłecki91458342010-01-18 00:21:35 +01001905 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +01001906
1907 for (i = 0; i < 2; i++) {
1908 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
1909 gain[i] = params[i].cal_gain;
1910 }
Rafał Miłecki2581b142010-01-18 00:21:21 +01001911
1912 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +01001913
1914 b43_nphy_tx_cal_radio_setup(dev);
Rafał Miłeckie53de672010-01-17 13:03:32 +01001915 b43_nphy_tx_cal_phy_setup(dev);
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +01001916
1917 phy6or5x = dev->phy.rev >= 6 ||
1918 (dev->phy.rev == 5 && nphy->ipa2g_on &&
1919 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
1920 if (phy6or5x) {
1921 /* TODO */
1922 }
1923
1924 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
1925
Rafał Miłeckiaa4c7b22010-01-22 01:53:12 +01001926 if (!dev->phy.is_40mhz)
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +01001927 freq = 2500;
1928 else
1929 freq = 5000;
1930
1931 if (nphy->mphase_cal_phase_id > 2)
Rafał Miłecki10a79872010-01-22 01:53:14 +01001932 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
1933 0xFFFF, 0, true, false);
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +01001934 else
1935 ;/* TODO: Call N PHY TX Tone with freq, 250, 1, 0 as arguments
1936 and save result as error */
1937
1938 if (error == 0) {
1939 if (nphy->mphase_cal_phase_id > 2) {
1940 table = nphy->mphase_txcal_bestcoeffs;
1941 length = 11;
1942 if (dev->phy.rev < 3)
1943 length -= 2;
1944 } else {
1945 if (!full && nphy->txiqlocal_coeffsvalid) {
1946 table = nphy->txiqlocal_bestc;
1947 length = 11;
1948 if (dev->phy.rev < 3)
1949 length -= 2;
1950 } else {
1951 full = true;
1952 if (dev->phy.rev >= 3) {
1953 table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
1954 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
1955 } else {
1956 table = tbl_tx_iqlo_cal_startcoefs;
1957 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
1958 }
1959 }
1960 }
1961
Rafał Miłecki2581b142010-01-18 00:21:21 +01001962 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +01001963
1964 if (full) {
1965 if (dev->phy.rev >= 3)
1966 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
1967 else
1968 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
1969 } else {
1970 if (dev->phy.rev >= 3)
1971 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
1972 else
1973 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
1974 }
1975
1976 if (mphase) {
1977 count = nphy->mphase_txcal_cmdidx;
1978 numb = min(max,
1979 (u16)(count + nphy->mphase_txcal_numcmds));
1980 } else {
1981 count = 0;
1982 numb = max;
1983 }
1984
1985 for (; count < numb; count++) {
1986 if (full) {
1987 if (dev->phy.rev >= 3)
1988 cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
1989 else
1990 cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
1991 } else {
1992 if (dev->phy.rev >= 3)
1993 cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
1994 else
1995 cmd = tbl_tx_iqlo_cal_cmds_recal[count];
1996 }
1997
1998 core = (cmd & 0x3000) >> 12;
1999 type = (cmd & 0x0F00) >> 8;
2000
2001 if (phy6or5x && updated[core] == 0) {
2002 b43_nphy_update_tx_cal_ladder(dev, core);
2003 updated[core] = 1;
2004 }
2005
2006 tmp = (params[core].ncorr[type] << 8) | 0x66;
2007 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
2008
2009 if (type == 1 || type == 3 || type == 4) {
Rafał Miłeckic643a662010-01-18 00:21:27 +01002010 buffer[0] = b43_ntab_read(dev,
2011 B43_NTAB16(15, 69 + core));
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +01002012 diq_start = buffer[0];
2013 buffer[0] = 0;
Rafał Miłeckid41a3552010-01-18 00:21:17 +01002014 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
2015 0);
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +01002016 }
2017
2018 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
2019 for (i = 0; i < 2000; i++) {
2020 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
2021 if (tmp & 0xC000)
2022 break;
2023 udelay(10);
2024 }
2025
Rafał Miłecki91458342010-01-18 00:21:35 +01002026 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2027 buffer);
Rafał Miłecki2581b142010-01-18 00:21:21 +01002028 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
2029 buffer);
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +01002030
2031 if (type == 1 || type == 3 || type == 4)
2032 buffer[0] = diq_start;
2033 }
2034
2035 if (mphase)
2036 nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
2037
2038 last = (dev->phy.rev < 3) ? 6 : 7;
2039
2040 if (!mphase || nphy->mphase_cal_phase_id == last) {
Rafał Miłecki2581b142010-01-18 00:21:21 +01002041 b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
Rafał Miłecki91458342010-01-18 00:21:35 +01002042 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +01002043 if (dev->phy.rev < 3) {
2044 buffer[0] = 0;
2045 buffer[1] = 0;
2046 buffer[2] = 0;
2047 buffer[3] = 0;
2048 }
Rafał Miłecki2581b142010-01-18 00:21:21 +01002049 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
2050 buffer);
2051 b43_ntab_write_bulk(dev, B43_NTAB16(15, 101), 2,
2052 buffer);
2053 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
2054 buffer);
2055 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
2056 buffer);
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +01002057 length = 11;
2058 if (dev->phy.rev < 3)
2059 length -= 2;
Rafał Miłecki91458342010-01-18 00:21:35 +01002060 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2061 nphy->txiqlocal_bestc);
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +01002062 nphy->txiqlocal_coeffsvalid = true;
2063 /* TODO: Set nphy->txiqlocal_chanspec to
2064 the current channel */
2065 } else {
2066 length = 11;
2067 if (dev->phy.rev < 3)
2068 length -= 2;
Rafał Miłecki91458342010-01-18 00:21:35 +01002069 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2070 nphy->mphase_txcal_bestcoeffs);
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +01002071 }
2072
Rafał Miłecki53ae8e82010-01-17 13:03:48 +01002073 b43_nphy_stop_playback(dev);
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +01002074 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
2075 }
2076
Rafał Miłeckie53de672010-01-17 13:03:32 +01002077 b43_nphy_tx_cal_phy_cleanup(dev);
Rafał Miłecki2581b142010-01-18 00:21:21 +01002078 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +01002079
2080 if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
2081 b43_nphy_tx_iq_workaround(dev);
2082
2083 if (dev->phy.rev >= 4)
2084 nphy->hang_avoid = avoid;
2085
2086 b43_nphy_stay_in_carrier_search(dev, false);
2087
2088 return error;
2089}
2090
Rafał Miłecki15931e32010-01-15 16:20:56 +01002091/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
2092static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
2093 struct nphy_txgains target, u8 type, bool debug)
2094{
2095 struct b43_phy_n *nphy = dev->phy.n;
2096 int i, j, index;
2097 u8 rfctl[2];
2098 u8 afectl_core;
2099 u16 tmp[6];
2100 u16 cur_hpf1, cur_hpf2, cur_lna;
2101 u32 real, imag;
2102 enum ieee80211_band band;
2103
2104 u8 use;
2105 u16 cur_hpf;
2106 u16 lna[3] = { 3, 3, 1 };
2107 u16 hpf1[3] = { 7, 2, 0 };
2108 u16 hpf2[3] = { 2, 0, 0 };
Rafał Miłeckide9a47f2010-01-18 00:21:49 +01002109 u32 power[3] = { };
Rafał Miłecki15931e32010-01-15 16:20:56 +01002110 u16 gain_save[2];
2111 u16 cal_gain[2];
2112 struct nphy_iqcal_params cal_params[2];
2113 struct nphy_iq_est est;
2114 int ret = 0;
2115 bool playtone = true;
2116 int desired = 13;
2117
2118 b43_nphy_stay_in_carrier_search(dev, 1);
2119
2120 if (dev->phy.rev < 2)
2121 ;/* TODO: Call N PHY Reapply TX Cal Coeffs */
Rafał Miłecki91458342010-01-18 00:21:35 +01002122 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
Rafał Miłecki15931e32010-01-15 16:20:56 +01002123 for (i = 0; i < 2; i++) {
2124 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
2125 cal_gain[i] = cal_params[i].cal_gain;
2126 }
Rafał Miłecki2581b142010-01-18 00:21:21 +01002127 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
Rafał Miłecki15931e32010-01-15 16:20:56 +01002128
2129 for (i = 0; i < 2; i++) {
2130 if (i == 0) {
2131 rfctl[0] = B43_NPHY_RFCTL_INTC1;
2132 rfctl[1] = B43_NPHY_RFCTL_INTC2;
2133 afectl_core = B43_NPHY_AFECTL_C1;
2134 } else {
2135 rfctl[0] = B43_NPHY_RFCTL_INTC2;
2136 rfctl[1] = B43_NPHY_RFCTL_INTC1;
2137 afectl_core = B43_NPHY_AFECTL_C2;
2138 }
2139
2140 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
2141 tmp[2] = b43_phy_read(dev, afectl_core);
2142 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2143 tmp[4] = b43_phy_read(dev, rfctl[0]);
2144 tmp[5] = b43_phy_read(dev, rfctl[1]);
2145
2146 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
2147 (u16)~B43_NPHY_RFSEQCA_RXDIS,
2148 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
2149 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
2150 (1 - i));
2151 b43_phy_set(dev, afectl_core, 0x0006);
2152 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
2153
2154 band = b43_current_band(dev->wl);
2155
2156 if (nphy->rxcalparams & 0xFF000000) {
2157 if (band == IEEE80211_BAND_5GHZ)
2158 b43_phy_write(dev, rfctl[0], 0x140);
2159 else
2160 b43_phy_write(dev, rfctl[0], 0x110);
2161 } else {
2162 if (band == IEEE80211_BAND_5GHZ)
2163 b43_phy_write(dev, rfctl[0], 0x180);
2164 else
2165 b43_phy_write(dev, rfctl[0], 0x120);
2166 }
2167
2168 if (band == IEEE80211_BAND_5GHZ)
2169 b43_phy_write(dev, rfctl[1], 0x148);
2170 else
2171 b43_phy_write(dev, rfctl[1], 0x114);
2172
2173 if (nphy->rxcalparams & 0x10000) {
2174 b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
2175 (i + 1));
2176 b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
2177 (2 - i));
2178 }
2179
2180 for (j = 0; i < 4; j++) {
2181 if (j < 3) {
2182 cur_lna = lna[j];
2183 cur_hpf1 = hpf1[j];
2184 cur_hpf2 = hpf2[j];
2185 } else {
2186 if (power[1] > 10000) {
2187 use = 1;
2188 cur_hpf = cur_hpf1;
2189 index = 2;
2190 } else {
2191 if (power[0] > 10000) {
2192 use = 1;
2193 cur_hpf = cur_hpf1;
2194 index = 1;
2195 } else {
2196 index = 0;
2197 use = 2;
2198 cur_hpf = cur_hpf2;
2199 }
2200 }
2201 cur_lna = lna[index];
2202 cur_hpf1 = hpf1[index];
2203 cur_hpf2 = hpf2[index];
2204 cur_hpf += desired - hweight32(power[index]);
2205 cur_hpf = clamp_val(cur_hpf, 0, 10);
2206 if (use == 1)
2207 cur_hpf1 = cur_hpf;
2208 else
2209 cur_hpf2 = cur_hpf;
2210 }
2211
2212 tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
2213 (cur_lna << 2));
Rafał Miłecki75377b22010-01-22 01:53:13 +01002214 b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
2215 false);
Rafał Miłeckide9a47f2010-01-18 00:21:49 +01002216 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
Rafał Miłecki53ae8e82010-01-17 13:03:48 +01002217 b43_nphy_stop_playback(dev);
Rafał Miłecki15931e32010-01-15 16:20:56 +01002218
2219 if (playtone) {
2220 /* TODO: Call N PHY TX Tone with 4000,
2221 (nphy_rxcalparams & 0xffff), 0, 0
2222 as arguments and save result as ret */
2223 playtone = false;
2224 } else {
Rafał Miłecki10a79872010-01-22 01:53:14 +01002225 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
2226 false, false);
Rafał Miłecki15931e32010-01-15 16:20:56 +01002227 }
2228
2229 if (ret == 0) {
2230 if (j < 3) {
2231 b43_nphy_rx_iq_est(dev, &est, 1024, 32,
2232 false);
2233 if (i == 0) {
2234 real = est.i0_pwr;
2235 imag = est.q0_pwr;
2236 } else {
2237 real = est.i1_pwr;
2238 imag = est.q1_pwr;
2239 }
2240 power[i] = ((real + imag) / 1024) + 1;
2241 } else {
2242 b43_nphy_calc_rx_iq_comp(dev, 1 << i);
2243 }
Rafał Miłecki53ae8e82010-01-17 13:03:48 +01002244 b43_nphy_stop_playback(dev);
Rafał Miłecki15931e32010-01-15 16:20:56 +01002245 }
2246
2247 if (ret != 0)
2248 break;
2249 }
2250
2251 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
2252 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
2253 b43_phy_write(dev, rfctl[1], tmp[5]);
2254 b43_phy_write(dev, rfctl[0], tmp[4]);
2255 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
2256 b43_phy_write(dev, afectl_core, tmp[2]);
2257 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
2258
2259 if (ret != 0)
2260 break;
2261 }
2262
Rafał Miłecki75377b22010-01-22 01:53:13 +01002263 b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
Rafał Miłecki67c0d6e2010-01-17 13:04:02 +01002264 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
Rafał Miłecki2581b142010-01-18 00:21:21 +01002265 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
Rafał Miłecki15931e32010-01-15 16:20:56 +01002266
2267 b43_nphy_stay_in_carrier_search(dev, 0);
2268
2269 return ret;
2270}
2271
2272static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
2273 struct nphy_txgains target, u8 type, bool debug)
2274{
2275 return -1;
2276}
2277
2278/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
2279static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
2280 struct nphy_txgains target, u8 type, bool debug)
2281{
2282 if (dev->phy.rev >= 3)
2283 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
2284 else
2285 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
2286}
2287
Rafał Miłecki42e15472010-01-15 15:06:47 +01002288/*
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002289 * Init N-PHY
2290 * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
2291 */
Michael Buesch424047e2008-01-09 16:13:56 +01002292int b43_phy_initn(struct b43_wldev *dev)
2293{
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002294 struct ssb_bus *bus = dev->dev->bus;
Michael Buesch95b66ba2008-01-18 01:09:25 +01002295 struct b43_phy *phy = &dev->phy;
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002296 struct b43_phy_n *nphy = phy->n;
2297 u8 tx_pwr_state;
2298 struct nphy_txgains target;
Michael Buesch95b66ba2008-01-18 01:09:25 +01002299 u16 tmp;
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002300 enum ieee80211_band tmp2;
2301 bool do_rssi_cal;
Michael Buesch424047e2008-01-09 16:13:56 +01002302
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002303 u16 clip[2];
2304 bool do_cal = false;
2305
2306 if ((dev->phy.rev >= 3) &&
2307 (bus->sprom.boardflags_lo & B43_BFL_EXTLNA) &&
2308 (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
2309 chipco_set32(&dev->dev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40);
2310 }
2311 nphy->deaf_count = 0;
Michael Buesch95b66ba2008-01-18 01:09:25 +01002312 b43_nphy_tables_init(dev);
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002313 nphy->crsminpwr_adjusted = false;
2314 nphy->noisevars_adjusted = false;
Michael Buesch95b66ba2008-01-18 01:09:25 +01002315
2316 /* Clear all overrides */
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002317 if (dev->phy.rev >= 3) {
2318 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
2319 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
2320 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
2321 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
2322 } else {
2323 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
2324 }
Michael Buesch95b66ba2008-01-18 01:09:25 +01002325 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
2326 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002327 if (dev->phy.rev < 6) {
2328 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
2329 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
2330 }
Michael Buesch95b66ba2008-01-18 01:09:25 +01002331 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
2332 ~(B43_NPHY_RFSEQMODE_CAOVER |
2333 B43_NPHY_RFSEQMODE_TROVER));
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002334 if (dev->phy.rev >= 3)
2335 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
Michael Buesch95b66ba2008-01-18 01:09:25 +01002336 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
2337
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002338 if (dev->phy.rev <= 2) {
2339 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
2340 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
2341 ~B43_NPHY_BPHY_CTL3_SCALE,
2342 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
2343 }
Michael Buesch95b66ba2008-01-18 01:09:25 +01002344 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
2345 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
2346
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002347 if (bus->sprom.boardflags2_lo & 0x100 ||
2348 (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
2349 bus->boardinfo.type == 0x8B))
2350 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
2351 else
2352 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
2353 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
2354 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
2355 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
Michael Buesch95b66ba2008-01-18 01:09:25 +01002356
Rafał Miłeckiad9716e2010-01-17 13:03:40 +01002357 b43_nphy_update_mimo_config(dev, nphy->preamble_override);
Rafał Miłecki4f4ab6c2010-01-17 13:03:55 +01002358 b43_nphy_update_txrx_chain(dev);
Michael Buesch95b66ba2008-01-18 01:09:25 +01002359
2360 if (phy->rev < 2) {
2361 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
2362 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
2363 }
Michael Buesch95b66ba2008-01-18 01:09:25 +01002364
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002365 tmp2 = b43_current_band(dev->wl);
2366 if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) ||
2367 (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) {
2368 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
2369 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
2370 nphy->papd_epsilon_offset[0] << 7);
2371 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
2372 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
2373 nphy->papd_epsilon_offset[1] << 7);
2374 /* TODO N PHY IPA Set TX Dig Filters */
2375 } else if (phy->rev >= 5) {
2376 /* TODO N PHY Ext PA Set TX Dig Filters */
2377 }
2378
2379 b43_nphy_workarounds(dev);
2380
2381 /* Reset CCA, in init code it differs a little from standard way */
Rafał Miłecki730dd702010-01-15 16:38:07 +01002382 b43_nphy_bmac_clock_fgc(dev, 1);
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002383 tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
2384 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
2385 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
Rafał Miłecki730dd702010-01-15 16:38:07 +01002386 b43_nphy_bmac_clock_fgc(dev, 0);
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002387
2388 /* TODO N PHY MAC PHY Clock Set with argument 1 */
2389
Rafał Miłeckie50cbcf2010-01-15 15:02:38 +01002390 b43_nphy_pa_override(dev, false);
Michael Buesch95b66ba2008-01-18 01:09:25 +01002391 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
2392 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
Rafał Miłeckie50cbcf2010-01-15 15:02:38 +01002393 b43_nphy_pa_override(dev, true);
Michael Buesch95b66ba2008-01-18 01:09:25 +01002394
Rafał Miłeckibbec3982010-01-15 14:31:39 +01002395 b43_nphy_classifier(dev, 0, 0);
2396 b43_nphy_read_clip_detection(dev, clip);
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002397 tx_pwr_state = nphy->txpwrctrl;
2398 /* TODO N PHY TX power control with argument 0
2399 (turning off power control) */
2400 /* TODO Fix the TX Power Settings */
2401 /* TODO N PHY TX Power Control Idle TSSI */
2402 /* TODO N PHY TX Power Control Setup */
Michael Buesch95b66ba2008-01-18 01:09:25 +01002403
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002404 if (phy->rev >= 3) {
2405 /* TODO */
2406 } else {
Rafał Miłecki2581b142010-01-18 00:21:21 +01002407 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128,
2408 b43_ntab_tx_gain_rev0_1_2);
2409 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128,
2410 b43_ntab_tx_gain_rev0_1_2);
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002411 }
2412
2413 if (nphy->phyrxchain != 3)
2414 ;/* TODO N PHY RX Core Set State with phyrxchain as argument */
2415 if (nphy->mphase_cal_phase_id > 0)
2416 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
2417
2418 do_rssi_cal = false;
2419 if (phy->rev >= 3) {
2420 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2421 do_rssi_cal = (nphy->rssical_chanspec_2G == 0);
2422 else
2423 do_rssi_cal = (nphy->rssical_chanspec_5G == 0);
2424
2425 if (do_rssi_cal)
Rafał Miłecki4cb99772010-01-15 13:40:58 +01002426 b43_nphy_rssi_cal(dev);
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002427 else
Rafał Miłecki42e15472010-01-15 15:06:47 +01002428 b43_nphy_restore_rssi_cal(dev);
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002429 } else {
Rafał Miłecki4cb99772010-01-15 13:40:58 +01002430 b43_nphy_rssi_cal(dev);
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002431 }
2432
2433 if (!((nphy->measure_hold & 0x6) != 0)) {
2434 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2435 do_cal = (nphy->iqcal_chanspec_2G == 0);
2436 else
2437 do_cal = (nphy->iqcal_chanspec_5G == 0);
2438
2439 if (nphy->mute)
2440 do_cal = false;
2441
2442 if (do_cal) {
Rafał Miłeckib0022e12010-01-15 15:40:50 +01002443 target = b43_nphy_get_tx_gains(dev);
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002444
2445 if (nphy->antsel_type == 2)
2446 ;/*TODO NPHY Superswitch Init with argument 1*/
2447 if (nphy->perical != 2) {
Rafał Miłecki90b97382010-01-15 14:48:21 +01002448 b43_nphy_rssi_cal(dev);
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002449 if (phy->rev >= 3) {
2450 nphy->cal_orig_pwr_idx[0] =
2451 nphy->txpwrindex[0].index_internal;
2452 nphy->cal_orig_pwr_idx[1] =
2453 nphy->txpwrindex[1].index_internal;
2454 /* TODO N PHY Pre Calibrate TX Gain */
Rafał Miłeckib0022e12010-01-15 15:40:50 +01002455 target = b43_nphy_get_tx_gains(dev);
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002456 }
2457 }
2458 }
2459 }
2460
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002461 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) {
2462 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
Rafał Miłecki15931e32010-01-15 16:20:56 +01002463 ;/* Call N PHY Save Cal */
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002464 else if (nphy->mphase_cal_phase_id == 0)
Rafał Miłecki15931e32010-01-15 16:20:56 +01002465 ;/* N PHY Periodic Calibration with argument 3 */
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002466 } else {
2467 b43_nphy_restore_cal(dev);
2468 }
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002469
Rafał Miłecki6dcd9d92010-01-15 16:24:57 +01002470 b43_nphy_tx_pwr_ctrl_coef_setup(dev);
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002471 /* TODO N PHY TX Power Control Enable with argument tx_pwr_state */
2472 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
2473 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
2474 if (phy->rev >= 3 && phy->rev <= 6)
2475 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
Rafał Miłeckife3e46e2010-01-15 15:51:55 +01002476 b43_nphy_tx_lp_fbw(dev);
Rafał Miłecki0988a7a2010-01-15 13:27:29 +01002477 /* TODO N PHY Spur Workaround */
Michael Buesch95b66ba2008-01-18 01:09:25 +01002478
2479 b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
Michael Buesch53a6e232008-01-13 21:23:44 +01002480 return 0;
Michael Buesch424047e2008-01-09 16:13:56 +01002481}
Michael Bueschef1a6282008-08-27 18:53:02 +02002482
2483static int b43_nphy_op_allocate(struct b43_wldev *dev)
2484{
2485 struct b43_phy_n *nphy;
2486
2487 nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
2488 if (!nphy)
2489 return -ENOMEM;
2490 dev->phy.n = nphy;
2491
Michael Bueschef1a6282008-08-27 18:53:02 +02002492 return 0;
2493}
2494
Michael Bueschfb111372008-09-02 13:00:34 +02002495static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
2496{
2497 struct b43_phy *phy = &dev->phy;
2498 struct b43_phy_n *nphy = phy->n;
2499
2500 memset(nphy, 0, sizeof(*nphy));
2501
2502 //TODO init struct b43_phy_n
2503}
2504
2505static void b43_nphy_op_free(struct b43_wldev *dev)
2506{
2507 struct b43_phy *phy = &dev->phy;
2508 struct b43_phy_n *nphy = phy->n;
2509
2510 kfree(nphy);
2511 phy->n = NULL;
2512}
2513
Michael Bueschef1a6282008-08-27 18:53:02 +02002514static int b43_nphy_op_init(struct b43_wldev *dev)
2515{
Michael Bueschfb111372008-09-02 13:00:34 +02002516 return b43_phy_initn(dev);
Michael Bueschef1a6282008-08-27 18:53:02 +02002517}
2518
2519static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
2520{
2521#if B43_DEBUG
2522 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
2523 /* OFDM registers are onnly available on A/G-PHYs */
2524 b43err(dev->wl, "Invalid OFDM PHY access at "
2525 "0x%04X on N-PHY\n", offset);
2526 dump_stack();
2527 }
2528 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
2529 /* Ext-G registers are only available on G-PHYs */
2530 b43err(dev->wl, "Invalid EXT-G PHY access at "
2531 "0x%04X on N-PHY\n", offset);
2532 dump_stack();
2533 }
2534#endif /* B43_DEBUG */
2535}
2536
2537static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
2538{
2539 check_phyreg(dev, reg);
2540 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
2541 return b43_read16(dev, B43_MMIO_PHY_DATA);
2542}
2543
2544static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
2545{
2546 check_phyreg(dev, reg);
2547 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
2548 b43_write16(dev, B43_MMIO_PHY_DATA, value);
2549}
2550
2551static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
2552{
2553 /* Register 1 is a 32-bit register. */
2554 B43_WARN_ON(reg == 1);
2555 /* N-PHY needs 0x100 for read access */
2556 reg |= 0x100;
2557
2558 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
2559 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
2560}
2561
2562static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
2563{
2564 /* Register 1 is a 32-bit register. */
2565 B43_WARN_ON(reg == 1);
2566
2567 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
2568 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
2569}
2570
2571static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
Johannes Berg19d337d2009-06-02 13:01:37 +02002572 bool blocked)
Michael Bueschef1a6282008-08-27 18:53:02 +02002573{//TODO
2574}
2575
Michael Bueschcb24f572008-09-03 12:12:20 +02002576static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
2577{
2578 b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
2579 on ? 0 : 0x7FFF);
2580}
2581
Michael Bueschef1a6282008-08-27 18:53:02 +02002582static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
2583 unsigned int new_channel)
2584{
2585 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2586 if ((new_channel < 1) || (new_channel > 14))
2587 return -EINVAL;
2588 } else {
2589 if (new_channel > 200)
2590 return -EINVAL;
2591 }
2592
2593 return nphy_channel_switch(dev, new_channel);
2594}
2595
2596static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
2597{
2598 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2599 return 1;
2600 return 36;
2601}
2602
Michael Bueschef1a6282008-08-27 18:53:02 +02002603const struct b43_phy_operations b43_phyops_n = {
2604 .allocate = b43_nphy_op_allocate,
Michael Bueschfb111372008-09-02 13:00:34 +02002605 .free = b43_nphy_op_free,
2606 .prepare_structs = b43_nphy_op_prepare_structs,
Michael Bueschef1a6282008-08-27 18:53:02 +02002607 .init = b43_nphy_op_init,
Michael Bueschef1a6282008-08-27 18:53:02 +02002608 .phy_read = b43_nphy_op_read,
2609 .phy_write = b43_nphy_op_write,
2610 .radio_read = b43_nphy_op_radio_read,
2611 .radio_write = b43_nphy_op_radio_write,
2612 .software_rfkill = b43_nphy_op_software_rfkill,
Michael Bueschcb24f572008-09-03 12:12:20 +02002613 .switch_analog = b43_nphy_op_switch_analog,
Michael Bueschef1a6282008-08-27 18:53:02 +02002614 .switch_channel = b43_nphy_op_switch_channel,
2615 .get_default_chan = b43_nphy_op_get_default_chan,
Michael Buesch18c8ade2008-08-28 19:33:40 +02002616 .recalc_txpower = b43_nphy_op_recalc_txpower,
2617 .adjust_txpower = b43_nphy_op_adjust_txpower,
Michael Bueschef1a6282008-08-27 18:53:02 +02002618};