Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 1 | /******************************************************************************* |
| 2 | |
| 3 | Intel 82599 Virtual Function driver |
Jeff Kirsher | dec0d8e | 2015-02-10 11:42:33 +0000 | [diff] [blame] | 4 | Copyright(c) 1999 - 2015 Intel Corporation. |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 5 | |
| 6 | This program is free software; you can redistribute it and/or modify it |
| 7 | under the terms and conditions of the GNU General Public License, |
| 8 | version 2, as published by the Free Software Foundation. |
| 9 | |
| 10 | This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | more details. |
| 14 | |
| 15 | You should have received a copy of the GNU General Public License along with |
Jeff Kirsher | dec0d8e | 2015-02-10 11:42:33 +0000 | [diff] [blame] | 16 | this program; if not, see <http://www.gnu.org/licenses/>. |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 17 | |
| 18 | The full GNU General Public License is included in this distribution in |
| 19 | the file called "COPYING". |
| 20 | |
| 21 | Contact Information: |
| 22 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
| 23 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 24 | |
| 25 | *******************************************************************************/ |
| 26 | |
| 27 | #ifndef _IXGBEVF_H_ |
| 28 | #define _IXGBEVF_H_ |
| 29 | |
| 30 | #include <linux/types.h> |
Jiri Pirko | dadcd65 | 2011-07-21 03:25:09 +0000 | [diff] [blame] | 31 | #include <linux/bitops.h> |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 32 | #include <linux/timer.h> |
| 33 | #include <linux/io.h> |
| 34 | #include <linux/netdevice.h> |
Jiri Pirko | dadcd65 | 2011-07-21 03:25:09 +0000 | [diff] [blame] | 35 | #include <linux/if_vlan.h> |
Eric Dumazet | 4197aa7 | 2011-06-22 05:01:35 +0000 | [diff] [blame] | 36 | #include <linux/u64_stats_sync.h> |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 37 | |
| 38 | #include "vf.h" |
| 39 | |
Jacob Keller | c777cdf | 2013-09-21 06:24:20 +0000 | [diff] [blame] | 40 | #ifdef CONFIG_NET_RX_BUSY_POLL |
| 41 | #include <net/busy_poll.h> |
Jacob Keller | 3b5dca2 | 2013-09-21 06:24:25 +0000 | [diff] [blame] | 42 | #define BP_EXTENDED_STATS |
Jacob Keller | c777cdf | 2013-09-21 06:24:20 +0000 | [diff] [blame] | 43 | #endif |
| 44 | |
Emil Tantilov | e08400b | 2015-01-28 03:21:24 +0000 | [diff] [blame] | 45 | #define IXGBE_MAX_TXD_PWR 14 |
| 46 | #define IXGBE_MAX_DATA_PER_TXD BIT(IXGBE_MAX_TXD_PWR) |
| 47 | |
| 48 | /* Tx Descriptors needed, worst case */ |
| 49 | #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD) |
| 50 | #define DESC_NEEDED (MAX_SKB_FRAGS + 4) |
| 51 | |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 52 | /* wrapper around a pointer to a socket buffer, |
Jeff Kirsher | dec0d8e | 2015-02-10 11:42:33 +0000 | [diff] [blame] | 53 | * so a DMA handle can be stored along with the buffer |
| 54 | */ |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 55 | struct ixgbevf_tx_buffer { |
Alexander Duyck | e757e3e | 2013-01-31 07:43:22 +0000 | [diff] [blame] | 56 | union ixgbe_adv_tx_desc *next_to_watch; |
Emil Tantilov | 7ad1a09 | 2014-01-17 18:30:03 -0800 | [diff] [blame] | 57 | unsigned long time_stamp; |
| 58 | struct sk_buff *skb; |
| 59 | unsigned int bytecount; |
| 60 | unsigned short gso_segs; |
| 61 | __be16 protocol; |
Emil Tantilov | 9bdfefd | 2014-01-17 18:30:04 -0800 | [diff] [blame] | 62 | DEFINE_DMA_UNMAP_ADDR(dma); |
| 63 | DEFINE_DMA_UNMAP_LEN(len); |
Emil Tantilov | 7ad1a09 | 2014-01-17 18:30:03 -0800 | [diff] [blame] | 64 | u32 tx_flags; |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 65 | }; |
| 66 | |
| 67 | struct ixgbevf_rx_buffer { |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 68 | dma_addr_t dma; |
Emil Tantilov | bad1723 | 2014-11-21 02:57:15 +0000 | [diff] [blame] | 69 | struct page *page; |
| 70 | unsigned int page_offset; |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 71 | }; |
| 72 | |
Emil Tantilov | 095e261 | 2014-01-17 18:30:00 -0800 | [diff] [blame] | 73 | struct ixgbevf_stats { |
| 74 | u64 packets; |
| 75 | u64 bytes; |
| 76 | #ifdef BP_EXTENDED_STATS |
| 77 | u64 yields; |
| 78 | u64 misses; |
| 79 | u64 cleaned; |
| 80 | #endif |
| 81 | }; |
| 82 | |
| 83 | struct ixgbevf_tx_queue_stats { |
| 84 | u64 restart_queue; |
| 85 | u64 tx_busy; |
| 86 | u64 tx_done_old; |
| 87 | }; |
| 88 | |
| 89 | struct ixgbevf_rx_queue_stats { |
Emil Tantilov | 095e261 | 2014-01-17 18:30:00 -0800 | [diff] [blame] | 90 | u64 alloc_rx_page_failed; |
| 91 | u64 alloc_rx_buff_failed; |
| 92 | u64 csum_err; |
| 93 | }; |
| 94 | |
Emil Tantilov | e08400b | 2015-01-28 03:21:24 +0000 | [diff] [blame] | 95 | enum ixgbevf_ring_state_t { |
| 96 | __IXGBEVF_TX_DETECT_HANG, |
| 97 | __IXGBEVF_HANG_CHECK_ARMED, |
| 98 | }; |
| 99 | |
| 100 | #define check_for_tx_hang(ring) \ |
| 101 | test_bit(__IXGBEVF_TX_DETECT_HANG, &(ring)->state) |
| 102 | #define set_check_for_tx_hang(ring) \ |
| 103 | set_bit(__IXGBEVF_TX_DETECT_HANG, &(ring)->state) |
| 104 | #define clear_check_for_tx_hang(ring) \ |
| 105 | clear_bit(__IXGBEVF_TX_DETECT_HANG, &(ring)->state) |
| 106 | |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 107 | struct ixgbevf_ring { |
Alexander Duyck | 6b43c44 | 2012-05-11 08:32:45 +0000 | [diff] [blame] | 108 | struct ixgbevf_ring *next; |
Alexander Duyck | fb40195 | 2012-05-11 08:33:16 +0000 | [diff] [blame] | 109 | struct net_device *netdev; |
| 110 | struct device *dev; |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 111 | void *desc; /* descriptor ring memory */ |
| 112 | dma_addr_t dma; /* phys. address of descriptor ring */ |
| 113 | unsigned int size; /* length in bytes */ |
Emil Tantilov | bad1723 | 2014-11-21 02:57:15 +0000 | [diff] [blame] | 114 | u16 count; /* amount of descriptors */ |
| 115 | u16 next_to_use; |
| 116 | u16 next_to_clean; |
| 117 | u16 next_to_alloc; |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 118 | |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 119 | union { |
| 120 | struct ixgbevf_tx_buffer *tx_buffer_info; |
| 121 | struct ixgbevf_rx_buffer *rx_buffer_info; |
| 122 | }; |
Emil Tantilov | e08400b | 2015-01-28 03:21:24 +0000 | [diff] [blame] | 123 | unsigned long state; |
Emil Tantilov | 095e261 | 2014-01-17 18:30:00 -0800 | [diff] [blame] | 124 | struct ixgbevf_stats stats; |
| 125 | struct u64_stats_sync syncp; |
| 126 | union { |
| 127 | struct ixgbevf_tx_queue_stats tx_stats; |
| 128 | struct ixgbevf_rx_queue_stats rx_stats; |
| 129 | }; |
| 130 | |
Greg Rose | 55fb277 | 2012-11-06 05:53:32 +0000 | [diff] [blame] | 131 | u64 hw_csum_rx_error; |
Don Skidmore | 5cdab2f | 2013-10-30 07:45:39 +0000 | [diff] [blame] | 132 | u8 __iomem *tail; |
Emil Tantilov | bad1723 | 2014-11-21 02:57:15 +0000 | [diff] [blame] | 133 | struct sk_buff *skb; |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 134 | |
Jeff Kirsher | dec0d8e | 2015-02-10 11:42:33 +0000 | [diff] [blame] | 135 | /* holds the special value that gets the hardware register offset |
| 136 | * associated with this ring, which is different for DCB and RSS modes |
| 137 | */ |
| 138 | u16 reg_idx; |
Emil Tantilov | 095e261 | 2014-01-17 18:30:00 -0800 | [diff] [blame] | 139 | int queue_index; /* needed for multiqueue queue management */ |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 140 | }; |
| 141 | |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 142 | /* How many Rx Buffers do we bundle into one write to the hardware ? */ |
| 143 | #define IXGBEVF_RX_BUFFER_WRITE 16 /* Must be power of 2 */ |
| 144 | |
Alexander Duyck | 56e9409 | 2012-07-20 08:10:03 +0000 | [diff] [blame] | 145 | #define MAX_RX_QUEUES IXGBE_VF_MAX_RX_QUEUES |
| 146 | #define MAX_TX_QUEUES IXGBE_VF_MAX_TX_QUEUES |
Jeff Kirsher | dec0d8e | 2015-02-10 11:42:33 +0000 | [diff] [blame] | 147 | #define IXGBEVF_MAX_RSS_QUEUES 2 |
Vlad Zolotarov | 94cf66f | 2015-03-30 21:35:26 +0300 | [diff] [blame] | 148 | #define IXGBEVF_82599_RETA_SIZE 128 |
Vlad Zolotarov | ad1431e | 2015-03-30 21:35:28 +0300 | [diff] [blame] | 149 | #define IXGBEVF_RSS_HASH_KEY_SIZE 40 |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 150 | |
Jeff Kirsher | dec0d8e | 2015-02-10 11:42:33 +0000 | [diff] [blame] | 151 | #define IXGBEVF_DEFAULT_TXD 1024 |
| 152 | #define IXGBEVF_DEFAULT_RXD 512 |
| 153 | #define IXGBEVF_MAX_TXD 4096 |
| 154 | #define IXGBEVF_MIN_TXD 64 |
| 155 | #define IXGBEVF_MAX_RXD 4096 |
| 156 | #define IXGBEVF_MIN_RXD 64 |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 157 | |
| 158 | /* Supported Rx Buffer Sizes */ |
Jeff Kirsher | dec0d8e | 2015-02-10 11:42:33 +0000 | [diff] [blame] | 159 | #define IXGBEVF_RXBUFFER_256 256 /* Used for packet split */ |
| 160 | #define IXGBEVF_RXBUFFER_2048 2048 |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 161 | |
Jeff Kirsher | dec0d8e | 2015-02-10 11:42:33 +0000 | [diff] [blame] | 162 | #define IXGBEVF_RX_HDR_SIZE IXGBEVF_RXBUFFER_256 |
| 163 | #define IXGBEVF_RX_BUFSZ IXGBEVF_RXBUFFER_2048 |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 164 | |
| 165 | #define MAXIMUM_ETHERNET_VLAN_SIZE (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN) |
| 166 | |
| 167 | #define IXGBE_TX_FLAGS_CSUM (u32)(1) |
| 168 | #define IXGBE_TX_FLAGS_VLAN (u32)(1 << 1) |
| 169 | #define IXGBE_TX_FLAGS_TSO (u32)(1 << 2) |
| 170 | #define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3) |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 171 | #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000 |
| 172 | #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000 |
| 173 | #define IXGBE_TX_FLAGS_VLAN_SHIFT 16 |
| 174 | |
Alexander Duyck | 6b43c44 | 2012-05-11 08:32:45 +0000 | [diff] [blame] | 175 | struct ixgbevf_ring_container { |
| 176 | struct ixgbevf_ring *ring; /* pointer to linked list of rings */ |
Alexander Duyck | 5f3600e | 2012-05-11 08:32:55 +0000 | [diff] [blame] | 177 | unsigned int total_bytes; /* total bytes processed this int */ |
| 178 | unsigned int total_packets; /* total packets processed this int */ |
Alexander Duyck | 6b43c44 | 2012-05-11 08:32:45 +0000 | [diff] [blame] | 179 | u8 count; /* total number of rings in vector */ |
| 180 | u8 itr; /* current ITR setting for ring */ |
| 181 | }; |
| 182 | |
| 183 | /* iterator for handling rings in ring container */ |
| 184 | #define ixgbevf_for_each_ring(pos, head) \ |
| 185 | for (pos = (head).ring; pos != NULL; pos = pos->next) |
| 186 | |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 187 | /* MAX_MSIX_Q_VECTORS of these are allocated, |
| 188 | * but we only use one per queue-specific vector. |
| 189 | */ |
| 190 | struct ixgbevf_q_vector { |
| 191 | struct ixgbevf_adapter *adapter; |
Jeff Kirsher | dec0d8e | 2015-02-10 11:42:33 +0000 | [diff] [blame] | 192 | /* index of q_vector within array, also used for finding the bit in |
| 193 | * EICR and friends that represents the vector for this ring |
| 194 | */ |
| 195 | u16 v_idx; |
| 196 | u16 itr; /* Interrupt throttle rate written to EITR */ |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 197 | struct napi_struct napi; |
Alexander Duyck | 6b43c44 | 2012-05-11 08:32:45 +0000 | [diff] [blame] | 198 | struct ixgbevf_ring_container rx, tx; |
Alexander Duyck | fa71ae2 | 2012-05-11 08:32:50 +0000 | [diff] [blame] | 199 | char name[IFNAMSIZ + 9]; |
Jacob Keller | c777cdf | 2013-09-21 06:24:20 +0000 | [diff] [blame] | 200 | #ifdef CONFIG_NET_RX_BUSY_POLL |
| 201 | unsigned int state; |
| 202 | #define IXGBEVF_QV_STATE_IDLE 0 |
| 203 | #define IXGBEVF_QV_STATE_NAPI 1 /* NAPI owns this QV */ |
| 204 | #define IXGBEVF_QV_STATE_POLL 2 /* poll owns this QV */ |
| 205 | #define IXGBEVF_QV_STATE_DISABLED 4 /* QV is disabled */ |
Jeff Kirsher | dec0d8e | 2015-02-10 11:42:33 +0000 | [diff] [blame] | 206 | #define IXGBEVF_QV_OWNED (IXGBEVF_QV_STATE_NAPI | IXGBEVF_QV_STATE_POLL) |
| 207 | #define IXGBEVF_QV_LOCKED (IXGBEVF_QV_OWNED | IXGBEVF_QV_STATE_DISABLED) |
Jacob Keller | c777cdf | 2013-09-21 06:24:20 +0000 | [diff] [blame] | 208 | #define IXGBEVF_QV_STATE_NAPI_YIELD 8 /* NAPI yielded this QV */ |
| 209 | #define IXGBEVF_QV_STATE_POLL_YIELD 16 /* poll yielded this QV */ |
Jeff Kirsher | dec0d8e | 2015-02-10 11:42:33 +0000 | [diff] [blame] | 210 | #define IXGBEVF_QV_YIELD (IXGBEVF_QV_STATE_NAPI_YIELD | \ |
| 211 | IXGBEVF_QV_STATE_POLL_YIELD) |
| 212 | #define IXGBEVF_QV_USER_PEND (IXGBEVF_QV_STATE_POLL | \ |
| 213 | IXGBEVF_QV_STATE_POLL_YIELD) |
Jacob Keller | c777cdf | 2013-09-21 06:24:20 +0000 | [diff] [blame] | 214 | spinlock_t lock; |
| 215 | #endif /* CONFIG_NET_RX_BUSY_POLL */ |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 216 | }; |
Jeff Kirsher | dec0d8e | 2015-02-10 11:42:33 +0000 | [diff] [blame] | 217 | |
Jacob Keller | c777cdf | 2013-09-21 06:24:20 +0000 | [diff] [blame] | 218 | #ifdef CONFIG_NET_RX_BUSY_POLL |
| 219 | static inline void ixgbevf_qv_init_lock(struct ixgbevf_q_vector *q_vector) |
| 220 | { |
Jacob Keller | c777cdf | 2013-09-21 06:24:20 +0000 | [diff] [blame] | 221 | spin_lock_init(&q_vector->lock); |
| 222 | q_vector->state = IXGBEVF_QV_STATE_IDLE; |
| 223 | } |
| 224 | |
| 225 | /* called from the device poll routine to get ownership of a q_vector */ |
| 226 | static inline bool ixgbevf_qv_lock_napi(struct ixgbevf_q_vector *q_vector) |
| 227 | { |
| 228 | int rc = true; |
Jeff Kirsher | dec0d8e | 2015-02-10 11:42:33 +0000 | [diff] [blame] | 229 | |
Jacob Keller | c777cdf | 2013-09-21 06:24:20 +0000 | [diff] [blame] | 230 | spin_lock_bh(&q_vector->lock); |
| 231 | if (q_vector->state & IXGBEVF_QV_LOCKED) { |
| 232 | WARN_ON(q_vector->state & IXGBEVF_QV_STATE_NAPI); |
| 233 | q_vector->state |= IXGBEVF_QV_STATE_NAPI_YIELD; |
| 234 | rc = false; |
Jacob Keller | 3b5dca2 | 2013-09-21 06:24:25 +0000 | [diff] [blame] | 235 | #ifdef BP_EXTENDED_STATS |
Emil Tantilov | 095e261 | 2014-01-17 18:30:00 -0800 | [diff] [blame] | 236 | q_vector->tx.ring->stats.yields++; |
Jacob Keller | 3b5dca2 | 2013-09-21 06:24:25 +0000 | [diff] [blame] | 237 | #endif |
Jacob Keller | c777cdf | 2013-09-21 06:24:20 +0000 | [diff] [blame] | 238 | } else { |
| 239 | /* we don't care if someone yielded */ |
| 240 | q_vector->state = IXGBEVF_QV_STATE_NAPI; |
| 241 | } |
| 242 | spin_unlock_bh(&q_vector->lock); |
| 243 | return rc; |
| 244 | } |
| 245 | |
| 246 | /* returns true is someone tried to get the qv while napi had it */ |
| 247 | static inline bool ixgbevf_qv_unlock_napi(struct ixgbevf_q_vector *q_vector) |
| 248 | { |
| 249 | int rc = false; |
Jeff Kirsher | dec0d8e | 2015-02-10 11:42:33 +0000 | [diff] [blame] | 250 | |
Jacob Keller | c777cdf | 2013-09-21 06:24:20 +0000 | [diff] [blame] | 251 | spin_lock_bh(&q_vector->lock); |
| 252 | WARN_ON(q_vector->state & (IXGBEVF_QV_STATE_POLL | |
| 253 | IXGBEVF_QV_STATE_NAPI_YIELD)); |
| 254 | |
| 255 | if (q_vector->state & IXGBEVF_QV_STATE_POLL_YIELD) |
| 256 | rc = true; |
| 257 | /* reset state to idle, unless QV is disabled */ |
| 258 | q_vector->state &= IXGBEVF_QV_STATE_DISABLED; |
| 259 | spin_unlock_bh(&q_vector->lock); |
| 260 | return rc; |
| 261 | } |
| 262 | |
| 263 | /* called from ixgbevf_low_latency_poll() */ |
| 264 | static inline bool ixgbevf_qv_lock_poll(struct ixgbevf_q_vector *q_vector) |
| 265 | { |
| 266 | int rc = true; |
Jeff Kirsher | dec0d8e | 2015-02-10 11:42:33 +0000 | [diff] [blame] | 267 | |
Jacob Keller | c777cdf | 2013-09-21 06:24:20 +0000 | [diff] [blame] | 268 | spin_lock_bh(&q_vector->lock); |
| 269 | if ((q_vector->state & IXGBEVF_QV_LOCKED)) { |
| 270 | q_vector->state |= IXGBEVF_QV_STATE_POLL_YIELD; |
| 271 | rc = false; |
Jacob Keller | 3b5dca2 | 2013-09-21 06:24:25 +0000 | [diff] [blame] | 272 | #ifdef BP_EXTENDED_STATS |
Emil Tantilov | 095e261 | 2014-01-17 18:30:00 -0800 | [diff] [blame] | 273 | q_vector->rx.ring->stats.yields++; |
Jacob Keller | 3b5dca2 | 2013-09-21 06:24:25 +0000 | [diff] [blame] | 274 | #endif |
Jacob Keller | c777cdf | 2013-09-21 06:24:20 +0000 | [diff] [blame] | 275 | } else { |
| 276 | /* preserve yield marks */ |
| 277 | q_vector->state |= IXGBEVF_QV_STATE_POLL; |
| 278 | } |
| 279 | spin_unlock_bh(&q_vector->lock); |
| 280 | return rc; |
| 281 | } |
| 282 | |
| 283 | /* returns true if someone tried to get the qv while it was locked */ |
| 284 | static inline bool ixgbevf_qv_unlock_poll(struct ixgbevf_q_vector *q_vector) |
| 285 | { |
| 286 | int rc = false; |
Jeff Kirsher | dec0d8e | 2015-02-10 11:42:33 +0000 | [diff] [blame] | 287 | |
Jacob Keller | c777cdf | 2013-09-21 06:24:20 +0000 | [diff] [blame] | 288 | spin_lock_bh(&q_vector->lock); |
| 289 | WARN_ON(q_vector->state & (IXGBEVF_QV_STATE_NAPI)); |
| 290 | |
| 291 | if (q_vector->state & IXGBEVF_QV_STATE_POLL_YIELD) |
| 292 | rc = true; |
| 293 | /* reset state to idle, unless QV is disabled */ |
| 294 | q_vector->state &= IXGBEVF_QV_STATE_DISABLED; |
| 295 | spin_unlock_bh(&q_vector->lock); |
| 296 | return rc; |
| 297 | } |
| 298 | |
| 299 | /* true if a socket is polling, even if it did not get the lock */ |
| 300 | static inline bool ixgbevf_qv_busy_polling(struct ixgbevf_q_vector *q_vector) |
| 301 | { |
| 302 | WARN_ON(!(q_vector->state & IXGBEVF_QV_OWNED)); |
| 303 | return q_vector->state & IXGBEVF_QV_USER_PEND; |
| 304 | } |
| 305 | |
| 306 | /* false if QV is currently owned */ |
| 307 | static inline bool ixgbevf_qv_disable(struct ixgbevf_q_vector *q_vector) |
| 308 | { |
| 309 | int rc = true; |
Jeff Kirsher | dec0d8e | 2015-02-10 11:42:33 +0000 | [diff] [blame] | 310 | |
Jacob Keller | c777cdf | 2013-09-21 06:24:20 +0000 | [diff] [blame] | 311 | spin_lock_bh(&q_vector->lock); |
| 312 | if (q_vector->state & IXGBEVF_QV_OWNED) |
| 313 | rc = false; |
Jacob Keller | e689e72 | 2014-01-16 02:30:06 -0800 | [diff] [blame] | 314 | q_vector->state |= IXGBEVF_QV_STATE_DISABLED; |
Jacob Keller | c777cdf | 2013-09-21 06:24:20 +0000 | [diff] [blame] | 315 | spin_unlock_bh(&q_vector->lock); |
| 316 | return rc; |
| 317 | } |
| 318 | |
| 319 | #endif /* CONFIG_NET_RX_BUSY_POLL */ |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 320 | |
Jeff Kirsher | dec0d8e | 2015-02-10 11:42:33 +0000 | [diff] [blame] | 321 | /* microsecond values for various ITR rates shifted by 2 to fit itr register |
Alexander Duyck | 5f3600e | 2012-05-11 08:32:55 +0000 | [diff] [blame] | 322 | * with the first 3 bits reserved 0 |
| 323 | */ |
| 324 | #define IXGBE_MIN_RSC_ITR 24 |
| 325 | #define IXGBE_100K_ITR 40 |
| 326 | #define IXGBE_20K_ITR 200 |
| 327 | #define IXGBE_10K_ITR 400 |
| 328 | #define IXGBE_8K_ITR 500 |
| 329 | |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 330 | /* Helper macros to switch between ints/sec and what the register uses. |
| 331 | * And yes, it's the same math going both ways. The lowest value |
| 332 | * supported by all of the ixgbe hardware is 8. |
| 333 | */ |
| 334 | #define EITR_INTS_PER_SEC_TO_REG(_eitr) \ |
| 335 | ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8) |
| 336 | #define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG |
| 337 | |
Emil Tantilov | ec62fe2 | 2014-11-08 01:39:20 +0000 | [diff] [blame] | 338 | /* ixgbevf_test_staterr - tests bits in Rx descriptor status and error fields */ |
| 339 | static inline __le32 ixgbevf_test_staterr(union ixgbe_adv_rx_desc *rx_desc, |
| 340 | const u32 stat_err_bits) |
| 341 | { |
| 342 | return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); |
| 343 | } |
| 344 | |
Don Skidmore | f880d07 | 2013-10-23 02:17:52 +0000 | [diff] [blame] | 345 | static inline u16 ixgbevf_desc_unused(struct ixgbevf_ring *ring) |
| 346 | { |
| 347 | u16 ntc = ring->next_to_clean; |
| 348 | u16 ntu = ring->next_to_use; |
| 349 | |
| 350 | return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; |
| 351 | } |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 352 | |
Mark Rustad | 06380db | 2014-03-04 03:02:23 +0000 | [diff] [blame] | 353 | static inline void ixgbevf_write_tail(struct ixgbevf_ring *ring, u32 value) |
| 354 | { |
| 355 | writel(value, ring->tail); |
| 356 | } |
| 357 | |
Jeff Kirsher | dec0d8e | 2015-02-10 11:42:33 +0000 | [diff] [blame] | 358 | #define IXGBEVF_RX_DESC(R, i) \ |
Alexander Duyck | 908421f | 2012-05-11 08:33:00 +0000 | [diff] [blame] | 359 | (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i])) |
Jeff Kirsher | dec0d8e | 2015-02-10 11:42:33 +0000 | [diff] [blame] | 360 | #define IXGBEVF_TX_DESC(R, i) \ |
Alexander Duyck | 908421f | 2012-05-11 08:33:00 +0000 | [diff] [blame] | 361 | (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i])) |
Jeff Kirsher | dec0d8e | 2015-02-10 11:42:33 +0000 | [diff] [blame] | 362 | #define IXGBEVF_TX_CTXTDESC(R, i) \ |
Alexander Duyck | 908421f | 2012-05-11 08:33:00 +0000 | [diff] [blame] | 363 | (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i])) |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 364 | |
Alexander Duyck | c88887e | 2012-08-22 02:04:37 +0000 | [diff] [blame] | 365 | #define IXGBE_MAX_JUMBO_FRAME_SIZE 9728 /* Maximum Supported Size 9.5KB */ |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 366 | |
Jeff Kirsher | dec0d8e | 2015-02-10 11:42:33 +0000 | [diff] [blame] | 367 | #define OTHER_VECTOR 1 |
| 368 | #define NON_Q_VECTORS (OTHER_VECTOR) |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 369 | |
Jeff Kirsher | dec0d8e | 2015-02-10 11:42:33 +0000 | [diff] [blame] | 370 | #define MAX_MSIX_Q_VECTORS 2 |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 371 | |
Jeff Kirsher | dec0d8e | 2015-02-10 11:42:33 +0000 | [diff] [blame] | 372 | #define MIN_MSIX_Q_VECTORS 1 |
| 373 | #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS) |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 374 | |
| 375 | /* board specific private data structure */ |
| 376 | struct ixgbevf_adapter { |
Emil Tantilov | dff8052 | 2014-11-08 01:39:25 +0000 | [diff] [blame] | 377 | /* this field must be first, see ixgbevf_process_skb_fields */ |
Jiri Pirko | dadcd65 | 2011-07-21 03:25:09 +0000 | [diff] [blame] | 378 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
Emil Tantilov | dff8052 | 2014-11-08 01:39:25 +0000 | [diff] [blame] | 379 | |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 380 | struct ixgbevf_q_vector *q_vector[MAX_MSIX_Q_VECTORS]; |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 381 | |
| 382 | /* Interrupt Throttle Rate */ |
Alexander Duyck | 5f3600e | 2012-05-11 08:32:55 +0000 | [diff] [blame] | 383 | u16 rx_itr_setting; |
| 384 | u16 tx_itr_setting; |
| 385 | |
| 386 | /* interrupt masks */ |
| 387 | u32 eims_enable_mask; |
| 388 | u32 eims_other; |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 389 | |
| 390 | /* TX */ |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 391 | int num_tx_queues; |
Emil Tantilov | 9703192 | 2014-01-17 18:30:01 -0800 | [diff] [blame] | 392 | struct ixgbevf_ring *tx_ring[MAX_TX_QUEUES]; /* One per active queue */ |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 393 | u64 restart_queue; |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 394 | u32 tx_timeout_count; |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 395 | |
| 396 | /* RX */ |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 397 | int num_rx_queues; |
Emil Tantilov | 9703192 | 2014-01-17 18:30:01 -0800 | [diff] [blame] | 398 | struct ixgbevf_ring *rx_ring[MAX_TX_QUEUES]; /* One per active queue */ |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 399 | u64 hw_csum_rx_error; |
| 400 | u64 hw_rx_no_dma_resources; |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 401 | int num_msix_vectors; |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 402 | u32 alloc_rx_page_failed; |
| 403 | u32 alloc_rx_buff_failed; |
| 404 | |
| 405 | /* Some features need tri-state capability, |
| 406 | * thus the additional *_CAPABLE flags. |
| 407 | */ |
| 408 | u32 flags; |
Emil Tantilov | 9ac5c5c | 2015-01-28 03:21:34 +0000 | [diff] [blame] | 409 | #define IXGBEVF_FLAG_RESET_REQUESTED (u32)(1) |
Don Skidmore | 220fe05 | 2013-09-21 01:40:49 +0000 | [diff] [blame] | 410 | #define IXGBEVF_FLAG_QUEUE_RESET_REQUESTED (u32)(1 << 2) |
Alexander Duyck | 77d5dfc | 2012-05-11 08:32:19 +0000 | [diff] [blame] | 411 | |
Emil Tantilov | 9703192 | 2014-01-17 18:30:01 -0800 | [diff] [blame] | 412 | struct msix_entry *msix_entries; |
| 413 | |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 414 | /* OS defined structs */ |
| 415 | struct net_device *netdev; |
| 416 | struct pci_dev *pdev; |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 417 | |
| 418 | /* structs defined in ixgbe_vf.h */ |
| 419 | struct ixgbe_hw hw; |
| 420 | u16 msg_enable; |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 421 | /* Interrupt Throttle Rate */ |
| 422 | u32 eitr_param; |
| 423 | |
Emil Tantilov | 9703192 | 2014-01-17 18:30:01 -0800 | [diff] [blame] | 424 | struct ixgbevf_hw_stats stats; |
| 425 | |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 426 | unsigned long state; |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 427 | u64 tx_busy; |
| 428 | unsigned int tx_ring_count; |
| 429 | unsigned int rx_ring_count; |
| 430 | |
Jacob Keller | 3b5dca2 | 2013-09-21 06:24:25 +0000 | [diff] [blame] | 431 | #ifdef BP_EXTENDED_STATS |
| 432 | u64 bp_rx_yields; |
| 433 | u64 bp_rx_cleaned; |
| 434 | u64 bp_rx_missed; |
| 435 | |
| 436 | u64 bp_tx_yields; |
| 437 | u64 bp_tx_cleaned; |
| 438 | u64 bp_tx_missed; |
| 439 | #endif |
| 440 | |
Mark Rustad | dbf8b0d | 2014-03-04 03:02:34 +0000 | [diff] [blame] | 441 | u8 __iomem *io_addr; /* Mainly for iounmap use */ |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 442 | u32 link_speed; |
| 443 | bool link_up; |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 444 | |
Emil Tantilov | 9ac5c5c | 2015-01-28 03:21:34 +0000 | [diff] [blame] | 445 | struct timer_list service_timer; |
| 446 | struct work_struct service_task; |
| 447 | |
Alexander Duyck | 1c55ed7 | 2012-05-11 08:33:06 +0000 | [diff] [blame] | 448 | spinlock_t mbx_lock; |
Emil Tantilov | e66c92a | 2015-01-28 03:21:29 +0000 | [diff] [blame] | 449 | unsigned long last_reset; |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 450 | }; |
| 451 | |
| 452 | enum ixbgevf_state_t { |
| 453 | __IXGBEVF_TESTING, |
| 454 | __IXGBEVF_RESETTING, |
Mark Rustad | 2e7cfbd | 2014-03-04 03:02:13 +0000 | [diff] [blame] | 455 | __IXGBEVF_DOWN, |
Mark Rustad | bc0c715 | 2014-03-12 00:38:45 +0000 | [diff] [blame] | 456 | __IXGBEVF_DISABLED, |
Mark Rustad | 2e7cfbd | 2014-03-04 03:02:13 +0000 | [diff] [blame] | 457 | __IXGBEVF_REMOVING, |
Emil Tantilov | 9ac5c5c | 2015-01-28 03:21:34 +0000 | [diff] [blame] | 458 | __IXGBEVF_SERVICE_SCHED, |
| 459 | __IXGBEVF_SERVICE_INITED, |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 460 | }; |
| 461 | |
| 462 | enum ixgbevf_boards { |
| 463 | board_82599_vf, |
Greg Rose | 2316aa2 | 2010-12-02 07:12:26 +0000 | [diff] [blame] | 464 | board_X540_vf, |
Emil Tantilov | 47068b0 | 2014-11-22 07:59:56 +0000 | [diff] [blame] | 465 | board_X550_vf, |
| 466 | board_X550EM_x_vf, |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 467 | }; |
| 468 | |
Stephen Hemminger | 3d8fe98 | 2012-01-18 22:13:34 +0000 | [diff] [blame] | 469 | extern const struct ixgbevf_info ixgbevf_82599_vf_info; |
| 470 | extern const struct ixgbevf_info ixgbevf_X540_vf_info; |
Emil Tantilov | 47068b0 | 2014-11-22 07:59:56 +0000 | [diff] [blame] | 471 | extern const struct ixgbevf_info ixgbevf_X550_vf_info; |
| 472 | extern const struct ixgbevf_info ixgbevf_X550EM_x_vf_info; |
Stephen Hemminger | b5417bf | 2012-01-18 22:13:33 +0000 | [diff] [blame] | 473 | extern const struct ixgbe_mbx_operations ixgbevf_mbx_ops; |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 474 | |
| 475 | /* needed by ethtool.c */ |
Stephen Hemminger | 3d8fe98 | 2012-01-18 22:13:34 +0000 | [diff] [blame] | 476 | extern const char ixgbevf_driver_name[]; |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 477 | extern const char ixgbevf_driver_version[]; |
| 478 | |
Joe Perches | 5ccc921 | 2013-09-23 11:37:59 -0700 | [diff] [blame] | 479 | void ixgbevf_up(struct ixgbevf_adapter *adapter); |
| 480 | void ixgbevf_down(struct ixgbevf_adapter *adapter); |
| 481 | void ixgbevf_reinit_locked(struct ixgbevf_adapter *adapter); |
| 482 | void ixgbevf_reset(struct ixgbevf_adapter *adapter); |
| 483 | void ixgbevf_set_ethtool_ops(struct net_device *netdev); |
Emil Tantilov | 05d063a | 2014-01-17 18:29:59 -0800 | [diff] [blame] | 484 | int ixgbevf_setup_rx_resources(struct ixgbevf_ring *); |
| 485 | int ixgbevf_setup_tx_resources(struct ixgbevf_ring *); |
| 486 | void ixgbevf_free_rx_resources(struct ixgbevf_ring *); |
| 487 | void ixgbevf_free_tx_resources(struct ixgbevf_ring *); |
Joe Perches | 5ccc921 | 2013-09-23 11:37:59 -0700 | [diff] [blame] | 488 | void ixgbevf_update_stats(struct ixgbevf_adapter *adapter); |
| 489 | int ethtool_ioctl(struct ifreq *ifr); |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 490 | |
Jacob Keller | 3849623 | 2013-10-22 06:19:18 +0000 | [diff] [blame] | 491 | extern void ixgbevf_write_eitr(struct ixgbevf_q_vector *q_vector); |
| 492 | |
Joe Perches | 5ccc921 | 2013-09-23 11:37:59 -0700 | [diff] [blame] | 493 | void ixgbe_napi_add_all(struct ixgbevf_adapter *adapter); |
| 494 | void ixgbe_napi_del_all(struct ixgbevf_adapter *adapter); |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 495 | |
| 496 | #ifdef DEBUG |
Joe Perches | 5ccc921 | 2013-09-23 11:37:59 -0700 | [diff] [blame] | 497 | char *ixgbevf_get_hw_dev_name(struct ixgbe_hw *hw); |
Greg Rose | 92915f7 | 2010-01-09 02:24:10 +0000 | [diff] [blame] | 498 | #define hw_dbg(hw, format, arg...) \ |
| 499 | printk(KERN_DEBUG "%s: " format, ixgbevf_get_hw_dev_name(hw), ##arg) |
| 500 | #else |
| 501 | #define hw_dbg(hw, format, arg...) do {} while (0) |
| 502 | #endif |
| 503 | |
| 504 | #endif /* _IXGBEVF_H_ */ |