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Jeeja KPe4e2d2f2015-10-07 11:31:52 +01001/*
2 * skl-topology.c - Implements Platform component ALSA controls/widget
3 * handlers.
4 *
5 * Copyright (C) 2014-2015 Intel Corp
6 * Author: Jeeja KP <jeeja.kp@intel.com>
7 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 */
18
19#include <linux/slab.h>
20#include <linux/types.h>
21#include <linux/firmware.h>
22#include <sound/soc.h>
23#include <sound/soc-topology.h>
24#include "skl-sst-dsp.h"
25#include "skl-sst-ipc.h"
26#include "skl-topology.h"
27#include "skl.h"
28#include "skl-tplg-interface.h"
29
Jeeja KPf7590d42015-10-07 11:31:53 +010030#define SKL_CH_FIXUP_MASK (1 << 0)
31#define SKL_RATE_FIXUP_MASK (1 << 1)
32#define SKL_FMT_FIXUP_MASK (1 << 2)
33
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010034/*
35 * SKL DSP driver modelling uses only few DAPM widgets so for rest we will
36 * ignore. This helpers checks if the SKL driver handles this widget type
37 */
38static int is_skl_dsp_widget_type(struct snd_soc_dapm_widget *w)
39{
40 switch (w->id) {
41 case snd_soc_dapm_dai_link:
42 case snd_soc_dapm_dai_in:
43 case snd_soc_dapm_aif_in:
44 case snd_soc_dapm_aif_out:
45 case snd_soc_dapm_dai_out:
46 case snd_soc_dapm_switch:
47 return false;
48 default:
49 return true;
50 }
51}
52
53/*
54 * Each pipelines needs memory to be allocated. Check if we have free memory
55 * from available pool. Then only add this to pool
56 * This is freed when pipe is deleted
57 * Note: DSP does actual memory management we only keep track for complete
58 * pool
59 */
60static bool skl_tplg_alloc_pipe_mem(struct skl *skl,
61 struct skl_module_cfg *mconfig)
62{
63 struct skl_sst *ctx = skl->skl_sst;
64
65 if (skl->resource.mem + mconfig->pipe->memory_pages >
66 skl->resource.max_mem) {
67 dev_err(ctx->dev,
68 "%s: module_id %d instance %d\n", __func__,
69 mconfig->id.module_id,
70 mconfig->id.instance_id);
71 dev_err(ctx->dev,
72 "exceeds ppl memory available %d mem %d\n",
73 skl->resource.max_mem, skl->resource.mem);
74 return false;
75 }
76
77 skl->resource.mem += mconfig->pipe->memory_pages;
78 return true;
79}
80
81/*
82 * Pipeline needs needs DSP CPU resources for computation, this is
83 * quantified in MCPS (Million Clocks Per Second) required for module/pipe
84 *
85 * Each pipelines needs mcps to be allocated. Check if we have mcps for this
86 * pipe. This adds the mcps to driver counter
87 * This is removed on pipeline delete
88 */
89static bool skl_tplg_alloc_pipe_mcps(struct skl *skl,
90 struct skl_module_cfg *mconfig)
91{
92 struct skl_sst *ctx = skl->skl_sst;
93
94 if (skl->resource.mcps + mconfig->mcps > skl->resource.max_mcps) {
95 dev_err(ctx->dev,
96 "%s: module_id %d instance %d\n", __func__,
97 mconfig->id.module_id, mconfig->id.instance_id);
98 dev_err(ctx->dev,
99 "exceeds ppl memory available %d > mem %d\n",
100 skl->resource.max_mcps, skl->resource.mcps);
101 return false;
102 }
103
104 skl->resource.mcps += mconfig->mcps;
105 return true;
106}
107
108/*
109 * Free the mcps when tearing down
110 */
111static void
112skl_tplg_free_pipe_mcps(struct skl *skl, struct skl_module_cfg *mconfig)
113{
114 skl->resource.mcps -= mconfig->mcps;
115}
116
117/*
118 * Free the memory when tearing down
119 */
120static void
121skl_tplg_free_pipe_mem(struct skl *skl, struct skl_module_cfg *mconfig)
122{
123 skl->resource.mem -= mconfig->pipe->memory_pages;
124}
125
Jeeja KPf7590d42015-10-07 11:31:53 +0100126
127static void skl_dump_mconfig(struct skl_sst *ctx,
128 struct skl_module_cfg *mcfg)
129{
130 dev_dbg(ctx->dev, "Dumping config\n");
131 dev_dbg(ctx->dev, "Input Format:\n");
Hardik T Shah4cd98992015-10-27 09:22:55 +0900132 dev_dbg(ctx->dev, "channels = %d\n", mcfg->in_fmt[0].channels);
133 dev_dbg(ctx->dev, "s_freq = %d\n", mcfg->in_fmt[0].s_freq);
134 dev_dbg(ctx->dev, "ch_cfg = %d\n", mcfg->in_fmt[0].ch_cfg);
135 dev_dbg(ctx->dev, "valid bit depth = %d\n", mcfg->in_fmt[0].valid_bit_depth);
Jeeja KPf7590d42015-10-07 11:31:53 +0100136 dev_dbg(ctx->dev, "Output Format:\n");
Hardik T Shah4cd98992015-10-27 09:22:55 +0900137 dev_dbg(ctx->dev, "channels = %d\n", mcfg->out_fmt[0].channels);
138 dev_dbg(ctx->dev, "s_freq = %d\n", mcfg->out_fmt[0].s_freq);
139 dev_dbg(ctx->dev, "valid bit depth = %d\n", mcfg->out_fmt[0].valid_bit_depth);
140 dev_dbg(ctx->dev, "ch_cfg = %d\n", mcfg->out_fmt[0].ch_cfg);
Jeeja KPf7590d42015-10-07 11:31:53 +0100141}
142
143static void skl_tplg_update_params(struct skl_module_fmt *fmt,
144 struct skl_pipe_params *params, int fixup)
145{
146 if (fixup & SKL_RATE_FIXUP_MASK)
147 fmt->s_freq = params->s_freq;
148 if (fixup & SKL_CH_FIXUP_MASK)
149 fmt->channels = params->ch;
Jeeja KP98256f82015-11-23 22:26:25 +0530150 if (fixup & SKL_FMT_FIXUP_MASK) {
151 fmt->valid_bit_depth = skl_get_bit_depth(params->s_fmt);
152
153 /*
154 * 16 bit is 16 bit container whereas 24 bit is in 32 bit
155 * container so update bit depth accordingly
156 */
157 switch (fmt->valid_bit_depth) {
158 case SKL_DEPTH_16BIT:
159 fmt->bit_depth = fmt->valid_bit_depth;
160 break;
161
162 default:
163 fmt->bit_depth = SKL_DEPTH_32BIT;
164 break;
165 }
166 }
167
Jeeja KPf7590d42015-10-07 11:31:53 +0100168}
169
170/*
171 * A pipeline may have modules which impact the pcm parameters, like SRC,
172 * channel converter, format converter.
173 * We need to calculate the output params by applying the 'fixup'
174 * Topology will tell driver which type of fixup is to be applied by
175 * supplying the fixup mask, so based on that we calculate the output
176 *
177 * Now In FE the pcm hw_params is source/target format. Same is applicable
178 * for BE with its hw_params invoked.
179 * here based on FE, BE pipeline and direction we calculate the input and
180 * outfix and then apply that for a module
181 */
182static void skl_tplg_update_params_fixup(struct skl_module_cfg *m_cfg,
183 struct skl_pipe_params *params, bool is_fe)
184{
185 int in_fixup, out_fixup;
186 struct skl_module_fmt *in_fmt, *out_fmt;
187
Hardik T Shah4cd98992015-10-27 09:22:55 +0900188 /* Fixups will be applied to pin 0 only */
189 in_fmt = &m_cfg->in_fmt[0];
190 out_fmt = &m_cfg->out_fmt[0];
Jeeja KPf7590d42015-10-07 11:31:53 +0100191
192 if (params->stream == SNDRV_PCM_STREAM_PLAYBACK) {
193 if (is_fe) {
194 in_fixup = m_cfg->params_fixup;
195 out_fixup = (~m_cfg->converter) &
196 m_cfg->params_fixup;
197 } else {
198 out_fixup = m_cfg->params_fixup;
199 in_fixup = (~m_cfg->converter) &
200 m_cfg->params_fixup;
201 }
202 } else {
203 if (is_fe) {
204 out_fixup = m_cfg->params_fixup;
205 in_fixup = (~m_cfg->converter) &
206 m_cfg->params_fixup;
207 } else {
208 in_fixup = m_cfg->params_fixup;
209 out_fixup = (~m_cfg->converter) &
210 m_cfg->params_fixup;
211 }
212 }
213
214 skl_tplg_update_params(in_fmt, params, in_fixup);
215 skl_tplg_update_params(out_fmt, params, out_fixup);
216}
217
218/*
219 * A module needs input and output buffers, which are dependent upon pcm
220 * params, so once we have calculate params, we need buffer calculation as
221 * well.
222 */
223static void skl_tplg_update_buffer_size(struct skl_sst *ctx,
224 struct skl_module_cfg *mcfg)
225{
226 int multiplier = 1;
Hardik T Shah4cd98992015-10-27 09:22:55 +0900227 struct skl_module_fmt *in_fmt, *out_fmt;
228
229
230 /* Since fixups is applied to pin 0 only, ibs, obs needs
231 * change for pin 0 only
232 */
233 in_fmt = &mcfg->in_fmt[0];
234 out_fmt = &mcfg->out_fmt[0];
Jeeja KPf7590d42015-10-07 11:31:53 +0100235
236 if (mcfg->m_type == SKL_MODULE_TYPE_SRCINT)
237 multiplier = 5;
Hardik T Shah4cd98992015-10-27 09:22:55 +0900238 mcfg->ibs = (in_fmt->s_freq / 1000) *
239 (mcfg->in_fmt->channels) *
240 (mcfg->in_fmt->bit_depth >> 3) *
Jeeja KPf7590d42015-10-07 11:31:53 +0100241 multiplier;
242
Hardik T Shah4cd98992015-10-27 09:22:55 +0900243 mcfg->obs = (mcfg->out_fmt->s_freq / 1000) *
244 (mcfg->out_fmt->channels) *
245 (mcfg->out_fmt->bit_depth >> 3) *
Jeeja KPf7590d42015-10-07 11:31:53 +0100246 multiplier;
247}
248
249static void skl_tplg_update_module_params(struct snd_soc_dapm_widget *w,
250 struct skl_sst *ctx)
251{
252 struct skl_module_cfg *m_cfg = w->priv;
253 struct skl_pipe_params *params = m_cfg->pipe->p_params;
254 int p_conn_type = m_cfg->pipe->conn_type;
255 bool is_fe;
256
257 if (!m_cfg->params_fixup)
258 return;
259
260 dev_dbg(ctx->dev, "Mconfig for widget=%s BEFORE updation\n",
261 w->name);
262
263 skl_dump_mconfig(ctx, m_cfg);
264
265 if (p_conn_type == SKL_PIPE_CONN_TYPE_FE)
266 is_fe = true;
267 else
268 is_fe = false;
269
270 skl_tplg_update_params_fixup(m_cfg, params, is_fe);
271 skl_tplg_update_buffer_size(ctx, m_cfg);
272
273 dev_dbg(ctx->dev, "Mconfig for widget=%s AFTER updation\n",
274 w->name);
275
276 skl_dump_mconfig(ctx, m_cfg);
277}
278
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100279/*
280 * A pipe can have multiple modules, each of them will be a DAPM widget as
281 * well. While managing a pipeline we need to get the list of all the
282 * widgets in a pipelines, so this helper - skl_tplg_get_pipe_widget() helps
283 * to get the SKL type widgets in that pipeline
284 */
285static int skl_tplg_alloc_pipe_widget(struct device *dev,
286 struct snd_soc_dapm_widget *w, struct skl_pipe *pipe)
287{
288 struct skl_module_cfg *src_module = NULL;
289 struct snd_soc_dapm_path *p = NULL;
290 struct skl_pipe_module *p_module = NULL;
291
292 p_module = devm_kzalloc(dev, sizeof(*p_module), GFP_KERNEL);
293 if (!p_module)
294 return -ENOMEM;
295
296 p_module->w = w;
297 list_add_tail(&p_module->node, &pipe->w_list);
298
299 snd_soc_dapm_widget_for_each_sink_path(w, p) {
300 if ((p->sink->priv == NULL)
301 && (!is_skl_dsp_widget_type(w)))
302 continue;
303
304 if ((p->sink->priv != NULL) && p->connect
305 && is_skl_dsp_widget_type(p->sink)) {
306
307 src_module = p->sink->priv;
308 if (pipe->ppl_id == src_module->pipe->ppl_id)
309 skl_tplg_alloc_pipe_widget(dev,
310 p->sink, pipe);
311 }
312 }
313 return 0;
314}
315
316/*
Jeeja KPabb74002015-11-28 15:01:49 +0530317 * some modules can have multiple params set from user control and
318 * need to be set after module is initialized. If set_param flag is
319 * set module params will be done after module is initialised.
320 */
321static int skl_tplg_set_module_params(struct snd_soc_dapm_widget *w,
322 struct skl_sst *ctx)
323{
324 int i, ret;
325 struct skl_module_cfg *mconfig = w->priv;
326 const struct snd_kcontrol_new *k;
327 struct soc_bytes_ext *sb;
328 struct skl_algo_data *bc;
329 struct skl_specific_cfg *sp_cfg;
330
331 if (mconfig->formats_config.caps_size > 0 &&
332 mconfig->formats_config.set_params) {
333 sp_cfg = &mconfig->formats_config;
334 ret = skl_set_module_params(ctx, sp_cfg->caps,
335 sp_cfg->caps_size,
336 sp_cfg->param_id, mconfig);
337 if (ret < 0)
338 return ret;
339 }
340
341 for (i = 0; i < w->num_kcontrols; i++) {
342 k = &w->kcontrol_news[i];
343 if (k->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
344 sb = (void *) k->private_value;
345 bc = (struct skl_algo_data *)sb->dobj.private;
346
347 if (bc->set_params) {
348 ret = skl_set_module_params(ctx,
349 (u32 *)bc->params, bc->max,
350 bc->param_id, mconfig);
351 if (ret < 0)
352 return ret;
353 }
354 }
355 }
356
357 return 0;
358}
359
360/*
361 * some module param can set from user control and this is required as
362 * when module is initailzed. if module param is required in init it is
363 * identifed by set_param flag. if set_param flag is not set, then this
364 * parameter needs to set as part of module init.
365 */
366static int skl_tplg_set_module_init_data(struct snd_soc_dapm_widget *w)
367{
368 const struct snd_kcontrol_new *k;
369 struct soc_bytes_ext *sb;
370 struct skl_algo_data *bc;
371 struct skl_module_cfg *mconfig = w->priv;
372 int i;
373
374 for (i = 0; i < w->num_kcontrols; i++) {
375 k = &w->kcontrol_news[i];
376 if (k->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
377 sb = (struct soc_bytes_ext *)k->private_value;
378 bc = (struct skl_algo_data *)sb->dobj.private;
379
380 if (bc->set_params)
381 continue;
382
383 mconfig->formats_config.caps = (u32 *)&bc->params;
384 mconfig->formats_config.caps_size = bc->max;
385
386 break;
387 }
388 }
389
390 return 0;
391}
392
393/*
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100394 * Inside a pipe instance, we can have various modules. These modules need
395 * to instantiated in DSP by invoking INIT_MODULE IPC, which is achieved by
396 * skl_init_module() routine, so invoke that for all modules in a pipeline
397 */
398static int
399skl_tplg_init_pipe_modules(struct skl *skl, struct skl_pipe *pipe)
400{
401 struct skl_pipe_module *w_module;
402 struct snd_soc_dapm_widget *w;
403 struct skl_module_cfg *mconfig;
404 struct skl_sst *ctx = skl->skl_sst;
405 int ret = 0;
406
407 list_for_each_entry(w_module, &pipe->w_list, node) {
408 w = w_module->w;
409 mconfig = w->priv;
410
411 /* check resource available */
412 if (!skl_tplg_alloc_pipe_mcps(skl, mconfig))
413 return -ENOMEM;
414
Jeeja KPf7590d42015-10-07 11:31:53 +0100415 /*
416 * apply fix/conversion to module params based on
417 * FE/BE params
418 */
419 skl_tplg_update_module_params(w, ctx);
Jeeja KPabb74002015-11-28 15:01:49 +0530420
421 skl_tplg_set_module_init_data(w);
Jeeja KP9939a9c2015-11-28 15:01:47 +0530422 ret = skl_init_module(ctx, mconfig);
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100423 if (ret < 0)
424 return ret;
Jeeja KPabb74002015-11-28 15:01:49 +0530425
426 ret = skl_tplg_set_module_params(w, ctx);
427 if (ret < 0)
428 return ret;
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100429 }
430
431 return 0;
432}
Vinod Kould93f8e52015-10-07 11:31:54 +0100433
434/*
435 * Mixer module represents a pipeline. So in the Pre-PMU event of mixer we
436 * need create the pipeline. So we do following:
437 * - check the resources
438 * - Create the pipeline
439 * - Initialize the modules in pipeline
440 * - finally bind all modules together
441 */
442static int skl_tplg_mixer_dapm_pre_pmu_event(struct snd_soc_dapm_widget *w,
443 struct skl *skl)
444{
445 int ret;
446 struct skl_module_cfg *mconfig = w->priv;
447 struct skl_pipe_module *w_module;
448 struct skl_pipe *s_pipe = mconfig->pipe;
449 struct skl_module_cfg *src_module = NULL, *dst_module;
450 struct skl_sst *ctx = skl->skl_sst;
451
452 /* check resource available */
453 if (!skl_tplg_alloc_pipe_mcps(skl, mconfig))
454 return -EBUSY;
455
456 if (!skl_tplg_alloc_pipe_mem(skl, mconfig))
457 return -ENOMEM;
458
459 /*
460 * Create a list of modules for pipe.
461 * This list contains modules from source to sink
462 */
463 ret = skl_create_pipeline(ctx, mconfig->pipe);
464 if (ret < 0)
465 return ret;
466
467 /*
468 * we create a w_list of all widgets in that pipe. This list is not
469 * freed on PMD event as widgets within a pipe are static. This
470 * saves us cycles to get widgets in pipe every time.
471 *
472 * So if we have already initialized all the widgets of a pipeline
473 * we skip, so check for list_empty and create the list if empty
474 */
475 if (list_empty(&s_pipe->w_list)) {
476 ret = skl_tplg_alloc_pipe_widget(ctx->dev, w, s_pipe);
477 if (ret < 0)
478 return ret;
479 }
480
481 /* Init all pipe modules from source to sink */
482 ret = skl_tplg_init_pipe_modules(skl, s_pipe);
483 if (ret < 0)
484 return ret;
485
486 /* Bind modules from source to sink */
487 list_for_each_entry(w_module, &s_pipe->w_list, node) {
488 dst_module = w_module->w->priv;
489
490 if (src_module == NULL) {
491 src_module = dst_module;
492 continue;
493 }
494
495 ret = skl_bind_modules(ctx, src_module, dst_module);
496 if (ret < 0)
497 return ret;
498
499 src_module = dst_module;
500 }
501
502 return 0;
503}
504
Jeeja KP8724ff12015-10-27 09:22:52 +0900505static int skl_tplg_bind_sinks(struct snd_soc_dapm_widget *w,
506 struct skl *skl,
507 struct skl_module_cfg *src_mconfig)
Vinod Kould93f8e52015-10-07 11:31:54 +0100508{
509 struct snd_soc_dapm_path *p;
Jeeja KP0ed95d72015-11-13 19:22:11 +0530510 struct snd_soc_dapm_widget *sink = NULL, *next_sink = NULL;
Jeeja KP8724ff12015-10-27 09:22:52 +0900511 struct skl_module_cfg *sink_mconfig;
Vinod Kould93f8e52015-10-07 11:31:54 +0100512 struct skl_sst *ctx = skl->skl_sst;
Jeeja KP8724ff12015-10-27 09:22:52 +0900513 int ret;
Vinod Kould93f8e52015-10-07 11:31:54 +0100514
Jeeja KP8724ff12015-10-27 09:22:52 +0900515 snd_soc_dapm_widget_for_each_sink_path(w, p) {
Vinod Kould93f8e52015-10-07 11:31:54 +0100516 if (!p->connect)
517 continue;
518
519 dev_dbg(ctx->dev, "%s: src widget=%s\n", __func__, w->name);
520 dev_dbg(ctx->dev, "%s: sink widget=%s\n", __func__, p->sink->name);
521
Jeeja KP0ed95d72015-11-13 19:22:11 +0530522 next_sink = p->sink;
Vinod Kould93f8e52015-10-07 11:31:54 +0100523 /*
524 * here we will check widgets in sink pipelines, so that
525 * can be any widgets type and we are only interested if
526 * they are ones used for SKL so check that first
527 */
528 if ((p->sink->priv != NULL) &&
529 is_skl_dsp_widget_type(p->sink)) {
530
531 sink = p->sink;
Vinod Kould93f8e52015-10-07 11:31:54 +0100532 sink_mconfig = sink->priv;
533
534 /* Bind source to sink, mixin is always source */
535 ret = skl_bind_modules(ctx, src_mconfig, sink_mconfig);
536 if (ret)
537 return ret;
538
539 /* Start sinks pipe first */
540 if (sink_mconfig->pipe->state != SKL_PIPE_STARTED) {
Jeeja KPd1730c32015-10-27 09:22:53 +0900541 if (sink_mconfig->pipe->conn_type !=
542 SKL_PIPE_CONN_TYPE_FE)
543 ret = skl_run_pipe(ctx,
544 sink_mconfig->pipe);
Vinod Kould93f8e52015-10-07 11:31:54 +0100545 if (ret)
546 return ret;
547 }
Vinod Kould93f8e52015-10-07 11:31:54 +0100548 }
549 }
550
Jeeja KP8724ff12015-10-27 09:22:52 +0900551 if (!sink)
Jeeja KP0ed95d72015-11-13 19:22:11 +0530552 return skl_tplg_bind_sinks(next_sink, skl, src_mconfig);
Jeeja KP8724ff12015-10-27 09:22:52 +0900553
554 return 0;
555}
556
557/*
558 * A PGA represents a module in a pipeline. So in the Pre-PMU event of PGA
559 * we need to do following:
560 * - Bind to sink pipeline
561 * Since the sink pipes can be running and we don't get mixer event on
562 * connect for already running mixer, we need to find the sink pipes
563 * here and bind to them. This way dynamic connect works.
564 * - Start sink pipeline, if not running
565 * - Then run current pipe
566 */
567static int skl_tplg_pga_dapm_pre_pmu_event(struct snd_soc_dapm_widget *w,
568 struct skl *skl)
569{
570 struct skl_module_cfg *src_mconfig;
571 struct skl_sst *ctx = skl->skl_sst;
572 int ret = 0;
573
574 src_mconfig = w->priv;
575
576 /*
577 * find which sink it is connected to, bind with the sink,
578 * if sink is not started, start sink pipe first, then start
579 * this pipe
580 */
581 ret = skl_tplg_bind_sinks(w, skl, src_mconfig);
582 if (ret)
583 return ret;
584
Vinod Kould93f8e52015-10-07 11:31:54 +0100585 /* Start source pipe last after starting all sinks */
Jeeja KPd1730c32015-10-27 09:22:53 +0900586 if (src_mconfig->pipe->conn_type != SKL_PIPE_CONN_TYPE_FE)
587 return skl_run_pipe(ctx, src_mconfig->pipe);
Vinod Kould93f8e52015-10-07 11:31:54 +0100588
589 return 0;
590}
591
Jeeja KP8724ff12015-10-27 09:22:52 +0900592static struct snd_soc_dapm_widget *skl_get_src_dsp_widget(
593 struct snd_soc_dapm_widget *w, struct skl *skl)
594{
595 struct snd_soc_dapm_path *p;
596 struct snd_soc_dapm_widget *src_w = NULL;
597 struct skl_sst *ctx = skl->skl_sst;
598
599 snd_soc_dapm_widget_for_each_source_path(w, p) {
600 src_w = p->source;
601 if (!p->connect)
602 continue;
603
604 dev_dbg(ctx->dev, "sink widget=%s\n", w->name);
605 dev_dbg(ctx->dev, "src widget=%s\n", p->source->name);
606
607 /*
608 * here we will check widgets in sink pipelines, so that can
609 * be any widgets type and we are only interested if they are
610 * ones used for SKL so check that first
611 */
612 if ((p->source->priv != NULL) &&
613 is_skl_dsp_widget_type(p->source)) {
614 return p->source;
615 }
616 }
617
618 if (src_w != NULL)
619 return skl_get_src_dsp_widget(src_w, skl);
620
621 return NULL;
622}
623
Vinod Kould93f8e52015-10-07 11:31:54 +0100624/*
625 * in the Post-PMU event of mixer we need to do following:
626 * - Check if this pipe is running
627 * - if not, then
628 * - bind this pipeline to its source pipeline
629 * if source pipe is already running, this means it is a dynamic
630 * connection and we need to bind only to that pipe
631 * - start this pipeline
632 */
633static int skl_tplg_mixer_dapm_post_pmu_event(struct snd_soc_dapm_widget *w,
634 struct skl *skl)
635{
636 int ret = 0;
Vinod Kould93f8e52015-10-07 11:31:54 +0100637 struct snd_soc_dapm_widget *source, *sink;
638 struct skl_module_cfg *src_mconfig, *sink_mconfig;
639 struct skl_sst *ctx = skl->skl_sst;
640 int src_pipe_started = 0;
641
642 sink = w;
643 sink_mconfig = sink->priv;
644
645 /*
646 * If source pipe is already started, that means source is driving
647 * one more sink before this sink got connected, Since source is
648 * started, bind this sink to source and start this pipe.
649 */
Jeeja KP8724ff12015-10-27 09:22:52 +0900650 source = skl_get_src_dsp_widget(w, skl);
651 if (source != NULL) {
652 src_mconfig = source->priv;
653 sink_mconfig = sink->priv;
654 src_pipe_started = 1;
Vinod Kould93f8e52015-10-07 11:31:54 +0100655
656 /*
Jeeja KP8724ff12015-10-27 09:22:52 +0900657 * check pipe state, then no need to bind or start the
658 * pipe
Vinod Kould93f8e52015-10-07 11:31:54 +0100659 */
Jeeja KP8724ff12015-10-27 09:22:52 +0900660 if (src_mconfig->pipe->state != SKL_PIPE_STARTED)
661 src_pipe_started = 0;
Vinod Kould93f8e52015-10-07 11:31:54 +0100662 }
663
664 if (src_pipe_started) {
665 ret = skl_bind_modules(ctx, src_mconfig, sink_mconfig);
666 if (ret)
667 return ret;
668
Jeeja KPd1730c32015-10-27 09:22:53 +0900669 if (sink_mconfig->pipe->conn_type != SKL_PIPE_CONN_TYPE_FE)
670 ret = skl_run_pipe(ctx, sink_mconfig->pipe);
Vinod Kould93f8e52015-10-07 11:31:54 +0100671 }
672
673 return ret;
674}
675
676/*
677 * in the Pre-PMD event of mixer we need to do following:
678 * - Stop the pipe
679 * - find the source connections and remove that from dapm_path_list
680 * - unbind with source pipelines if still connected
681 */
682static int skl_tplg_mixer_dapm_pre_pmd_event(struct snd_soc_dapm_widget *w,
683 struct skl *skl)
684{
Vinod Kould93f8e52015-10-07 11:31:54 +0100685 struct skl_module_cfg *src_mconfig, *sink_mconfig;
Jeeja KPce1b5552015-10-27 09:22:51 +0900686 int ret = 0, i;
Vinod Kould93f8e52015-10-07 11:31:54 +0100687 struct skl_sst *ctx = skl->skl_sst;
688
Jeeja KPce1b5552015-10-27 09:22:51 +0900689 sink_mconfig = w->priv;
Vinod Kould93f8e52015-10-07 11:31:54 +0100690
691 /* Stop the pipe */
692 ret = skl_stop_pipe(ctx, sink_mconfig->pipe);
693 if (ret)
694 return ret;
695
Jeeja KPce1b5552015-10-27 09:22:51 +0900696 for (i = 0; i < sink_mconfig->max_in_queue; i++) {
697 if (sink_mconfig->m_in_pin[i].pin_state == SKL_PIN_BIND_DONE) {
698 src_mconfig = sink_mconfig->m_in_pin[i].tgt_mcfg;
699 if (!src_mconfig)
700 continue;
701 /*
702 * If path_found == 1, that means pmd for source
703 * pipe has not occurred, source is connected to
704 * some other sink. so its responsibility of sink
705 * to unbind itself from source.
706 */
707 ret = skl_stop_pipe(ctx, src_mconfig->pipe);
708 if (ret < 0)
709 return ret;
Vinod Kould93f8e52015-10-07 11:31:54 +0100710
Jeeja KPce1b5552015-10-27 09:22:51 +0900711 ret = skl_unbind_modules(ctx,
712 src_mconfig, sink_mconfig);
Vinod Kould93f8e52015-10-07 11:31:54 +0100713 }
714 }
715
Vinod Kould93f8e52015-10-07 11:31:54 +0100716 return ret;
717}
718
719/*
720 * in the Post-PMD event of mixer we need to do following:
721 * - Free the mcps used
722 * - Free the mem used
723 * - Unbind the modules within the pipeline
724 * - Delete the pipeline (modules are not required to be explicitly
725 * deleted, pipeline delete is enough here
726 */
727static int skl_tplg_mixer_dapm_post_pmd_event(struct snd_soc_dapm_widget *w,
728 struct skl *skl)
729{
730 struct skl_module_cfg *mconfig = w->priv;
731 struct skl_pipe_module *w_module;
732 struct skl_module_cfg *src_module = NULL, *dst_module;
733 struct skl_sst *ctx = skl->skl_sst;
734 struct skl_pipe *s_pipe = mconfig->pipe;
735 int ret = 0;
736
737 skl_tplg_free_pipe_mcps(skl, mconfig);
Vinod Koul65976872015-11-23 22:26:29 +0530738 skl_tplg_free_pipe_mem(skl, mconfig);
Vinod Kould93f8e52015-10-07 11:31:54 +0100739
740 list_for_each_entry(w_module, &s_pipe->w_list, node) {
741 dst_module = w_module->w->priv;
742
Vinod Koul7ae3cb12015-11-05 21:34:10 +0530743 skl_tplg_free_pipe_mcps(skl, dst_module);
Vinod Kould93f8e52015-10-07 11:31:54 +0100744 if (src_module == NULL) {
745 src_module = dst_module;
746 continue;
747 }
748
749 ret = skl_unbind_modules(ctx, src_module, dst_module);
750 if (ret < 0)
751 return ret;
752
753 src_module = dst_module;
754 }
755
756 ret = skl_delete_pipe(ctx, mconfig->pipe);
Vinod Kould93f8e52015-10-07 11:31:54 +0100757
758 return ret;
759}
760
761/*
762 * in the Post-PMD event of PGA we need to do following:
763 * - Free the mcps used
764 * - Stop the pipeline
765 * - In source pipe is connected, unbind with source pipelines
766 */
767static int skl_tplg_pga_dapm_post_pmd_event(struct snd_soc_dapm_widget *w,
768 struct skl *skl)
769{
Vinod Kould93f8e52015-10-07 11:31:54 +0100770 struct skl_module_cfg *src_mconfig, *sink_mconfig;
Jeeja KPce1b5552015-10-27 09:22:51 +0900771 int ret = 0, i;
Vinod Kould93f8e52015-10-07 11:31:54 +0100772 struct skl_sst *ctx = skl->skl_sst;
773
Jeeja KPce1b5552015-10-27 09:22:51 +0900774 src_mconfig = w->priv;
Vinod Kould93f8e52015-10-07 11:31:54 +0100775
Vinod Kould93f8e52015-10-07 11:31:54 +0100776 /* Stop the pipe since this is a mixin module */
777 ret = skl_stop_pipe(ctx, src_mconfig->pipe);
778 if (ret)
779 return ret;
780
Jeeja KPce1b5552015-10-27 09:22:51 +0900781 for (i = 0; i < src_mconfig->max_out_queue; i++) {
782 if (src_mconfig->m_out_pin[i].pin_state == SKL_PIN_BIND_DONE) {
783 sink_mconfig = src_mconfig->m_out_pin[i].tgt_mcfg;
784 if (!sink_mconfig)
785 continue;
786 /*
787 * This is a connecter and if path is found that means
788 * unbind between source and sink has not happened yet
789 */
790 ret = skl_stop_pipe(ctx, sink_mconfig->pipe);
791 if (ret < 0)
792 return ret;
793 ret = skl_unbind_modules(ctx, src_mconfig,
794 sink_mconfig);
Vinod Kould93f8e52015-10-07 11:31:54 +0100795 }
796 }
797
Vinod Kould93f8e52015-10-07 11:31:54 +0100798 return ret;
799}
800
801/*
802 * In modelling, we assume there will be ONLY one mixer in a pipeline. If
803 * mixer is not required then it is treated as static mixer aka vmixer with
804 * a hard path to source module
805 * So we don't need to check if source is started or not as hard path puts
806 * dependency on each other
807 */
808static int skl_tplg_vmixer_event(struct snd_soc_dapm_widget *w,
809 struct snd_kcontrol *k, int event)
810{
811 struct snd_soc_dapm_context *dapm = w->dapm;
812 struct skl *skl = get_skl_ctx(dapm->dev);
813
814 switch (event) {
815 case SND_SOC_DAPM_PRE_PMU:
816 return skl_tplg_mixer_dapm_pre_pmu_event(w, skl);
817
818 case SND_SOC_DAPM_POST_PMD:
819 return skl_tplg_mixer_dapm_post_pmd_event(w, skl);
820 }
821
822 return 0;
823}
824
825/*
826 * In modelling, we assume there will be ONLY one mixer in a pipeline. If a
827 * second one is required that is created as another pipe entity.
828 * The mixer is responsible for pipe management and represent a pipeline
829 * instance
830 */
831static int skl_tplg_mixer_event(struct snd_soc_dapm_widget *w,
832 struct snd_kcontrol *k, int event)
833{
834 struct snd_soc_dapm_context *dapm = w->dapm;
835 struct skl *skl = get_skl_ctx(dapm->dev);
836
837 switch (event) {
838 case SND_SOC_DAPM_PRE_PMU:
839 return skl_tplg_mixer_dapm_pre_pmu_event(w, skl);
840
841 case SND_SOC_DAPM_POST_PMU:
842 return skl_tplg_mixer_dapm_post_pmu_event(w, skl);
843
844 case SND_SOC_DAPM_PRE_PMD:
845 return skl_tplg_mixer_dapm_pre_pmd_event(w, skl);
846
847 case SND_SOC_DAPM_POST_PMD:
848 return skl_tplg_mixer_dapm_post_pmd_event(w, skl);
849 }
850
851 return 0;
852}
853
854/*
855 * In modelling, we assumed rest of the modules in pipeline are PGA. But we
856 * are interested in last PGA (leaf PGA) in a pipeline to disconnect with
857 * the sink when it is running (two FE to one BE or one FE to two BE)
858 * scenarios
859 */
860static int skl_tplg_pga_event(struct snd_soc_dapm_widget *w,
861 struct snd_kcontrol *k, int event)
862
863{
864 struct snd_soc_dapm_context *dapm = w->dapm;
865 struct skl *skl = get_skl_ctx(dapm->dev);
866
867 switch (event) {
868 case SND_SOC_DAPM_PRE_PMU:
869 return skl_tplg_pga_dapm_pre_pmu_event(w, skl);
870
871 case SND_SOC_DAPM_POST_PMD:
872 return skl_tplg_pga_dapm_post_pmd_event(w, skl);
873 }
874
875 return 0;
876}
Vinod Koulcfb0a872015-10-07 11:31:55 +0100877
Jeeja KP140adfb2015-11-28 15:01:50 +0530878static int skl_tplg_tlv_control_get(struct snd_kcontrol *kcontrol,
879 unsigned int __user *data, unsigned int size)
880{
881 struct soc_bytes_ext *sb =
882 (struct soc_bytes_ext *)kcontrol->private_value;
883 struct skl_algo_data *bc = (struct skl_algo_data *)sb->dobj.private;
884
885 if (bc->params) {
886 if (copy_to_user(data, &bc->param_id, sizeof(u32)))
887 return -EFAULT;
888 if (copy_to_user(data + sizeof(u32), &size, sizeof(u32)))
889 return -EFAULT;
890 if (copy_to_user(data + 2 * sizeof(u32), bc->params, size))
891 return -EFAULT;
892 }
893
894 return 0;
895}
896
897#define SKL_PARAM_VENDOR_ID 0xff
898
899static int skl_tplg_tlv_control_set(struct snd_kcontrol *kcontrol,
900 const unsigned int __user *data, unsigned int size)
901{
902 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kcontrol);
903 struct skl_module_cfg *mconfig = w->priv;
904 struct soc_bytes_ext *sb =
905 (struct soc_bytes_ext *)kcontrol->private_value;
906 struct skl_algo_data *ac = (struct skl_algo_data *)sb->dobj.private;
907 struct skl *skl = get_skl_ctx(w->dapm->dev);
908
909 if (ac->params) {
910 /*
911 * if the param_is is of type Vendor, firmware expects actual
912 * parameter id and size from the control.
913 */
914 if (ac->param_id == SKL_PARAM_VENDOR_ID) {
915 if (copy_from_user(ac->params, data, size))
916 return -EFAULT;
917 } else {
918 if (copy_from_user(ac->params,
919 data + 2 * sizeof(u32), size))
920 return -EFAULT;
921 }
922
923 if (w->power)
924 return skl_set_module_params(skl->skl_sst,
925 (u32 *)ac->params, ac->max,
926 ac->param_id, mconfig);
927 }
928
929 return 0;
930}
931
Vinod Koulcfb0a872015-10-07 11:31:55 +0100932/*
933 * The FE params are passed by hw_params of the DAI.
934 * On hw_params, the params are stored in Gateway module of the FE and we
935 * need to calculate the format in DSP module configuration, that
936 * conversion is done here
937 */
938int skl_tplg_update_pipe_params(struct device *dev,
939 struct skl_module_cfg *mconfig,
940 struct skl_pipe_params *params)
941{
942 struct skl_pipe *pipe = mconfig->pipe;
943 struct skl_module_fmt *format = NULL;
944
945 memcpy(pipe->p_params, params, sizeof(*params));
946
947 if (params->stream == SNDRV_PCM_STREAM_PLAYBACK)
Hardik T Shah4cd98992015-10-27 09:22:55 +0900948 format = &mconfig->in_fmt[0];
Vinod Koulcfb0a872015-10-07 11:31:55 +0100949 else
Hardik T Shah4cd98992015-10-27 09:22:55 +0900950 format = &mconfig->out_fmt[0];
Vinod Koulcfb0a872015-10-07 11:31:55 +0100951
952 /* set the hw_params */
953 format->s_freq = params->s_freq;
954 format->channels = params->ch;
955 format->valid_bit_depth = skl_get_bit_depth(params->s_fmt);
956
957 /*
958 * 16 bit is 16 bit container whereas 24 bit is in 32 bit
959 * container so update bit depth accordingly
960 */
961 switch (format->valid_bit_depth) {
962 case SKL_DEPTH_16BIT:
963 format->bit_depth = format->valid_bit_depth;
964 break;
965
966 case SKL_DEPTH_24BIT:
Jeeja KP6654f392015-10-27 09:22:46 +0900967 case SKL_DEPTH_32BIT:
Vinod Koulcfb0a872015-10-07 11:31:55 +0100968 format->bit_depth = SKL_DEPTH_32BIT;
969 break;
970
971 default:
972 dev_err(dev, "Invalid bit depth %x for pipe\n",
973 format->valid_bit_depth);
974 return -EINVAL;
975 }
976
977 if (params->stream == SNDRV_PCM_STREAM_PLAYBACK) {
978 mconfig->ibs = (format->s_freq / 1000) *
979 (format->channels) *
980 (format->bit_depth >> 3);
981 } else {
982 mconfig->obs = (format->s_freq / 1000) *
983 (format->channels) *
984 (format->bit_depth >> 3);
985 }
986
987 return 0;
988}
989
990/*
991 * Query the module config for the FE DAI
992 * This is used to find the hw_params set for that DAI and apply to FE
993 * pipeline
994 */
995struct skl_module_cfg *
996skl_tplg_fe_get_cpr_module(struct snd_soc_dai *dai, int stream)
997{
998 struct snd_soc_dapm_widget *w;
999 struct snd_soc_dapm_path *p = NULL;
1000
1001 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1002 w = dai->playback_widget;
Subhransu S. Prustyf0900eb2015-10-22 23:22:36 +05301003 snd_soc_dapm_widget_for_each_sink_path(w, p) {
Vinod Koulcfb0a872015-10-07 11:31:55 +01001004 if (p->connect && p->sink->power &&
Jeeja KPa28f51d2015-10-27 09:22:44 +09001005 !is_skl_dsp_widget_type(p->sink))
Vinod Koulcfb0a872015-10-07 11:31:55 +01001006 continue;
1007
1008 if (p->sink->priv) {
1009 dev_dbg(dai->dev, "set params for %s\n",
1010 p->sink->name);
1011 return p->sink->priv;
1012 }
1013 }
1014 } else {
1015 w = dai->capture_widget;
Subhransu S. Prustyf0900eb2015-10-22 23:22:36 +05301016 snd_soc_dapm_widget_for_each_source_path(w, p) {
Vinod Koulcfb0a872015-10-07 11:31:55 +01001017 if (p->connect && p->source->power &&
Jeeja KPa28f51d2015-10-27 09:22:44 +09001018 !is_skl_dsp_widget_type(p->source))
Vinod Koulcfb0a872015-10-07 11:31:55 +01001019 continue;
1020
1021 if (p->source->priv) {
1022 dev_dbg(dai->dev, "set params for %s\n",
1023 p->source->name);
1024 return p->source->priv;
1025 }
1026 }
1027 }
1028
1029 return NULL;
1030}
1031
1032static u8 skl_tplg_be_link_type(int dev_type)
1033{
1034 int ret;
1035
1036 switch (dev_type) {
1037 case SKL_DEVICE_BT:
1038 ret = NHLT_LINK_SSP;
1039 break;
1040
1041 case SKL_DEVICE_DMIC:
1042 ret = NHLT_LINK_DMIC;
1043 break;
1044
1045 case SKL_DEVICE_I2S:
1046 ret = NHLT_LINK_SSP;
1047 break;
1048
1049 case SKL_DEVICE_HDALINK:
1050 ret = NHLT_LINK_HDA;
1051 break;
1052
1053 default:
1054 ret = NHLT_LINK_INVALID;
1055 break;
1056 }
1057
1058 return ret;
1059}
1060
1061/*
1062 * Fill the BE gateway parameters
1063 * The BE gateway expects a blob of parameters which are kept in the ACPI
1064 * NHLT blob, so query the blob for interface type (i2s/pdm) and instance.
1065 * The port can have multiple settings so pick based on the PCM
1066 * parameters
1067 */
1068static int skl_tplg_be_fill_pipe_params(struct snd_soc_dai *dai,
1069 struct skl_module_cfg *mconfig,
1070 struct skl_pipe_params *params)
1071{
1072 struct skl_pipe *pipe = mconfig->pipe;
1073 struct nhlt_specific_cfg *cfg;
1074 struct skl *skl = get_skl_ctx(dai->dev);
1075 int link_type = skl_tplg_be_link_type(mconfig->dev_type);
1076
1077 memcpy(pipe->p_params, params, sizeof(*params));
1078
Jeeja KPb30c2752015-10-27 09:22:48 +09001079 if (link_type == NHLT_LINK_HDA)
1080 return 0;
1081
Vinod Koulcfb0a872015-10-07 11:31:55 +01001082 /* update the blob based on virtual bus_id*/
1083 cfg = skl_get_ep_blob(skl, mconfig->vbus_id, link_type,
1084 params->s_fmt, params->ch,
1085 params->s_freq, params->stream);
1086 if (cfg) {
1087 mconfig->formats_config.caps_size = cfg->size;
Jeeja KPbc032812015-10-22 23:22:35 +05301088 mconfig->formats_config.caps = (u32 *) &cfg->caps;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001089 } else {
1090 dev_err(dai->dev, "Blob NULL for id %x type %d dirn %d\n",
1091 mconfig->vbus_id, link_type,
1092 params->stream);
1093 dev_err(dai->dev, "PCM: ch %d, freq %d, fmt %d\n",
1094 params->ch, params->s_freq, params->s_fmt);
1095 return -EINVAL;
1096 }
1097
1098 return 0;
1099}
1100
1101static int skl_tplg_be_set_src_pipe_params(struct snd_soc_dai *dai,
1102 struct snd_soc_dapm_widget *w,
1103 struct skl_pipe_params *params)
1104{
1105 struct snd_soc_dapm_path *p;
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301106 int ret = -EIO;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001107
Subhransu S. Prustyf0900eb2015-10-22 23:22:36 +05301108 snd_soc_dapm_widget_for_each_source_path(w, p) {
Vinod Koulcfb0a872015-10-07 11:31:55 +01001109 if (p->connect && is_skl_dsp_widget_type(p->source) &&
1110 p->source->priv) {
1111
Jeeja KP9a03cb42015-10-27 09:22:54 +09001112 ret = skl_tplg_be_fill_pipe_params(dai,
1113 p->source->priv, params);
1114 if (ret < 0)
1115 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001116 } else {
Jeeja KP9a03cb42015-10-27 09:22:54 +09001117 ret = skl_tplg_be_set_src_pipe_params(dai,
1118 p->source, params);
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301119 if (ret < 0)
1120 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001121 }
1122 }
1123
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301124 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001125}
1126
1127static int skl_tplg_be_set_sink_pipe_params(struct snd_soc_dai *dai,
1128 struct snd_soc_dapm_widget *w, struct skl_pipe_params *params)
1129{
1130 struct snd_soc_dapm_path *p = NULL;
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301131 int ret = -EIO;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001132
Subhransu S. Prustyf0900eb2015-10-22 23:22:36 +05301133 snd_soc_dapm_widget_for_each_sink_path(w, p) {
Vinod Koulcfb0a872015-10-07 11:31:55 +01001134 if (p->connect && is_skl_dsp_widget_type(p->sink) &&
1135 p->sink->priv) {
1136
Jeeja KP9a03cb42015-10-27 09:22:54 +09001137 ret = skl_tplg_be_fill_pipe_params(dai,
1138 p->sink->priv, params);
1139 if (ret < 0)
1140 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001141 } else {
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301142 ret = skl_tplg_be_set_sink_pipe_params(
Vinod Koulcfb0a872015-10-07 11:31:55 +01001143 dai, p->sink, params);
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301144 if (ret < 0)
1145 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001146 }
1147 }
1148
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301149 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001150}
1151
1152/*
1153 * BE hw_params can be a source parameters (capture) or sink parameters
1154 * (playback). Based on sink and source we need to either find the source
1155 * list or the sink list and set the pipeline parameters
1156 */
1157int skl_tplg_be_update_params(struct snd_soc_dai *dai,
1158 struct skl_pipe_params *params)
1159{
1160 struct snd_soc_dapm_widget *w;
1161
1162 if (params->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1163 w = dai->playback_widget;
1164
1165 return skl_tplg_be_set_src_pipe_params(dai, w, params);
1166
1167 } else {
1168 w = dai->capture_widget;
1169
1170 return skl_tplg_be_set_sink_pipe_params(dai, w, params);
1171 }
1172
1173 return 0;
1174}
Vinod Koul3af36702015-10-07 11:31:56 +01001175
1176static const struct snd_soc_tplg_widget_events skl_tplg_widget_ops[] = {
1177 {SKL_MIXER_EVENT, skl_tplg_mixer_event},
1178 {SKL_VMIXER_EVENT, skl_tplg_vmixer_event},
1179 {SKL_PGA_EVENT, skl_tplg_pga_event},
1180};
1181
Jeeja KP140adfb2015-11-28 15:01:50 +05301182static const struct snd_soc_tplg_bytes_ext_ops skl_tlv_ops[] = {
1183 {SKL_CONTROL_TYPE_BYTE_TLV, skl_tplg_tlv_control_get,
1184 skl_tplg_tlv_control_set},
1185};
1186
Vinod Koul3af36702015-10-07 11:31:56 +01001187/*
1188 * The topology binary passes the pin info for a module so initialize the pin
1189 * info passed into module instance
1190 */
Jeeja KP6abca1d2015-10-22 23:22:42 +05301191static void skl_fill_module_pin_info(struct skl_dfw_module_pin *dfw_pin,
1192 struct skl_module_pin *m_pin,
1193 bool is_dynamic, int max_pin)
Vinod Koul3af36702015-10-07 11:31:56 +01001194{
1195 int i;
1196
1197 for (i = 0; i < max_pin; i++) {
Jeeja KP6abca1d2015-10-22 23:22:42 +05301198 m_pin[i].id.module_id = dfw_pin[i].module_id;
1199 m_pin[i].id.instance_id = dfw_pin[i].instance_id;
Vinod Koul3af36702015-10-07 11:31:56 +01001200 m_pin[i].in_use = false;
Jeeja KP6abca1d2015-10-22 23:22:42 +05301201 m_pin[i].is_dynamic = is_dynamic;
Jeeja KP4f745702015-10-27 09:22:49 +09001202 m_pin[i].pin_state = SKL_PIN_UNBIND;
Vinod Koul3af36702015-10-07 11:31:56 +01001203 }
1204}
1205
1206/*
1207 * Add pipeline from topology binary into driver pipeline list
1208 *
1209 * If already added we return that instance
1210 * Otherwise we create a new instance and add into driver list
1211 */
1212static struct skl_pipe *skl_tplg_add_pipe(struct device *dev,
1213 struct skl *skl, struct skl_dfw_pipe *dfw_pipe)
1214{
1215 struct skl_pipeline *ppl;
1216 struct skl_pipe *pipe;
1217 struct skl_pipe_params *params;
1218
1219 list_for_each_entry(ppl, &skl->ppl_list, node) {
1220 if (ppl->pipe->ppl_id == dfw_pipe->pipe_id)
1221 return ppl->pipe;
1222 }
1223
1224 ppl = devm_kzalloc(dev, sizeof(*ppl), GFP_KERNEL);
1225 if (!ppl)
1226 return NULL;
1227
1228 pipe = devm_kzalloc(dev, sizeof(*pipe), GFP_KERNEL);
1229 if (!pipe)
1230 return NULL;
1231
1232 params = devm_kzalloc(dev, sizeof(*params), GFP_KERNEL);
1233 if (!params)
1234 return NULL;
1235
1236 pipe->ppl_id = dfw_pipe->pipe_id;
1237 pipe->memory_pages = dfw_pipe->memory_pages;
1238 pipe->pipe_priority = dfw_pipe->pipe_priority;
1239 pipe->conn_type = dfw_pipe->conn_type;
1240 pipe->state = SKL_PIPE_INVALID;
1241 pipe->p_params = params;
1242 INIT_LIST_HEAD(&pipe->w_list);
1243
1244 ppl->pipe = pipe;
1245 list_add(&ppl->node, &skl->ppl_list);
1246
1247 return ppl->pipe;
1248}
1249
Hardik T Shah4cd98992015-10-27 09:22:55 +09001250static void skl_tplg_fill_fmt(struct skl_module_fmt *dst_fmt,
1251 struct skl_dfw_module_fmt *src_fmt,
1252 int pins)
1253{
1254 int i;
1255
1256 for (i = 0; i < pins; i++) {
1257 dst_fmt[i].channels = src_fmt[i].channels;
1258 dst_fmt[i].s_freq = src_fmt[i].freq;
1259 dst_fmt[i].bit_depth = src_fmt[i].bit_depth;
1260 dst_fmt[i].valid_bit_depth = src_fmt[i].valid_bit_depth;
1261 dst_fmt[i].ch_cfg = src_fmt[i].ch_cfg;
1262 dst_fmt[i].ch_map = src_fmt[i].ch_map;
1263 dst_fmt[i].interleaving_style = src_fmt[i].interleaving_style;
1264 dst_fmt[i].sample_type = src_fmt[i].sample_type;
1265 }
1266}
1267
Vinod Koul3af36702015-10-07 11:31:56 +01001268/*
1269 * Topology core widget load callback
1270 *
1271 * This is used to save the private data for each widget which gives
1272 * information to the driver about module and pipeline parameters which DSP
1273 * FW expects like ids, resource values, formats etc
1274 */
1275static int skl_tplg_widget_load(struct snd_soc_component *cmpnt,
Jeeja KPb663a8c2015-10-07 11:31:57 +01001276 struct snd_soc_dapm_widget *w,
1277 struct snd_soc_tplg_dapm_widget *tplg_w)
Vinod Koul3af36702015-10-07 11:31:56 +01001278{
1279 int ret;
1280 struct hdac_ext_bus *ebus = snd_soc_component_get_drvdata(cmpnt);
1281 struct skl *skl = ebus_to_skl(ebus);
1282 struct hdac_bus *bus = ebus_to_hbus(ebus);
1283 struct skl_module_cfg *mconfig;
1284 struct skl_pipe *pipe;
Jeeja KPb663a8c2015-10-07 11:31:57 +01001285 struct skl_dfw_module *dfw_config =
1286 (struct skl_dfw_module *)tplg_w->priv.data;
Vinod Koul3af36702015-10-07 11:31:56 +01001287
1288 if (!tplg_w->priv.size)
1289 goto bind_event;
1290
1291 mconfig = devm_kzalloc(bus->dev, sizeof(*mconfig), GFP_KERNEL);
1292
1293 if (!mconfig)
1294 return -ENOMEM;
1295
1296 w->priv = mconfig;
1297 mconfig->id.module_id = dfw_config->module_id;
1298 mconfig->id.instance_id = dfw_config->instance_id;
1299 mconfig->mcps = dfw_config->max_mcps;
1300 mconfig->ibs = dfw_config->ibs;
1301 mconfig->obs = dfw_config->obs;
1302 mconfig->core_id = dfw_config->core_id;
1303 mconfig->max_in_queue = dfw_config->max_in_queue;
1304 mconfig->max_out_queue = dfw_config->max_out_queue;
1305 mconfig->is_loadable = dfw_config->is_loadable;
Hardik T Shah4cd98992015-10-27 09:22:55 +09001306 skl_tplg_fill_fmt(mconfig->in_fmt, dfw_config->in_fmt,
1307 MODULE_MAX_IN_PINS);
1308 skl_tplg_fill_fmt(mconfig->out_fmt, dfw_config->out_fmt,
1309 MODULE_MAX_OUT_PINS);
1310
Vinod Koul3af36702015-10-07 11:31:56 +01001311 mconfig->params_fixup = dfw_config->params_fixup;
1312 mconfig->converter = dfw_config->converter;
1313 mconfig->m_type = dfw_config->module_type;
1314 mconfig->vbus_id = dfw_config->vbus_id;
1315
1316 pipe = skl_tplg_add_pipe(bus->dev, skl, &dfw_config->pipe);
1317 if (pipe)
1318 mconfig->pipe = pipe;
1319
1320 mconfig->dev_type = dfw_config->dev_type;
1321 mconfig->hw_conn_type = dfw_config->hw_conn_type;
1322 mconfig->time_slot = dfw_config->time_slot;
1323 mconfig->formats_config.caps_size = dfw_config->caps.caps_size;
1324
Hardik T Shah65aecfa2015-10-27 09:22:57 +09001325 if (dfw_config->is_loadable)
1326 memcpy(mconfig->guid, dfw_config->uuid,
1327 ARRAY_SIZE(dfw_config->uuid));
1328
Hardik T Shah4cd98992015-10-27 09:22:55 +09001329 mconfig->m_in_pin = devm_kzalloc(bus->dev, (mconfig->max_in_queue) *
1330 sizeof(*mconfig->m_in_pin),
1331 GFP_KERNEL);
Vinod Koul3af36702015-10-07 11:31:56 +01001332 if (!mconfig->m_in_pin)
1333 return -ENOMEM;
1334
Jeeja KP6abca1d2015-10-22 23:22:42 +05301335 mconfig->m_out_pin = devm_kzalloc(bus->dev, (mconfig->max_out_queue) *
1336 sizeof(*mconfig->m_out_pin),
1337 GFP_KERNEL);
Vinod Koul3af36702015-10-07 11:31:56 +01001338 if (!mconfig->m_out_pin)
1339 return -ENOMEM;
1340
Jeeja KP6abca1d2015-10-22 23:22:42 +05301341 skl_fill_module_pin_info(dfw_config->in_pin, mconfig->m_in_pin,
1342 dfw_config->is_dynamic_in_pin,
1343 mconfig->max_in_queue);
1344
1345 skl_fill_module_pin_info(dfw_config->out_pin, mconfig->m_out_pin,
1346 dfw_config->is_dynamic_out_pin,
1347 mconfig->max_out_queue);
1348
Vinod Koul3af36702015-10-07 11:31:56 +01001349
1350 if (mconfig->formats_config.caps_size == 0)
1351 goto bind_event;
1352
1353 mconfig->formats_config.caps = (u32 *)devm_kzalloc(bus->dev,
Jeeja KPb663a8c2015-10-07 11:31:57 +01001354 mconfig->formats_config.caps_size, GFP_KERNEL);
Vinod Koul3af36702015-10-07 11:31:56 +01001355
1356 if (mconfig->formats_config.caps == NULL)
1357 return -ENOMEM;
1358
1359 memcpy(mconfig->formats_config.caps, dfw_config->caps.caps,
Jeeja KPabb74002015-11-28 15:01:49 +05301360 dfw_config->caps.caps_size);
1361 mconfig->formats_config.param_id = dfw_config->caps.param_id;
1362 mconfig->formats_config.set_params = dfw_config->caps.set_params;
Vinod Koul3af36702015-10-07 11:31:56 +01001363
1364bind_event:
1365 if (tplg_w->event_type == 0) {
Vinod Koul3373f712015-10-07 16:39:38 +01001366 dev_dbg(bus->dev, "ASoC: No event handler required\n");
Vinod Koul3af36702015-10-07 11:31:56 +01001367 return 0;
1368 }
1369
1370 ret = snd_soc_tplg_widget_bind_event(w, skl_tplg_widget_ops,
Jeeja KPb663a8c2015-10-07 11:31:57 +01001371 ARRAY_SIZE(skl_tplg_widget_ops),
1372 tplg_w->event_type);
Vinod Koul3af36702015-10-07 11:31:56 +01001373
1374 if (ret) {
1375 dev_err(bus->dev, "%s: No matching event handlers found for %d\n",
1376 __func__, tplg_w->event_type);
1377 return -EINVAL;
1378 }
1379
1380 return 0;
1381}
1382
Jeeja KP140adfb2015-11-28 15:01:50 +05301383static int skl_init_algo_data(struct device *dev, struct soc_bytes_ext *be,
1384 struct snd_soc_tplg_bytes_control *bc)
1385{
1386 struct skl_algo_data *ac;
1387 struct skl_dfw_algo_data *dfw_ac =
1388 (struct skl_dfw_algo_data *)bc->priv.data;
1389
1390 ac = devm_kzalloc(dev, sizeof(*ac), GFP_KERNEL);
1391 if (!ac)
1392 return -ENOMEM;
1393
1394 /* Fill private data */
1395 ac->max = dfw_ac->max;
1396 ac->param_id = dfw_ac->param_id;
1397 ac->set_params = dfw_ac->set_params;
1398
1399 if (ac->max) {
1400 ac->params = (char *) devm_kzalloc(dev, ac->max, GFP_KERNEL);
1401 if (!ac->params)
1402 return -ENOMEM;
1403
1404 if (dfw_ac->params)
1405 memcpy(ac->params, dfw_ac->params, ac->max);
1406 }
1407
1408 be->dobj.private = ac;
1409 return 0;
1410}
1411
1412static int skl_tplg_control_load(struct snd_soc_component *cmpnt,
1413 struct snd_kcontrol_new *kctl,
1414 struct snd_soc_tplg_ctl_hdr *hdr)
1415{
1416 struct soc_bytes_ext *sb;
1417 struct snd_soc_tplg_bytes_control *tplg_bc;
1418 struct hdac_ext_bus *ebus = snd_soc_component_get_drvdata(cmpnt);
1419 struct hdac_bus *bus = ebus_to_hbus(ebus);
1420
1421 switch (hdr->ops.info) {
1422 case SND_SOC_TPLG_CTL_BYTES:
1423 tplg_bc = container_of(hdr,
1424 struct snd_soc_tplg_bytes_control, hdr);
1425 if (kctl->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
1426 sb = (struct soc_bytes_ext *)kctl->private_value;
1427 if (tplg_bc->priv.size)
1428 return skl_init_algo_data(
1429 bus->dev, sb, tplg_bc);
1430 }
1431 break;
1432
1433 default:
1434 dev_warn(bus->dev, "Control load not supported %d:%d:%d\n",
1435 hdr->ops.get, hdr->ops.put, hdr->ops.info);
1436 break;
1437 }
1438
1439 return 0;
1440}
1441
Vinod Koul3af36702015-10-07 11:31:56 +01001442static struct snd_soc_tplg_ops skl_tplg_ops = {
1443 .widget_load = skl_tplg_widget_load,
Jeeja KP140adfb2015-11-28 15:01:50 +05301444 .control_load = skl_tplg_control_load,
1445 .bytes_ext_ops = skl_tlv_ops,
1446 .bytes_ext_ops_count = ARRAY_SIZE(skl_tlv_ops),
Vinod Koul3af36702015-10-07 11:31:56 +01001447};
1448
1449/* This will be read from topology manifest, currently defined here */
1450#define SKL_MAX_MCPS 30000000
1451#define SKL_FW_MAX_MEM 1000000
1452
1453/*
1454 * SKL topology init routine
1455 */
1456int skl_tplg_init(struct snd_soc_platform *platform, struct hdac_ext_bus *ebus)
1457{
1458 int ret;
1459 const struct firmware *fw;
1460 struct hdac_bus *bus = ebus_to_hbus(ebus);
1461 struct skl *skl = ebus_to_skl(ebus);
1462
1463 ret = request_firmware(&fw, "dfw_sst.bin", bus->dev);
1464 if (ret < 0) {
Jeeja KPb663a8c2015-10-07 11:31:57 +01001465 dev_err(bus->dev, "tplg fw %s load failed with %d\n",
Vinod Koul3af36702015-10-07 11:31:56 +01001466 "dfw_sst.bin", ret);
1467 return ret;
1468 }
1469
1470 /*
1471 * The complete tplg for SKL is loaded as index 0, we don't use
1472 * any other index
1473 */
Jeeja KPb663a8c2015-10-07 11:31:57 +01001474 ret = snd_soc_tplg_component_load(&platform->component,
1475 &skl_tplg_ops, fw, 0);
Vinod Koul3af36702015-10-07 11:31:56 +01001476 if (ret < 0) {
1477 dev_err(bus->dev, "tplg component load failed%d\n", ret);
1478 return -EINVAL;
1479 }
1480
1481 skl->resource.max_mcps = SKL_MAX_MCPS;
1482 skl->resource.max_mem = SKL_FW_MAX_MEM;
1483
1484 return 0;
1485}