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gerrit-public.fairphone.software / kernel / msm-5.4 / 75f36d861957cb05b7889af24c8cd4a789398304 / . / drivers / gpu / drm / radeon / radeon_asic.h
blob: 953607d69eb1733ebd53892693ef87ded5926f12 [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_ASIC_H__
29#define __RADEON_ASIC_H__
30
31/*
32 * common functions
33 */
Rafał Miłecki74338742009-11-03 00:53:02 +0100[diff] [blame]34uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]35void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
Rafał Miłecki5ea597f2009-12-17 13:50:09 +0100[diff] [blame]36uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]37void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
38
Rafał Miłecki74338742009-11-03 00:53:02 +0100[diff] [blame]39uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]40void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
Rafał Miłecki74338742009-11-03 00:53:02 +0100[diff] [blame]41uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]42void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
43void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
44
Alex Deucher37e9b6a2012-08-03 11:39:43 -0400[diff] [blame]45void atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level);
Alex Deucher6d92f812012-09-14 09:59:26 -0400[diff] [blame]46u8 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder);
Alex Deucher37e9b6a2012-08-03 11:39:43 -0400[diff] [blame]47void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level);
Alex Deucher6d92f812012-09-14 09:59:26 -0400[diff] [blame]48u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder);
Alex Deucher37e9b6a2012-08-03 11:39:43 -0400[diff] [blame]49
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]50/*
Pauli Nieminen44ca7472010-02-11 17:25:47 +0000[diff] [blame]51 * r100,rv100,rs100,rv200,rs200
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]52 */
Daniel Vetter2b497502010-03-11 21:19:18 +0000[diff] [blame]53struct r100_mc_save {
54 u32 GENMO_WT;
55 u32 CRTC_EXT_CNTL;
56 u32 CRTC_GEN_CNTL;
57 u32 CRTC2_GEN_CNTL;
58 u32 CUR_OFFSET;
59 u32 CUR2_OFFSET;
60};
61int r100_init(struct radeon_device *rdev);
62void r100_fini(struct radeon_device *rdev);
63int r100_suspend(struct radeon_device *rdev);
64int r100_resume(struct radeon_device *rdev);
Dave Airlie28d52042009-09-21 14:33:58 +1000[diff] [blame]65void r100_vga_set_state(struct radeon_device *rdev, bool state);
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]66bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
Jerome Glissea2d07b72010-03-09 14:45:11 +0000[diff] [blame]67int r100_asic_reset(struct radeon_device *rdev);
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200[diff] [blame]68u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]69void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
70int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
Alex Deucherf7128122012-02-23 17:53:45 -0500[diff] [blame]71void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]72int r100_irq_set(struct radeon_device *rdev);
73int r100_irq_process(struct radeon_device *rdev);
74void r100_fence_ring_emit(struct radeon_device *rdev,
75 struct radeon_fence *fence);
Christian König1654b812013-11-12 12:58:05 +0100[diff] [blame]76bool r100_semaphore_ring_emit(struct radeon_device *rdev,
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]77 struct radeon_ring *cp,
Christian König15d33322011-09-15 19:02:22 +0200[diff] [blame]78 struct radeon_semaphore *semaphore,
Christian König7b1f2482011-09-23 15:11:23 +0200[diff] [blame]79 bool emit_wait);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]80int r100_cs_parse(struct radeon_cs_parser *p);
81void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
82uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
83int r100_copy_blit(struct radeon_device *rdev,
84 uint64_t src_offset,
85 uint64_t dst_offset,
Alex Deucher003cefe2011-09-16 12:04:08 -0400[diff] [blame]86 unsigned num_gpu_pages,
Christian König876dc9f2012-05-08 14:24:01 +0200[diff] [blame]87 struct radeon_fence **fence);
Dave Airliee024e112009-06-24 09:48:08 +1000[diff] [blame]88int r100_set_surface_reg(struct radeon_device *rdev, int reg,
89 uint32_t tiling_flags, uint32_t pitch,
90 uint32_t offset, uint32_t obj_size);
Daniel Vetter9479c542010-03-11 21:19:16 +0000[diff] [blame]91void r100_clear_surface_reg(struct radeon_device *rdev, int reg);
Jerome Glissec93bb852009-07-13 21:04:08 +0200[diff] [blame]92void r100_bandwidth_update(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]93void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]94int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
Alex Deucher429770b2009-12-04 15:26:55 -0500[diff] [blame]95void r100_hpd_init(struct radeon_device *rdev);
96void r100_hpd_fini(struct radeon_device *rdev);
97bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
98void r100_hpd_set_polarity(struct radeon_device *rdev,
99 enum radeon_hpd_id hpd);
Daniel Vetter2b497502010-03-11 21:19:18 +0000[diff] [blame]100int r100_debugfs_rbbm_init(struct radeon_device *rdev);
101int r100_debugfs_cp_init(struct radeon_device *rdev);
102void r100_cp_disable(struct radeon_device *rdev);
103int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
104void r100_cp_fini(struct radeon_device *rdev);
105int r100_pci_gart_init(struct radeon_device *rdev);
106void r100_pci_gart_fini(struct radeon_device *rdev);
107int r100_pci_gart_enable(struct radeon_device *rdev);
108void r100_pci_gart_disable(struct radeon_device *rdev);
109int r100_debugfs_mc_info_init(struct radeon_device *rdev);
110int r100_gui_wait_for_idle(struct radeon_device *rdev);
Alex Deucherf7128122012-02-23 17:53:45 -0500[diff] [blame]111int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
Daniel Vetter2b497502010-03-11 21:19:18 +0000[diff] [blame]112void r100_irq_disable(struct radeon_device *rdev);
113void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
114void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
115void r100_vram_init_sizes(struct radeon_device *rdev);
Daniel Vetter2b497502010-03-11 21:19:18 +0000[diff] [blame]116int r100_cp_reset(struct radeon_device *rdev);
117void r100_vga_render_disable(struct radeon_device *rdev);
Dave Airlie4c712e62010-07-15 12:13:50 +1000[diff] [blame]118void r100_restore_sanity(struct radeon_device *rdev);
Daniel Vetter2b497502010-03-11 21:19:18 +0000[diff] [blame]119int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
120 struct radeon_cs_packet *pkt,
121 struct radeon_bo *robj);
122int r100_cs_parse_packet0(struct radeon_cs_parser *p,
123 struct radeon_cs_packet *pkt,
124 const unsigned *auth, unsigned n,
125 radeon_packet0_check_t check);
126int r100_cs_packet_parse(struct radeon_cs_parser *p,
127 struct radeon_cs_packet *pkt,
128 unsigned idx);
129void r100_enable_bm(struct radeon_device *rdev);
130void r100_set_common_regs(struct radeon_device *rdev);
Jerome Glisse90aca4d2010-03-09 14:45:12 +0000[diff] [blame]131void r100_bm_disable(struct radeon_device *rdev);
Alex Deucherdef9ba92010-04-22 12:39:58 -0400[diff] [blame]132extern bool r100_gui_idle(struct radeon_device *rdev);
Alex Deucher49e02b72010-04-23 17:57:27 -0400[diff] [blame]133extern void r100_pm_misc(struct radeon_device *rdev);
134extern void r100_pm_prepare(struct radeon_device *rdev);
135extern void r100_pm_finish(struct radeon_device *rdev);
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]136extern void r100_pm_init_profile(struct radeon_device *rdev);
137extern void r100_pm_get_dynpm_state(struct radeon_device *rdev);
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]138extern u32 r100_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
Alex Deucher3ae19b72012-02-23 17:53:37 -0500[diff] [blame]139extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]140extern int r100_mc_wait_for_idle(struct radeon_device *rdev);
Alex Deucherbae6b5622010-04-22 13:38:05 -0400[diff] [blame]141
Alex Deucherea31bf62013-12-09 19:44:30 -0500[diff] [blame]142u32 r100_gfx_get_rptr(struct radeon_device *rdev,
143 struct radeon_ring *ring);
144u32 r100_gfx_get_wptr(struct radeon_device *rdev,
145 struct radeon_ring *ring);
146void r100_gfx_set_wptr(struct radeon_device *rdev,
147 struct radeon_ring *ring);
148
Pauli Nieminen44ca7472010-02-11 17:25:47 +0000[diff] [blame]149/*
150 * r200,rv250,rs300,rv280
151 */
152extern int r200_copy_dma(struct radeon_device *rdev,
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]153 uint64_t src_offset,
154 uint64_t dst_offset,
Alex Deucher003cefe2011-09-16 12:04:08 -0400[diff] [blame]155 unsigned num_gpu_pages,
Christian König876dc9f2012-05-08 14:24:01 +0200[diff] [blame]156 struct radeon_fence **fence);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]157void r200_set_safe_registers(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]158
159/*
160 * r300,r350,rv350,rv380
161 */
Jerome Glisse207bf9e2009-09-30 15:35:32 +0200[diff] [blame]162extern int r300_init(struct radeon_device *rdev);
163extern void r300_fini(struct radeon_device *rdev);
164extern int r300_suspend(struct radeon_device *rdev);
165extern int r300_resume(struct radeon_device *rdev);
Jerome Glissea2d07b72010-03-09 14:45:11 +0000[diff] [blame]166extern int r300_asic_reset(struct radeon_device *rdev);
Alex Deucherf7128122012-02-23 17:53:45 -0500[diff] [blame]167extern void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
Jerome Glisse207bf9e2009-09-30 15:35:32 +0200[diff] [blame]168extern void r300_fence_ring_emit(struct radeon_device *rdev,
169 struct radeon_fence *fence);
170extern int r300_cs_parse(struct radeon_cs_parser *p);
171extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
172extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
Jerome Glisse207bf9e2009-09-30 15:35:32 +0200[diff] [blame]173extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
Alex Deucherc836a412009-12-23 10:07:50 -0500[diff] [blame]174extern int rv370_get_pcie_lanes(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]175extern void r300_set_reg_safe(struct radeon_device *rdev);
176extern void r300_mc_program(struct radeon_device *rdev);
177extern void r300_mc_init(struct radeon_device *rdev);
178extern void r300_clock_startup(struct radeon_device *rdev);
179extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
180extern int rv370_pcie_gart_init(struct radeon_device *rdev);
181extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
182extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
183extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]184extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
Pauli Nieminen44ca7472010-02-11 17:25:47 +0000[diff] [blame]185
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]186/*
187 * r420,r423,rv410
188 */
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200[diff] [blame]189extern int r420_init(struct radeon_device *rdev);
190extern void r420_fini(struct radeon_device *rdev);
191extern int r420_suspend(struct radeon_device *rdev);
192extern int r420_resume(struct radeon_device *rdev);
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]193extern void r420_pm_init_profile(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]194extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
195extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
196extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
197extern void r420_pipes_init(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]198
199/*
200 * rs400,rs480
201 */
Jerome Glisseca6ffc62009-10-01 10:20:52 +0200[diff] [blame]202extern int rs400_init(struct radeon_device *rdev);
203extern void rs400_fini(struct radeon_device *rdev);
204extern int rs400_suspend(struct radeon_device *rdev);
205extern int rs400_resume(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]206void rs400_gart_tlb_flush(struct radeon_device *rdev);
207int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
208uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
209void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]210int rs400_gart_init(struct radeon_device *rdev);
211int rs400_gart_enable(struct radeon_device *rdev);
212void rs400_gart_adjust_size(struct radeon_device *rdev);
213void rs400_gart_disable(struct radeon_device *rdev);
214void rs400_gart_fini(struct radeon_device *rdev);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]215extern int rs400_mc_wait_for_idle(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]216
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]217/*
218 * rs600.
219 */
Jerome Glisse90aca4d2010-03-09 14:45:12 +0000[diff] [blame]220extern int rs600_asic_reset(struct radeon_device *rdev);
Jerome Glissec010f802009-09-30 22:09:06 +0200[diff] [blame]221extern int rs600_init(struct radeon_device *rdev);
222extern void rs600_fini(struct radeon_device *rdev);
223extern int rs600_suspend(struct radeon_device *rdev);
224extern int rs600_resume(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]225int rs600_irq_set(struct radeon_device *rdev);
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200[diff] [blame]226int rs600_irq_process(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]227void rs600_irq_disable(struct radeon_device *rdev);
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200[diff] [blame]228u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]229void rs600_gart_tlb_flush(struct radeon_device *rdev);
230int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
231uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
232void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Jerome Glissec93bb852009-07-13 21:04:08 +0200[diff] [blame]233void rs600_bandwidth_update(struct radeon_device *rdev);
Alex Deucher429770b2009-12-04 15:26:55 -0500[diff] [blame]234void rs600_hpd_init(struct radeon_device *rdev);
235void rs600_hpd_fini(struct radeon_device *rdev);
236bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
237void rs600_hpd_set_polarity(struct radeon_device *rdev,
238 enum radeon_hpd_id hpd);
Alex Deucher49e02b72010-04-23 17:57:27 -0400[diff] [blame]239extern void rs600_pm_misc(struct radeon_device *rdev);
240extern void rs600_pm_prepare(struct radeon_device *rdev);
241extern void rs600_pm_finish(struct radeon_device *rdev);
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]242extern u32 rs600_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]243void rs600_set_safe_registers(struct radeon_device *rdev);
Alex Deucher3ae19b72012-02-23 17:53:37 -0500[diff] [blame]244extern void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]245extern int rs600_mc_wait_for_idle(struct radeon_device *rdev);
Alex Deucher429770b2009-12-04 15:26:55 -0500[diff] [blame]246
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]247/*
248 * rs690,rs740
249 */
Jerome Glisse3bc68532009-10-01 09:39:24 +0200[diff] [blame]250int rs690_init(struct radeon_device *rdev);
251void rs690_fini(struct radeon_device *rdev);
252int rs690_resume(struct radeon_device *rdev);
253int rs690_suspend(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]254uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
255void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Jerome Glissec93bb852009-07-13 21:04:08 +0200[diff] [blame]256void rs690_bandwidth_update(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]257void rs690_line_buffer_adjust(struct radeon_device *rdev,
258 struct drm_display_mode *mode1,
259 struct drm_display_mode *mode2);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]260extern int rs690_mc_wait_for_idle(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]261
262/*
263 * rv515
264 */
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]265struct rv515_mc_save {
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]266 u32 vga_render_control;
267 u32 vga_hdp_control;
Alex Deucher6253e4c2012-12-12 14:30:32 -0500[diff] [blame]268 bool crtc_enabled[2];
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]269};
Jerome Glisse81ee8fb2012-07-27 16:32:24 -0400[diff] [blame]270
Jerome Glisse068a1172009-06-17 13:28:30 +0200[diff] [blame]271int rv515_init(struct radeon_device *rdev);
Jerome Glissed39c3b82009-09-28 18:34:43 +0200[diff] [blame]272void rv515_fini(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]273uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
274void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Alex Deucherf7128122012-02-23 17:53:45 -0500[diff] [blame]275void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
Jerome Glissec93bb852009-07-13 21:04:08 +0200[diff] [blame]276void rv515_bandwidth_update(struct radeon_device *rdev);
Jerome Glissed39c3b82009-09-28 18:34:43 +0200[diff] [blame]277int rv515_resume(struct radeon_device *rdev);
278int rv515_suspend(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]279void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
280void rv515_vga_render_disable(struct radeon_device *rdev);
281void rv515_set_safe_registers(struct radeon_device *rdev);
282void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
283void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
284void rv515_clock_startup(struct radeon_device *rdev);
285void rv515_debugfs(struct radeon_device *rdev);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]286int rv515_mc_wait_for_idle(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]287
288/*
289 * r520,rv530,rv560,rv570,r580
290 */
Jerome Glissed39c3b82009-09-28 18:34:43 +0200[diff] [blame]291int r520_init(struct radeon_device *rdev);
Jerome Glissef0ed1f62009-09-28 20:39:19 +0200[diff] [blame]292int r520_resume(struct radeon_device *rdev);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]293int r520_mc_wait_for_idle(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]294
295/*
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]296 * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]297 */
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]298int r600_init(struct radeon_device *rdev);
299void r600_fini(struct radeon_device *rdev);
300int r600_suspend(struct radeon_device *rdev);
301int r600_resume(struct radeon_device *rdev);
Dave Airlie28d52042009-09-21 14:33:58 +1000[diff] [blame]302void r600_vga_set_state(struct radeon_device *rdev, bool state);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]303int r600_wb_init(struct radeon_device *rdev);
304void r600_wb_fini(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]305void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]306uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
307void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]308int r600_cs_parse(struct radeon_cs_parser *p);
Alex Deuchercf4ccd02011-11-18 10:19:47 -0500[diff] [blame]309int r600_dma_cs_parse(struct radeon_cs_parser *p);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]310void r600_fence_ring_emit(struct radeon_device *rdev,
311 struct radeon_fence *fence);
Christian König1654b812013-11-12 12:58:05 +0100[diff] [blame]312bool r600_semaphore_ring_emit(struct radeon_device *rdev,
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]313 struct radeon_ring *cp,
Christian König15d33322011-09-15 19:02:22 +0200[diff] [blame]314 struct radeon_semaphore *semaphore,
Christian König7b1f2482011-09-23 15:11:23 +0200[diff] [blame]315 bool emit_wait);
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]316void r600_dma_fence_ring_emit(struct radeon_device *rdev,
317 struct radeon_fence *fence);
Christian König1654b812013-11-12 12:58:05 +0100[diff] [blame]318bool r600_dma_semaphore_ring_emit(struct radeon_device *rdev,
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]319 struct radeon_ring *ring,
320 struct radeon_semaphore *semaphore,
321 bool emit_wait);
322void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
323bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
Alex Deucher123bc182013-01-24 11:37:19 -0500[diff] [blame]324bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
Jerome Glissea2d07b72010-03-09 14:45:11 +0000[diff] [blame]325int r600_asic_reset(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]326int r600_set_surface_reg(struct radeon_device *rdev, int reg,
327 uint32_t tiling_flags, uint32_t pitch,
328 uint32_t offset, uint32_t obj_size);
Daniel Vetter9479c542010-03-11 21:19:16 +0000[diff] [blame]329void r600_clear_surface_reg(struct radeon_device *rdev, int reg);
Alex Deucherf7128122012-02-23 17:53:45 -0500[diff] [blame]330int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]331int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]332void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]333int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]334int r600_dma_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
Alex Deucher072b5ac2013-07-11 14:48:05 -0400[diff] [blame]335int r600_copy_cpdma(struct radeon_device *rdev,
336 uint64_t src_offset, uint64_t dst_offset,
337 unsigned num_gpu_pages, struct radeon_fence **fence);
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]338int r600_copy_dma(struct radeon_device *rdev,
339 uint64_t src_offset, uint64_t dst_offset,
340 unsigned num_gpu_pages, struct radeon_fence **fence);
Alex Deucher429770b2009-12-04 15:26:55 -0500[diff] [blame]341void r600_hpd_init(struct radeon_device *rdev);
342void r600_hpd_fini(struct radeon_device *rdev);
343bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
344void r600_hpd_set_polarity(struct radeon_device *rdev,
345 enum radeon_hpd_id hpd);
Jerome Glisse062b3892010-02-04 20:36:39 +0100[diff] [blame]346extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo);
Alex Deucherdef9ba92010-04-22 12:39:58 -0400[diff] [blame]347extern bool r600_gui_idle(struct radeon_device *rdev);
Alex Deucher49e02b72010-04-23 17:57:27 -0400[diff] [blame]348extern void r600_pm_misc(struct radeon_device *rdev);
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]349extern void r600_pm_init_profile(struct radeon_device *rdev);
350extern void rs780_pm_init_profile(struct radeon_device *rdev);
Samuel Li65337e62013-04-05 17:50:53 -0400[diff] [blame]351extern uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg);
352extern void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]353extern void r600_pm_get_dynpm_state(struct radeon_device *rdev);
Alex Deucher3313e3d2011-01-06 18:49:34 -0500[diff] [blame]354extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes);
355extern int r600_get_pcie_lanes(struct radeon_device *rdev);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]356bool r600_card_posted(struct radeon_device *rdev);
357void r600_cp_stop(struct radeon_device *rdev);
358int r600_cp_start(struct radeon_device *rdev);
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]359void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]360int r600_cp_resume(struct radeon_device *rdev);
361void r600_cp_fini(struct radeon_device *rdev);
362int r600_count_pipe_bits(uint32_t val);
363int r600_mc_wait_for_idle(struct radeon_device *rdev);
364int r600_pcie_gart_init(struct radeon_device *rdev);
365void r600_scratch_init(struct radeon_device *rdev);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]366int r600_init_microcode(struct radeon_device *rdev);
Alex Deucherea31bf62013-12-09 19:44:30 -0500[diff] [blame]367u32 r600_gfx_get_rptr(struct radeon_device *rdev,
368 struct radeon_ring *ring);
369u32 r600_gfx_get_wptr(struct radeon_device *rdev,
370 struct radeon_ring *ring);
371void r600_gfx_set_wptr(struct radeon_device *rdev,
372 struct radeon_ring *ring);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]373/* r600 irq */
374int r600_irq_process(struct radeon_device *rdev);
375int r600_irq_init(struct radeon_device *rdev);
376void r600_irq_fini(struct radeon_device *rdev);
377void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
378int r600_irq_set(struct radeon_device *rdev);
379void r600_irq_suspend(struct radeon_device *rdev);
380void r600_disable_interrupts(struct radeon_device *rdev);
381void r600_rlc_stop(struct radeon_device *rdev);
382/* r600 audio */
383int r600_audio_init(struct radeon_device *rdev);
Alex Deucherb5306022013-07-31 16:51:33 -0400[diff] [blame]384struct r600_audio_pin r600_audio_status(struct radeon_device *rdev);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]385void r600_audio_fini(struct radeon_device *rdev);
Rafał Miłecki8f33a152014-05-16 11:36:24 +0200[diff] [blame]386void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock);
387void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder, void *buffer,
388 size_t size);
389void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock);
390void r600_hdmi_audio_workaround(struct drm_encoder *encoder);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]391int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
392void r600_hdmi_update_audio_settings(struct drm_encoder *encoder);
Alex Deuchera973bea2013-04-18 11:32:16 -0400[diff] [blame]393void r600_hdmi_enable(struct drm_encoder *encoder, bool enable);
394void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]395int r600_mc_wait_for_idle(struct radeon_device *rdev);
Alex Deucher454d2e22013-02-14 10:04:02 -0500[diff] [blame]396u32 r600_get_xclk(struct radeon_device *rdev);
Alex Deucherd0418892013-01-24 10:35:23 -0500[diff] [blame]397uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev);
Alex Deucher6bd1c382013-06-21 14:38:03 -0400[diff] [blame]398int rv6xx_get_temp(struct radeon_device *rdev);
Alex Deucher1b9ba702013-09-05 09:52:37 -0400[diff] [blame]399int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
Alex Deucher98243912013-01-16 13:13:42 -0500[diff] [blame]400int r600_dpm_pre_set_power_state(struct radeon_device *rdev);
401void r600_dpm_post_set_power_state(struct radeon_device *rdev);
Alex Deuchera4643ba2013-12-19 12:18:13 -0500[diff] [blame]402int r600_dpm_late_enable(struct radeon_device *rdev);
Christian König2e1e6da2013-08-13 11:56:52 +0200[diff] [blame]403/* r600 dma */
404uint32_t r600_dma_get_rptr(struct radeon_device *rdev,
405 struct radeon_ring *ring);
406uint32_t r600_dma_get_wptr(struct radeon_device *rdev,
407 struct radeon_ring *ring);
408void r600_dma_set_wptr(struct radeon_device *rdev,
409 struct radeon_ring *ring);
Alex Deucher4a6369e2013-04-12 14:04:10 -0400[diff] [blame]410/* rv6xx dpm */
411int rv6xx_dpm_init(struct radeon_device *rdev);
412int rv6xx_dpm_enable(struct radeon_device *rdev);
413void rv6xx_dpm_disable(struct radeon_device *rdev);
414int rv6xx_dpm_set_power_state(struct radeon_device *rdev);
415void rv6xx_setup_asic(struct radeon_device *rdev);
416void rv6xx_dpm_display_configuration_changed(struct radeon_device *rdev);
417void rv6xx_dpm_fini(struct radeon_device *rdev);
418u32 rv6xx_dpm_get_sclk(struct radeon_device *rdev, bool low);
419u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low);
420void rv6xx_dpm_print_power_state(struct radeon_device *rdev,
421 struct radeon_ps *ps);
Alex Deucher242916a2013-06-28 14:20:53 -0400[diff] [blame]422void rv6xx_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
423 struct seq_file *m);
Alex Deucherf4f85a82013-07-25 20:07:25 -0400[diff] [blame]424int rv6xx_dpm_force_performance_level(struct radeon_device *rdev,
425 enum radeon_dpm_forced_level level);
Alex Deucher9d670062013-04-12 13:59:22 -0400[diff] [blame]426/* rs780 dpm */
427int rs780_dpm_init(struct radeon_device *rdev);
428int rs780_dpm_enable(struct radeon_device *rdev);
429void rs780_dpm_disable(struct radeon_device *rdev);
430int rs780_dpm_set_power_state(struct radeon_device *rdev);
431void rs780_dpm_setup_asic(struct radeon_device *rdev);
432void rs780_dpm_display_configuration_changed(struct radeon_device *rdev);
433void rs780_dpm_fini(struct radeon_device *rdev);
434u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low);
435u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low);
436void rs780_dpm_print_power_state(struct radeon_device *rdev,
437 struct radeon_ps *ps);
Alex Deucher444bddc2013-07-02 13:05:23 -0400[diff] [blame]438void rs780_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
439 struct seq_file *m);
Anthoine Bourgeois63580c32013-09-03 13:52:19 -0400[diff] [blame]440int rs780_dpm_force_performance_level(struct radeon_device *rdev,
441 enum radeon_dpm_forced_level level);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]442
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]443/*
444 * rv770,rv730,rv710,rv740
445 */
446int rv770_init(struct radeon_device *rdev);
447void rv770_fini(struct radeon_device *rdev);
448int rv770_suspend(struct radeon_device *rdev);
449int rv770_resume(struct radeon_device *rdev);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]450void rv770_pm_misc(struct radeon_device *rdev);
451u32 rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
452void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
453void r700_cp_stop(struct radeon_device *rdev);
454void r700_cp_fini(struct radeon_device *rdev);
Alex Deucher43fb7782013-01-04 09:24:18 -0500[diff] [blame]455int rv770_copy_dma(struct radeon_device *rdev,
456 uint64_t src_offset, uint64_t dst_offset,
457 unsigned num_gpu_pages,
458 struct radeon_fence **fence);
Alex Deucher454d2e22013-02-14 10:04:02 -0500[diff] [blame]459u32 rv770_get_xclk(struct radeon_device *rdev);
Christian Königef0e6e62013-04-08 12:41:35 +0200[diff] [blame]460int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
Alex Deucher6bd1c382013-06-21 14:38:03 -0400[diff] [blame]461int rv770_get_temp(struct radeon_device *rdev);
Rafał Miłecki8f33a152014-05-16 11:36:24 +0200[diff] [blame]462/* hdmi */
463void dce3_1_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
Alex Deucher66229b22013-06-26 00:11:19 -0400[diff] [blame]464/* rv7xx pm */
465int rv770_dpm_init(struct radeon_device *rdev);
466int rv770_dpm_enable(struct radeon_device *rdev);
Alex Deuchera3f11242013-12-19 13:48:36 -0500[diff] [blame]467int rv770_dpm_late_enable(struct radeon_device *rdev);
Alex Deucher66229b22013-06-26 00:11:19 -0400[diff] [blame]468void rv770_dpm_disable(struct radeon_device *rdev);
469int rv770_dpm_set_power_state(struct radeon_device *rdev);
470void rv770_dpm_setup_asic(struct radeon_device *rdev);
471void rv770_dpm_display_configuration_changed(struct radeon_device *rdev);
472void rv770_dpm_fini(struct radeon_device *rdev);
473u32 rv770_dpm_get_sclk(struct radeon_device *rdev, bool low);
474u32 rv770_dpm_get_mclk(struct radeon_device *rdev, bool low);
475void rv770_dpm_print_power_state(struct radeon_device *rdev,
476 struct radeon_ps *ps);
Alex Deucherbd210d12013-06-28 10:06:26 -0400[diff] [blame]477void rv770_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
478 struct seq_file *m);
Alex Deucher8b5e6b72013-07-02 18:40:35 -0400[diff] [blame]479int rv770_dpm_force_performance_level(struct radeon_device *rdev,
480 enum radeon_dpm_forced_level level);
Alex Deucherb06195d2013-07-08 11:49:48 -0400[diff] [blame]481bool rv770_dpm_vblank_too_short(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]482
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500[diff] [blame]483/*
484 * evergreen
485 */
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]486struct evergreen_mc_save {
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]487 u32 vga_render_control;
488 u32 vga_hdp_control;
Alex Deucher62444b72012-08-15 17:18:42 -0400[diff] [blame]489 bool crtc_enabled[RADEON_MAX_CRTCS];
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]490};
Jerome Glisse81ee8fb2012-07-27 16:32:24 -0400[diff] [blame]491
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]492void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev);
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500[diff] [blame]493int evergreen_init(struct radeon_device *rdev);
494void evergreen_fini(struct radeon_device *rdev);
495int evergreen_suspend(struct radeon_device *rdev);
496int evergreen_resume(struct radeon_device *rdev);
Alex Deucher123bc182013-01-24 11:37:19 -0500[diff] [blame]497bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
498bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
Jerome Glissea2d07b72010-03-09 14:45:11 +0000[diff] [blame]499int evergreen_asic_reset(struct radeon_device *rdev);
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500[diff] [blame]500void evergreen_bandwidth_update(struct radeon_device *rdev);
Alex Deucher12920592011-02-02 12:37:40 -0500[diff] [blame]501void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500[diff] [blame]502void evergreen_hpd_init(struct radeon_device *rdev);
503void evergreen_hpd_fini(struct radeon_device *rdev);
504bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
505void evergreen_hpd_set_polarity(struct radeon_device *rdev,
506 enum radeon_hpd_id hpd);
Alex Deucher45f9a392010-03-24 13:55:51 -0400[diff] [blame]507u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc);
508int evergreen_irq_set(struct radeon_device *rdev);
509int evergreen_irq_process(struct radeon_device *rdev);
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]510extern int evergreen_cs_parse(struct radeon_cs_parser *p);
Alex Deucherd2ead3e2012-12-13 09:55:45 -0500[diff] [blame]511extern int evergreen_dma_cs_parse(struct radeon_cs_parser *p);
Alex Deucher49e02b72010-04-23 17:57:27 -0400[diff] [blame]512extern void evergreen_pm_misc(struct radeon_device *rdev);
513extern void evergreen_pm_prepare(struct radeon_device *rdev);
514extern void evergreen_pm_finish(struct radeon_device *rdev);
Alex Deuchera4c9e2e2011-11-04 10:09:41 -0400[diff] [blame]515extern void sumo_pm_init_profile(struct radeon_device *rdev);
Alex Deucher27810fb2012-10-01 19:25:11 -0400[diff] [blame]516extern void btc_pm_init_profile(struct radeon_device *rdev);
Alex Deucher23d33ba2013-04-08 12:41:32 +0200[diff] [blame]517int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
Alex Deuchera8b49252013-04-08 12:41:33 +0200[diff] [blame]518int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]519extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
Alex Deucher3ae19b72012-02-23 17:53:37 -0500[diff] [blame]520extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]521void evergreen_disable_interrupt_state(struct radeon_device *rdev);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]522int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
Alex Deucher233d1ad2012-12-04 15:25:59 -0500[diff] [blame]523void evergreen_dma_fence_ring_emit(struct radeon_device *rdev,
524 struct radeon_fence *fence);
525void evergreen_dma_ring_ib_execute(struct radeon_device *rdev,
526 struct radeon_ib *ib);
527int evergreen_copy_dma(struct radeon_device *rdev,
528 uint64_t src_offset, uint64_t dst_offset,
529 unsigned num_gpu_pages,
530 struct radeon_fence **fence);
Alex Deuchera973bea2013-04-18 11:32:16 -0400[diff] [blame]531void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable);
532void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
Alex Deucher6bd1c382013-06-21 14:38:03 -0400[diff] [blame]533int evergreen_get_temp(struct radeon_device *rdev);
534int sumo_get_temp(struct radeon_device *rdev);
Alex Deucher29a15222012-12-14 11:57:36 -0500[diff] [blame]535int tn_get_temp(struct radeon_device *rdev);
Alex Deucherdc50ba72013-06-26 00:33:35 -0400[diff] [blame]536int cypress_dpm_init(struct radeon_device *rdev);
537void cypress_dpm_setup_asic(struct radeon_device *rdev);
538int cypress_dpm_enable(struct radeon_device *rdev);
539void cypress_dpm_disable(struct radeon_device *rdev);
540int cypress_dpm_set_power_state(struct radeon_device *rdev);
541void cypress_dpm_display_configuration_changed(struct radeon_device *rdev);
542void cypress_dpm_fini(struct radeon_device *rdev);
Alex Deucherd0b54bd2013-07-08 11:56:09 -0400[diff] [blame]543bool cypress_dpm_vblank_too_short(struct radeon_device *rdev);
Alex Deucher6596afd2013-06-26 00:15:24 -0400[diff] [blame]544int btc_dpm_init(struct radeon_device *rdev);
545void btc_dpm_setup_asic(struct radeon_device *rdev);
546int btc_dpm_enable(struct radeon_device *rdev);
547void btc_dpm_disable(struct radeon_device *rdev);
Alex Deuchere8a95392013-01-16 14:17:23 -0500[diff] [blame]548int btc_dpm_pre_set_power_state(struct radeon_device *rdev);
Alex Deucher6596afd2013-06-26 00:15:24 -0400[diff] [blame]549int btc_dpm_set_power_state(struct radeon_device *rdev);
Alex Deuchere8a95392013-01-16 14:17:23 -0500[diff] [blame]550void btc_dpm_post_set_power_state(struct radeon_device *rdev);
Alex Deucher6596afd2013-06-26 00:15:24 -0400[diff] [blame]551void btc_dpm_fini(struct radeon_device *rdev);
Alex Deuchere8a95392013-01-16 14:17:23 -0500[diff] [blame]552u32 btc_dpm_get_sclk(struct radeon_device *rdev, bool low);
553u32 btc_dpm_get_mclk(struct radeon_device *rdev, bool low);
Alex Deuchera84301c2013-07-08 12:03:55 -0400[diff] [blame]554bool btc_dpm_vblank_too_short(struct radeon_device *rdev);
Alex Deucher9f3f63f2014-01-30 11:19:22 -0500[diff] [blame]555void btc_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
556 struct seq_file *m);
Alex Deucher80ea2c12013-04-12 14:56:21 -0400[diff] [blame]557int sumo_dpm_init(struct radeon_device *rdev);
558int sumo_dpm_enable(struct radeon_device *rdev);
Alex Deucher14ec9fa2013-12-19 11:56:52 -0500[diff] [blame]559int sumo_dpm_late_enable(struct radeon_device *rdev);
Alex Deucher80ea2c12013-04-12 14:56:21 -0400[diff] [blame]560void sumo_dpm_disable(struct radeon_device *rdev);
Alex Deucher422a56b2013-06-25 15:40:21 -0400[diff] [blame]561int sumo_dpm_pre_set_power_state(struct radeon_device *rdev);
Alex Deucher80ea2c12013-04-12 14:56:21 -0400[diff] [blame]562int sumo_dpm_set_power_state(struct radeon_device *rdev);
Alex Deucher422a56b2013-06-25 15:40:21 -0400[diff] [blame]563void sumo_dpm_post_set_power_state(struct radeon_device *rdev);
Alex Deucher80ea2c12013-04-12 14:56:21 -0400[diff] [blame]564void sumo_dpm_setup_asic(struct radeon_device *rdev);
565void sumo_dpm_display_configuration_changed(struct radeon_device *rdev);
566void sumo_dpm_fini(struct radeon_device *rdev);
567u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low);
568u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low);
569void sumo_dpm_print_power_state(struct radeon_device *rdev,
570 struct radeon_ps *ps);
Alex Deucherfb701602013-06-28 10:47:56 -0400[diff] [blame]571void sumo_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
572 struct seq_file *m);
Alex Deucher5d5e5592013-07-02 18:50:09 -0400[diff] [blame]573int sumo_dpm_force_performance_level(struct radeon_device *rdev,
574 enum radeon_dpm_forced_level level);
Daniel Vetter4546b2c2011-02-18 17:59:21 +0100[diff] [blame]575
Alex Deuchere3487622011-03-02 20:07:36 -0500[diff] [blame]576/*
577 * cayman
578 */
Alex Deucherb40e7e12011-11-17 14:57:50 -0500[diff] [blame]579void cayman_fence_ring_emit(struct radeon_device *rdev,
580 struct radeon_fence *fence);
Alex Deuchere3487622011-03-02 20:07:36 -0500[diff] [blame]581void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev);
582int cayman_init(struct radeon_device *rdev);
583void cayman_fini(struct radeon_device *rdev);
584int cayman_suspend(struct radeon_device *rdev);
585int cayman_resume(struct radeon_device *rdev);
Alex Deuchere3487622011-03-02 20:07:36 -0500[diff] [blame]586int cayman_asic_reset(struct radeon_device *rdev);
Jerome Glisse721604a2012-01-05 22:11:05 -0500[diff] [blame]587void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
588int cayman_vm_init(struct radeon_device *rdev);
589void cayman_vm_fini(struct radeon_device *rdev);
Alex Deucher498522b2012-10-02 14:43:38 -0400[diff] [blame]590void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
Christian König089a7862012-08-11 11:54:05 +0200[diff] [blame]591uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags);
Jerome Glisse721604a2012-01-05 22:11:05 -0500[diff] [blame]592int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
Alex Deuchercd459e52012-12-13 12:17:38 -0500[diff] [blame]593int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
Alex Deucherf60cbd12012-12-04 15:27:33 -0500[diff] [blame]594void cayman_dma_ring_ib_execute(struct radeon_device *rdev,
595 struct radeon_ib *ib);
Alex Deucher123bc182013-01-24 11:37:19 -0500[diff] [blame]596bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
Alex Deucherf60cbd12012-12-04 15:27:33 -0500[diff] [blame]597bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
Christian König24c16432013-10-30 11:51:09 -0400[diff] [blame]598void cayman_dma_vm_set_page(struct radeon_device *rdev,
599 struct radeon_ib *ib,
600 uint64_t pe,
601 uint64_t addr, unsigned count,
602 uint32_t incr, uint32_t flags);
603
Alex Deucherf60cbd12012-12-04 15:27:33 -0500[diff] [blame]604void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
Alex Deucher45f9a392010-03-24 13:55:51 -0400[diff] [blame]605
Alex Deucherea31bf62013-12-09 19:44:30 -0500[diff] [blame]606u32 cayman_gfx_get_rptr(struct radeon_device *rdev,
607 struct radeon_ring *ring);
608u32 cayman_gfx_get_wptr(struct radeon_device *rdev,
609 struct radeon_ring *ring);
610void cayman_gfx_set_wptr(struct radeon_device *rdev,
611 struct radeon_ring *ring);
612uint32_t cayman_dma_get_rptr(struct radeon_device *rdev,
613 struct radeon_ring *ring);
614uint32_t cayman_dma_get_wptr(struct radeon_device *rdev,
615 struct radeon_ring *ring);
616void cayman_dma_set_wptr(struct radeon_device *rdev,
617 struct radeon_ring *ring);
618
Alex Deucher69e0b572013-04-12 16:42:42 -0400[diff] [blame]619int ni_dpm_init(struct radeon_device *rdev);
620void ni_dpm_setup_asic(struct radeon_device *rdev);
621int ni_dpm_enable(struct radeon_device *rdev);
622void ni_dpm_disable(struct radeon_device *rdev);
Alex Deucherfee3d742013-01-16 14:35:39 -0500[diff] [blame]623int ni_dpm_pre_set_power_state(struct radeon_device *rdev);
Alex Deucher69e0b572013-04-12 16:42:42 -0400[diff] [blame]624int ni_dpm_set_power_state(struct radeon_device *rdev);
Alex Deucherfee3d742013-01-16 14:35:39 -0500[diff] [blame]625void ni_dpm_post_set_power_state(struct radeon_device *rdev);
Alex Deucher69e0b572013-04-12 16:42:42 -0400[diff] [blame]626void ni_dpm_fini(struct radeon_device *rdev);
627u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low);
628u32 ni_dpm_get_mclk(struct radeon_device *rdev, bool low);
629void ni_dpm_print_power_state(struct radeon_device *rdev,
630 struct radeon_ps *ps);
Alex Deucherbdf0c4f2013-06-28 17:49:02 -0400[diff] [blame]631void ni_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
632 struct seq_file *m);
Alex Deucher170a47f2013-07-02 18:43:53 -0400[diff] [blame]633int ni_dpm_force_performance_level(struct radeon_device *rdev,
634 enum radeon_dpm_forced_level level);
Alex Deucher76ad73e2013-07-08 12:09:41 -0400[diff] [blame]635bool ni_dpm_vblank_too_short(struct radeon_device *rdev);
Alex Deucherd70229f2013-04-12 16:40:41 -0400[diff] [blame]636int trinity_dpm_init(struct radeon_device *rdev);
637int trinity_dpm_enable(struct radeon_device *rdev);
Alex Deucherbda44c12013-12-19 12:03:35 -0500[diff] [blame]638int trinity_dpm_late_enable(struct radeon_device *rdev);
Alex Deucherd70229f2013-04-12 16:40:41 -0400[diff] [blame]639void trinity_dpm_disable(struct radeon_device *rdev);
Alex Deuchera284c482013-01-16 13:53:40 -0500[diff] [blame]640int trinity_dpm_pre_set_power_state(struct radeon_device *rdev);
Alex Deucherd70229f2013-04-12 16:40:41 -0400[diff] [blame]641int trinity_dpm_set_power_state(struct radeon_device *rdev);
Alex Deuchera284c482013-01-16 13:53:40 -0500[diff] [blame]642void trinity_dpm_post_set_power_state(struct radeon_device *rdev);
Alex Deucherd70229f2013-04-12 16:40:41 -0400[diff] [blame]643void trinity_dpm_setup_asic(struct radeon_device *rdev);
644void trinity_dpm_display_configuration_changed(struct radeon_device *rdev);
645void trinity_dpm_fini(struct radeon_device *rdev);
646u32 trinity_dpm_get_sclk(struct radeon_device *rdev, bool low);
647u32 trinity_dpm_get_mclk(struct radeon_device *rdev, bool low);
648void trinity_dpm_print_power_state(struct radeon_device *rdev,
649 struct radeon_ps *ps);
Alex Deucher490ab932013-06-28 12:01:38 -0400[diff] [blame]650void trinity_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
651 struct seq_file *m);
Alex Deucher9b5de592013-07-02 18:52:10 -0400[diff] [blame]652int trinity_dpm_force_performance_level(struct radeon_device *rdev,
653 enum radeon_dpm_forced_level level);
Alex Deucher11877062013-09-09 19:19:52 -0400[diff] [blame]654void trinity_dpm_enable_bapm(struct radeon_device *rdev, bool enable);
Alex Deucherd70229f2013-04-12 16:40:41 -0400[diff] [blame]655
Alex Deucher43b3cd92012-03-20 17:18:00 -0400[diff] [blame]656/* DCE6 - SI */
657void dce6_bandwidth_update(struct radeon_device *rdev);
Alex Deucherb5306022013-07-31 16:51:33 -0400[diff] [blame]658int dce6_audio_init(struct radeon_device *rdev);
659void dce6_audio_fini(struct radeon_device *rdev);
Alex Deucher43b3cd92012-03-20 17:18:00 -0400[diff] [blame]660
Alex Deucher02779c02012-03-20 17:18:25 -0400[diff] [blame]661/*
662 * si
663 */
664void si_fence_ring_emit(struct radeon_device *rdev,
665 struct radeon_fence *fence);
666void si_pcie_gart_tlb_flush(struct radeon_device *rdev);
667int si_init(struct radeon_device *rdev);
668void si_fini(struct radeon_device *rdev);
669int si_suspend(struct radeon_device *rdev);
670int si_resume(struct radeon_device *rdev);
Alex Deucher123bc182013-01-24 11:37:19 -0500[diff] [blame]671bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
672bool si_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
Alex Deucher02779c02012-03-20 17:18:25 -0400[diff] [blame]673int si_asic_reset(struct radeon_device *rdev);
674void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
675int si_irq_set(struct radeon_device *rdev);
676int si_irq_process(struct radeon_device *rdev);
677int si_vm_init(struct radeon_device *rdev);
678void si_vm_fini(struct radeon_device *rdev);
Alex Deucher498522b2012-10-02 14:43:38 -0400[diff] [blame]679void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
Alex Deucher02779c02012-03-20 17:18:25 -0400[diff] [blame]680int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
Alex Deucher8c5fd7e2012-12-04 15:28:18 -0500[diff] [blame]681int si_copy_dma(struct radeon_device *rdev,
682 uint64_t src_offset, uint64_t dst_offset,
683 unsigned num_gpu_pages,
684 struct radeon_fence **fence);
Christian König24c16432013-10-30 11:51:09 -0400[diff] [blame]685void si_dma_vm_set_page(struct radeon_device *rdev,
686 struct radeon_ib *ib,
687 uint64_t pe,
688 uint64_t addr, unsigned count,
689 uint32_t incr, uint32_t flags);
Alex Deucher8c5fd7e2012-12-04 15:28:18 -0500[diff] [blame]690void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
Alex Deucher454d2e22013-02-14 10:04:02 -0500[diff] [blame]691u32 si_get_xclk(struct radeon_device *rdev);
Alex Deucherd0418892013-01-24 10:35:23 -0500[diff] [blame]692uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev);
Christian König2539eb02013-04-08 12:41:34 +0200[diff] [blame]693int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
Alex Deucher6bd1c382013-06-21 14:38:03 -0400[diff] [blame]694int si_get_temp(struct radeon_device *rdev);
Alex Deuchera9e61412013-06-25 17:56:16 -0400[diff] [blame]695int si_dpm_init(struct radeon_device *rdev);
696void si_dpm_setup_asic(struct radeon_device *rdev);
697int si_dpm_enable(struct radeon_device *rdev);
Alex Deucher963c1152013-12-19 13:54:35 -0500[diff] [blame]698int si_dpm_late_enable(struct radeon_device *rdev);
Alex Deuchera9e61412013-06-25 17:56:16 -0400[diff] [blame]699void si_dpm_disable(struct radeon_device *rdev);
700int si_dpm_pre_set_power_state(struct radeon_device *rdev);
701int si_dpm_set_power_state(struct radeon_device *rdev);
702void si_dpm_post_set_power_state(struct radeon_device *rdev);
703void si_dpm_fini(struct radeon_device *rdev);
704void si_dpm_display_configuration_changed(struct radeon_device *rdev);
Alex Deucher79821282013-06-28 18:02:19 -0400[diff] [blame]705void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
706 struct seq_file *m);
Alex Deuchera160a6a2013-07-02 18:46:28 -0400[diff] [blame]707int si_dpm_force_performance_level(struct radeon_device *rdev,
708 enum radeon_dpm_forced_level level);
Alex Deucher02779c02012-03-20 17:18:25 -0400[diff] [blame]709
Alex Deucher0672e272013-04-09 16:22:31 -0400[diff] [blame]710/* DCE8 - CIK */
711void dce8_bandwidth_update(struct radeon_device *rdev);
712
Alex Deucher44fa3462012-12-18 22:17:00 -0500[diff] [blame]713/*
714 * cik
715 */
716uint64_t cik_get_gpu_clock_counter(struct radeon_device *rdev);
Alex Deucher2c679122013-04-09 13:32:18 -0400[diff] [blame]717u32 cik_get_xclk(struct radeon_device *rdev);
Alex Deucher6e2c3c02013-04-03 19:28:32 -0400[diff] [blame]718uint32_t cik_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
719void cik_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Christian König87167bb2013-04-09 13:39:21 -0400[diff] [blame]720int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
Alex Deucher5ad6bf92013-08-22 17:09:06 -0400[diff] [blame]721int cik_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk);
Alex Deucher0672e272013-04-09 16:22:31 -0400[diff] [blame]722void cik_sdma_fence_ring_emit(struct radeon_device *rdev,
723 struct radeon_fence *fence);
Christian König1654b812013-11-12 12:58:05 +0100[diff] [blame]724bool cik_sdma_semaphore_ring_emit(struct radeon_device *rdev,
Alex Deucher0672e272013-04-09 16:22:31 -0400[diff] [blame]725 struct radeon_ring *ring,
726 struct radeon_semaphore *semaphore,
727 bool emit_wait);
728void cik_sdma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
729int cik_copy_dma(struct radeon_device *rdev,
730 uint64_t src_offset, uint64_t dst_offset,
731 unsigned num_gpu_pages,
732 struct radeon_fence **fence);
Alex Deucherc9dbd702013-10-01 16:36:51 -0400[diff] [blame]733int cik_copy_cpdma(struct radeon_device *rdev,
734 uint64_t src_offset, uint64_t dst_offset,
735 unsigned num_gpu_pages,
736 struct radeon_fence **fence);
Alex Deucher0672e272013-04-09 16:22:31 -0400[diff] [blame]737int cik_sdma_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
738int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
739bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
740void cik_fence_gfx_ring_emit(struct radeon_device *rdev,
741 struct radeon_fence *fence);
742void cik_fence_compute_ring_emit(struct radeon_device *rdev,
743 struct radeon_fence *fence);
Christian König1654b812013-11-12 12:58:05 +0100[diff] [blame]744bool cik_semaphore_ring_emit(struct radeon_device *rdev,
Alex Deucher0672e272013-04-09 16:22:31 -0400[diff] [blame]745 struct radeon_ring *cp,
746 struct radeon_semaphore *semaphore,
747 bool emit_wait);
748void cik_pcie_gart_tlb_flush(struct radeon_device *rdev);
749int cik_init(struct radeon_device *rdev);
750void cik_fini(struct radeon_device *rdev);
751int cik_suspend(struct radeon_device *rdev);
752int cik_resume(struct radeon_device *rdev);
753bool cik_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
754int cik_asic_reset(struct radeon_device *rdev);
755void cik_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
756int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
757int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
758int cik_irq_set(struct radeon_device *rdev);
759int cik_irq_process(struct radeon_device *rdev);
760int cik_vm_init(struct radeon_device *rdev);
761void cik_vm_fini(struct radeon_device *rdev);
762void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
Christian König24c16432013-10-30 11:51:09 -0400[diff] [blame]763void cik_sdma_vm_set_page(struct radeon_device *rdev,
764 struct radeon_ib *ib,
765 uint64_t pe,
766 uint64_t addr, unsigned count,
767 uint32_t incr, uint32_t flags);
Alex Deucher0672e272013-04-09 16:22:31 -0400[diff] [blame]768void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
769int cik_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
Alex Deucherea31bf62013-12-09 19:44:30 -0500[diff] [blame]770u32 cik_gfx_get_rptr(struct radeon_device *rdev,
771 struct radeon_ring *ring);
772u32 cik_gfx_get_wptr(struct radeon_device *rdev,
773 struct radeon_ring *ring);
774void cik_gfx_set_wptr(struct radeon_device *rdev,
775 struct radeon_ring *ring);
776u32 cik_compute_get_rptr(struct radeon_device *rdev,
777 struct radeon_ring *ring);
778u32 cik_compute_get_wptr(struct radeon_device *rdev,
779 struct radeon_ring *ring);
780void cik_compute_set_wptr(struct radeon_device *rdev,
781 struct radeon_ring *ring);
782u32 cik_sdma_get_rptr(struct radeon_device *rdev,
783 struct radeon_ring *ring);
784u32 cik_sdma_get_wptr(struct radeon_device *rdev,
785 struct radeon_ring *ring);
786void cik_sdma_set_wptr(struct radeon_device *rdev,
787 struct radeon_ring *ring);
Alex Deucher286d9cc2013-06-21 15:50:47 -0400[diff] [blame]788int ci_get_temp(struct radeon_device *rdev);
789int kv_get_temp(struct radeon_device *rdev);
Alex Deucher44fa3462012-12-18 22:17:00 -0500[diff] [blame]790
Alex Deuchercc8dbbb2013-08-14 01:03:41 -0400[diff] [blame]791int ci_dpm_init(struct radeon_device *rdev);
792int ci_dpm_enable(struct radeon_device *rdev);
Alex Deucher90208422013-12-19 13:59:46 -0500[diff] [blame]793int ci_dpm_late_enable(struct radeon_device *rdev);
Alex Deuchercc8dbbb2013-08-14 01:03:41 -0400[diff] [blame]794void ci_dpm_disable(struct radeon_device *rdev);
795int ci_dpm_pre_set_power_state(struct radeon_device *rdev);
796int ci_dpm_set_power_state(struct radeon_device *rdev);
797void ci_dpm_post_set_power_state(struct radeon_device *rdev);
798void ci_dpm_setup_asic(struct radeon_device *rdev);
799void ci_dpm_display_configuration_changed(struct radeon_device *rdev);
800void ci_dpm_fini(struct radeon_device *rdev);
801u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low);
802u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low);
803void ci_dpm_print_power_state(struct radeon_device *rdev,
804 struct radeon_ps *ps);
Alex Deucher94b4adc2013-07-15 17:34:33 -0400[diff] [blame]805void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
806 struct seq_file *m);
Alex Deucher89536fd2013-07-15 18:14:24 -0400[diff] [blame]807int ci_dpm_force_performance_level(struct radeon_device *rdev,
808 enum radeon_dpm_forced_level level);
Alex Deucher54961312013-07-15 18:24:31 -0400[diff] [blame]809bool ci_dpm_vblank_too_short(struct radeon_device *rdev);
Alex Deucher942bdf72013-08-09 10:05:24 -0400[diff] [blame]810void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
Alex Deuchercc8dbbb2013-08-14 01:03:41 -0400[diff] [blame]811
Alex Deucher41a524a2013-08-14 01:01:40 -0400[diff] [blame]812int kv_dpm_init(struct radeon_device *rdev);
813int kv_dpm_enable(struct radeon_device *rdev);
Alex Deucherd8852c32013-12-19 14:03:36 -0500[diff] [blame]814int kv_dpm_late_enable(struct radeon_device *rdev);
Alex Deucher41a524a2013-08-14 01:01:40 -0400[diff] [blame]815void kv_dpm_disable(struct radeon_device *rdev);
816int kv_dpm_pre_set_power_state(struct radeon_device *rdev);
817int kv_dpm_set_power_state(struct radeon_device *rdev);
818void kv_dpm_post_set_power_state(struct radeon_device *rdev);
819void kv_dpm_setup_asic(struct radeon_device *rdev);
820void kv_dpm_display_configuration_changed(struct radeon_device *rdev);
821void kv_dpm_fini(struct radeon_device *rdev);
822u32 kv_dpm_get_sclk(struct radeon_device *rdev, bool low);
823u32 kv_dpm_get_mclk(struct radeon_device *rdev, bool low);
824void kv_dpm_print_power_state(struct radeon_device *rdev,
825 struct radeon_ps *ps);
Alex Deucherae3e40e2013-07-18 16:39:53 -0400[diff] [blame]826void kv_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
827 struct seq_file *m);
Alex Deucher2b4c8022013-07-18 16:48:46 -0400[diff] [blame]828int kv_dpm_force_performance_level(struct radeon_device *rdev,
829 enum radeon_dpm_forced_level level);
Alex Deucher77df5082013-08-09 10:02:40 -0400[diff] [blame]830void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
Alex Deucherb7a5ae92013-09-09 19:33:08 -0400[diff] [blame]831void kv_dpm_enable_bapm(struct radeon_device *rdev, bool enable);
Alex Deucher41a524a2013-08-14 01:01:40 -0400[diff] [blame]832
Christian Könige409b122013-08-13 11:56:53 +0200[diff] [blame]833/* uvd v1.0 */
834uint32_t uvd_v1_0_get_rptr(struct radeon_device *rdev,
835 struct radeon_ring *ring);
836uint32_t uvd_v1_0_get_wptr(struct radeon_device *rdev,
837 struct radeon_ring *ring);
838void uvd_v1_0_set_wptr(struct radeon_device *rdev,
839 struct radeon_ring *ring);
840
841int uvd_v1_0_init(struct radeon_device *rdev);
842void uvd_v1_0_fini(struct radeon_device *rdev);
843int uvd_v1_0_start(struct radeon_device *rdev);
844void uvd_v1_0_stop(struct radeon_device *rdev);
845
846int uvd_v1_0_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
847int uvd_v1_0_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
Christian König1654b812013-11-12 12:58:05 +0100[diff] [blame]848bool uvd_v1_0_semaphore_emit(struct radeon_device *rdev,
Christian Könige409b122013-08-13 11:56:53 +0200[diff] [blame]849 struct radeon_ring *ring,
850 struct radeon_semaphore *semaphore,
851 bool emit_wait);
852void uvd_v1_0_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
853
854/* uvd v2.2 */
855int uvd_v2_2_resume(struct radeon_device *rdev);
856void uvd_v2_2_fence_emit(struct radeon_device *rdev,
857 struct radeon_fence *fence);
858
859/* uvd v3.1 */
Christian König1654b812013-11-12 12:58:05 +0100[diff] [blame]860bool uvd_v3_1_semaphore_emit(struct radeon_device *rdev,
Christian Könige409b122013-08-13 11:56:53 +0200[diff] [blame]861 struct radeon_ring *ring,
862 struct radeon_semaphore *semaphore,
863 bool emit_wait);
864
865/* uvd v4.2 */
866int uvd_v4_2_resume(struct radeon_device *rdev);
867
Christian Königd93f7932013-05-23 12:10:04 +0200[diff] [blame]868/* vce v1.0 */
869uint32_t vce_v1_0_get_rptr(struct radeon_device *rdev,
870 struct radeon_ring *ring);
871uint32_t vce_v1_0_get_wptr(struct radeon_device *rdev,
872 struct radeon_ring *ring);
873void vce_v1_0_set_wptr(struct radeon_device *rdev,
874 struct radeon_ring *ring);
875int vce_v1_0_init(struct radeon_device *rdev);
876int vce_v1_0_start(struct radeon_device *rdev);
877
878/* vce v2.0 */
879int vce_v2_0_resume(struct radeon_device *rdev);
880
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]881#endif