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gerrit-public.fairphone.software / kernel / msm-5.4 / fb70160c5f2ae1b0648801f39138b25990f7ae18 / . / drivers / gpu / drm / radeon / radeon_asic.h
blob: 958d30f3306606e278e4b7097d1cb6384739898f [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_ASIC_H__
29#define __RADEON_ASIC_H__
30
31/*
32 * common functions
33 */
Rafał Miłecki74338742009-11-03 00:53:02 +0100[diff] [blame]34uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]35void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
Rafał Miłecki5ea597f2009-12-17 13:50:09 +0100[diff] [blame]36uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]37void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
38
Rafał Miłecki74338742009-11-03 00:53:02 +0100[diff] [blame]39uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]40void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
Rafał Miłecki74338742009-11-03 00:53:02 +0100[diff] [blame]41uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]42void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
43void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
44
Alex Deucher37e9b6a2012-08-03 11:39:43 -0400[diff] [blame]45void atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level);
Alex Deucher6d92f812012-09-14 09:59:26 -0400[diff] [blame]46u8 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder);
Alex Deucher37e9b6a2012-08-03 11:39:43 -0400[diff] [blame]47void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level);
Alex Deucher6d92f812012-09-14 09:59:26 -0400[diff] [blame]48u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder);
Alex Deucher37e9b6a2012-08-03 11:39:43 -0400[diff] [blame]49
Alex Deucherf93bdef2013-01-29 14:10:56 -0500[diff] [blame]50u32 radeon_ring_generic_get_rptr(struct radeon_device *rdev,
51 struct radeon_ring *ring);
52u32 radeon_ring_generic_get_wptr(struct radeon_device *rdev,
53 struct radeon_ring *ring);
54void radeon_ring_generic_set_wptr(struct radeon_device *rdev,
55 struct radeon_ring *ring);
Alex Deucher37e9b6a2012-08-03 11:39:43 -0400[diff] [blame]56
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]57/*
Pauli Nieminen44ca7472010-02-11 17:25:47 +0000[diff] [blame]58 * r100,rv100,rs100,rv200,rs200
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]59 */
Daniel Vetter2b497502010-03-11 21:19:18 +0000[diff] [blame]60struct r100_mc_save {
61 u32 GENMO_WT;
62 u32 CRTC_EXT_CNTL;
63 u32 CRTC_GEN_CNTL;
64 u32 CRTC2_GEN_CNTL;
65 u32 CUR_OFFSET;
66 u32 CUR2_OFFSET;
67};
68int r100_init(struct radeon_device *rdev);
69void r100_fini(struct radeon_device *rdev);
70int r100_suspend(struct radeon_device *rdev);
71int r100_resume(struct radeon_device *rdev);
Dave Airlie28d52042009-09-21 14:33:58 +1000[diff] [blame]72void r100_vga_set_state(struct radeon_device *rdev, bool state);
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]73bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
Jerome Glissea2d07b72010-03-09 14:45:11 +0000[diff] [blame]74int r100_asic_reset(struct radeon_device *rdev);
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200[diff] [blame]75u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]76void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
77int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
Alex Deucherf7128122012-02-23 17:53:45 -0500[diff] [blame]78void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]79int r100_irq_set(struct radeon_device *rdev);
80int r100_irq_process(struct radeon_device *rdev);
81void r100_fence_ring_emit(struct radeon_device *rdev,
82 struct radeon_fence *fence);
Christian König15d33322011-09-15 19:02:22 +0200[diff] [blame]83void r100_semaphore_ring_emit(struct radeon_device *rdev,
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]84 struct radeon_ring *cp,
Christian König15d33322011-09-15 19:02:22 +0200[diff] [blame]85 struct radeon_semaphore *semaphore,
Christian König7b1f2482011-09-23 15:11:23 +0200[diff] [blame]86 bool emit_wait);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]87int r100_cs_parse(struct radeon_cs_parser *p);
88void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
89uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
90int r100_copy_blit(struct radeon_device *rdev,
91 uint64_t src_offset,
92 uint64_t dst_offset,
Alex Deucher003cefe2011-09-16 12:04:08 -0400[diff] [blame]93 unsigned num_gpu_pages,
Christian König876dc9f2012-05-08 14:24:01 +0200[diff] [blame]94 struct radeon_fence **fence);
Dave Airliee024e112009-06-24 09:48:08 +1000[diff] [blame]95int r100_set_surface_reg(struct radeon_device *rdev, int reg,
96 uint32_t tiling_flags, uint32_t pitch,
97 uint32_t offset, uint32_t obj_size);
Daniel Vetter9479c542010-03-11 21:19:16 +0000[diff] [blame]98void r100_clear_surface_reg(struct radeon_device *rdev, int reg);
Jerome Glissec93bb852009-07-13 21:04:08 +0200[diff] [blame]99void r100_bandwidth_update(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]100void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]101int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
Alex Deucher429770b2009-12-04 15:26:55 -0500[diff] [blame]102void r100_hpd_init(struct radeon_device *rdev);
103void r100_hpd_fini(struct radeon_device *rdev);
104bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
105void r100_hpd_set_polarity(struct radeon_device *rdev,
106 enum radeon_hpd_id hpd);
Daniel Vetter2b497502010-03-11 21:19:18 +0000[diff] [blame]107int r100_debugfs_rbbm_init(struct radeon_device *rdev);
108int r100_debugfs_cp_init(struct radeon_device *rdev);
109void r100_cp_disable(struct radeon_device *rdev);
110int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
111void r100_cp_fini(struct radeon_device *rdev);
112int r100_pci_gart_init(struct radeon_device *rdev);
113void r100_pci_gart_fini(struct radeon_device *rdev);
114int r100_pci_gart_enable(struct radeon_device *rdev);
115void r100_pci_gart_disable(struct radeon_device *rdev);
116int r100_debugfs_mc_info_init(struct radeon_device *rdev);
117int r100_gui_wait_for_idle(struct radeon_device *rdev);
Alex Deucherf7128122012-02-23 17:53:45 -0500[diff] [blame]118int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
Daniel Vetter2b497502010-03-11 21:19:18 +0000[diff] [blame]119void r100_irq_disable(struct radeon_device *rdev);
120void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
121void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
122void r100_vram_init_sizes(struct radeon_device *rdev);
Daniel Vetter2b497502010-03-11 21:19:18 +0000[diff] [blame]123int r100_cp_reset(struct radeon_device *rdev);
124void r100_vga_render_disable(struct radeon_device *rdev);
Dave Airlie4c712e62010-07-15 12:13:50 +1000[diff] [blame]125void r100_restore_sanity(struct radeon_device *rdev);
Daniel Vetter2b497502010-03-11 21:19:18 +0000[diff] [blame]126int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
127 struct radeon_cs_packet *pkt,
128 struct radeon_bo *robj);
129int r100_cs_parse_packet0(struct radeon_cs_parser *p,
130 struct radeon_cs_packet *pkt,
131 const unsigned *auth, unsigned n,
132 radeon_packet0_check_t check);
133int r100_cs_packet_parse(struct radeon_cs_parser *p,
134 struct radeon_cs_packet *pkt,
135 unsigned idx);
136void r100_enable_bm(struct radeon_device *rdev);
137void r100_set_common_regs(struct radeon_device *rdev);
Jerome Glisse90aca4d2010-03-09 14:45:12 +0000[diff] [blame]138void r100_bm_disable(struct radeon_device *rdev);
Alex Deucherdef9ba92010-04-22 12:39:58 -0400[diff] [blame]139extern bool r100_gui_idle(struct radeon_device *rdev);
Alex Deucher49e02b72010-04-23 17:57:27 -0400[diff] [blame]140extern void r100_pm_misc(struct radeon_device *rdev);
141extern void r100_pm_prepare(struct radeon_device *rdev);
142extern void r100_pm_finish(struct radeon_device *rdev);
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]143extern void r100_pm_init_profile(struct radeon_device *rdev);
144extern void r100_pm_get_dynpm_state(struct radeon_device *rdev);
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]145extern void r100_pre_page_flip(struct radeon_device *rdev, int crtc);
146extern u32 r100_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
147extern void r100_post_page_flip(struct radeon_device *rdev, int crtc);
Alex Deucher3ae19b72012-02-23 17:53:37 -0500[diff] [blame]148extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]149extern int r100_mc_wait_for_idle(struct radeon_device *rdev);
Alex Deucherbae6b5622010-04-22 13:38:05 -0400[diff] [blame]150
Pauli Nieminen44ca7472010-02-11 17:25:47 +0000[diff] [blame]151/*
152 * r200,rv250,rs300,rv280
153 */
154extern int r200_copy_dma(struct radeon_device *rdev,
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]155 uint64_t src_offset,
156 uint64_t dst_offset,
Alex Deucher003cefe2011-09-16 12:04:08 -0400[diff] [blame]157 unsigned num_gpu_pages,
Christian König876dc9f2012-05-08 14:24:01 +0200[diff] [blame]158 struct radeon_fence **fence);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]159void r200_set_safe_registers(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]160
161/*
162 * r300,r350,rv350,rv380
163 */
Jerome Glisse207bf9e2009-09-30 15:35:32 +0200[diff] [blame]164extern int r300_init(struct radeon_device *rdev);
165extern void r300_fini(struct radeon_device *rdev);
166extern int r300_suspend(struct radeon_device *rdev);
167extern int r300_resume(struct radeon_device *rdev);
Jerome Glissea2d07b72010-03-09 14:45:11 +0000[diff] [blame]168extern int r300_asic_reset(struct radeon_device *rdev);
Alex Deucherf7128122012-02-23 17:53:45 -0500[diff] [blame]169extern void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
Jerome Glisse207bf9e2009-09-30 15:35:32 +0200[diff] [blame]170extern void r300_fence_ring_emit(struct radeon_device *rdev,
171 struct radeon_fence *fence);
172extern int r300_cs_parse(struct radeon_cs_parser *p);
173extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
174extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
Jerome Glisse207bf9e2009-09-30 15:35:32 +0200[diff] [blame]175extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
Alex Deucherc836a412009-12-23 10:07:50 -0500[diff] [blame]176extern int rv370_get_pcie_lanes(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]177extern void r300_set_reg_safe(struct radeon_device *rdev);
178extern void r300_mc_program(struct radeon_device *rdev);
179extern void r300_mc_init(struct radeon_device *rdev);
180extern void r300_clock_startup(struct radeon_device *rdev);
181extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
182extern int rv370_pcie_gart_init(struct radeon_device *rdev);
183extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
184extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
185extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]186extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
Pauli Nieminen44ca7472010-02-11 17:25:47 +0000[diff] [blame]187
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]188/*
189 * r420,r423,rv410
190 */
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200[diff] [blame]191extern int r420_init(struct radeon_device *rdev);
192extern void r420_fini(struct radeon_device *rdev);
193extern int r420_suspend(struct radeon_device *rdev);
194extern int r420_resume(struct radeon_device *rdev);
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]195extern void r420_pm_init_profile(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]196extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
197extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
198extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
199extern void r420_pipes_init(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]200
201/*
202 * rs400,rs480
203 */
Jerome Glisseca6ffc62009-10-01 10:20:52 +0200[diff] [blame]204extern int rs400_init(struct radeon_device *rdev);
205extern void rs400_fini(struct radeon_device *rdev);
206extern int rs400_suspend(struct radeon_device *rdev);
207extern int rs400_resume(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]208void rs400_gart_tlb_flush(struct radeon_device *rdev);
209int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
210uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
211void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]212int rs400_gart_init(struct radeon_device *rdev);
213int rs400_gart_enable(struct radeon_device *rdev);
214void rs400_gart_adjust_size(struct radeon_device *rdev);
215void rs400_gart_disable(struct radeon_device *rdev);
216void rs400_gart_fini(struct radeon_device *rdev);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]217extern int rs400_mc_wait_for_idle(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]218
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]219/*
220 * rs600.
221 */
Jerome Glisse90aca4d2010-03-09 14:45:12 +0000[diff] [blame]222extern int rs600_asic_reset(struct radeon_device *rdev);
Jerome Glissec010f802009-09-30 22:09:06 +0200[diff] [blame]223extern int rs600_init(struct radeon_device *rdev);
224extern void rs600_fini(struct radeon_device *rdev);
225extern int rs600_suspend(struct radeon_device *rdev);
226extern int rs600_resume(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]227int rs600_irq_set(struct radeon_device *rdev);
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200[diff] [blame]228int rs600_irq_process(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]229void rs600_irq_disable(struct radeon_device *rdev);
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200[diff] [blame]230u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]231void rs600_gart_tlb_flush(struct radeon_device *rdev);
232int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
233uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
234void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Jerome Glissec93bb852009-07-13 21:04:08 +0200[diff] [blame]235void rs600_bandwidth_update(struct radeon_device *rdev);
Alex Deucher429770b2009-12-04 15:26:55 -0500[diff] [blame]236void rs600_hpd_init(struct radeon_device *rdev);
237void rs600_hpd_fini(struct radeon_device *rdev);
238bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
239void rs600_hpd_set_polarity(struct radeon_device *rdev,
240 enum radeon_hpd_id hpd);
Alex Deucher49e02b72010-04-23 17:57:27 -0400[diff] [blame]241extern void rs600_pm_misc(struct radeon_device *rdev);
242extern void rs600_pm_prepare(struct radeon_device *rdev);
243extern void rs600_pm_finish(struct radeon_device *rdev);
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]244extern void rs600_pre_page_flip(struct radeon_device *rdev, int crtc);
245extern u32 rs600_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
246extern void rs600_post_page_flip(struct radeon_device *rdev, int crtc);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]247void rs600_set_safe_registers(struct radeon_device *rdev);
Alex Deucher3ae19b72012-02-23 17:53:37 -0500[diff] [blame]248extern void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]249extern int rs600_mc_wait_for_idle(struct radeon_device *rdev);
Alex Deucher429770b2009-12-04 15:26:55 -0500[diff] [blame]250
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]251/*
252 * rs690,rs740
253 */
Jerome Glisse3bc68532009-10-01 09:39:24 +0200[diff] [blame]254int rs690_init(struct radeon_device *rdev);
255void rs690_fini(struct radeon_device *rdev);
256int rs690_resume(struct radeon_device *rdev);
257int rs690_suspend(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]258uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
259void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Jerome Glissec93bb852009-07-13 21:04:08 +0200[diff] [blame]260void rs690_bandwidth_update(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]261void rs690_line_buffer_adjust(struct radeon_device *rdev,
262 struct drm_display_mode *mode1,
263 struct drm_display_mode *mode2);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]264extern int rs690_mc_wait_for_idle(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]265
266/*
267 * rv515
268 */
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]269struct rv515_mc_save {
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]270 u32 vga_render_control;
271 u32 vga_hdp_control;
Alex Deucher6253e4c2012-12-12 14:30:32 -0500[diff] [blame]272 bool crtc_enabled[2];
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]273};
Jerome Glisse81ee8fb2012-07-27 16:32:24 -0400[diff] [blame]274
Jerome Glisse068a1172009-06-17 13:28:30 +0200[diff] [blame]275int rv515_init(struct radeon_device *rdev);
Jerome Glissed39c3b82009-09-28 18:34:43 +0200[diff] [blame]276void rv515_fini(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]277uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
278void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Alex Deucherf7128122012-02-23 17:53:45 -0500[diff] [blame]279void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
Jerome Glissec93bb852009-07-13 21:04:08 +0200[diff] [blame]280void rv515_bandwidth_update(struct radeon_device *rdev);
Jerome Glissed39c3b82009-09-28 18:34:43 +0200[diff] [blame]281int rv515_resume(struct radeon_device *rdev);
282int rv515_suspend(struct radeon_device *rdev);
Daniel Vetter187f3da2010-11-28 19:06:09 +0100[diff] [blame]283void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
284void rv515_vga_render_disable(struct radeon_device *rdev);
285void rv515_set_safe_registers(struct radeon_device *rdev);
286void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
287void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
288void rv515_clock_startup(struct radeon_device *rdev);
289void rv515_debugfs(struct radeon_device *rdev);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]290int rv515_mc_wait_for_idle(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]291
292/*
293 * r520,rv530,rv560,rv570,r580
294 */
Jerome Glissed39c3b82009-09-28 18:34:43 +0200[diff] [blame]295int r520_init(struct radeon_device *rdev);
Jerome Glissef0ed1f62009-09-28 20:39:19 +0200[diff] [blame]296int r520_resume(struct radeon_device *rdev);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]297int r520_mc_wait_for_idle(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]298
299/*
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]300 * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]301 */
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]302int r600_init(struct radeon_device *rdev);
303void r600_fini(struct radeon_device *rdev);
304int r600_suspend(struct radeon_device *rdev);
305int r600_resume(struct radeon_device *rdev);
Dave Airlie28d52042009-09-21 14:33:58 +1000[diff] [blame]306void r600_vga_set_state(struct radeon_device *rdev, bool state);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]307int r600_wb_init(struct radeon_device *rdev);
308void r600_wb_fini(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]309void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]310uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
311void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]312int r600_cs_parse(struct radeon_cs_parser *p);
Alex Deuchercf4ccd02011-11-18 10:19:47 -0500[diff] [blame]313int r600_dma_cs_parse(struct radeon_cs_parser *p);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]314void r600_fence_ring_emit(struct radeon_device *rdev,
315 struct radeon_fence *fence);
Christian König15d33322011-09-15 19:02:22 +0200[diff] [blame]316void r600_semaphore_ring_emit(struct radeon_device *rdev,
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]317 struct radeon_ring *cp,
Christian König15d33322011-09-15 19:02:22 +0200[diff] [blame]318 struct radeon_semaphore *semaphore,
Christian König7b1f2482011-09-23 15:11:23 +0200[diff] [blame]319 bool emit_wait);
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]320void r600_dma_fence_ring_emit(struct radeon_device *rdev,
321 struct radeon_fence *fence);
322void r600_dma_semaphore_ring_emit(struct radeon_device *rdev,
323 struct radeon_ring *ring,
324 struct radeon_semaphore *semaphore,
325 bool emit_wait);
326void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
327bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
Alex Deucher123bc182013-01-24 11:37:19 -0500[diff] [blame]328bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
Jerome Glissea2d07b72010-03-09 14:45:11 +0000[diff] [blame]329int r600_asic_reset(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]330int r600_set_surface_reg(struct radeon_device *rdev, int reg,
331 uint32_t tiling_flags, uint32_t pitch,
332 uint32_t offset, uint32_t obj_size);
Daniel Vetter9479c542010-03-11 21:19:16 +0000[diff] [blame]333void r600_clear_surface_reg(struct radeon_device *rdev, int reg);
Alex Deucherf7128122012-02-23 17:53:45 -0500[diff] [blame]334int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]335int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]336void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]337int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]338int r600_dma_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
Christian Königf2ba57b2013-04-08 12:41:29 +0200[diff] [blame]339int r600_uvd_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]340int r600_copy_blit(struct radeon_device *rdev,
341 uint64_t src_offset, uint64_t dst_offset,
Christian König876dc9f2012-05-08 14:24:01 +0200[diff] [blame]342 unsigned num_gpu_pages, struct radeon_fence **fence);
Alex Deucher4d756582012-09-27 15:08:35 -0400[diff] [blame]343int r600_copy_dma(struct radeon_device *rdev,
344 uint64_t src_offset, uint64_t dst_offset,
345 unsigned num_gpu_pages, struct radeon_fence **fence);
Alex Deucher429770b2009-12-04 15:26:55 -0500[diff] [blame]346void r600_hpd_init(struct radeon_device *rdev);
347void r600_hpd_fini(struct radeon_device *rdev);
348bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
349void r600_hpd_set_polarity(struct radeon_device *rdev,
350 enum radeon_hpd_id hpd);
Jerome Glisse062b3892010-02-04 20:36:39 +0100[diff] [blame]351extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo);
Alex Deucherdef9ba92010-04-22 12:39:58 -0400[diff] [blame]352extern bool r600_gui_idle(struct radeon_device *rdev);
Alex Deucher49e02b72010-04-23 17:57:27 -0400[diff] [blame]353extern void r600_pm_misc(struct radeon_device *rdev);
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]354extern void r600_pm_init_profile(struct radeon_device *rdev);
355extern void rs780_pm_init_profile(struct radeon_device *rdev);
Samuel Li65337e62013-04-05 17:50:53 -0400[diff] [blame]356extern uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg);
357extern void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Alex Deucherce8f5372010-05-07 15:10:16 -0400[diff] [blame]358extern void r600_pm_get_dynpm_state(struct radeon_device *rdev);
Alex Deucher3313e3d2011-01-06 18:49:34 -0500[diff] [blame]359extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes);
360extern int r600_get_pcie_lanes(struct radeon_device *rdev);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]361bool r600_card_posted(struct radeon_device *rdev);
362void r600_cp_stop(struct radeon_device *rdev);
363int r600_cp_start(struct radeon_device *rdev);
Christian Könige32eb502011-10-23 12:56:27 +0200[diff] [blame]364void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]365int r600_cp_resume(struct radeon_device *rdev);
366void r600_cp_fini(struct radeon_device *rdev);
367int r600_count_pipe_bits(uint32_t val);
368int r600_mc_wait_for_idle(struct radeon_device *rdev);
369int r600_pcie_gart_init(struct radeon_device *rdev);
370void r600_scratch_init(struct radeon_device *rdev);
371int r600_blit_init(struct radeon_device *rdev);
372void r600_blit_fini(struct radeon_device *rdev);
373int r600_init_microcode(struct radeon_device *rdev);
374/* r600 irq */
375int r600_irq_process(struct radeon_device *rdev);
376int r600_irq_init(struct radeon_device *rdev);
377void r600_irq_fini(struct radeon_device *rdev);
378void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
379int r600_irq_set(struct radeon_device *rdev);
380void r600_irq_suspend(struct radeon_device *rdev);
381void r600_disable_interrupts(struct radeon_device *rdev);
382void r600_rlc_stop(struct radeon_device *rdev);
383/* r600 audio */
384int r600_audio_init(struct radeon_device *rdev);
Rafał Miłecki3299de92012-05-14 21:25:57 +0200[diff] [blame]385struct r600_audio r600_audio_status(struct radeon_device *rdev);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]386void r600_audio_fini(struct radeon_device *rdev);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]387int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
388void r600_hdmi_update_audio_settings(struct drm_encoder *encoder);
Alex Deuchera973bea2013-04-18 11:32:16 -0400[diff] [blame]389void r600_hdmi_enable(struct drm_encoder *encoder, bool enable);
390void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
Daniel Vetter4546b2c2011-02-18 17:59:21 +0100[diff] [blame]391/* r600 blit */
Christian Königf2377502012-05-09 15:35:01 +0200[diff] [blame]392int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages,
Christian König220907d2012-05-10 16:46:43 +0200[diff] [blame]393 struct radeon_fence **fence, struct radeon_sa_bo **vb,
394 struct radeon_semaphore **sem);
Christian König876dc9f2012-05-08 14:24:01 +0200[diff] [blame]395void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence **fence,
Christian König220907d2012-05-10 16:46:43 +0200[diff] [blame]396 struct radeon_sa_bo *vb, struct radeon_semaphore *sem);
Daniel Vetter4546b2c2011-02-18 17:59:21 +0100[diff] [blame]397void r600_kms_blit_copy(struct radeon_device *rdev,
398 u64 src_gpu_addr, u64 dst_gpu_addr,
Christian Königf2377502012-05-09 15:35:01 +0200[diff] [blame]399 unsigned num_gpu_pages,
400 struct radeon_sa_bo *vb);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]401int r600_mc_wait_for_idle(struct radeon_device *rdev);
Alex Deucher454d2e22013-02-14 10:04:02 -0500[diff] [blame]402u32 r600_get_xclk(struct radeon_device *rdev);
Alex Deucherd0418892013-01-24 10:35:23 -0500[diff] [blame]403uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev);
Alex Deucher6bd1c382013-06-21 14:38:03 -0400[diff] [blame]404int rv6xx_get_temp(struct radeon_device *rdev);
Alex Deucher98243912013-01-16 13:13:42 -0500[diff] [blame]405int r600_dpm_pre_set_power_state(struct radeon_device *rdev);
406void r600_dpm_post_set_power_state(struct radeon_device *rdev);
Alex Deucher4a6369e2013-04-12 14:04:10 -0400[diff] [blame]407/* rv6xx dpm */
408int rv6xx_dpm_init(struct radeon_device *rdev);
409int rv6xx_dpm_enable(struct radeon_device *rdev);
410void rv6xx_dpm_disable(struct radeon_device *rdev);
411int rv6xx_dpm_set_power_state(struct radeon_device *rdev);
412void rv6xx_setup_asic(struct radeon_device *rdev);
413void rv6xx_dpm_display_configuration_changed(struct radeon_device *rdev);
414void rv6xx_dpm_fini(struct radeon_device *rdev);
415u32 rv6xx_dpm_get_sclk(struct radeon_device *rdev, bool low);
416u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low);
417void rv6xx_dpm_print_power_state(struct radeon_device *rdev,
418 struct radeon_ps *ps);
Alex Deucher242916a2013-06-28 14:20:53 -0400[diff] [blame]419void rv6xx_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
420 struct seq_file *m);
Alex Deucher9d670062013-04-12 13:59:22 -0400[diff] [blame]421/* rs780 dpm */
422int rs780_dpm_init(struct radeon_device *rdev);
423int rs780_dpm_enable(struct radeon_device *rdev);
424void rs780_dpm_disable(struct radeon_device *rdev);
425int rs780_dpm_set_power_state(struct radeon_device *rdev);
426void rs780_dpm_setup_asic(struct radeon_device *rdev);
427void rs780_dpm_display_configuration_changed(struct radeon_device *rdev);
428void rs780_dpm_fini(struct radeon_device *rdev);
429u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low);
430u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low);
431void rs780_dpm_print_power_state(struct radeon_device *rdev,
432 struct radeon_ps *ps);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]433
Christian Königf2ba57b2013-04-08 12:41:29 +0200[diff] [blame]434/* uvd */
435int r600_uvd_init(struct radeon_device *rdev);
436int r600_uvd_rbc_start(struct radeon_device *rdev);
437void r600_uvd_rbc_stop(struct radeon_device *rdev);
438int r600_uvd_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
439void r600_uvd_fence_emit(struct radeon_device *rdev,
440 struct radeon_fence *fence);
441void r600_uvd_semaphore_emit(struct radeon_device *rdev,
442 struct radeon_ring *ring,
443 struct radeon_semaphore *semaphore,
444 bool emit_wait);
445void r600_uvd_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
446
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]447/*
448 * rv770,rv730,rv710,rv740
449 */
450int rv770_init(struct radeon_device *rdev);
451void rv770_fini(struct radeon_device *rdev);
452int rv770_suspend(struct radeon_device *rdev);
453int rv770_resume(struct radeon_device *rdev);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]454void rv770_pm_misc(struct radeon_device *rdev);
455u32 rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
456void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
457void r700_cp_stop(struct radeon_device *rdev);
458void r700_cp_fini(struct radeon_device *rdev);
Alex Deucher43fb7782013-01-04 09:24:18 -0500[diff] [blame]459int rv770_copy_dma(struct radeon_device *rdev,
460 uint64_t src_offset, uint64_t dst_offset,
461 unsigned num_gpu_pages,
462 struct radeon_fence **fence);
Alex Deucher454d2e22013-02-14 10:04:02 -0500[diff] [blame]463u32 rv770_get_xclk(struct radeon_device *rdev);
Christian Königf2ba57b2013-04-08 12:41:29 +0200[diff] [blame]464int rv770_uvd_resume(struct radeon_device *rdev);
Christian Königef0e6e62013-04-08 12:41:35 +0200[diff] [blame]465int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
Alex Deucher6bd1c382013-06-21 14:38:03 -0400[diff] [blame]466int rv770_get_temp(struct radeon_device *rdev);
Alex Deucher66229b22013-06-26 00:11:19 -0400[diff] [blame]467/* rv7xx pm */
468int rv770_dpm_init(struct radeon_device *rdev);
469int rv770_dpm_enable(struct radeon_device *rdev);
470void rv770_dpm_disable(struct radeon_device *rdev);
471int rv770_dpm_set_power_state(struct radeon_device *rdev);
472void rv770_dpm_setup_asic(struct radeon_device *rdev);
473void rv770_dpm_display_configuration_changed(struct radeon_device *rdev);
474void rv770_dpm_fini(struct radeon_device *rdev);
475u32 rv770_dpm_get_sclk(struct radeon_device *rdev, bool low);
476u32 rv770_dpm_get_mclk(struct radeon_device *rdev, bool low);
477void rv770_dpm_print_power_state(struct radeon_device *rdev,
478 struct radeon_ps *ps);
Alex Deucherbd210d12013-06-28 10:06:26 -0400[diff] [blame]479void rv770_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
480 struct seq_file *m);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]481
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500[diff] [blame]482/*
483 * evergreen
484 */
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]485struct evergreen_mc_save {
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]486 u32 vga_render_control;
487 u32 vga_hdp_control;
Alex Deucher62444b72012-08-15 17:18:42 -0400[diff] [blame]488 bool crtc_enabled[RADEON_MAX_CRTCS];
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]489};
Jerome Glisse81ee8fb2012-07-27 16:32:24 -0400[diff] [blame]490
Alex Deucher0fcdb612010-03-24 13:20:41 -0400[diff] [blame]491void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev);
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500[diff] [blame]492int evergreen_init(struct radeon_device *rdev);
493void evergreen_fini(struct radeon_device *rdev);
494int evergreen_suspend(struct radeon_device *rdev);
495int evergreen_resume(struct radeon_device *rdev);
Alex Deucher123bc182013-01-24 11:37:19 -0500[diff] [blame]496bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
497bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
Jerome Glissea2d07b72010-03-09 14:45:11 +0000[diff] [blame]498int evergreen_asic_reset(struct radeon_device *rdev);
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500[diff] [blame]499void evergreen_bandwidth_update(struct radeon_device *rdev);
Alex Deucher12920592011-02-02 12:37:40 -0500[diff] [blame]500void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500[diff] [blame]501void evergreen_hpd_init(struct radeon_device *rdev);
502void evergreen_hpd_fini(struct radeon_device *rdev);
503bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
504void evergreen_hpd_set_polarity(struct radeon_device *rdev,
505 enum radeon_hpd_id hpd);
Alex Deucher45f9a392010-03-24 13:55:51 -0400[diff] [blame]506u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc);
507int evergreen_irq_set(struct radeon_device *rdev);
508int evergreen_irq_process(struct radeon_device *rdev);
Alex Deuchercb5fcbd2010-05-28 19:01:35 -0400[diff] [blame]509extern int evergreen_cs_parse(struct radeon_cs_parser *p);
Alex Deucherd2ead3e2012-12-13 09:55:45 -0500[diff] [blame]510extern int evergreen_dma_cs_parse(struct radeon_cs_parser *p);
Alex Deucher49e02b72010-04-23 17:57:27 -0400[diff] [blame]511extern void evergreen_pm_misc(struct radeon_device *rdev);
512extern void evergreen_pm_prepare(struct radeon_device *rdev);
513extern void evergreen_pm_finish(struct radeon_device *rdev);
Alex Deuchera4c9e2e2011-11-04 10:09:41 -0400[diff] [blame]514extern void sumo_pm_init_profile(struct radeon_device *rdev);
Alex Deucher27810fb2012-10-01 19:25:11 -0400[diff] [blame]515extern void btc_pm_init_profile(struct radeon_device *rdev);
Alex Deucher23d33ba2013-04-08 12:41:32 +0200[diff] [blame]516int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
Alex Deuchera8b49252013-04-08 12:41:33 +0200[diff] [blame]517int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
Alex Deucher6f34be52010-11-21 10:59:01 -0500[diff] [blame]518extern void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc);
519extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
520extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc);
Alex Deucher3ae19b72012-02-23 17:53:37 -0500[diff] [blame]521extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc);
Daniel Vetter3574dda2011-02-18 17:59:19 +0100[diff] [blame]522void evergreen_disable_interrupt_state(struct radeon_device *rdev);
523int evergreen_blit_init(struct radeon_device *rdev);
Alex Deucher89e51812012-02-23 17:53:38 -0500[diff] [blame]524int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
Alex Deucher233d1ad2012-12-04 15:25:59 -0500[diff] [blame]525void evergreen_dma_fence_ring_emit(struct radeon_device *rdev,
526 struct radeon_fence *fence);
527void evergreen_dma_ring_ib_execute(struct radeon_device *rdev,
528 struct radeon_ib *ib);
529int evergreen_copy_dma(struct radeon_device *rdev,
530 uint64_t src_offset, uint64_t dst_offset,
531 unsigned num_gpu_pages,
532 struct radeon_fence **fence);
Alex Deuchera973bea2013-04-18 11:32:16 -0400[diff] [blame]533void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable);
534void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
Alex Deucher6bd1c382013-06-21 14:38:03 -0400[diff] [blame]535int evergreen_get_temp(struct radeon_device *rdev);
536int sumo_get_temp(struct radeon_device *rdev);
Alex Deucher29a15222012-12-14 11:57:36 -0500[diff] [blame]537int tn_get_temp(struct radeon_device *rdev);
Alex Deucherdc50ba72013-06-26 00:33:35 -0400[diff] [blame]538int cypress_dpm_init(struct radeon_device *rdev);
539void cypress_dpm_setup_asic(struct radeon_device *rdev);
540int cypress_dpm_enable(struct radeon_device *rdev);
541void cypress_dpm_disable(struct radeon_device *rdev);
542int cypress_dpm_set_power_state(struct radeon_device *rdev);
543void cypress_dpm_display_configuration_changed(struct radeon_device *rdev);
544void cypress_dpm_fini(struct radeon_device *rdev);
Alex Deucher6596afd2013-06-26 00:15:24 -0400[diff] [blame]545int btc_dpm_init(struct radeon_device *rdev);
546void btc_dpm_setup_asic(struct radeon_device *rdev);
547int btc_dpm_enable(struct radeon_device *rdev);
548void btc_dpm_disable(struct radeon_device *rdev);
Alex Deuchere8a95392013-01-16 14:17:23 -0500[diff] [blame]549int btc_dpm_pre_set_power_state(struct radeon_device *rdev);
Alex Deucher6596afd2013-06-26 00:15:24 -0400[diff] [blame]550int btc_dpm_set_power_state(struct radeon_device *rdev);
Alex Deuchere8a95392013-01-16 14:17:23 -0500[diff] [blame]551void btc_dpm_post_set_power_state(struct radeon_device *rdev);
Alex Deucher6596afd2013-06-26 00:15:24 -0400[diff] [blame]552void btc_dpm_fini(struct radeon_device *rdev);
Alex Deuchere8a95392013-01-16 14:17:23 -0500[diff] [blame]553u32 btc_dpm_get_sclk(struct radeon_device *rdev, bool low);
554u32 btc_dpm_get_mclk(struct radeon_device *rdev, bool low);
Alex Deucher80ea2c12013-04-12 14:56:21 -0400[diff] [blame]555int sumo_dpm_init(struct radeon_device *rdev);
556int sumo_dpm_enable(struct radeon_device *rdev);
557void sumo_dpm_disable(struct radeon_device *rdev);
Alex Deucher422a56b2013-06-25 15:40:21 -0400[diff] [blame]558int sumo_dpm_pre_set_power_state(struct radeon_device *rdev);
Alex Deucher80ea2c12013-04-12 14:56:21 -0400[diff] [blame]559int sumo_dpm_set_power_state(struct radeon_device *rdev);
Alex Deucher422a56b2013-06-25 15:40:21 -0400[diff] [blame]560void sumo_dpm_post_set_power_state(struct radeon_device *rdev);
Alex Deucher80ea2c12013-04-12 14:56:21 -0400[diff] [blame]561void sumo_dpm_setup_asic(struct radeon_device *rdev);
562void sumo_dpm_display_configuration_changed(struct radeon_device *rdev);
563void sumo_dpm_fini(struct radeon_device *rdev);
564u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low);
565u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low);
566void sumo_dpm_print_power_state(struct radeon_device *rdev,
567 struct radeon_ps *ps);
Alex Deucherfb701602013-06-28 10:47:56 -0400[diff] [blame^]568void sumo_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
569 struct seq_file *m);
Daniel Vetter4546b2c2011-02-18 17:59:21 +0100[diff] [blame]570
Alex Deuchere3487622011-03-02 20:07:36 -0500[diff] [blame]571/*
572 * cayman
573 */
Alex Deucherb40e7e12011-11-17 14:57:50 -0500[diff] [blame]574void cayman_fence_ring_emit(struct radeon_device *rdev,
575 struct radeon_fence *fence);
Christian Königf2ba57b2013-04-08 12:41:29 +0200[diff] [blame]576void cayman_uvd_semaphore_emit(struct radeon_device *rdev,
577 struct radeon_ring *ring,
578 struct radeon_semaphore *semaphore,
579 bool emit_wait);
Alex Deuchere3487622011-03-02 20:07:36 -0500[diff] [blame]580void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev);
581int cayman_init(struct radeon_device *rdev);
582void cayman_fini(struct radeon_device *rdev);
583int cayman_suspend(struct radeon_device *rdev);
584int cayman_resume(struct radeon_device *rdev);
Alex Deuchere3487622011-03-02 20:07:36 -0500[diff] [blame]585int cayman_asic_reset(struct radeon_device *rdev);
Jerome Glisse721604a2012-01-05 22:11:05 -0500[diff] [blame]586void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
587int cayman_vm_init(struct radeon_device *rdev);
588void cayman_vm_fini(struct radeon_device *rdev);
Alex Deucher498522b2012-10-02 14:43:38 -0400[diff] [blame]589void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
Christian König089a7862012-08-11 11:54:05 +0200[diff] [blame]590uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags);
Alex Deucher43f12142013-02-01 17:32:42 +0100[diff] [blame]591void cayman_vm_set_page(struct radeon_device *rdev,
592 struct radeon_ib *ib,
593 uint64_t pe,
Christian Königdce34bf2012-09-17 19:36:18 +0200[diff] [blame]594 uint64_t addr, unsigned count,
595 uint32_t incr, uint32_t flags);
Jerome Glisse721604a2012-01-05 22:11:05 -0500[diff] [blame]596int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
Alex Deuchercd459e52012-12-13 12:17:38 -0500[diff] [blame]597int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
Alex Deucherf60cbd12012-12-04 15:27:33 -0500[diff] [blame]598void cayman_dma_ring_ib_execute(struct radeon_device *rdev,
599 struct radeon_ib *ib);
Alex Deucher123bc182013-01-24 11:37:19 -0500[diff] [blame]600bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
Alex Deucherf60cbd12012-12-04 15:27:33 -0500[diff] [blame]601bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
602void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
Alex Deucher45f9a392010-03-24 13:55:51 -0400[diff] [blame]603
Alex Deucher69e0b572013-04-12 16:42:42 -0400[diff] [blame]604int ni_dpm_init(struct radeon_device *rdev);
605void ni_dpm_setup_asic(struct radeon_device *rdev);
606int ni_dpm_enable(struct radeon_device *rdev);
607void ni_dpm_disable(struct radeon_device *rdev);
Alex Deucherfee3d742013-01-16 14:35:39 -0500[diff] [blame]608int ni_dpm_pre_set_power_state(struct radeon_device *rdev);
Alex Deucher69e0b572013-04-12 16:42:42 -0400[diff] [blame]609int ni_dpm_set_power_state(struct radeon_device *rdev);
Alex Deucherfee3d742013-01-16 14:35:39 -0500[diff] [blame]610void ni_dpm_post_set_power_state(struct radeon_device *rdev);
Alex Deucher69e0b572013-04-12 16:42:42 -0400[diff] [blame]611void ni_dpm_fini(struct radeon_device *rdev);
612u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low);
613u32 ni_dpm_get_mclk(struct radeon_device *rdev, bool low);
614void ni_dpm_print_power_state(struct radeon_device *rdev,
615 struct radeon_ps *ps);
Alex Deucherd70229f2013-04-12 16:40:41 -0400[diff] [blame]616int trinity_dpm_init(struct radeon_device *rdev);
617int trinity_dpm_enable(struct radeon_device *rdev);
618void trinity_dpm_disable(struct radeon_device *rdev);
Alex Deuchera284c482013-01-16 13:53:40 -0500[diff] [blame]619int trinity_dpm_pre_set_power_state(struct radeon_device *rdev);
Alex Deucherd70229f2013-04-12 16:40:41 -0400[diff] [blame]620int trinity_dpm_set_power_state(struct radeon_device *rdev);
Alex Deuchera284c482013-01-16 13:53:40 -0500[diff] [blame]621void trinity_dpm_post_set_power_state(struct radeon_device *rdev);
Alex Deucherd70229f2013-04-12 16:40:41 -0400[diff] [blame]622void trinity_dpm_setup_asic(struct radeon_device *rdev);
623void trinity_dpm_display_configuration_changed(struct radeon_device *rdev);
624void trinity_dpm_fini(struct radeon_device *rdev);
625u32 trinity_dpm_get_sclk(struct radeon_device *rdev, bool low);
626u32 trinity_dpm_get_mclk(struct radeon_device *rdev, bool low);
627void trinity_dpm_print_power_state(struct radeon_device *rdev,
628 struct radeon_ps *ps);
629
Alex Deucher43b3cd92012-03-20 17:18:00 -0400[diff] [blame]630/* DCE6 - SI */
631void dce6_bandwidth_update(struct radeon_device *rdev);
632
Alex Deucher02779c02012-03-20 17:18:25 -0400[diff] [blame]633/*
634 * si
635 */
636void si_fence_ring_emit(struct radeon_device *rdev,
637 struct radeon_fence *fence);
638void si_pcie_gart_tlb_flush(struct radeon_device *rdev);
639int si_init(struct radeon_device *rdev);
640void si_fini(struct radeon_device *rdev);
641int si_suspend(struct radeon_device *rdev);
642int si_resume(struct radeon_device *rdev);
Alex Deucher123bc182013-01-24 11:37:19 -0500[diff] [blame]643bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
644bool si_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
Alex Deucher02779c02012-03-20 17:18:25 -0400[diff] [blame]645int si_asic_reset(struct radeon_device *rdev);
646void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
647int si_irq_set(struct radeon_device *rdev);
648int si_irq_process(struct radeon_device *rdev);
649int si_vm_init(struct radeon_device *rdev);
650void si_vm_fini(struct radeon_device *rdev);
Alex Deucher43f12142013-02-01 17:32:42 +0100[diff] [blame]651void si_vm_set_page(struct radeon_device *rdev,
652 struct radeon_ib *ib,
653 uint64_t pe,
Alex Deucher82ffd922012-10-02 14:47:46 -0400[diff] [blame]654 uint64_t addr, unsigned count,
655 uint32_t incr, uint32_t flags);
Alex Deucher498522b2012-10-02 14:43:38 -0400[diff] [blame]656void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
Alex Deucher02779c02012-03-20 17:18:25 -0400[diff] [blame]657int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
Alex Deucher8c5fd7e2012-12-04 15:28:18 -0500[diff] [blame]658int si_copy_dma(struct radeon_device *rdev,
659 uint64_t src_offset, uint64_t dst_offset,
660 unsigned num_gpu_pages,
661 struct radeon_fence **fence);
662void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
Alex Deucher454d2e22013-02-14 10:04:02 -0500[diff] [blame]663u32 si_get_xclk(struct radeon_device *rdev);
Alex Deucherd0418892013-01-24 10:35:23 -0500[diff] [blame]664uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev);
Christian König2539eb02013-04-08 12:41:34 +0200[diff] [blame]665int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
Alex Deucher6bd1c382013-06-21 14:38:03 -0400[diff] [blame]666int si_get_temp(struct radeon_device *rdev);
Alex Deuchera9e61412013-06-25 17:56:16 -0400[diff] [blame]667int si_dpm_init(struct radeon_device *rdev);
668void si_dpm_setup_asic(struct radeon_device *rdev);
669int si_dpm_enable(struct radeon_device *rdev);
670void si_dpm_disable(struct radeon_device *rdev);
671int si_dpm_pre_set_power_state(struct radeon_device *rdev);
672int si_dpm_set_power_state(struct radeon_device *rdev);
673void si_dpm_post_set_power_state(struct radeon_device *rdev);
674void si_dpm_fini(struct radeon_device *rdev);
675void si_dpm_display_configuration_changed(struct radeon_device *rdev);
Alex Deucher02779c02012-03-20 17:18:25 -0400[diff] [blame]676
Alex Deucher0672e272013-04-09 16:22:31 -0400[diff] [blame]677/* DCE8 - CIK */
678void dce8_bandwidth_update(struct radeon_device *rdev);
679
Alex Deucher44fa3462012-12-18 22:17:00 -0500[diff] [blame]680/*
681 * cik
682 */
683uint64_t cik_get_gpu_clock_counter(struct radeon_device *rdev);
Alex Deucher2c679122013-04-09 13:32:18 -0400[diff] [blame]684u32 cik_get_xclk(struct radeon_device *rdev);
Alex Deucher6e2c3c02013-04-03 19:28:32 -0400[diff] [blame]685uint32_t cik_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
686void cik_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Christian König87167bb2013-04-09 13:39:21 -0400[diff] [blame]687int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
688int cik_uvd_resume(struct radeon_device *rdev);
Alex Deucher0672e272013-04-09 16:22:31 -0400[diff] [blame]689void cik_sdma_fence_ring_emit(struct radeon_device *rdev,
690 struct radeon_fence *fence);
691void cik_sdma_semaphore_ring_emit(struct radeon_device *rdev,
692 struct radeon_ring *ring,
693 struct radeon_semaphore *semaphore,
694 bool emit_wait);
695void cik_sdma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
696int cik_copy_dma(struct radeon_device *rdev,
697 uint64_t src_offset, uint64_t dst_offset,
698 unsigned num_gpu_pages,
699 struct radeon_fence **fence);
700int cik_sdma_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
701int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
702bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
703void cik_fence_gfx_ring_emit(struct radeon_device *rdev,
704 struct radeon_fence *fence);
705void cik_fence_compute_ring_emit(struct radeon_device *rdev,
706 struct radeon_fence *fence);
707void cik_semaphore_ring_emit(struct radeon_device *rdev,
708 struct radeon_ring *cp,
709 struct radeon_semaphore *semaphore,
710 bool emit_wait);
711void cik_pcie_gart_tlb_flush(struct radeon_device *rdev);
712int cik_init(struct radeon_device *rdev);
713void cik_fini(struct radeon_device *rdev);
714int cik_suspend(struct radeon_device *rdev);
715int cik_resume(struct radeon_device *rdev);
716bool cik_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
717int cik_asic_reset(struct radeon_device *rdev);
718void cik_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
719int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
720int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
721int cik_irq_set(struct radeon_device *rdev);
722int cik_irq_process(struct radeon_device *rdev);
723int cik_vm_init(struct radeon_device *rdev);
724void cik_vm_fini(struct radeon_device *rdev);
725void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
726void cik_vm_set_page(struct radeon_device *rdev,
727 struct radeon_ib *ib,
728 uint64_t pe,
729 uint64_t addr, unsigned count,
730 uint32_t incr, uint32_t flags);
731void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
732int cik_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
733u32 cik_compute_ring_get_rptr(struct radeon_device *rdev,
734 struct radeon_ring *ring);
735u32 cik_compute_ring_get_wptr(struct radeon_device *rdev,
736 struct radeon_ring *ring);
737void cik_compute_ring_set_wptr(struct radeon_device *rdev,
738 struct radeon_ring *ring);
Alex Deucher44fa3462012-12-18 22:17:00 -0500[diff] [blame]739
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]740#endif