blob: 858a57a735894d9f7788f30cf8fab386ca965808 [file] [log] [blame]
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001/* QLogic qed NIC Driver
Mintz, Yuvale8f1cb52017-01-01 13:57:00 +02002 * Copyright (c) 2015-2017 QLogic Corporation
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003 *
Mintz, Yuvale8f1cb52017-01-01 13:57:00 +02004 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020031 */
32
33#ifndef _QED_HSI_H
34#define _QED_HSI_H
35
36#include <linux/types.h>
37#include <linux/io.h>
38#include <linux/bitops.h>
39#include <linux/delay.h>
40#include <linux/kernel.h>
41#include <linux/list.h>
42#include <linux/slab.h>
43#include <linux/qed/common_hsi.h>
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030044#include <linux/qed/storage_common.h>
45#include <linux/qed/tcp_common.h>
Arun Easi1e128c82017-02-15 06:28:22 -080046#include <linux/qed/fcoe_common.h>
Yuval Mintz25c089d2015-10-26 11:02:26 +020047#include <linux/qed/eth_common.h>
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030048#include <linux/qed/iscsi_common.h>
49#include <linux/qed/rdma_common.h>
50#include <linux/qed/roce_common.h>
Arun Easi1e128c82017-02-15 06:28:22 -080051#include <linux/qed/qed_fcoe_if.h>
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020052
53struct qed_hwfn;
54struct qed_ptt;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020055
56/* opcodes for the event ring */
57enum common_event_opcode {
58 COMMON_EVENT_PF_START,
59 COMMON_EVENT_PF_STOP,
Yuval Mintz1408cc1f2016-05-11 16:36:14 +030060 COMMON_EVENT_VF_START,
Yuval Mintz0b55e272016-05-11 16:36:15 +030061 COMMON_EVENT_VF_STOP,
Yuval Mintz37bff2b2016-05-11 16:36:13 +030062 COMMON_EVENT_VF_PF_CHANNEL,
Yuval Mintz351a4ded2016-06-02 10:23:29 +030063 COMMON_EVENT_VF_FLR,
64 COMMON_EVENT_PF_UPDATE,
65 COMMON_EVENT_MALICIOUS_VF,
66 COMMON_EVENT_RL_UPDATE,
Yuval Mintzfc48b7a2016-02-15 13:22:35 -050067 COMMON_EVENT_EMPTY,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020068 MAX_COMMON_EVENT_OPCODE
69};
70
71/* Common Ramrod Command IDs */
72enum common_ramrod_cmd_id {
73 COMMON_RAMROD_UNUSED,
Yuval Mintz351a4ded2016-06-02 10:23:29 +030074 COMMON_RAMROD_PF_START,
75 COMMON_RAMROD_PF_STOP,
Yuval Mintz1408cc1f2016-05-11 16:36:14 +030076 COMMON_RAMROD_VF_START,
Yuval Mintz0b55e272016-05-11 16:36:15 +030077 COMMON_RAMROD_VF_STOP,
Manish Chopra464f6642016-04-14 01:38:29 -040078 COMMON_RAMROD_PF_UPDATE,
Yuval Mintz351a4ded2016-06-02 10:23:29 +030079 COMMON_RAMROD_RL_UPDATE,
Yuval Mintzfc48b7a2016-02-15 13:22:35 -050080 COMMON_RAMROD_EMPTY,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020081 MAX_COMMON_RAMROD_CMD_ID
82};
83
84/* The core storm context for the Ystorm */
85struct ystorm_core_conn_st_ctx {
86 __le32 reserved[4];
87};
88
89/* The core storm context for the Pstorm */
90struct pstorm_core_conn_st_ctx {
91 __le32 reserved[4];
92};
93
94/* Core Slowpath Connection storm context of Xstorm */
95struct xstorm_core_conn_st_ctx {
Yuval Mintz351a4ded2016-06-02 10:23:29 +030096 __le32 spq_base_lo;
97 __le32 spq_base_hi;
98 struct regpair consolid_base_addr;
99 __le16 spq_cons;
100 __le16 consolid_cons;
101 __le32 reserved0[55];
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200102};
103
104struct xstorm_core_conn_ag_ctx {
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300105 u8 reserved0;
106 u8 core_state;
107 u8 flags0;
108#define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
109#define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
110#define XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK 0x1
111#define XSTORM_CORE_CONN_AG_CTX_RESERVED1_SHIFT 1
112#define XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK 0x1
113#define XSTORM_CORE_CONN_AG_CTX_RESERVED2_SHIFT 2
114#define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
115#define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
116#define XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK 0x1
117#define XSTORM_CORE_CONN_AG_CTX_RESERVED3_SHIFT 4
118#define XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK 0x1
119#define XSTORM_CORE_CONN_AG_CTX_RESERVED4_SHIFT 5
120#define XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK 0x1
121#define XSTORM_CORE_CONN_AG_CTX_RESERVED5_SHIFT 6
122#define XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK 0x1
123#define XSTORM_CORE_CONN_AG_CTX_RESERVED6_SHIFT 7
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200124 u8 flags1;
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300125#define XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK 0x1
126#define XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT 0
127#define XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK 0x1
128#define XSTORM_CORE_CONN_AG_CTX_RESERVED8_SHIFT 1
129#define XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK 0x1
130#define XSTORM_CORE_CONN_AG_CTX_RESERVED9_SHIFT 2
131#define XSTORM_CORE_CONN_AG_CTX_BIT11_MASK 0x1
132#define XSTORM_CORE_CONN_AG_CTX_BIT11_SHIFT 3
133#define XSTORM_CORE_CONN_AG_CTX_BIT12_MASK 0x1
134#define XSTORM_CORE_CONN_AG_CTX_BIT12_SHIFT 4
135#define XSTORM_CORE_CONN_AG_CTX_BIT13_MASK 0x1
136#define XSTORM_CORE_CONN_AG_CTX_BIT13_SHIFT 5
137#define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
138#define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
139#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
140#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200141 u8 flags2;
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300142#define XSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
143#define XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 0
144#define XSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
145#define XSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 2
146#define XSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
147#define XSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 4
148#define XSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
149#define XSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 6
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200150 u8 flags3;
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300151#define XSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
152#define XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 0
153#define XSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
154#define XSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 2
155#define XSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
156#define XSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 4
157#define XSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3
158#define XSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 6
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200159 u8 flags4;
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300160#define XSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3
161#define XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 0
162#define XSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3
163#define XSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 2
164#define XSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3
165#define XSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 4
166#define XSTORM_CORE_CONN_AG_CTX_CF11_MASK 0x3
167#define XSTORM_CORE_CONN_AG_CTX_CF11_SHIFT 6
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200168 u8 flags5;
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300169#define XSTORM_CORE_CONN_AG_CTX_CF12_MASK 0x3
170#define XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT 0
171#define XSTORM_CORE_CONN_AG_CTX_CF13_MASK 0x3
172#define XSTORM_CORE_CONN_AG_CTX_CF13_SHIFT 2
173#define XSTORM_CORE_CONN_AG_CTX_CF14_MASK 0x3
174#define XSTORM_CORE_CONN_AG_CTX_CF14_SHIFT 4
175#define XSTORM_CORE_CONN_AG_CTX_CF15_MASK 0x3
176#define XSTORM_CORE_CONN_AG_CTX_CF15_SHIFT 6
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200177 u8 flags6;
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300178#define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK 0x3
179#define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT 0
180#define XSTORM_CORE_CONN_AG_CTX_CF17_MASK 0x3
181#define XSTORM_CORE_CONN_AG_CTX_CF17_SHIFT 2
182#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK 0x3
183#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_SHIFT 4
184#define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
185#define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200186 u8 flags7;
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300187#define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
188#define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
189#define XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK 0x3
190#define XSTORM_CORE_CONN_AG_CTX_RESERVED10_SHIFT 2
191#define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
192#define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_SHIFT 4
193#define XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
194#define XSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 6
195#define XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
196#define XSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 7
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200197 u8 flags8;
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300198#define XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
199#define XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 0
200#define XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
201#define XSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 1
202#define XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
203#define XSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 2
204#define XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
205#define XSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 3
206#define XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
207#define XSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 4
208#define XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1
209#define XSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 5
210#define XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1
211#define XSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 6
212#define XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1
213#define XSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 7
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200214 u8 flags9;
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300215#define XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1
216#define XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 0
217#define XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK 0x1
218#define XSTORM_CORE_CONN_AG_CTX_CF11EN_SHIFT 1
219#define XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK 0x1
220#define XSTORM_CORE_CONN_AG_CTX_CF12EN_SHIFT 2
221#define XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK 0x1
222#define XSTORM_CORE_CONN_AG_CTX_CF13EN_SHIFT 3
223#define XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK 0x1
224#define XSTORM_CORE_CONN_AG_CTX_CF14EN_SHIFT 4
225#define XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK 0x1
226#define XSTORM_CORE_CONN_AG_CTX_CF15EN_SHIFT 5
227#define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK 0x1
228#define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_SHIFT 6
229#define XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK 0x1
230#define XSTORM_CORE_CONN_AG_CTX_CF17EN_SHIFT 7
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200231 u8 flags10;
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300232#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
233#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
234#define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
235#define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
236#define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
237#define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
238#define XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK 0x1
239#define XSTORM_CORE_CONN_AG_CTX_RESERVED11_SHIFT 3
240#define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
241#define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
242#define XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK 0x1
243#define XSTORM_CORE_CONN_AG_CTX_CF23EN_SHIFT 5
244#define XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK 0x1
245#define XSTORM_CORE_CONN_AG_CTX_RESERVED12_SHIFT 6
246#define XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK 0x1
247#define XSTORM_CORE_CONN_AG_CTX_RESERVED13_SHIFT 7
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200248 u8 flags11;
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300249#define XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK 0x1
250#define XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT 0
251#define XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK 0x1
252#define XSTORM_CORE_CONN_AG_CTX_RESERVED15_SHIFT 1
253#define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
254#define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
255#define XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
256#define XSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 3
257#define XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
258#define XSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 4
259#define XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
260#define XSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 5
261#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
262#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
263#define XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK 0x1
264#define XSTORM_CORE_CONN_AG_CTX_RULE9EN_SHIFT 7
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200265 u8 flags12;
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300266#define XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK 0x1
267#define XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT 0
268#define XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK 0x1
269#define XSTORM_CORE_CONN_AG_CTX_RULE11EN_SHIFT 1
270#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
271#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
272#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
273#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
274#define XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK 0x1
275#define XSTORM_CORE_CONN_AG_CTX_RULE14EN_SHIFT 4
276#define XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK 0x1
277#define XSTORM_CORE_CONN_AG_CTX_RULE15EN_SHIFT 5
278#define XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK 0x1
279#define XSTORM_CORE_CONN_AG_CTX_RULE16EN_SHIFT 6
280#define XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK 0x1
281#define XSTORM_CORE_CONN_AG_CTX_RULE17EN_SHIFT 7
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200282 u8 flags13;
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300283#define XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK 0x1
284#define XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT 0
285#define XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK 0x1
286#define XSTORM_CORE_CONN_AG_CTX_RULE19EN_SHIFT 1
287#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
288#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
289#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
290#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
291#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
292#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
293#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
294#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
295#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
296#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
297#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
298#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200299 u8 flags14;
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300300#define XSTORM_CORE_CONN_AG_CTX_BIT16_MASK 0x1
301#define XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT 0
302#define XSTORM_CORE_CONN_AG_CTX_BIT17_MASK 0x1
303#define XSTORM_CORE_CONN_AG_CTX_BIT17_SHIFT 1
304#define XSTORM_CORE_CONN_AG_CTX_BIT18_MASK 0x1
305#define XSTORM_CORE_CONN_AG_CTX_BIT18_SHIFT 2
306#define XSTORM_CORE_CONN_AG_CTX_BIT19_MASK 0x1
307#define XSTORM_CORE_CONN_AG_CTX_BIT19_SHIFT 3
308#define XSTORM_CORE_CONN_AG_CTX_BIT20_MASK 0x1
309#define XSTORM_CORE_CONN_AG_CTX_BIT20_SHIFT 4
310#define XSTORM_CORE_CONN_AG_CTX_BIT21_MASK 0x1
311#define XSTORM_CORE_CONN_AG_CTX_BIT21_SHIFT 5
312#define XSTORM_CORE_CONN_AG_CTX_CF23_MASK 0x3
313#define XSTORM_CORE_CONN_AG_CTX_CF23_SHIFT 6
314 u8 byte2;
315 __le16 physical_q0;
316 __le16 consolid_prod;
317 __le16 reserved16;
318 __le16 tx_bd_cons;
319 __le16 tx_bd_or_spq_prod;
320 __le16 word5;
321 __le16 conn_dpi;
322 u8 byte3;
323 u8 byte4;
324 u8 byte5;
325 u8 byte6;
326 __le32 reg0;
327 __le32 reg1;
328 __le32 reg2;
329 __le32 reg3;
330 __le32 reg4;
331 __le32 reg5;
332 __le32 reg6;
333 __le16 word7;
334 __le16 word8;
335 __le16 word9;
336 __le16 word10;
337 __le32 reg7;
338 __le32 reg8;
339 __le32 reg9;
340 u8 byte7;
341 u8 byte8;
342 u8 byte9;
343 u8 byte10;
344 u8 byte11;
345 u8 byte12;
346 u8 byte13;
347 u8 byte14;
348 u8 byte15;
349 u8 byte16;
350 __le16 word11;
351 __le32 reg10;
352 __le32 reg11;
353 __le32 reg12;
354 __le32 reg13;
355 __le32 reg14;
356 __le32 reg15;
357 __le32 reg16;
358 __le32 reg17;
359 __le32 reg18;
360 __le32 reg19;
361 __le16 word12;
362 __le16 word13;
363 __le16 word14;
364 __le16 word15;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200365};
366
Yuval Mintzfc48b7a2016-02-15 13:22:35 -0500367struct tstorm_core_conn_ag_ctx {
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300368 u8 byte0;
369 u8 byte1;
370 u8 flags0;
371#define TSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
372#define TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
373#define TSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
374#define TSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
375#define TSTORM_CORE_CONN_AG_CTX_BIT2_MASK 0x1
376#define TSTORM_CORE_CONN_AG_CTX_BIT2_SHIFT 2
377#define TSTORM_CORE_CONN_AG_CTX_BIT3_MASK 0x1
378#define TSTORM_CORE_CONN_AG_CTX_BIT3_SHIFT 3
379#define TSTORM_CORE_CONN_AG_CTX_BIT4_MASK 0x1
380#define TSTORM_CORE_CONN_AG_CTX_BIT4_SHIFT 4
381#define TSTORM_CORE_CONN_AG_CTX_BIT5_MASK 0x1
382#define TSTORM_CORE_CONN_AG_CTX_BIT5_SHIFT 5
383#define TSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
384#define TSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 6
Yuval Mintzfc48b7a2016-02-15 13:22:35 -0500385 u8 flags1;
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300386#define TSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
387#define TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 0
388#define TSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
389#define TSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 2
390#define TSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
391#define TSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 4
392#define TSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
393#define TSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 6
Yuval Mintzfc48b7a2016-02-15 13:22:35 -0500394 u8 flags2;
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300395#define TSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
396#define TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 0
397#define TSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
398#define TSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 2
399#define TSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3
400#define TSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 4
401#define TSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3
402#define TSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 6
Yuval Mintzfc48b7a2016-02-15 13:22:35 -0500403 u8 flags3;
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300404#define TSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3
405#define TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 0
406#define TSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3
407#define TSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 2
408#define TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
409#define TSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 4
410#define TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
411#define TSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 5
412#define TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
413#define TSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 6
414#define TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
415#define TSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 7
Yuval Mintzfc48b7a2016-02-15 13:22:35 -0500416 u8 flags4;
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300417#define TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
418#define TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 0
419#define TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
420#define TSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 1
421#define TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
422#define TSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 2
423#define TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1
424#define TSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 3
425#define TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1
426#define TSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 4
427#define TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1
428#define TSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 5
429#define TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1
430#define TSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 6
431#define TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
432#define TSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
Yuval Mintzfc48b7a2016-02-15 13:22:35 -0500433 u8 flags5;
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300434#define TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
435#define TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
436#define TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
437#define TSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
438#define TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
439#define TSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
440#define TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
441#define TSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
442#define TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
443#define TSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
444#define TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
445#define TSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
446#define TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
447#define TSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
448#define TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1
449#define TSTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
450 __le32 reg0;
451 __le32 reg1;
452 __le32 reg2;
453 __le32 reg3;
454 __le32 reg4;
455 __le32 reg5;
456 __le32 reg6;
457 __le32 reg7;
458 __le32 reg8;
459 u8 byte2;
460 u8 byte3;
461 __le16 word0;
462 u8 byte4;
463 u8 byte5;
464 __le16 word1;
465 __le16 word2;
466 __le16 word3;
467 __le32 reg9;
468 __le32 reg10;
Yuval Mintzfc48b7a2016-02-15 13:22:35 -0500469};
470
471struct ustorm_core_conn_ag_ctx {
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300472 u8 reserved;
473 u8 byte1;
474 u8 flags0;
475#define USTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
476#define USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
477#define USTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
478#define USTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
479#define USTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
480#define USTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
481#define USTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
482#define USTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
483#define USTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
484#define USTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
Yuval Mintzfc48b7a2016-02-15 13:22:35 -0500485 u8 flags1;
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300486#define USTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
487#define USTORM_CORE_CONN_AG_CTX_CF3_SHIFT 0
488#define USTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
489#define USTORM_CORE_CONN_AG_CTX_CF4_SHIFT 2
490#define USTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
491#define USTORM_CORE_CONN_AG_CTX_CF5_SHIFT 4
492#define USTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
493#define USTORM_CORE_CONN_AG_CTX_CF6_SHIFT 6
Yuval Mintzfc48b7a2016-02-15 13:22:35 -0500494 u8 flags2;
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300495#define USTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
496#define USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
497#define USTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
498#define USTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
499#define USTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
500#define USTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
501#define USTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
502#define USTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 3
503#define USTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
504#define USTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 4
505#define USTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
506#define USTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 5
507#define USTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
508#define USTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 6
509#define USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
510#define USTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
Yuval Mintzfc48b7a2016-02-15 13:22:35 -0500511 u8 flags3;
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300512#define USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
513#define USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
514#define USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
515#define USTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
516#define USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
517#define USTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
518#define USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
519#define USTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
520#define USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
521#define USTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
522#define USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
523#define USTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
524#define USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
525#define USTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
526#define USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1
527#define USTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
528 u8 byte2;
529 u8 byte3;
530 __le16 word0;
531 __le16 word1;
532 __le32 rx_producers;
533 __le32 reg1;
534 __le32 reg2;
535 __le32 reg3;
536 __le16 word2;
537 __le16 word3;
Yuval Mintzfc48b7a2016-02-15 13:22:35 -0500538};
539
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200540/* The core storm context for the Mstorm */
541struct mstorm_core_conn_st_ctx {
542 __le32 reserved[24];
543};
544
545/* The core storm context for the Ustorm */
546struct ustorm_core_conn_st_ctx {
547 __le32 reserved[4];
548};
549
550/* core connection context */
551struct core_conn_context {
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300552 struct ystorm_core_conn_st_ctx ystorm_st_context;
553 struct regpair ystorm_st_padding[2];
554 struct pstorm_core_conn_st_ctx pstorm_st_context;
555 struct regpair pstorm_st_padding[2];
556 struct xstorm_core_conn_st_ctx xstorm_st_context;
557 struct xstorm_core_conn_ag_ctx xstorm_ag_context;
558 struct tstorm_core_conn_ag_ctx tstorm_ag_context;
559 struct ustorm_core_conn_ag_ctx ustorm_ag_context;
560 struct mstorm_core_conn_st_ctx mstorm_st_context;
561 struct ustorm_core_conn_st_ctx ustorm_st_context;
562 struct regpair ustorm_st_padding[2];
563};
564
Yuval Mintz05fafbf2016-08-19 09:33:31 +0300565enum core_error_handle {
566 LL2_DROP_PACKET,
567 LL2_DO_NOTHING,
568 LL2_ASSERT,
569 MAX_CORE_ERROR_HANDLE
570};
571
572enum core_event_opcode {
573 CORE_EVENT_TX_QUEUE_START,
574 CORE_EVENT_TX_QUEUE_STOP,
575 CORE_EVENT_RX_QUEUE_START,
576 CORE_EVENT_RX_QUEUE_STOP,
Mintz, Yuvalbe086e72017-03-11 18:39:18 +0200577 CORE_EVENT_RX_QUEUE_FLUSH,
Yuval Mintz05fafbf2016-08-19 09:33:31 +0300578 MAX_CORE_EVENT_OPCODE
579};
580
581enum core_l4_pseudo_checksum_mode {
582 CORE_L4_PSEUDO_CSUM_CORRECT_LENGTH,
583 CORE_L4_PSEUDO_CSUM_ZERO_LENGTH,
584 MAX_CORE_L4_PSEUDO_CHECKSUM_MODE
585};
586
587struct core_ll2_port_stats {
588 struct regpair gsi_invalid_hdr;
589 struct regpair gsi_invalid_pkt_length;
590 struct regpair gsi_unsupported_pkt_typ;
591 struct regpair gsi_crcchksm_error;
592};
593
594struct core_ll2_pstorm_per_queue_stat {
595 struct regpair sent_ucast_bytes;
596 struct regpair sent_mcast_bytes;
597 struct regpair sent_bcast_bytes;
598 struct regpair sent_ucast_pkts;
599 struct regpair sent_mcast_pkts;
600 struct regpair sent_bcast_pkts;
601};
602
603struct core_ll2_rx_prod {
604 __le16 bd_prod;
605 __le16 cqe_prod;
606 __le32 reserved;
607};
608
609struct core_ll2_tstorm_per_queue_stat {
610 struct regpair packet_too_big_discard;
611 struct regpair no_buff_discard;
612};
613
614struct core_ll2_ustorm_per_queue_stat {
615 struct regpair rcv_ucast_bytes;
616 struct regpair rcv_mcast_bytes;
617 struct regpair rcv_bcast_bytes;
618 struct regpair rcv_ucast_pkts;
619 struct regpair rcv_mcast_pkts;
620 struct regpair rcv_bcast_pkts;
621};
622
623enum core_ramrod_cmd_id {
624 CORE_RAMROD_UNUSED,
625 CORE_RAMROD_RX_QUEUE_START,
626 CORE_RAMROD_TX_QUEUE_START,
627 CORE_RAMROD_RX_QUEUE_STOP,
628 CORE_RAMROD_TX_QUEUE_STOP,
Mintz, Yuvalbe086e72017-03-11 18:39:18 +0200629 CORE_RAMROD_RX_QUEUE_FLUSH,
Yuval Mintz05fafbf2016-08-19 09:33:31 +0300630 MAX_CORE_RAMROD_CMD_ID
631};
632
633enum core_roce_flavor_type {
634 CORE_ROCE,
635 CORE_RROCE,
636 MAX_CORE_ROCE_FLAVOR_TYPE
637};
638
639struct core_rx_action_on_error {
640 u8 error_type;
641#define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_MASK 0x3
642#define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_SHIFT 0
643#define CORE_RX_ACTION_ON_ERROR_NO_BUFF_MASK 0x3
644#define CORE_RX_ACTION_ON_ERROR_NO_BUFF_SHIFT 2
645#define CORE_RX_ACTION_ON_ERROR_RESERVED_MASK 0xF
646#define CORE_RX_ACTION_ON_ERROR_RESERVED_SHIFT 4
647};
648
649struct core_rx_bd {
650 struct regpair addr;
651 __le16 reserved[4];
652};
653
654struct core_rx_bd_with_buff_len {
655 struct regpair addr;
656 __le16 buff_length;
657 __le16 reserved[3];
658};
659
660union core_rx_bd_union {
661 struct core_rx_bd rx_bd;
662 struct core_rx_bd_with_buff_len rx_bd_with_len;
663};
664
665struct core_rx_cqe_opaque_data {
666 __le32 data[2];
667};
668
669enum core_rx_cqe_type {
670 CORE_RX_CQE_ILLIGAL_TYPE,
671 CORE_RX_CQE_TYPE_REGULAR,
672 CORE_RX_CQE_TYPE_GSI_OFFLOAD,
673 CORE_RX_CQE_TYPE_SLOW_PATH,
674 MAX_CORE_RX_CQE_TYPE
675};
676
677struct core_rx_fast_path_cqe {
678 u8 type;
679 u8 placement_offset;
680 struct parsing_and_err_flags parse_flags;
681 __le16 packet_length;
682 __le16 vlan;
683 struct core_rx_cqe_opaque_data opaque_data;
684 __le32 reserved[4];
685};
686
687struct core_rx_gsi_offload_cqe {
688 u8 type;
689 u8 data_length_error;
690 struct parsing_and_err_flags parse_flags;
691 __le16 data_length;
692 __le16 vlan;
693 __le32 src_mac_addrhi;
694 __le16 src_mac_addrlo;
695 u8 reserved1[2];
696 __le32 gid_dst[4];
697};
698
699struct core_rx_slow_path_cqe {
700 u8 type;
701 u8 ramrod_cmd_id;
702 __le16 echo;
Mintz, Yuvalbe086e72017-03-11 18:39:18 +0200703 struct core_rx_cqe_opaque_data opaque_data;
704 __le32 reserved1[5];
Yuval Mintz05fafbf2016-08-19 09:33:31 +0300705};
706
707union core_rx_cqe_union {
708 struct core_rx_fast_path_cqe rx_cqe_fp;
709 struct core_rx_gsi_offload_cqe rx_cqe_gsi;
710 struct core_rx_slow_path_cqe rx_cqe_sp;
711};
712
713struct core_rx_start_ramrod_data {
714 struct regpair bd_base;
715 struct regpair cqe_pbl_addr;
716 __le16 mtu;
717 __le16 sb_id;
718 u8 sb_index;
719 u8 complete_cqe_flg;
720 u8 complete_event_flg;
721 u8 drop_ttl0_flg;
722 __le16 num_of_pbl_pages;
723 u8 inner_vlan_removal_en;
724 u8 queue_id;
725 u8 main_func_queue;
726 u8 mf_si_bcast_accept_all;
727 u8 mf_si_mcast_accept_all;
728 struct core_rx_action_on_error action_on_error;
729 u8 gsi_offload_flag;
730 u8 reserved[7];
731};
732
733struct core_rx_stop_ramrod_data {
734 u8 complete_cqe_flg;
735 u8 complete_event_flg;
736 u8 queue_id;
737 u8 reserved1;
738 __le16 reserved2[2];
739};
740
Mintz, Yuvalbe086e72017-03-11 18:39:18 +0200741struct core_tx_bd_data {
742 __le16 as_bitfield;
743#define CORE_TX_BD_DATA_FORCE_VLAN_MODE_MASK 0x1
744#define CORE_TX_BD_DATA_FORCE_VLAN_MODE_SHIFT 0
745#define CORE_TX_BD_DATA_VLAN_INSERTION_MASK 0x1
746#define CORE_TX_BD_DATA_VLAN_INSERTION_SHIFT 1
747#define CORE_TX_BD_DATA_START_BD_MASK 0x1
748#define CORE_TX_BD_DATA_START_BD_SHIFT 2
749#define CORE_TX_BD_DATA_IP_CSUM_MASK 0x1
750#define CORE_TX_BD_DATA_IP_CSUM_SHIFT 3
751#define CORE_TX_BD_DATA_L4_CSUM_MASK 0x1
752#define CORE_TX_BD_DATA_L4_CSUM_SHIFT 4
753#define CORE_TX_BD_DATA_IPV6_EXT_MASK 0x1
754#define CORE_TX_BD_DATA_IPV6_EXT_SHIFT 5
755#define CORE_TX_BD_DATA_L4_PROTOCOL_MASK 0x1
756#define CORE_TX_BD_DATA_L4_PROTOCOL_SHIFT 6
757#define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_MASK 0x1
758#define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_SHIFT 7
759#define CORE_TX_BD_DATA_NBDS_MASK 0xF
760#define CORE_TX_BD_DATA_NBDS_SHIFT 8
761#define CORE_TX_BD_DATA_ROCE_FLAV_MASK 0x1
762#define CORE_TX_BD_DATA_ROCE_FLAV_SHIFT 12
763#define CORE_TX_BD_DATA_IP_LEN_MASK 0x1
764#define CORE_TX_BD_DATA_IP_LEN_SHIFT 13
765#define CORE_TX_BD_DATA_RESERVED0_MASK 0x3
766#define CORE_TX_BD_DATA_RESERVED0_SHIFT 14
Yuval Mintz05fafbf2016-08-19 09:33:31 +0300767};
768
769struct core_tx_bd {
770 struct regpair addr;
771 __le16 nbytes;
772 __le16 nw_vlan_or_lb_echo;
Mintz, Yuvalbe086e72017-03-11 18:39:18 +0200773 struct core_tx_bd_data bd_data;
Yuval Mintz05fafbf2016-08-19 09:33:31 +0300774 __le16 bitfield1;
775#define CORE_TX_BD_L4_HDR_OFFSET_W_MASK 0x3FFF
776#define CORE_TX_BD_L4_HDR_OFFSET_W_SHIFT 0
777#define CORE_TX_BD_TX_DST_MASK 0x1
778#define CORE_TX_BD_TX_DST_SHIFT 14
Mintz, Yuvalbe086e72017-03-11 18:39:18 +0200779#define CORE_TX_BD_RESERVED_MASK 0x1
780#define CORE_TX_BD_RESERVED_SHIFT 15
Yuval Mintz05fafbf2016-08-19 09:33:31 +0300781};
782
783enum core_tx_dest {
784 CORE_TX_DEST_NW,
785 CORE_TX_DEST_LB,
786 MAX_CORE_TX_DEST
787};
788
789struct core_tx_start_ramrod_data {
790 struct regpair pbl_base_addr;
791 __le16 mtu;
792 __le16 sb_id;
793 u8 sb_index;
794 u8 stats_en;
795 u8 stats_id;
796 u8 conn_type;
797 __le16 pbl_size;
798 __le16 qm_pq_id;
799 u8 gsi_offload_flag;
800 u8 resrved[3];
801};
802
803struct core_tx_stop_ramrod_data {
804 __le32 reserved0[2];
805};
806
Mintz, Yuvalbe086e72017-03-11 18:39:18 +0200807enum dcb_dhcp_update_flag {
808 DONT_UPDATE_DCB_DHCP,
809 UPDATE_DCB,
810 UPDATE_DSCP,
811 UPDATE_DCB_DSCP,
812 MAX_DCB_DHCP_UPDATE_FLAG
813};
814
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300815struct eth_mstorm_per_pf_stat {
816 struct regpair gre_discard_pkts;
817 struct regpair vxlan_discard_pkts;
818 struct regpair geneve_discard_pkts;
819 struct regpair lb_discard_pkts;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200820};
821
Manish Chopra9df2ed02015-10-26 11:02:33 +0200822struct eth_mstorm_per_queue_stat {
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300823 struct regpair ttl0_discard;
824 struct regpair packet_too_big_discard;
825 struct regpair no_buff_discard;
826 struct regpair not_active_discard;
827 struct regpair tpa_coalesced_pkts;
828 struct regpair tpa_coalesced_events;
829 struct regpair tpa_aborts_num;
830 struct regpair tpa_coalesced_bytes;
Manish Chopra9df2ed02015-10-26 11:02:33 +0200831};
832
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300833/* Ethernet TX Per PF */
834struct eth_pstorm_per_pf_stat {
835 struct regpair sent_lb_ucast_bytes;
836 struct regpair sent_lb_mcast_bytes;
837 struct regpair sent_lb_bcast_bytes;
838 struct regpair sent_lb_ucast_pkts;
839 struct regpair sent_lb_mcast_pkts;
840 struct regpair sent_lb_bcast_pkts;
841 struct regpair sent_gre_bytes;
842 struct regpair sent_vxlan_bytes;
843 struct regpair sent_geneve_bytes;
844 struct regpair sent_gre_pkts;
845 struct regpair sent_vxlan_pkts;
846 struct regpair sent_geneve_pkts;
847 struct regpair gre_drop_pkts;
848 struct regpair vxlan_drop_pkts;
849 struct regpair geneve_drop_pkts;
850};
851
852/* Ethernet TX Per Queue Stats */
Manish Chopra9df2ed02015-10-26 11:02:33 +0200853struct eth_pstorm_per_queue_stat {
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300854 struct regpair sent_ucast_bytes;
855 struct regpair sent_mcast_bytes;
856 struct regpair sent_bcast_bytes;
857 struct regpair sent_ucast_pkts;
858 struct regpair sent_mcast_pkts;
859 struct regpair sent_bcast_pkts;
860 struct regpair error_drop_pkts;
861};
862
863/* ETH Rx producers data */
864struct eth_rx_rate_limit {
865 __le16 mult;
866 __le16 cnst;
867 u8 add_sub_cnst;
868 u8 reserved0;
869 __le16 reserved1;
870};
871
872struct eth_ustorm_per_pf_stat {
873 struct regpair rcv_lb_ucast_bytes;
874 struct regpair rcv_lb_mcast_bytes;
875 struct regpair rcv_lb_bcast_bytes;
876 struct regpair rcv_lb_ucast_pkts;
877 struct regpair rcv_lb_mcast_pkts;
878 struct regpair rcv_lb_bcast_pkts;
879 struct regpair rcv_gre_bytes;
880 struct regpair rcv_vxlan_bytes;
881 struct regpair rcv_geneve_bytes;
882 struct regpair rcv_gre_pkts;
883 struct regpair rcv_vxlan_pkts;
884 struct regpair rcv_geneve_pkts;
Manish Chopra9df2ed02015-10-26 11:02:33 +0200885};
886
887struct eth_ustorm_per_queue_stat {
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300888 struct regpair rcv_ucast_bytes;
889 struct regpair rcv_mcast_bytes;
890 struct regpair rcv_bcast_bytes;
891 struct regpair rcv_ucast_pkts;
892 struct regpair rcv_mcast_pkts;
893 struct regpair rcv_bcast_pkts;
Manish Chopra9df2ed02015-10-26 11:02:33 +0200894};
895
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200896/* Event Ring Next Page Address */
897struct event_ring_next_addr {
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300898 struct regpair addr;
899 __le32 reserved[2];
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200900};
901
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300902/* Event Ring Element */
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200903union event_ring_element {
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300904 struct event_ring_entry entry;
905 struct event_ring_next_addr next_addr;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200906};
907
Mintz, Yuvalbe086e72017-03-11 18:39:18 +0200908enum fw_flow_ctrl_mode {
909 flow_ctrl_pause,
910 flow_ctrl_pfc,
911 MAX_FW_FLOW_CTRL_MODE
912};
913
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300914/* Major and Minor hsi Versions */
915struct hsi_fp_ver_struct {
916 u8 minor_ver_arr[2];
917 u8 major_ver_arr[2];
918};
919
920/* Mstorm non-triggering VF zone */
Yuval Mintz05fafbf2016-08-19 09:33:31 +0300921enum malicious_vf_error_id {
922 MALICIOUS_VF_NO_ERROR,
923 VF_PF_CHANNEL_NOT_READY,
924 VF_ZONE_MSG_NOT_VALID,
925 VF_ZONE_FUNC_NOT_ENABLED,
926 ETH_PACKET_TOO_SMALL,
927 ETH_ILLEGAL_VLAN_MODE,
928 ETH_MTU_VIOLATION,
929 ETH_ILLEGAL_INBAND_TAGS,
930 ETH_VLAN_INSERT_AND_INBAND_VLAN,
931 ETH_ILLEGAL_NBDS,
932 ETH_FIRST_BD_WO_SOP,
933 ETH_INSUFFICIENT_BDS,
934 ETH_ILLEGAL_LSO_HDR_NBDS,
935 ETH_ILLEGAL_LSO_MSS,
936 ETH_ZERO_SIZE_BD,
937 ETH_ILLEGAL_LSO_HDR_LEN,
938 ETH_INSUFFICIENT_PAYLOAD,
939 ETH_EDPM_OUT_OF_SYNC,
940 ETH_TUNN_IPV6_EXT_NBD_ERR,
941 ETH_CONTROL_PACKET_VIOLATION,
Mintz, Yuvalbe086e72017-03-11 18:39:18 +0200942 ETH_ANTI_SPOOFING_ERR,
Yuval Mintz05fafbf2016-08-19 09:33:31 +0300943 MAX_MALICIOUS_VF_ERROR_ID
944};
945
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300946struct mstorm_non_trigger_vf_zone {
947 struct eth_mstorm_per_queue_stat eth_queue_stat;
Yuval Mintz05fafbf2016-08-19 09:33:31 +0300948 struct eth_rx_prod_data eth_rx_queue_producers[ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD];
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300949};
950
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300951/* Mstorm VF zone */
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300952struct mstorm_vf_zone {
953 struct mstorm_non_trigger_vf_zone non_trigger;
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300954
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300955};
956
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300957/* personality per PF */
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200958enum personality_type {
Yuval Mintzfc48b7a2016-02-15 13:22:35 -0500959 BAD_PERSONALITY_TYP,
Yuval Mintzc5ac9312016-06-03 14:35:34 +0300960 PERSONALITY_ISCSI,
Arun Easi1e128c82017-02-15 06:28:22 -0800961 PERSONALITY_FCOE,
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300962 PERSONALITY_RDMA_AND_ETH,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200963 PERSONALITY_RESERVED3,
Yuval Mintzfc48b7a2016-02-15 13:22:35 -0500964 PERSONALITY_CORE,
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300965 PERSONALITY_ETH,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200966 PERSONALITY_RESERVED4,
967 MAX_PERSONALITY_TYPE
968};
969
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300970/* tunnel configuration */
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200971struct pf_start_tunnel_config {
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300972 u8 set_vxlan_udp_port_flg;
973 u8 set_geneve_udp_port_flg;
974 u8 tx_enable_vxlan;
975 u8 tx_enable_l2geneve;
976 u8 tx_enable_ipgeneve;
977 u8 tx_enable_l2gre;
978 u8 tx_enable_ipgre;
979 u8 tunnel_clss_vxlan;
980 u8 tunnel_clss_l2geneve;
981 u8 tunnel_clss_ipgeneve;
982 u8 tunnel_clss_l2gre;
983 u8 tunnel_clss_ipgre;
984 __le16 vxlan_udp_port;
985 __le16 geneve_udp_port;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200986};
987
988/* Ramrod data for PF start ramrod */
989struct pf_start_ramrod_data {
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300990 struct regpair event_ring_pbl_addr;
991 struct regpair consolid_q_pbl_addr;
992 struct pf_start_tunnel_config tunnel_config;
993 __le16 event_ring_sb_id;
994 u8 base_vf_id;
995 u8 num_vfs;
996 u8 event_ring_num_pages;
997 u8 event_ring_sb_index;
998 u8 path_id;
999 u8 warning_as_error;
1000 u8 dont_log_ramrods;
1001 u8 personality;
1002 __le16 log_type_mask;
1003 u8 mf_mode;
1004 u8 integ_phase;
1005 u8 allow_npar_tx_switching;
1006 u8 inner_to_outer_pri_map[8];
1007 u8 pri_map_valid;
1008 __le32 outer_tag;
1009 struct hsi_fp_ver_struct hsi_fp_ver;
1010
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001011};
1012
Sudarsana Reddy Kalluru39651ab2016-05-17 06:44:26 -04001013struct protocol_dcb_data {
1014 u8 dcb_enable_flag;
Yuval Mintz05fafbf2016-08-19 09:33:31 +03001015 u8 reserved_a;
Sudarsana Reddy Kalluru39651ab2016-05-17 06:44:26 -04001016 u8 dcb_priority;
1017 u8 dcb_tc;
Yuval Mintz05fafbf2016-08-19 09:33:31 +03001018 u8 reserved_b;
1019 u8 reserved0;
Sudarsana Reddy Kalluru39651ab2016-05-17 06:44:26 -04001020};
1021
Manish Chopra464f6642016-04-14 01:38:29 -04001022struct pf_update_tunnel_config {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001023 u8 update_rx_pf_clss;
Yuval Mintz05fafbf2016-08-19 09:33:31 +03001024 u8 update_rx_def_ucast_clss;
1025 u8 update_rx_def_non_ucast_clss;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001026 u8 update_tx_pf_clss;
1027 u8 set_vxlan_udp_port_flg;
1028 u8 set_geneve_udp_port_flg;
1029 u8 tx_enable_vxlan;
1030 u8 tx_enable_l2geneve;
1031 u8 tx_enable_ipgeneve;
1032 u8 tx_enable_l2gre;
1033 u8 tx_enable_ipgre;
1034 u8 tunnel_clss_vxlan;
1035 u8 tunnel_clss_l2geneve;
1036 u8 tunnel_clss_ipgeneve;
1037 u8 tunnel_clss_l2gre;
1038 u8 tunnel_clss_ipgre;
1039 __le16 vxlan_udp_port;
1040 __le16 geneve_udp_port;
Yuval Mintz05fafbf2016-08-19 09:33:31 +03001041 __le16 reserved[2];
Manish Chopra464f6642016-04-14 01:38:29 -04001042};
1043
1044struct pf_update_ramrod_data {
Sudarsana Reddy Kalluru39651ab2016-05-17 06:44:26 -04001045 u8 pf_id;
1046 u8 update_eth_dcb_data_flag;
1047 u8 update_fcoe_dcb_data_flag;
1048 u8 update_iscsi_dcb_data_flag;
1049 u8 update_roce_dcb_data_flag;
Yuval Mintz05fafbf2016-08-19 09:33:31 +03001050 u8 update_rroce_dcb_data_flag;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001051 u8 update_iwarp_dcb_data_flag;
Sudarsana Reddy Kalluru39651ab2016-05-17 06:44:26 -04001052 u8 update_mf_vlan_flag;
Sudarsana Reddy Kalluru39651ab2016-05-17 06:44:26 -04001053 struct protocol_dcb_data eth_dcb_data;
1054 struct protocol_dcb_data fcoe_dcb_data;
1055 struct protocol_dcb_data iscsi_dcb_data;
1056 struct protocol_dcb_data roce_dcb_data;
Yuval Mintz05fafbf2016-08-19 09:33:31 +03001057 struct protocol_dcb_data rroce_dcb_data;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001058 struct protocol_dcb_data iwarp_dcb_data;
1059 __le16 mf_vlan;
Yuval Mintz05fafbf2016-08-19 09:33:31 +03001060 __le16 reserved;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001061 struct pf_update_tunnel_config tunnel_config;
1062};
1063
1064/* Ports mode */
1065enum ports_mode {
1066 ENGX2_PORTX1,
1067 ENGX2_PORTX2,
1068 ENGX1_PORTX1,
1069 ENGX1_PORTX2,
1070 ENGX1_PORTX4,
1071 MAX_PORTS_MODE
1072};
1073
1074/* use to index in hsi_fp_[major|minor]_ver_arr per protocol */
1075enum protocol_version_array_key {
1076 ETH_VER_KEY = 0,
1077 ROCE_VER_KEY,
1078 MAX_PROTOCOL_VERSION_ARRAY_KEY
1079};
1080
Yuval Mintz05fafbf2016-08-19 09:33:31 +03001081struct rdma_sent_stats {
1082 struct regpair sent_bytes;
1083 struct regpair sent_pkts;
1084};
1085
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001086struct pstorm_non_trigger_vf_zone {
1087 struct eth_pstorm_per_queue_stat eth_queue_stat;
Yuval Mintz05fafbf2016-08-19 09:33:31 +03001088 struct rdma_sent_stats rdma_stats;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001089};
1090
1091/* Pstorm VF zone */
1092struct pstorm_vf_zone {
1093 struct pstorm_non_trigger_vf_zone non_trigger;
1094 struct regpair reserved[7];
1095};
1096
1097/* Ramrod Header of SPQE */
1098struct ramrod_header {
1099 __le32 cid;
1100 u8 cmd_id;
1101 u8 protocol_id;
1102 __le16 echo;
1103};
1104
Yuval Mintz05fafbf2016-08-19 09:33:31 +03001105struct rdma_rcv_stats {
1106 struct regpair rcv_bytes;
1107 struct regpair rcv_pkts;
1108};
1109
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001110struct slow_path_element {
1111 struct ramrod_header hdr;
1112 struct regpair data_ptr;
1113};
1114
1115/* Tstorm non-triggering VF zone */
1116struct tstorm_non_trigger_vf_zone {
Yuval Mintz05fafbf2016-08-19 09:33:31 +03001117 struct rdma_rcv_stats rdma_stats;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001118};
1119
1120struct tstorm_per_port_stat {
1121 struct regpair trunc_error_discard;
1122 struct regpair mac_error_discard;
1123 struct regpair mftag_filter_discard;
1124 struct regpair eth_mac_filter_discard;
Yuval Mintz05fafbf2016-08-19 09:33:31 +03001125 struct regpair ll2_mac_filter_discard;
1126 struct regpair ll2_conn_disabled_discard;
1127 struct regpair iscsi_irregular_pkt;
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02001128 struct regpair fcoe_irregular_pkt;
Yuval Mintz05fafbf2016-08-19 09:33:31 +03001129 struct regpair roce_irregular_pkt;
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02001130 struct regpair reserved;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001131 struct regpair eth_irregular_pkt;
Yuval Mintz05fafbf2016-08-19 09:33:31 +03001132 struct regpair reserved1;
1133 struct regpair preroce_irregular_pkt;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001134 struct regpair eth_gre_tunn_filter_discard;
1135 struct regpair eth_vxlan_tunn_filter_discard;
1136 struct regpair eth_geneve_tunn_filter_discard;
1137};
1138
1139/* Tstorm VF zone */
1140struct tstorm_vf_zone {
1141 struct tstorm_non_trigger_vf_zone non_trigger;
Manish Chopra464f6642016-04-14 01:38:29 -04001142};
1143
1144/* Tunnel classification scheme */
1145enum tunnel_clss {
1146 TUNNEL_CLSS_MAC_VLAN = 0,
1147 TUNNEL_CLSS_MAC_VNI,
1148 TUNNEL_CLSS_INNER_MAC_VLAN,
1149 TUNNEL_CLSS_INNER_MAC_VNI,
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001150 TUNNEL_CLSS_MAC_VLAN_DUAL_STAGE,
Manish Chopra464f6642016-04-14 01:38:29 -04001151 MAX_TUNNEL_CLSS
1152};
1153
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001154/* Ustorm non-triggering VF zone */
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001155struct ustorm_non_trigger_vf_zone {
1156 struct eth_ustorm_per_queue_stat eth_queue_stat;
1157 struct regpair vf_pf_msg_addr;
1158};
1159
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001160/* Ustorm triggering VF zone */
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001161struct ustorm_trigger_vf_zone {
1162 u8 vf_pf_msg_valid;
1163 u8 reserved[7];
1164};
1165
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001166/* Ustorm VF zone */
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001167struct ustorm_vf_zone {
1168 struct ustorm_non_trigger_vf_zone non_trigger;
1169 struct ustorm_trigger_vf_zone trigger;
1170};
1171
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001172/* VF-PF channel data */
1173struct vf_pf_channel_data {
1174 __le32 ready;
1175 u8 valid;
1176 u8 reserved0;
1177 __le16 reserved1;
1178};
1179
1180/* Ramrod data for VF start ramrod */
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001181struct vf_start_ramrod_data {
1182 u8 vf_id;
1183 u8 enable_flr_ack;
1184 __le16 opaque_fid;
1185 u8 personality;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001186 u8 reserved[7];
1187 struct hsi_fp_ver_struct hsi_fp_ver;
1188
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001189};
1190
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001191/* Ramrod data for VF start ramrod */
Yuval Mintz0b55e272016-05-11 16:36:15 +03001192struct vf_stop_ramrod_data {
1193 u8 vf_id;
1194 u8 reserved0;
1195 __le16 reserved1;
1196 __le32 reserved2;
1197};
1198
Yuval Mintz05fafbf2016-08-19 09:33:31 +03001199enum vf_zone_size_mode {
1200 VF_ZONE_SIZE_MODE_DEFAULT,
1201 VF_ZONE_SIZE_MODE_DOUBLE,
1202 VF_ZONE_SIZE_MODE_QUAD,
1203 MAX_VF_ZONE_SIZE_MODE
1204};
1205
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001206struct atten_status_block {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001207 __le32 atten_bits;
1208 __le32 atten_ack;
1209 __le16 reserved0;
1210 __le16 sb_index;
1211 __le32 reserved1;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001212};
1213
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001214enum command_type_bit {
1215 IGU_COMMAND_TYPE_NOP = 0,
1216 IGU_COMMAND_TYPE_SET = 1,
1217 MAX_COMMAND_TYPE_BIT
1218};
1219
1220/* DMAE command */
1221struct dmae_cmd {
1222 __le32 opcode;
1223#define DMAE_CMD_SRC_MASK 0x1
1224#define DMAE_CMD_SRC_SHIFT 0
1225#define DMAE_CMD_DST_MASK 0x3
1226#define DMAE_CMD_DST_SHIFT 1
1227#define DMAE_CMD_C_DST_MASK 0x1
1228#define DMAE_CMD_C_DST_SHIFT 3
1229#define DMAE_CMD_CRC_RESET_MASK 0x1
1230#define DMAE_CMD_CRC_RESET_SHIFT 4
1231#define DMAE_CMD_SRC_ADDR_RESET_MASK 0x1
1232#define DMAE_CMD_SRC_ADDR_RESET_SHIFT 5
1233#define DMAE_CMD_DST_ADDR_RESET_MASK 0x1
1234#define DMAE_CMD_DST_ADDR_RESET_SHIFT 6
1235#define DMAE_CMD_COMP_FUNC_MASK 0x1
1236#define DMAE_CMD_COMP_FUNC_SHIFT 7
1237#define DMAE_CMD_COMP_WORD_EN_MASK 0x1
1238#define DMAE_CMD_COMP_WORD_EN_SHIFT 8
1239#define DMAE_CMD_COMP_CRC_EN_MASK 0x1
1240#define DMAE_CMD_COMP_CRC_EN_SHIFT 9
1241#define DMAE_CMD_COMP_CRC_OFFSET_MASK 0x7
1242#define DMAE_CMD_COMP_CRC_OFFSET_SHIFT 10
1243#define DMAE_CMD_RESERVED1_MASK 0x1
1244#define DMAE_CMD_RESERVED1_SHIFT 13
1245#define DMAE_CMD_ENDIANITY_MODE_MASK 0x3
1246#define DMAE_CMD_ENDIANITY_MODE_SHIFT 14
1247#define DMAE_CMD_ERR_HANDLING_MASK 0x3
1248#define DMAE_CMD_ERR_HANDLING_SHIFT 16
1249#define DMAE_CMD_PORT_ID_MASK 0x3
1250#define DMAE_CMD_PORT_ID_SHIFT 18
1251#define DMAE_CMD_SRC_PF_ID_MASK 0xF
1252#define DMAE_CMD_SRC_PF_ID_SHIFT 20
1253#define DMAE_CMD_DST_PF_ID_MASK 0xF
1254#define DMAE_CMD_DST_PF_ID_SHIFT 24
1255#define DMAE_CMD_SRC_VF_ID_VALID_MASK 0x1
1256#define DMAE_CMD_SRC_VF_ID_VALID_SHIFT 28
1257#define DMAE_CMD_DST_VF_ID_VALID_MASK 0x1
1258#define DMAE_CMD_DST_VF_ID_VALID_SHIFT 29
1259#define DMAE_CMD_RESERVED2_MASK 0x3
1260#define DMAE_CMD_RESERVED2_SHIFT 30
1261 __le32 src_addr_lo;
1262 __le32 src_addr_hi;
1263 __le32 dst_addr_lo;
1264 __le32 dst_addr_hi;
1265 __le16 length_dw;
1266 __le16 opcode_b;
1267#define DMAE_CMD_SRC_VF_ID_MASK 0xFF
1268#define DMAE_CMD_SRC_VF_ID_SHIFT 0
1269#define DMAE_CMD_DST_VF_ID_MASK 0xFF
1270#define DMAE_CMD_DST_VF_ID_SHIFT 8
1271 __le32 comp_addr_lo;
1272 __le32 comp_addr_hi;
1273 __le32 comp_val;
1274 __le32 crc32;
1275 __le32 crc_32_c;
1276 __le16 crc16;
1277 __le16 crc16_c;
1278 __le16 crc10;
1279 __le16 reserved;
1280 __le16 xsum16;
1281 __le16 xsum8;
1282};
1283
1284enum dmae_cmd_comp_crc_en_enum {
1285 dmae_cmd_comp_crc_disabled,
1286 dmae_cmd_comp_crc_enabled,
1287 MAX_DMAE_CMD_COMP_CRC_EN_ENUM
1288};
1289
1290enum dmae_cmd_comp_func_enum {
1291 dmae_cmd_comp_func_to_src,
1292 dmae_cmd_comp_func_to_dst,
1293 MAX_DMAE_CMD_COMP_FUNC_ENUM
1294};
1295
1296enum dmae_cmd_comp_word_en_enum {
1297 dmae_cmd_comp_word_disabled,
1298 dmae_cmd_comp_word_enabled,
1299 MAX_DMAE_CMD_COMP_WORD_EN_ENUM
1300};
1301
1302enum dmae_cmd_c_dst_enum {
1303 dmae_cmd_c_dst_pcie,
1304 dmae_cmd_c_dst_grc,
1305 MAX_DMAE_CMD_C_DST_ENUM
1306};
1307
1308enum dmae_cmd_dst_enum {
1309 dmae_cmd_dst_none_0,
1310 dmae_cmd_dst_pcie,
1311 dmae_cmd_dst_grc,
1312 dmae_cmd_dst_none_3,
1313 MAX_DMAE_CMD_DST_ENUM
1314};
1315
1316enum dmae_cmd_error_handling_enum {
1317 dmae_cmd_error_handling_send_regular_comp,
1318 dmae_cmd_error_handling_send_comp_with_err,
1319 dmae_cmd_error_handling_dont_send_comp,
1320 MAX_DMAE_CMD_ERROR_HANDLING_ENUM
1321};
1322
1323enum dmae_cmd_src_enum {
1324 dmae_cmd_src_pcie,
1325 dmae_cmd_src_grc,
1326 MAX_DMAE_CMD_SRC_ENUM
1327};
1328
1329/* IGU cleanup command */
1330struct igu_cleanup {
1331 __le32 sb_id_and_flags;
1332#define IGU_CLEANUP_RESERVED0_MASK 0x7FFFFFF
1333#define IGU_CLEANUP_RESERVED0_SHIFT 0
1334#define IGU_CLEANUP_CLEANUP_SET_MASK 0x1
1335#define IGU_CLEANUP_CLEANUP_SET_SHIFT 27
1336#define IGU_CLEANUP_CLEANUP_TYPE_MASK 0x7
1337#define IGU_CLEANUP_CLEANUP_TYPE_SHIFT 28
1338#define IGU_CLEANUP_COMMAND_TYPE_MASK 0x1
1339#define IGU_CLEANUP_COMMAND_TYPE_SHIFT 31
1340 __le32 reserved1;
1341};
1342
1343/* IGU firmware driver command */
1344union igu_command {
1345 struct igu_prod_cons_update prod_cons_update;
1346 struct igu_cleanup cleanup;
1347};
1348
1349/* IGU firmware driver command */
1350struct igu_command_reg_ctrl {
1351 __le16 opaque_fid;
1352 __le16 igu_command_reg_ctrl_fields;
1353#define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_MASK 0xFFF
1354#define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_SHIFT 0
1355#define IGU_COMMAND_REG_CTRL_RESERVED_MASK 0x7
1356#define IGU_COMMAND_REG_CTRL_RESERVED_SHIFT 12
1357#define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_MASK 0x1
1358#define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_SHIFT 15
1359};
1360
1361/* IGU mapping line structure */
1362struct igu_mapping_line {
1363 __le32 igu_mapping_line_fields;
1364#define IGU_MAPPING_LINE_VALID_MASK 0x1
1365#define IGU_MAPPING_LINE_VALID_SHIFT 0
1366#define IGU_MAPPING_LINE_VECTOR_NUMBER_MASK 0xFF
1367#define IGU_MAPPING_LINE_VECTOR_NUMBER_SHIFT 1
1368#define IGU_MAPPING_LINE_FUNCTION_NUMBER_MASK 0xFF
1369#define IGU_MAPPING_LINE_FUNCTION_NUMBER_SHIFT 9
1370#define IGU_MAPPING_LINE_PF_VALID_MASK 0x1
1371#define IGU_MAPPING_LINE_PF_VALID_SHIFT 17
1372#define IGU_MAPPING_LINE_IPS_GROUP_MASK 0x3F
1373#define IGU_MAPPING_LINE_IPS_GROUP_SHIFT 18
1374#define IGU_MAPPING_LINE_RESERVED_MASK 0xFF
1375#define IGU_MAPPING_LINE_RESERVED_SHIFT 24
1376};
1377
1378/* IGU MSIX line structure */
1379struct igu_msix_vector {
1380 struct regpair address;
1381 __le32 data;
1382 __le32 msix_vector_fields;
1383#define IGU_MSIX_VECTOR_MASK_BIT_MASK 0x1
1384#define IGU_MSIX_VECTOR_MASK_BIT_SHIFT 0
1385#define IGU_MSIX_VECTOR_RESERVED0_MASK 0x7FFF
1386#define IGU_MSIX_VECTOR_RESERVED0_SHIFT 1
1387#define IGU_MSIX_VECTOR_STEERING_TAG_MASK 0xFF
1388#define IGU_MSIX_VECTOR_STEERING_TAG_SHIFT 16
1389#define IGU_MSIX_VECTOR_RESERVED1_MASK 0xFF
1390#define IGU_MSIX_VECTOR_RESERVED1_SHIFT 24
1391};
1392
1393struct mstorm_core_conn_ag_ctx {
1394 u8 byte0;
1395 u8 byte1;
1396 u8 flags0;
1397#define MSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
1398#define MSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
1399#define MSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
1400#define MSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
1401#define MSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
1402#define MSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
1403#define MSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
1404#define MSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
1405#define MSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
1406#define MSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
1407 u8 flags1;
1408#define MSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
1409#define MSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
1410#define MSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
1411#define MSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
1412#define MSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
1413#define MSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
1414#define MSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
1415#define MSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3
1416#define MSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
1417#define MSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4
1418#define MSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
1419#define MSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5
1420#define MSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
1421#define MSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6
1422#define MSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
1423#define MSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7
1424 __le16 word0;
1425 __le16 word1;
1426 __le32 reg0;
1427 __le32 reg1;
1428};
1429
1430/* per encapsulation type enabling flags */
1431struct prs_reg_encapsulation_type_en {
1432 u8 flags;
1433#define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_MASK 0x1
1434#define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT 0
1435#define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_MASK 0x1
1436#define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT 1
1437#define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_MASK 0x1
1438#define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT 2
1439#define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_MASK 0x1
1440#define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_SHIFT 3
1441#define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_MASK 0x1
1442#define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_SHIFT 4
1443#define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_MASK 0x1
1444#define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT 5
1445#define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_MASK 0x3
1446#define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_SHIFT 6
1447};
1448
1449enum pxp_tph_st_hint {
1450 TPH_ST_HINT_BIDIR,
1451 TPH_ST_HINT_REQUESTER,
1452 TPH_ST_HINT_TARGET,
1453 TPH_ST_HINT_TARGET_PRIO,
1454 MAX_PXP_TPH_ST_HINT
1455};
1456
1457/* QM hardware structure of enable bypass credit mask */
1458struct qm_rf_bypass_mask {
1459 u8 flags;
1460#define QM_RF_BYPASS_MASK_LINEVOQ_MASK 0x1
1461#define QM_RF_BYPASS_MASK_LINEVOQ_SHIFT 0
1462#define QM_RF_BYPASS_MASK_RESERVED0_MASK 0x1
1463#define QM_RF_BYPASS_MASK_RESERVED0_SHIFT 1
1464#define QM_RF_BYPASS_MASK_PFWFQ_MASK 0x1
1465#define QM_RF_BYPASS_MASK_PFWFQ_SHIFT 2
1466#define QM_RF_BYPASS_MASK_VPWFQ_MASK 0x1
1467#define QM_RF_BYPASS_MASK_VPWFQ_SHIFT 3
1468#define QM_RF_BYPASS_MASK_PFRL_MASK 0x1
1469#define QM_RF_BYPASS_MASK_PFRL_SHIFT 4
1470#define QM_RF_BYPASS_MASK_VPQCNRL_MASK 0x1
1471#define QM_RF_BYPASS_MASK_VPQCNRL_SHIFT 5
1472#define QM_RF_BYPASS_MASK_FWPAUSE_MASK 0x1
1473#define QM_RF_BYPASS_MASK_FWPAUSE_SHIFT 6
1474#define QM_RF_BYPASS_MASK_RESERVED1_MASK 0x1
1475#define QM_RF_BYPASS_MASK_RESERVED1_SHIFT 7
1476};
1477
1478/* QM hardware structure of opportunistic credit mask */
1479struct qm_rf_opportunistic_mask {
1480 __le16 flags;
1481#define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_MASK 0x1
1482#define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_SHIFT 0
1483#define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_MASK 0x1
1484#define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_SHIFT 1
1485#define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_MASK 0x1
1486#define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_SHIFT 2
1487#define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_MASK 0x1
1488#define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_SHIFT 3
1489#define QM_RF_OPPORTUNISTIC_MASK_PFRL_MASK 0x1
1490#define QM_RF_OPPORTUNISTIC_MASK_PFRL_SHIFT 4
1491#define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_MASK 0x1
1492#define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_SHIFT 5
1493#define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_MASK 0x1
1494#define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_SHIFT 6
1495#define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_MASK 0x1
1496#define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_SHIFT 7
1497#define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_MASK 0x1
1498#define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_SHIFT 8
1499#define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_MASK 0x7F
1500#define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_SHIFT 9
1501};
1502
1503/* QM hardware structure of QM map memory */
1504struct qm_rf_pq_map {
1505 __le32 reg;
1506#define QM_RF_PQ_MAP_PQ_VALID_MASK 0x1
1507#define QM_RF_PQ_MAP_PQ_VALID_SHIFT 0
1508#define QM_RF_PQ_MAP_RL_ID_MASK 0xFF
1509#define QM_RF_PQ_MAP_RL_ID_SHIFT 1
1510#define QM_RF_PQ_MAP_VP_PQ_ID_MASK 0x1FF
1511#define QM_RF_PQ_MAP_VP_PQ_ID_SHIFT 9
1512#define QM_RF_PQ_MAP_VOQ_MASK 0x1F
1513#define QM_RF_PQ_MAP_VOQ_SHIFT 18
1514#define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_MASK 0x3
1515#define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_SHIFT 23
1516#define QM_RF_PQ_MAP_RL_VALID_MASK 0x1
1517#define QM_RF_PQ_MAP_RL_VALID_SHIFT 25
1518#define QM_RF_PQ_MAP_RESERVED_MASK 0x3F
1519#define QM_RF_PQ_MAP_RESERVED_SHIFT 26
1520};
1521
1522/* Completion params for aggregated interrupt completion */
1523struct sdm_agg_int_comp_params {
1524 __le16 params;
1525#define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_MASK 0x3F
1526#define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT 0
1527#define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_MASK 0x1
1528#define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT 6
1529#define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_MASK 0x1FF
1530#define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT 7
1531};
1532
1533/* SDM operation gen command (generate aggregative interrupt) */
1534struct sdm_op_gen {
1535 __le32 command;
1536#define SDM_OP_GEN_COMP_PARAM_MASK 0xFFFF
1537#define SDM_OP_GEN_COMP_PARAM_SHIFT 0
1538#define SDM_OP_GEN_COMP_TYPE_MASK 0xF
1539#define SDM_OP_GEN_COMP_TYPE_SHIFT 16
1540#define SDM_OP_GEN_RESERVED_MASK 0xFFF
1541#define SDM_OP_GEN_RESERVED_SHIFT 20
1542};
1543
1544struct ystorm_core_conn_ag_ctx {
1545 u8 byte0;
1546 u8 byte1;
1547 u8 flags0;
1548#define YSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
1549#define YSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
1550#define YSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
1551#define YSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
1552#define YSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
1553#define YSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
1554#define YSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
1555#define YSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
1556#define YSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
1557#define YSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
1558 u8 flags1;
1559#define YSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
1560#define YSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
1561#define YSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
1562#define YSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
1563#define YSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
1564#define YSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
1565#define YSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
1566#define YSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3
1567#define YSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
1568#define YSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4
1569#define YSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
1570#define YSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5
1571#define YSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
1572#define YSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6
1573#define YSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
1574#define YSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7
1575 u8 byte2;
1576 u8 byte3;
1577 __le16 word0;
1578 __le32 reg0;
1579 __le32 reg1;
1580 __le16 word1;
1581 __le16 word2;
1582 __le16 word3;
1583 __le16 word4;
1584 __le32 reg2;
1585 __le32 reg3;
1586};
1587
1588/****************************************/
1589/* Debug Tools HSI constants and macros */
1590/****************************************/
1591
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001592enum block_addr {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001593 GRCBASE_GRC = 0x50000,
1594 GRCBASE_MISCS = 0x9000,
1595 GRCBASE_MISC = 0x8000,
1596 GRCBASE_DBU = 0xa000,
1597 GRCBASE_PGLUE_B = 0x2a8000,
1598 GRCBASE_CNIG = 0x218000,
1599 GRCBASE_CPMU = 0x30000,
1600 GRCBASE_NCSI = 0x40000,
1601 GRCBASE_OPTE = 0x53000,
1602 GRCBASE_BMB = 0x540000,
1603 GRCBASE_PCIE = 0x54000,
1604 GRCBASE_MCP = 0xe00000,
1605 GRCBASE_MCP2 = 0x52000,
1606 GRCBASE_PSWHST = 0x2a0000,
1607 GRCBASE_PSWHST2 = 0x29e000,
1608 GRCBASE_PSWRD = 0x29c000,
1609 GRCBASE_PSWRD2 = 0x29d000,
1610 GRCBASE_PSWWR = 0x29a000,
1611 GRCBASE_PSWWR2 = 0x29b000,
1612 GRCBASE_PSWRQ = 0x280000,
1613 GRCBASE_PSWRQ2 = 0x240000,
1614 GRCBASE_PGLCS = 0x0,
1615 GRCBASE_DMAE = 0xc000,
1616 GRCBASE_PTU = 0x560000,
1617 GRCBASE_TCM = 0x1180000,
1618 GRCBASE_MCM = 0x1200000,
1619 GRCBASE_UCM = 0x1280000,
1620 GRCBASE_XCM = 0x1000000,
1621 GRCBASE_YCM = 0x1080000,
1622 GRCBASE_PCM = 0x1100000,
1623 GRCBASE_QM = 0x2f0000,
1624 GRCBASE_TM = 0x2c0000,
1625 GRCBASE_DORQ = 0x100000,
1626 GRCBASE_BRB = 0x340000,
1627 GRCBASE_SRC = 0x238000,
1628 GRCBASE_PRS = 0x1f0000,
1629 GRCBASE_TSDM = 0xfb0000,
1630 GRCBASE_MSDM = 0xfc0000,
1631 GRCBASE_USDM = 0xfd0000,
1632 GRCBASE_XSDM = 0xf80000,
1633 GRCBASE_YSDM = 0xf90000,
1634 GRCBASE_PSDM = 0xfa0000,
1635 GRCBASE_TSEM = 0x1700000,
1636 GRCBASE_MSEM = 0x1800000,
1637 GRCBASE_USEM = 0x1900000,
1638 GRCBASE_XSEM = 0x1400000,
1639 GRCBASE_YSEM = 0x1500000,
1640 GRCBASE_PSEM = 0x1600000,
1641 GRCBASE_RSS = 0x238800,
1642 GRCBASE_TMLD = 0x4d0000,
1643 GRCBASE_MULD = 0x4e0000,
1644 GRCBASE_YULD = 0x4c8000,
1645 GRCBASE_XYLD = 0x4c0000,
1646 GRCBASE_PRM = 0x230000,
1647 GRCBASE_PBF_PB1 = 0xda0000,
1648 GRCBASE_PBF_PB2 = 0xda4000,
1649 GRCBASE_RPB = 0x23c000,
1650 GRCBASE_BTB = 0xdb0000,
1651 GRCBASE_PBF = 0xd80000,
1652 GRCBASE_RDIF = 0x300000,
1653 GRCBASE_TDIF = 0x310000,
1654 GRCBASE_CDU = 0x580000,
1655 GRCBASE_CCFC = 0x2e0000,
1656 GRCBASE_TCFC = 0x2d0000,
1657 GRCBASE_IGU = 0x180000,
1658 GRCBASE_CAU = 0x1c0000,
1659 GRCBASE_UMAC = 0x51000,
1660 GRCBASE_XMAC = 0x210000,
1661 GRCBASE_DBG = 0x10000,
1662 GRCBASE_NIG = 0x500000,
1663 GRCBASE_WOL = 0x600000,
1664 GRCBASE_BMBN = 0x610000,
1665 GRCBASE_IPC = 0x20000,
1666 GRCBASE_NWM = 0x800000,
1667 GRCBASE_NWS = 0x700000,
1668 GRCBASE_MS = 0x6a0000,
1669 GRCBASE_PHY_PCIE = 0x620000,
1670 GRCBASE_LED = 0x6b8000,
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02001671 GRCBASE_AVS_WRAP = 0x6b0000,
1672 GRCBASE_RGFS = 0x19d0000,
1673 GRCBASE_TGFS = 0x19e0000,
1674 GRCBASE_PTLD = 0x19f0000,
1675 GRCBASE_YPLD = 0x1a10000,
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001676 GRCBASE_MISC_AEU = 0x8000,
1677 GRCBASE_BAR0_MAP = 0x1c00000,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001678 MAX_BLOCK_ADDR
1679};
1680
1681enum block_id {
1682 BLOCK_GRC,
1683 BLOCK_MISCS,
1684 BLOCK_MISC,
1685 BLOCK_DBU,
1686 BLOCK_PGLUE_B,
1687 BLOCK_CNIG,
1688 BLOCK_CPMU,
1689 BLOCK_NCSI,
1690 BLOCK_OPTE,
1691 BLOCK_BMB,
1692 BLOCK_PCIE,
1693 BLOCK_MCP,
1694 BLOCK_MCP2,
1695 BLOCK_PSWHST,
1696 BLOCK_PSWHST2,
1697 BLOCK_PSWRD,
1698 BLOCK_PSWRD2,
1699 BLOCK_PSWWR,
1700 BLOCK_PSWWR2,
1701 BLOCK_PSWRQ,
1702 BLOCK_PSWRQ2,
1703 BLOCK_PGLCS,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001704 BLOCK_DMAE,
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001705 BLOCK_PTU,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001706 BLOCK_TCM,
1707 BLOCK_MCM,
1708 BLOCK_UCM,
1709 BLOCK_XCM,
1710 BLOCK_YCM,
1711 BLOCK_PCM,
1712 BLOCK_QM,
1713 BLOCK_TM,
1714 BLOCK_DORQ,
1715 BLOCK_BRB,
1716 BLOCK_SRC,
1717 BLOCK_PRS,
1718 BLOCK_TSDM,
1719 BLOCK_MSDM,
1720 BLOCK_USDM,
1721 BLOCK_XSDM,
1722 BLOCK_YSDM,
1723 BLOCK_PSDM,
1724 BLOCK_TSEM,
1725 BLOCK_MSEM,
1726 BLOCK_USEM,
1727 BLOCK_XSEM,
1728 BLOCK_YSEM,
1729 BLOCK_PSEM,
1730 BLOCK_RSS,
1731 BLOCK_TMLD,
1732 BLOCK_MULD,
1733 BLOCK_YULD,
1734 BLOCK_XYLD,
1735 BLOCK_PRM,
1736 BLOCK_PBF_PB1,
1737 BLOCK_PBF_PB2,
1738 BLOCK_RPB,
1739 BLOCK_BTB,
1740 BLOCK_PBF,
1741 BLOCK_RDIF,
1742 BLOCK_TDIF,
1743 BLOCK_CDU,
1744 BLOCK_CCFC,
1745 BLOCK_TCFC,
1746 BLOCK_IGU,
1747 BLOCK_CAU,
1748 BLOCK_UMAC,
1749 BLOCK_XMAC,
1750 BLOCK_DBG,
1751 BLOCK_NIG,
1752 BLOCK_WOL,
1753 BLOCK_BMBN,
1754 BLOCK_IPC,
1755 BLOCK_NWM,
1756 BLOCK_NWS,
1757 BLOCK_MS,
1758 BLOCK_PHY_PCIE,
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001759 BLOCK_LED,
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02001760 BLOCK_AVS_WRAP,
1761 BLOCK_RGFS,
1762 BLOCK_TGFS,
1763 BLOCK_PTLD,
1764 BLOCK_YPLD,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001765 BLOCK_MISC_AEU,
1766 BLOCK_BAR0_MAP,
1767 MAX_BLOCK_ID
1768};
1769
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001770/* binary debug buffer types */
1771enum bin_dbg_buffer_type {
1772 BIN_BUF_DBG_MODE_TREE,
1773 BIN_BUF_DBG_DUMP_REG,
1774 BIN_BUF_DBG_DUMP_MEM,
1775 BIN_BUF_DBG_IDLE_CHK_REGS,
1776 BIN_BUF_DBG_IDLE_CHK_IMMS,
1777 BIN_BUF_DBG_IDLE_CHK_RULES,
1778 BIN_BUF_DBG_IDLE_CHK_PARSING_DATA,
1779 BIN_BUF_DBG_ATTN_BLOCKS,
1780 BIN_BUF_DBG_ATTN_REGS,
1781 BIN_BUF_DBG_ATTN_INDEXES,
1782 BIN_BUF_DBG_ATTN_NAME_OFFSETS,
1783 BIN_BUF_DBG_PARSING_STRINGS,
1784 MAX_BIN_DBG_BUFFER_TYPE
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001785};
1786
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001787
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001788/* Attention bit mapping */
1789struct dbg_attn_bit_mapping {
1790 __le16 data;
1791#define DBG_ATTN_BIT_MAPPING_VAL_MASK 0x7FFF
1792#define DBG_ATTN_BIT_MAPPING_VAL_SHIFT 0
1793#define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_MASK 0x1
1794#define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_SHIFT 15
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001795};
1796
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001797/* Attention block per-type data */
1798struct dbg_attn_block_type_data {
1799 __le16 names_offset;
1800 __le16 reserved1;
1801 u8 num_regs;
1802 u8 reserved2;
1803 __le16 regs_offset;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001804};
1805
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001806/* Block attentions */
1807struct dbg_attn_block {
1808 struct dbg_attn_block_type_data per_type_data[2];
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001809};
1810
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001811/* Attention register result */
1812struct dbg_attn_reg_result {
1813 __le32 data;
1814#define DBG_ATTN_REG_RESULT_STS_ADDRESS_MASK 0xFFFFFF
1815#define DBG_ATTN_REG_RESULT_STS_ADDRESS_SHIFT 0
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02001816#define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_MASK 0xFF
1817#define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_SHIFT 24
1818 __le16 block_attn_offset;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001819 __le16 reserved;
1820 __le32 sts_val;
1821 __le32 mask_val;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001822};
1823
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001824/* Attention block result */
1825struct dbg_attn_block_result {
1826 u8 block_id;
1827 u8 data;
1828#define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_MASK 0x3
1829#define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_SHIFT 0
1830#define DBG_ATTN_BLOCK_RESULT_NUM_REGS_MASK 0x3F
1831#define DBG_ATTN_BLOCK_RESULT_NUM_REGS_SHIFT 2
1832 __le16 names_offset;
1833 struct dbg_attn_reg_result reg_results[15];
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001834};
1835
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001836/* mode header */
1837struct dbg_mode_hdr {
1838 __le16 data;
1839#define DBG_MODE_HDR_EVAL_MODE_MASK 0x1
1840#define DBG_MODE_HDR_EVAL_MODE_SHIFT 0
1841#define DBG_MODE_HDR_MODES_BUF_OFFSET_MASK 0x7FFF
1842#define DBG_MODE_HDR_MODES_BUF_OFFSET_SHIFT 1
1843};
1844
1845/* Attention register */
1846struct dbg_attn_reg {
1847 struct dbg_mode_hdr mode;
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02001848 __le16 block_attn_offset;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001849 __le32 data;
1850#define DBG_ATTN_REG_STS_ADDRESS_MASK 0xFFFFFF
1851#define DBG_ATTN_REG_STS_ADDRESS_SHIFT 0
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02001852#define DBG_ATTN_REG_NUM_REG_ATTN_MASK 0xFF
1853#define DBG_ATTN_REG_NUM_REG_ATTN_SHIFT 24
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001854 __le32 sts_clr_address;
1855 __le32 mask_address;
1856};
1857
1858/* attention types */
1859enum dbg_attn_type {
1860 ATTN_TYPE_INTERRUPT,
1861 ATTN_TYPE_PARITY,
1862 MAX_DBG_ATTN_TYPE
1863};
1864
Tomer Tayarc965db42016-09-07 16:36:24 +03001865/* condition header for registers dump */
1866struct dbg_dump_cond_hdr {
1867 struct dbg_mode_hdr mode; /* Mode header */
1868 u8 block_id; /* block ID */
1869 u8 data_size; /* size in dwords of the data following this header */
1870};
1871
1872/* memory data for registers dump */
1873struct dbg_dump_mem {
1874 __le32 dword0;
1875#define DBG_DUMP_MEM_ADDRESS_MASK 0xFFFFFF
1876#define DBG_DUMP_MEM_ADDRESS_SHIFT 0
1877#define DBG_DUMP_MEM_MEM_GROUP_ID_MASK 0xFF
1878#define DBG_DUMP_MEM_MEM_GROUP_ID_SHIFT 24
1879 __le32 dword1;
1880#define DBG_DUMP_MEM_LENGTH_MASK 0xFFFFFF
1881#define DBG_DUMP_MEM_LENGTH_SHIFT 0
1882#define DBG_DUMP_MEM_RESERVED_MASK 0xFF
1883#define DBG_DUMP_MEM_RESERVED_SHIFT 24
1884};
1885
1886/* register data for registers dump */
1887struct dbg_dump_reg {
1888 __le32 data;
1889#define DBG_DUMP_REG_ADDRESS_MASK 0xFFFFFF /* register address (in dwords) */
1890#define DBG_DUMP_REG_ADDRESS_SHIFT 0
1891#define DBG_DUMP_REG_LENGTH_MASK 0xFF /* register size (in dwords) */
1892#define DBG_DUMP_REG_LENGTH_SHIFT 24
1893};
1894
1895/* split header for registers dump */
1896struct dbg_dump_split_hdr {
1897 __le32 hdr;
1898#define DBG_DUMP_SPLIT_HDR_DATA_SIZE_MASK 0xFFFFFF
1899#define DBG_DUMP_SPLIT_HDR_DATA_SIZE_SHIFT 0
1900#define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_MASK 0xFF
1901#define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_SHIFT 24
1902};
1903
1904/* condition header for idle check */
1905struct dbg_idle_chk_cond_hdr {
1906 struct dbg_mode_hdr mode; /* Mode header */
1907 __le16 data_size; /* size in dwords of the data following this header */
1908};
1909
1910/* Idle Check condition register */
1911struct dbg_idle_chk_cond_reg {
1912 __le32 data;
1913#define DBG_IDLE_CHK_COND_REG_ADDRESS_MASK 0xFFFFFF
1914#define DBG_IDLE_CHK_COND_REG_ADDRESS_SHIFT 0
1915#define DBG_IDLE_CHK_COND_REG_BLOCK_ID_MASK 0xFF
1916#define DBG_IDLE_CHK_COND_REG_BLOCK_ID_SHIFT 24
1917 __le16 num_entries; /* number of registers entries to check */
1918 u8 entry_size; /* size of registers entry (in dwords) */
1919 u8 start_entry; /* index of the first entry to check */
1920};
1921
1922/* Idle Check info register */
1923struct dbg_idle_chk_info_reg {
1924 __le32 data;
1925#define DBG_IDLE_CHK_INFO_REG_ADDRESS_MASK 0xFFFFFF
1926#define DBG_IDLE_CHK_INFO_REG_ADDRESS_SHIFT 0
1927#define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_MASK 0xFF
1928#define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_SHIFT 24
1929 __le16 size; /* register size in dwords */
1930 struct dbg_mode_hdr mode; /* Mode header */
1931};
1932
1933/* Idle Check register */
1934union dbg_idle_chk_reg {
1935 struct dbg_idle_chk_cond_reg cond_reg; /* condition register */
1936 struct dbg_idle_chk_info_reg info_reg; /* info register */
1937};
1938
1939/* Idle Check result header */
1940struct dbg_idle_chk_result_hdr {
1941 __le16 rule_id; /* Failing rule index */
1942 __le16 mem_entry_id; /* Failing memory entry index */
1943 u8 num_dumped_cond_regs; /* number of dumped condition registers */
1944 u8 num_dumped_info_regs; /* number of dumped condition registers */
1945 u8 severity; /* from dbg_idle_chk_severity_types enum */
1946 u8 reserved;
1947};
1948
1949/* Idle Check result register header */
1950struct dbg_idle_chk_result_reg_hdr {
1951 u8 data;
1952#define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_MASK 0x1
1953#define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_SHIFT 0
1954#define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_MASK 0x7F
1955#define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_SHIFT 1
1956 u8 start_entry; /* index of the first checked entry */
1957 __le16 size; /* register size in dwords */
1958};
1959
1960/* Idle Check rule */
1961struct dbg_idle_chk_rule {
1962 __le16 rule_id; /* Idle Check rule ID */
1963 u8 severity; /* value from dbg_idle_chk_severity_types enum */
1964 u8 cond_id; /* Condition ID */
1965 u8 num_cond_regs; /* number of condition registers */
1966 u8 num_info_regs; /* number of info registers */
1967 u8 num_imms; /* number of immediates in the condition */
1968 u8 reserved1;
1969 __le16 reg_offset; /* offset of this rules registers in the idle check
1970 * register array (in dbg_idle_chk_reg units).
1971 */
1972 __le16 imm_offset; /* offset of this rules immediate values in the
1973 * immediate values array (in dwords).
1974 */
1975};
1976
1977/* Idle Check rule parsing data */
1978struct dbg_idle_chk_rule_parsing_data {
1979 __le32 data;
1980#define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_MASK 0x1
1981#define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_SHIFT 0
1982#define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_MASK 0x7FFFFFFF
1983#define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_SHIFT 1
1984};
1985
1986/* idle check severity types */
1987enum dbg_idle_chk_severity_types {
1988 /* idle check failure should cause an error */
1989 IDLE_CHK_SEVERITY_ERROR,
1990 /* idle check failure should cause an error only if theres no traffic */
1991 IDLE_CHK_SEVERITY_ERROR_NO_TRAFFIC,
1992 /* idle check failure should cause a warning */
1993 IDLE_CHK_SEVERITY_WARNING,
1994 MAX_DBG_IDLE_CHK_SEVERITY_TYPES
1995};
1996
1997/* Debug Bus block data */
1998struct dbg_bus_block_data {
1999 u8 enabled; /* Indicates if the block is enabled for recording (0/1) */
2000 u8 hw_id; /* HW ID associated with the block */
2001 u8 line_num; /* Debug line number to select */
2002 u8 right_shift; /* Number of units to right the debug data (0-3) */
2003 u8 cycle_en; /* 4-bit value: bit i set -> unit i is enabled. */
2004 u8 force_valid; /* 4-bit value: bit i set -> unit i is forced valid. */
2005 u8 force_frame; /* 4-bit value: bit i set -> unit i frame bit is forced.
2006 */
2007 u8 reserved;
2008};
2009
2010/* Debug Bus Clients */
2011enum dbg_bus_clients {
2012 DBG_BUS_CLIENT_RBCN,
2013 DBG_BUS_CLIENT_RBCP,
2014 DBG_BUS_CLIENT_RBCR,
2015 DBG_BUS_CLIENT_RBCT,
2016 DBG_BUS_CLIENT_RBCU,
2017 DBG_BUS_CLIENT_RBCF,
2018 DBG_BUS_CLIENT_RBCX,
2019 DBG_BUS_CLIENT_RBCS,
2020 DBG_BUS_CLIENT_RBCH,
2021 DBG_BUS_CLIENT_RBCZ,
2022 DBG_BUS_CLIENT_OTHER_ENGINE,
2023 DBG_BUS_CLIENT_TIMESTAMP,
2024 DBG_BUS_CLIENT_CPU,
2025 DBG_BUS_CLIENT_RBCY,
2026 DBG_BUS_CLIENT_RBCQ,
2027 DBG_BUS_CLIENT_RBCM,
2028 DBG_BUS_CLIENT_RBCB,
2029 DBG_BUS_CLIENT_RBCW,
2030 DBG_BUS_CLIENT_RBCV,
2031 MAX_DBG_BUS_CLIENTS
2032};
2033
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02002034enum dbg_bus_constraint_ops {
2035 DBG_BUS_CONSTRAINT_OP_EQ,
2036 DBG_BUS_CONSTRAINT_OP_NE,
2037 DBG_BUS_CONSTRAINT_OP_LT,
2038 DBG_BUS_CONSTRAINT_OP_LTC,
2039 DBG_BUS_CONSTRAINT_OP_LE,
2040 DBG_BUS_CONSTRAINT_OP_LEC,
2041 DBG_BUS_CONSTRAINT_OP_GT,
2042 DBG_BUS_CONSTRAINT_OP_GTC,
2043 DBG_BUS_CONSTRAINT_OP_GE,
2044 DBG_BUS_CONSTRAINT_OP_GEC,
2045 MAX_DBG_BUS_CONSTRAINT_OPS
2046};
2047
Tomer Tayarc965db42016-09-07 16:36:24 +03002048/* Debug Bus memory address */
2049struct dbg_bus_mem_addr {
2050 __le32 lo;
2051 __le32 hi;
2052};
2053
2054/* Debug Bus PCI buffer data */
2055struct dbg_bus_pci_buf_data {
2056 struct dbg_bus_mem_addr phys_addr; /* PCI buffer physical address */
2057 struct dbg_bus_mem_addr virt_addr; /* PCI buffer virtual address */
2058 __le32 size; /* PCI buffer size in bytes */
2059};
2060
2061/* Debug Bus Storm EID range filter params */
2062struct dbg_bus_storm_eid_range_params {
2063 u8 min; /* Minimal event ID to filter on */
2064 u8 max; /* Maximal event ID to filter on */
2065};
2066
2067/* Debug Bus Storm EID mask filter params */
2068struct dbg_bus_storm_eid_mask_params {
2069 u8 val; /* Event ID value */
2070 u8 mask; /* Event ID mask. 1s in the mask = dont care bits. */
2071};
2072
2073/* Debug Bus Storm EID filter params */
2074union dbg_bus_storm_eid_params {
2075 struct dbg_bus_storm_eid_range_params range;
2076 struct dbg_bus_storm_eid_mask_params mask;
2077};
2078
2079/* Debug Bus Storm data */
2080struct dbg_bus_storm_data {
2081 u8 fast_enabled;
2082 u8 fast_mode;
2083 u8 slow_enabled;
2084 u8 slow_mode;
2085 u8 hw_id;
2086 u8 eid_filter_en;
2087 u8 eid_range_not_mask;
2088 u8 cid_filter_en;
2089 union dbg_bus_storm_eid_params eid_filter_params;
2090 __le16 reserved;
2091 __le32 cid;
2092};
2093
2094/* Debug Bus data */
2095struct dbg_bus_data {
2096 __le32 app_version; /* The tools version number of the application */
2097 u8 state; /* The current debug bus state */
2098 u8 hw_dwords; /* HW dwords per cycle */
2099 u8 next_hw_id; /* Next HW ID to be associated with an input */
2100 u8 num_enabled_blocks; /* Number of blocks enabled for recording */
2101 u8 num_enabled_storms; /* Number of Storms enabled for recording */
2102 u8 target; /* Output target */
2103 u8 next_trigger_state; /* ID of next trigger state to be added */
2104 u8 next_constraint_id; /* ID of next filter/trigger constraint to be
2105 * added.
2106 */
2107 u8 one_shot_en; /* Indicates if one-shot mode is enabled (0/1) */
2108 u8 grc_input_en; /* Indicates if GRC recording is enabled (0/1) */
2109 u8 timestamp_input_en; /* Indicates if timestamp recording is enabled
2110 * (0/1).
2111 */
2112 u8 filter_en; /* Indicates if the recording filter is enabled (0/1) */
2113 u8 trigger_en; /* Indicates if the recording trigger is enabled (0/1) */
2114 u8 adding_filter; /* If true, the next added constraint belong to the
2115 * filter. Otherwise, it belongs to the last added
2116 * trigger state. Valid only if either filter or
2117 * triggers are enabled.
2118 */
2119 u8 filter_pre_trigger; /* Indicates if the recording filter should be
2120 * applied before the trigger. Valid only if both
2121 * filter and trigger are enabled (0/1).
2122 */
2123 u8 filter_post_trigger; /* Indicates if the recording filter should be
2124 * applied after the trigger. Valid only if both
2125 * filter and trigger are enabled (0/1).
2126 */
2127 u8 unify_inputs; /* If true, all inputs are associated with HW ID 0.
2128 * Otherwise, each input is assigned a different HW ID
2129 * (0/1).
2130 */
2131 u8 rcv_from_other_engine; /* Indicates if the other engine sends it NW
2132 * recording to this engine (0/1).
2133 */
2134 struct dbg_bus_pci_buf_data pci_buf; /* Debug Bus PCI buffer data. Valid
2135 * only when the target is
2136 * DBG_BUS_TARGET_ID_PCI.
2137 */
2138 __le16 reserved;
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02002139 struct dbg_bus_block_data blocks[88];/* Debug Bus data for each block */
Tomer Tayarc965db42016-09-07 16:36:24 +03002140 struct dbg_bus_storm_data storms[6]; /* Debug Bus data for each block */
2141};
2142
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02002143enum dbg_bus_filter_types {
2144 DBG_BUS_FILTER_TYPE_OFF,
2145 DBG_BUS_FILTER_TYPE_PRE,
2146 DBG_BUS_FILTER_TYPE_POST,
2147 DBG_BUS_FILTER_TYPE_ON,
2148 MAX_DBG_BUS_FILTER_TYPES
2149};
2150
Tomer Tayarc965db42016-09-07 16:36:24 +03002151/* Debug bus frame modes */
2152enum dbg_bus_frame_modes {
2153 DBG_BUS_FRAME_MODE_0HW_4ST = 0, /* 0 HW dwords, 4 Storm dwords */
2154 DBG_BUS_FRAME_MODE_4HW_0ST = 3, /* 4 HW dwords, 0 Storm dwords */
2155 DBG_BUS_FRAME_MODE_8HW_0ST = 4, /* 8 HW dwords, 0 Storm dwords */
2156 MAX_DBG_BUS_FRAME_MODES
2157};
2158
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02002159enum dbg_bus_input_types {
2160 DBG_BUS_INPUT_TYPE_STORM,
2161 DBG_BUS_INPUT_TYPE_BLOCK,
2162 MAX_DBG_BUS_INPUT_TYPES
2163};
2164
2165enum dbg_bus_other_engine_modes {
2166 DBG_BUS_OTHER_ENGINE_MODE_NONE,
2167 DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_TX,
2168 DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_RX,
2169 DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_TX,
2170 DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_RX,
2171 MAX_DBG_BUS_OTHER_ENGINE_MODES
2172};
2173
2174enum dbg_bus_post_trigger_types {
2175 DBG_BUS_POST_TRIGGER_RECORD,
2176 DBG_BUS_POST_TRIGGER_DROP,
2177 MAX_DBG_BUS_POST_TRIGGER_TYPES
2178};
2179
2180enum dbg_bus_pre_trigger_types {
2181 DBG_BUS_PRE_TRIGGER_START_FROM_ZERO,
2182 DBG_BUS_PRE_TRIGGER_NUM_CHUNKS,
2183 DBG_BUS_PRE_TRIGGER_DROP,
2184 MAX_DBG_BUS_PRE_TRIGGER_TYPES
2185};
2186
2187enum dbg_bus_semi_frame_modes {
2188 DBG_BUS_SEMI_FRAME_MODE_0SLOW_4FAST = 0,
2189 DBG_BUS_SEMI_FRAME_MODE_4SLOW_0FAST = 3,
2190 MAX_DBG_BUS_SEMI_FRAME_MODES
2191};
2192
Tomer Tayarc965db42016-09-07 16:36:24 +03002193/* Debug bus states */
2194enum dbg_bus_states {
2195 DBG_BUS_STATE_IDLE, /* debug bus idle state (not recording) */
2196 DBG_BUS_STATE_READY, /* debug bus is ready for configuration and
2197 * recording.
2198 */
2199 DBG_BUS_STATE_RECORDING, /* debug bus is currently recording */
2200 DBG_BUS_STATE_STOPPED, /* debug bus recording has stopped */
2201 MAX_DBG_BUS_STATES
2202};
2203
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02002204enum dbg_bus_storm_modes {
2205 DBG_BUS_STORM_MODE_PRINTF,
2206 DBG_BUS_STORM_MODE_PRAM_ADDR,
2207 DBG_BUS_STORM_MODE_DRA_RW,
2208 DBG_BUS_STORM_MODE_DRA_W,
2209 DBG_BUS_STORM_MODE_LD_ST_ADDR,
2210 DBG_BUS_STORM_MODE_DRA_FSM,
2211 DBG_BUS_STORM_MODE_RH,
2212 DBG_BUS_STORM_MODE_FOC,
2213 DBG_BUS_STORM_MODE_EXT_STORE,
2214 MAX_DBG_BUS_STORM_MODES
2215};
2216
Tomer Tayarc965db42016-09-07 16:36:24 +03002217/* Debug bus target IDs */
2218enum dbg_bus_targets {
2219 /* records debug bus to DBG block internal buffer */
2220 DBG_BUS_TARGET_ID_INT_BUF,
2221 /* records debug bus to the NW */
2222 DBG_BUS_TARGET_ID_NIG,
2223 /* records debug bus to a PCI buffer */
2224 DBG_BUS_TARGET_ID_PCI,
2225 MAX_DBG_BUS_TARGETS
2226};
2227
2228/* GRC Dump data */
2229struct dbg_grc_data {
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02002230 u8 params_initialized;
2231 u8 reserved1;
2232 __le16 reserved2;
2233 __le32 param_val[48];
Tomer Tayarc965db42016-09-07 16:36:24 +03002234};
2235
2236/* Debug GRC params */
2237enum dbg_grc_params {
2238 DBG_GRC_PARAM_DUMP_TSTORM, /* dump Tstorm memories (0/1) */
2239 DBG_GRC_PARAM_DUMP_MSTORM, /* dump Mstorm memories (0/1) */
2240 DBG_GRC_PARAM_DUMP_USTORM, /* dump Ustorm memories (0/1) */
2241 DBG_GRC_PARAM_DUMP_XSTORM, /* dump Xstorm memories (0/1) */
2242 DBG_GRC_PARAM_DUMP_YSTORM, /* dump Ystorm memories (0/1) */
2243 DBG_GRC_PARAM_DUMP_PSTORM, /* dump Pstorm memories (0/1) */
2244 DBG_GRC_PARAM_DUMP_REGS, /* dump non-memory registers (0/1) */
2245 DBG_GRC_PARAM_DUMP_RAM, /* dump Storm internal RAMs (0/1) */
2246 DBG_GRC_PARAM_DUMP_PBUF, /* dump Storm passive buffer (0/1) */
2247 DBG_GRC_PARAM_DUMP_IOR, /* dump Storm IORs (0/1) */
2248 DBG_GRC_PARAM_DUMP_VFC, /* dump VFC memories (0/1) */
2249 DBG_GRC_PARAM_DUMP_CM_CTX, /* dump CM contexts (0/1) */
2250 DBG_GRC_PARAM_DUMP_PXP, /* dump PXP memories (0/1) */
2251 DBG_GRC_PARAM_DUMP_RSS, /* dump RSS memories (0/1) */
2252 DBG_GRC_PARAM_DUMP_CAU, /* dump CAU memories (0/1) */
2253 DBG_GRC_PARAM_DUMP_QM, /* dump QM memories (0/1) */
2254 DBG_GRC_PARAM_DUMP_MCP, /* dump MCP memories (0/1) */
2255 DBG_GRC_PARAM_RESERVED, /* reserved */
2256 DBG_GRC_PARAM_DUMP_CFC, /* dump CFC memories (0/1) */
2257 DBG_GRC_PARAM_DUMP_IGU, /* dump IGU memories (0/1) */
2258 DBG_GRC_PARAM_DUMP_BRB, /* dump BRB memories (0/1) */
2259 DBG_GRC_PARAM_DUMP_BTB, /* dump BTB memories (0/1) */
2260 DBG_GRC_PARAM_DUMP_BMB, /* dump BMB memories (0/1) */
2261 DBG_GRC_PARAM_DUMP_NIG, /* dump NIG memories (0/1) */
2262 DBG_GRC_PARAM_DUMP_MULD, /* dump MULD memories (0/1) */
2263 DBG_GRC_PARAM_DUMP_PRS, /* dump PRS memories (0/1) */
2264 DBG_GRC_PARAM_DUMP_DMAE, /* dump PRS memories (0/1) */
2265 DBG_GRC_PARAM_DUMP_TM, /* dump TM (timers) memories (0/1) */
2266 DBG_GRC_PARAM_DUMP_SDM, /* dump SDM memories (0/1) */
2267 DBG_GRC_PARAM_DUMP_DIF, /* dump DIF memories (0/1) */
2268 DBG_GRC_PARAM_DUMP_STATIC, /* dump static debug data (0/1) */
2269 DBG_GRC_PARAM_UNSTALL, /* un-stall Storms after dump (0/1) */
2270 DBG_GRC_PARAM_NUM_LCIDS, /* number of LCIDs (0..320) */
2271 DBG_GRC_PARAM_NUM_LTIDS, /* number of LTIDs (0..320) */
2272 /* preset: exclude all memories from dump (1 only) */
2273 DBG_GRC_PARAM_EXCLUDE_ALL,
2274 /* preset: include memories for crash dump (1 only) */
2275 DBG_GRC_PARAM_CRASH,
2276 /* perform dump only if MFW is responding (0/1) */
2277 DBG_GRC_PARAM_PARITY_SAFE,
2278 DBG_GRC_PARAM_DUMP_CM, /* dump CM memories (0/1) */
2279 DBG_GRC_PARAM_DUMP_PHY, /* dump PHY memories (0/1) */
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02002280 DBG_GRC_PARAM_NO_MCP,
2281 DBG_GRC_PARAM_NO_FW_VER,
Tomer Tayarc965db42016-09-07 16:36:24 +03002282 MAX_DBG_GRC_PARAMS
2283};
2284
2285/* Debug reset registers */
2286enum dbg_reset_regs {
2287 DBG_RESET_REG_MISCS_PL_UA,
2288 DBG_RESET_REG_MISCS_PL_HV,
2289 DBG_RESET_REG_MISCS_PL_HV_2,
2290 DBG_RESET_REG_MISC_PL_UA,
2291 DBG_RESET_REG_MISC_PL_HV,
2292 DBG_RESET_REG_MISC_PL_PDA_VMAIN_1,
2293 DBG_RESET_REG_MISC_PL_PDA_VMAIN_2,
2294 DBG_RESET_REG_MISC_PL_PDA_VAUX,
2295 MAX_DBG_RESET_REGS
2296};
2297
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002298/* Debug status codes */
2299enum dbg_status {
2300 DBG_STATUS_OK,
2301 DBG_STATUS_APP_VERSION_NOT_SET,
2302 DBG_STATUS_UNSUPPORTED_APP_VERSION,
2303 DBG_STATUS_DBG_BLOCK_NOT_RESET,
2304 DBG_STATUS_INVALID_ARGS,
2305 DBG_STATUS_OUTPUT_ALREADY_SET,
2306 DBG_STATUS_INVALID_PCI_BUF_SIZE,
2307 DBG_STATUS_PCI_BUF_ALLOC_FAILED,
2308 DBG_STATUS_PCI_BUF_NOT_ALLOCATED,
2309 DBG_STATUS_TOO_MANY_INPUTS,
2310 DBG_STATUS_INPUT_OVERLAP,
2311 DBG_STATUS_HW_ONLY_RECORDING,
2312 DBG_STATUS_STORM_ALREADY_ENABLED,
2313 DBG_STATUS_STORM_NOT_ENABLED,
2314 DBG_STATUS_BLOCK_ALREADY_ENABLED,
2315 DBG_STATUS_BLOCK_NOT_ENABLED,
2316 DBG_STATUS_NO_INPUT_ENABLED,
2317 DBG_STATUS_NO_FILTER_TRIGGER_64B,
2318 DBG_STATUS_FILTER_ALREADY_ENABLED,
2319 DBG_STATUS_TRIGGER_ALREADY_ENABLED,
2320 DBG_STATUS_TRIGGER_NOT_ENABLED,
2321 DBG_STATUS_CANT_ADD_CONSTRAINT,
2322 DBG_STATUS_TOO_MANY_TRIGGER_STATES,
2323 DBG_STATUS_TOO_MANY_CONSTRAINTS,
2324 DBG_STATUS_RECORDING_NOT_STARTED,
2325 DBG_STATUS_DATA_DIDNT_TRIGGER,
2326 DBG_STATUS_NO_DATA_RECORDED,
2327 DBG_STATUS_DUMP_BUF_TOO_SMALL,
2328 DBG_STATUS_DUMP_NOT_CHUNK_ALIGNED,
2329 DBG_STATUS_UNKNOWN_CHIP,
2330 DBG_STATUS_VIRT_MEM_ALLOC_FAILED,
2331 DBG_STATUS_BLOCK_IN_RESET,
2332 DBG_STATUS_INVALID_TRACE_SIGNATURE,
2333 DBG_STATUS_INVALID_NVRAM_BUNDLE,
2334 DBG_STATUS_NVRAM_GET_IMAGE_FAILED,
2335 DBG_STATUS_NON_ALIGNED_NVRAM_IMAGE,
2336 DBG_STATUS_NVRAM_READ_FAILED,
2337 DBG_STATUS_IDLE_CHK_PARSE_FAILED,
2338 DBG_STATUS_MCP_TRACE_BAD_DATA,
2339 DBG_STATUS_MCP_TRACE_NO_META,
2340 DBG_STATUS_MCP_COULD_NOT_HALT,
2341 DBG_STATUS_MCP_COULD_NOT_RESUME,
2342 DBG_STATUS_DMAE_FAILED,
2343 DBG_STATUS_SEMI_FIFO_NOT_EMPTY,
2344 DBG_STATUS_IGU_FIFO_BAD_DATA,
2345 DBG_STATUS_MCP_COULD_NOT_MASK_PRTY,
2346 DBG_STATUS_FW_ASSERTS_PARSE_FAILED,
2347 DBG_STATUS_REG_FIFO_BAD_DATA,
2348 DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA,
2349 DBG_STATUS_DBG_ARRAY_NOT_SET,
Yuval Mintz05fafbf2016-08-19 09:33:31 +03002350 DBG_STATUS_MULTI_BLOCKS_WITH_FILTER,
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002351 MAX_DBG_STATUS
2352};
2353
Tomer Tayarc965db42016-09-07 16:36:24 +03002354/* Debug Storms IDs */
2355enum dbg_storms {
2356 DBG_TSTORM_ID,
2357 DBG_MSTORM_ID,
2358 DBG_USTORM_ID,
2359 DBG_XSTORM_ID,
2360 DBG_YSTORM_ID,
2361 DBG_PSTORM_ID,
2362 MAX_DBG_STORMS
2363};
2364
2365/* Idle Check data */
2366struct idle_chk_data {
2367 __le32 buf_size; /* Idle check buffer size in dwords */
2368 u8 buf_size_set; /* Indicates if the idle check buffer size was set
2369 * (0/1).
2370 */
2371 u8 reserved1;
2372 __le16 reserved2;
2373};
2374
2375/* Debug Tools data (per HW function) */
2376struct dbg_tools_data {
2377 struct dbg_grc_data grc; /* GRC Dump data */
2378 struct dbg_bus_data bus; /* Debug Bus data */
2379 struct idle_chk_data idle_chk; /* Idle Check data */
2380 u8 mode_enable[40]; /* Indicates if a mode is enabled (0/1) */
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02002381 u8 block_in_reset[88]; /* Indicates if a block is in reset state (0/1).
Tomer Tayarc965db42016-09-07 16:36:24 +03002382 */
2383 u8 chip_id; /* Chip ID (from enum chip_ids) */
2384 u8 platform_id; /* Platform ID (from enum platform_ids) */
2385 u8 initialized; /* Indicates if the data was initialized */
2386 u8 reserved;
2387};
2388
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002389/********************************/
2390/* HSI Init Functions constants */
2391/********************************/
2392
2393/* Number of VLAN priorities */
2394#define NUM_OF_VLAN_PRIORITIES 8
2395
Yuval Mintz05fafbf2016-08-19 09:33:31 +03002396struct init_brb_ram_req {
2397 __le32 guranteed_per_tc;
2398 __le32 headroom_per_tc;
2399 __le32 min_pkt_size;
2400 __le32 max_ports_per_engine;
2401 u8 num_active_tcs[MAX_NUM_PORTS];
2402};
2403
2404struct init_ets_tc_req {
2405 u8 use_sp;
2406 u8 use_wfq;
2407 __le16 weight;
2408};
2409
2410struct init_ets_req {
2411 __le32 mtu;
2412 struct init_ets_tc_req tc_req[NUM_OF_TCS];
2413};
2414
2415struct init_nig_lb_rl_req {
2416 __le16 lb_mac_rate;
2417 __le16 lb_rate;
2418 __le32 mtu;
2419 __le16 tc_rate[NUM_OF_PHYS_TCS];
2420};
2421
2422struct init_nig_pri_tc_map_entry {
2423 u8 tc_id;
2424 u8 valid;
2425};
2426
2427struct init_nig_pri_tc_map_req {
2428 struct init_nig_pri_tc_map_entry pri[NUM_OF_VLAN_PRIORITIES];
2429};
2430
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002431struct init_qm_port_params {
2432 u8 active;
2433 u8 active_phys_tcs;
2434 __le16 num_pbf_cmd_lines;
2435 __le16 num_btb_blocks;
2436 __le16 reserved;
2437};
2438
2439/* QM per-PQ init parameters */
2440struct init_qm_pq_params {
2441 u8 vport_id;
2442 u8 tc_id;
2443 u8 wrr_group;
2444 u8 rl_valid;
2445};
2446
2447/* QM per-vport init parameters */
2448struct init_qm_vport_params {
2449 __le32 vport_rl;
2450 __le16 vport_wfq;
2451 __le16 first_tx_pq_id[NUM_OF_TCS];
2452};
2453
2454/**************************************/
2455/* Init Tool HSI constants and macros */
2456/**************************************/
2457
2458/* Width of GRC address in bits (addresses are specified in dwords) */
2459#define GRC_ADDR_BITS 23
Yuval Mintz05fafbf2016-08-19 09:33:31 +03002460#define MAX_GRC_ADDR (BIT(GRC_ADDR_BITS) - 1)
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002461
2462/* indicates an init that should be applied to any phase ID */
2463#define ANY_PHASE_ID 0xffff
2464
2465/* Max size in dwords of a zipped array */
2466#define MAX_ZIPPED_SIZE 8192
2467
Tomer Tayarc965db42016-09-07 16:36:24 +03002468struct fw_asserts_ram_section {
2469 __le16 section_ram_line_offset;
2470 __le16 section_ram_line_size;
2471 u8 list_dword_offset;
2472 u8 list_element_dword_size;
2473 u8 list_num_elements;
2474 u8 list_next_index_dword_offset;
2475};
2476
2477struct fw_ver_num {
2478 u8 major; /* Firmware major version number */
2479 u8 minor; /* Firmware minor version number */
2480 u8 rev; /* Firmware revision version number */
2481 u8 eng; /* Firmware engineering version number (for bootleg versions) */
2482};
2483
2484struct fw_ver_info {
2485 __le16 tools_ver; /* Tools version number */
2486 u8 image_id; /* FW image ID (e.g. main) */
2487 u8 reserved1;
2488 struct fw_ver_num num; /* FW version number */
2489 __le32 timestamp; /* FW Timestamp in unix time (sec. since 1970) */
2490 __le32 reserved2;
2491};
2492
2493struct fw_info {
2494 struct fw_ver_info ver;
2495 struct fw_asserts_ram_section fw_asserts_section;
2496};
2497
2498struct fw_info_location {
2499 __le32 grc_addr;
2500 __le32 size;
2501};
2502
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002503enum init_modes {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002504 MODE_RESERVED,
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02002505 MODE_BB,
Tomer Tayarc965db42016-09-07 16:36:24 +03002506 MODE_K2,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002507 MODE_ASIC,
Tomer Tayarc965db42016-09-07 16:36:24 +03002508 MODE_RESERVED2,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002509 MODE_RESERVED3,
2510 MODE_RESERVED4,
2511 MODE_RESERVED5,
2512 MODE_SF,
2513 MODE_MF_SD,
2514 MODE_MF_SI,
2515 MODE_PORTS_PER_ENG_1,
2516 MODE_PORTS_PER_ENG_2,
2517 MODE_PORTS_PER_ENG_4,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002518 MODE_100G,
Tomer Tayarc965db42016-09-07 16:36:24 +03002519 MODE_RESERVED6,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002520 MAX_INIT_MODES
2521};
2522
2523enum init_phases {
2524 PHASE_ENGINE,
2525 PHASE_PORT,
2526 PHASE_PF,
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03002527 PHASE_VF,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002528 PHASE_QM_PF,
2529 MAX_INIT_PHASES
2530};
2531
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002532enum init_split_types {
2533 SPLIT_TYPE_NONE,
2534 SPLIT_TYPE_PORT,
2535 SPLIT_TYPE_PF,
2536 SPLIT_TYPE_PORT_PF,
2537 SPLIT_TYPE_VF,
2538 MAX_INIT_SPLIT_TYPES
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002539};
2540
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002541/* Binary buffer header */
2542struct bin_buffer_hdr {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002543 __le32 offset;
2544 __le32 length;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002545};
2546
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002547/* binary init buffer types */
2548enum bin_init_buffer_type {
Yuval Mintz05fafbf2016-08-19 09:33:31 +03002549 BIN_BUF_INIT_FW_VER_INFO,
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002550 BIN_BUF_INIT_CMD,
2551 BIN_BUF_INIT_VAL,
2552 BIN_BUF_INIT_MODE_TREE,
Yuval Mintz05fafbf2016-08-19 09:33:31 +03002553 BIN_BUF_INIT_IRO,
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002554 MAX_BIN_INIT_BUFFER_TYPE
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002555};
2556
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002557/* init array header: raw */
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002558struct init_array_raw_hdr {
2559 __le32 data;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002560#define INIT_ARRAY_RAW_HDR_TYPE_MASK 0xF
2561#define INIT_ARRAY_RAW_HDR_TYPE_SHIFT 0
2562#define INIT_ARRAY_RAW_HDR_PARAMS_MASK 0xFFFFFFF
2563#define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT 4
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002564};
2565
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002566/* init array header: standard */
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002567struct init_array_standard_hdr {
2568 __le32 data;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002569#define INIT_ARRAY_STANDARD_HDR_TYPE_MASK 0xF
2570#define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0
2571#define INIT_ARRAY_STANDARD_HDR_SIZE_MASK 0xFFFFFFF
2572#define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT 4
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002573};
2574
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002575/* init array header: zipped */
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002576struct init_array_zipped_hdr {
2577 __le32 data;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002578#define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK 0xF
2579#define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT 0
2580#define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK 0xFFFFFFF
2581#define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT 4
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002582};
2583
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002584/* init array header: pattern */
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002585struct init_array_pattern_hdr {
2586 __le32 data;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002587#define INIT_ARRAY_PATTERN_HDR_TYPE_MASK 0xF
2588#define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT 0
2589#define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK 0xF
2590#define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT 4
2591#define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK 0xFFFFFF
2592#define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT 8
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002593};
2594
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002595/* init array header union */
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002596union init_array_hdr {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002597 struct init_array_raw_hdr raw;
2598 struct init_array_standard_hdr standard;
2599 struct init_array_zipped_hdr zipped;
2600 struct init_array_pattern_hdr pattern;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002601};
2602
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002603/* init array types */
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002604enum init_array_types {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002605 INIT_ARR_STANDARD,
2606 INIT_ARR_ZIPPED,
2607 INIT_ARR_PATTERN,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002608 MAX_INIT_ARRAY_TYPES
2609};
2610
2611/* init operation: callback */
2612struct init_callback_op {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002613 __le32 op_data;
2614#define INIT_CALLBACK_OP_OP_MASK 0xF
2615#define INIT_CALLBACK_OP_OP_SHIFT 0
2616#define INIT_CALLBACK_OP_RESERVED_MASK 0xFFFFFFF
2617#define INIT_CALLBACK_OP_RESERVED_SHIFT 4
2618 __le16 callback_id;
2619 __le16 block_id;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002620};
2621
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002622/* init operation: delay */
2623struct init_delay_op {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002624 __le32 op_data;
2625#define INIT_DELAY_OP_OP_MASK 0xF
2626#define INIT_DELAY_OP_OP_SHIFT 0
2627#define INIT_DELAY_OP_RESERVED_MASK 0xFFFFFFF
2628#define INIT_DELAY_OP_RESERVED_SHIFT 4
2629 __le32 delay;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002630};
2631
2632/* init operation: if_mode */
2633struct init_if_mode_op {
2634 __le32 op_data;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002635#define INIT_IF_MODE_OP_OP_MASK 0xF
2636#define INIT_IF_MODE_OP_OP_SHIFT 0
2637#define INIT_IF_MODE_OP_RESERVED1_MASK 0xFFF
2638#define INIT_IF_MODE_OP_RESERVED1_SHIFT 4
2639#define INIT_IF_MODE_OP_CMD_OFFSET_MASK 0xFFFF
2640#define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT 16
2641 __le16 reserved2;
2642 __le16 modes_buf_offset;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002643};
2644
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002645/* init operation: if_phase */
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002646struct init_if_phase_op {
2647 __le32 op_data;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002648#define INIT_IF_PHASE_OP_OP_MASK 0xF
2649#define INIT_IF_PHASE_OP_OP_SHIFT 0
2650#define INIT_IF_PHASE_OP_DMAE_ENABLE_MASK 0x1
2651#define INIT_IF_PHASE_OP_DMAE_ENABLE_SHIFT 4
2652#define INIT_IF_PHASE_OP_RESERVED1_MASK 0x7FF
2653#define INIT_IF_PHASE_OP_RESERVED1_SHIFT 5
2654#define INIT_IF_PHASE_OP_CMD_OFFSET_MASK 0xFFFF
2655#define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT 16
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002656 __le32 phase_data;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002657#define INIT_IF_PHASE_OP_PHASE_MASK 0xFF
2658#define INIT_IF_PHASE_OP_PHASE_SHIFT 0
2659#define INIT_IF_PHASE_OP_RESERVED2_MASK 0xFF
2660#define INIT_IF_PHASE_OP_RESERVED2_SHIFT 8
2661#define INIT_IF_PHASE_OP_PHASE_ID_MASK 0xFFFF
2662#define INIT_IF_PHASE_OP_PHASE_ID_SHIFT 16
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002663};
2664
2665/* init mode operators */
2666enum init_mode_ops {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002667 INIT_MODE_OP_NOT,
2668 INIT_MODE_OP_OR,
2669 INIT_MODE_OP_AND,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002670 MAX_INIT_MODE_OPS
2671};
2672
2673/* init operation: raw */
2674struct init_raw_op {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002675 __le32 op_data;
2676#define INIT_RAW_OP_OP_MASK 0xF
2677#define INIT_RAW_OP_OP_SHIFT 0
2678#define INIT_RAW_OP_PARAM1_MASK 0xFFFFFFF
2679#define INIT_RAW_OP_PARAM1_SHIFT 4
2680 __le32 param2;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002681};
2682
2683/* init array params */
2684struct init_op_array_params {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002685 __le16 size;
2686 __le16 offset;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002687};
2688
2689/* Write init operation arguments */
2690union init_write_args {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002691 __le32 inline_val;
2692 __le32 zeros_count;
2693 __le32 array_offset;
2694 struct init_op_array_params runtime;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002695};
2696
2697/* init operation: write */
2698struct init_write_op {
2699 __le32 data;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002700#define INIT_WRITE_OP_OP_MASK 0xF
2701#define INIT_WRITE_OP_OP_SHIFT 0
2702#define INIT_WRITE_OP_SOURCE_MASK 0x7
2703#define INIT_WRITE_OP_SOURCE_SHIFT 4
2704#define INIT_WRITE_OP_RESERVED_MASK 0x1
2705#define INIT_WRITE_OP_RESERVED_SHIFT 7
2706#define INIT_WRITE_OP_WIDE_BUS_MASK 0x1
2707#define INIT_WRITE_OP_WIDE_BUS_SHIFT 8
2708#define INIT_WRITE_OP_ADDRESS_MASK 0x7FFFFF
2709#define INIT_WRITE_OP_ADDRESS_SHIFT 9
2710 union init_write_args args;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002711};
2712
2713/* init operation: read */
2714struct init_read_op {
2715 __le32 op_data;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002716#define INIT_READ_OP_OP_MASK 0xF
2717#define INIT_READ_OP_OP_SHIFT 0
2718#define INIT_READ_OP_POLL_TYPE_MASK 0xF
2719#define INIT_READ_OP_POLL_TYPE_SHIFT 4
2720#define INIT_READ_OP_RESERVED_MASK 0x1
2721#define INIT_READ_OP_RESERVED_SHIFT 8
2722#define INIT_READ_OP_ADDRESS_MASK 0x7FFFFF
2723#define INIT_READ_OP_ADDRESS_SHIFT 9
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002724 __le32 expected_val;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002725
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002726};
2727
2728/* Init operations union */
2729union init_op {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002730 struct init_raw_op raw;
2731 struct init_write_op write;
2732 struct init_read_op read;
2733 struct init_if_mode_op if_mode;
2734 struct init_if_phase_op if_phase;
2735 struct init_callback_op callback;
2736 struct init_delay_op delay;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002737};
2738
2739/* Init command operation types */
2740enum init_op_types {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002741 INIT_OP_READ,
2742 INIT_OP_WRITE,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002743 INIT_OP_IF_MODE,
2744 INIT_OP_IF_PHASE,
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002745 INIT_OP_DELAY,
2746 INIT_OP_CALLBACK,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002747 MAX_INIT_OP_TYPES
2748};
2749
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002750/* init polling types */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002751enum init_poll_types {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002752 INIT_POLL_NONE,
2753 INIT_POLL_EQ,
2754 INIT_POLL_OR,
2755 INIT_POLL_AND,
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002756 MAX_INIT_POLL_TYPES
2757};
2758
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002759/* init source types */
2760enum init_source_types {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002761 INIT_SRC_INLINE,
2762 INIT_SRC_ZEROS,
2763 INIT_SRC_ARRAY,
2764 INIT_SRC_RUNTIME,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002765 MAX_INIT_SOURCE_TYPES
2766};
2767
2768/* Internal RAM Offsets macro data */
2769struct iro {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002770 __le32 base;
2771 __le16 m1;
2772 __le16 m2;
2773 __le16 m3;
2774 __le16 size;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002775};
2776
Tomer Tayarc965db42016-09-07 16:36:24 +03002777/***************************** Public Functions *******************************/
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002778/**
Tomer Tayarc965db42016-09-07 16:36:24 +03002779 * @brief qed_dbg_set_bin_ptr - Sets a pointer to the binary data with debug
2780 * arrays.
2781 *
2782 * @param bin_ptr - a pointer to the binary data with debug arrays.
2783 */
2784enum dbg_status qed_dbg_set_bin_ptr(const u8 * const bin_ptr);
2785/**
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02002786 * @brief qed_dbg_grc_set_params_default - Reverts all GRC parameters to their
2787 * default value.
2788 *
2789 * @param p_hwfn - HW device data
2790 */
2791void qed_dbg_grc_set_params_default(struct qed_hwfn *p_hwfn);
2792/**
Tomer Tayarc965db42016-09-07 16:36:24 +03002793 * @brief qed_dbg_grc_get_dump_buf_size - Returns the required buffer size for
2794 * GRC Dump.
2795 *
2796 * @param p_hwfn - HW device data
2797 * @param p_ptt - Ptt window used for writing the registers.
2798 * @param buf_size - OUT: required buffer size (in dwords) for the GRC Dump
2799 * data.
2800 *
2801 * @return error if one of the following holds:
2802 * - the version wasn't set
2803 * Otherwise, returns ok.
2804 */
2805enum dbg_status qed_dbg_grc_get_dump_buf_size(struct qed_hwfn *p_hwfn,
2806 struct qed_ptt *p_ptt,
2807 u32 *buf_size);
2808/**
2809 * @brief qed_dbg_grc_dump - Dumps GRC data into the specified buffer.
2810 *
2811 * @param p_hwfn - HW device data
2812 * @param p_ptt - Ptt window used for writing the registers.
2813 * @param dump_buf - Pointer to write the collected GRC data into.
2814 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
2815 * @param num_dumped_dwords - OUT: number of dumped dwords.
2816 *
2817 * @return error if one of the following holds:
2818 * - the version wasn't set
2819 * - the specified dump buffer is too small
2820 * Otherwise, returns ok.
2821 */
2822enum dbg_status qed_dbg_grc_dump(struct qed_hwfn *p_hwfn,
2823 struct qed_ptt *p_ptt,
2824 u32 *dump_buf,
2825 u32 buf_size_in_dwords,
2826 u32 *num_dumped_dwords);
2827/**
2828 * @brief qed_dbg_idle_chk_get_dump_buf_size - Returns the required buffer size
2829 * for idle check results.
2830 *
2831 * @param p_hwfn - HW device data
2832 * @param p_ptt - Ptt window used for writing the registers.
2833 * @param buf_size - OUT: required buffer size (in dwords) for the idle check
2834 * data.
2835 *
2836 * @return error if one of the following holds:
2837 * - the version wasn't set
2838 * Otherwise, returns ok.
2839 */
2840enum dbg_status qed_dbg_idle_chk_get_dump_buf_size(struct qed_hwfn *p_hwfn,
2841 struct qed_ptt *p_ptt,
2842 u32 *buf_size);
2843/**
2844 * @brief qed_dbg_idle_chk_dump - Performs idle check and writes the results
2845 * into the specified buffer.
2846 *
2847 * @param p_hwfn - HW device data
2848 * @param p_ptt - Ptt window used for writing the registers.
2849 * @param dump_buf - Pointer to write the idle check data into.
2850 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
2851 * @param num_dumped_dwords - OUT: number of dumped dwords.
2852 *
2853 * @return error if one of the following holds:
2854 * - the version wasn't set
2855 * - the specified buffer is too small
2856 * Otherwise, returns ok.
2857 */
2858enum dbg_status qed_dbg_idle_chk_dump(struct qed_hwfn *p_hwfn,
2859 struct qed_ptt *p_ptt,
2860 u32 *dump_buf,
2861 u32 buf_size_in_dwords,
2862 u32 *num_dumped_dwords);
2863/**
2864 * @brief qed_dbg_mcp_trace_get_dump_buf_size - Returns the required buffer size
2865 * for mcp trace results.
2866 *
2867 * @param p_hwfn - HW device data
2868 * @param p_ptt - Ptt window used for writing the registers.
2869 * @param buf_size - OUT: required buffer size (in dwords) for mcp trace data.
2870 *
2871 * @return error if one of the following holds:
2872 * - the version wasn't set
2873 * - the trace data in MCP scratchpad contain an invalid signature
2874 * - the bundle ID in NVRAM is invalid
2875 * - the trace meta data cannot be found (in NVRAM or image file)
2876 * Otherwise, returns ok.
2877 */
2878enum dbg_status qed_dbg_mcp_trace_get_dump_buf_size(struct qed_hwfn *p_hwfn,
2879 struct qed_ptt *p_ptt,
2880 u32 *buf_size);
2881/**
2882 * @brief qed_dbg_mcp_trace_dump - Performs mcp trace and writes the results
2883 * into the specified buffer.
2884 *
2885 * @param p_hwfn - HW device data
2886 * @param p_ptt - Ptt window used for writing the registers.
2887 * @param dump_buf - Pointer to write the mcp trace data into.
2888 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
2889 * @param num_dumped_dwords - OUT: number of dumped dwords.
2890 *
2891 * @return error if one of the following holds:
2892 * - the version wasn't set
2893 * - the specified buffer is too small
2894 * - the trace data in MCP scratchpad contain an invalid signature
2895 * - the bundle ID in NVRAM is invalid
2896 * - the trace meta data cannot be found (in NVRAM or image file)
2897 * - the trace meta data cannot be read (from NVRAM or image file)
2898 * Otherwise, returns ok.
2899 */
2900enum dbg_status qed_dbg_mcp_trace_dump(struct qed_hwfn *p_hwfn,
2901 struct qed_ptt *p_ptt,
2902 u32 *dump_buf,
2903 u32 buf_size_in_dwords,
2904 u32 *num_dumped_dwords);
2905/**
2906 * @brief qed_dbg_reg_fifo_get_dump_buf_size - Returns the required buffer size
2907 * for grc trace fifo results.
2908 *
2909 * @param p_hwfn - HW device data
2910 * @param p_ptt - Ptt window used for writing the registers.
2911 * @param buf_size - OUT: required buffer size (in dwords) for reg fifo data.
2912 *
2913 * @return error if one of the following holds:
2914 * - the version wasn't set
2915 * Otherwise, returns ok.
2916 */
2917enum dbg_status qed_dbg_reg_fifo_get_dump_buf_size(struct qed_hwfn *p_hwfn,
2918 struct qed_ptt *p_ptt,
2919 u32 *buf_size);
2920/**
2921 * @brief qed_dbg_reg_fifo_dump - Reads the reg fifo and writes the results into
2922 * the specified buffer.
2923 *
2924 * @param p_hwfn - HW device data
2925 * @param p_ptt - Ptt window used for writing the registers.
2926 * @param dump_buf - Pointer to write the reg fifo data into.
2927 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
2928 * @param num_dumped_dwords - OUT: number of dumped dwords.
2929 *
2930 * @return error if one of the following holds:
2931 * - the version wasn't set
2932 * - the specified buffer is too small
2933 * - DMAE transaction failed
2934 * Otherwise, returns ok.
2935 */
2936enum dbg_status qed_dbg_reg_fifo_dump(struct qed_hwfn *p_hwfn,
2937 struct qed_ptt *p_ptt,
2938 u32 *dump_buf,
2939 u32 buf_size_in_dwords,
2940 u32 *num_dumped_dwords);
2941/**
2942 * @brief qed_dbg_igu_fifo_get_dump_buf_size - Returns the required buffer size
2943 * for the IGU fifo results.
2944 *
2945 * @param p_hwfn - HW device data
2946 * @param p_ptt - Ptt window used for writing the registers.
2947 * @param buf_size - OUT: required buffer size (in dwords) for the IGU fifo
2948 * data.
2949 *
2950 * @return error if one of the following holds:
2951 * - the version wasn't set
2952 * Otherwise, returns ok.
2953 */
2954enum dbg_status qed_dbg_igu_fifo_get_dump_buf_size(struct qed_hwfn *p_hwfn,
2955 struct qed_ptt *p_ptt,
2956 u32 *buf_size);
2957/**
2958 * @brief qed_dbg_igu_fifo_dump - Reads the IGU fifo and writes the results into
2959 * the specified buffer.
2960 *
2961 * @param p_hwfn - HW device data
2962 * @param p_ptt - Ptt window used for writing the registers.
2963 * @param dump_buf - Pointer to write the IGU fifo data into.
2964 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
2965 * @param num_dumped_dwords - OUT: number of dumped dwords.
2966 *
2967 * @return error if one of the following holds:
2968 * - the version wasn't set
2969 * - the specified buffer is too small
2970 * - DMAE transaction failed
2971 * Otherwise, returns ok.
2972 */
2973enum dbg_status qed_dbg_igu_fifo_dump(struct qed_hwfn *p_hwfn,
2974 struct qed_ptt *p_ptt,
2975 u32 *dump_buf,
2976 u32 buf_size_in_dwords,
2977 u32 *num_dumped_dwords);
2978/**
2979 * @brief qed_dbg_protection_override_get_dump_buf_size - Returns the required
2980 * buffer size for protection override window results.
2981 *
2982 * @param p_hwfn - HW device data
2983 * @param p_ptt - Ptt window used for writing the registers.
2984 * @param buf_size - OUT: required buffer size (in dwords) for protection
2985 * override data.
2986 *
2987 * @return error if one of the following holds:
2988 * - the version wasn't set
2989 * Otherwise, returns ok.
2990 */
2991enum dbg_status
2992qed_dbg_protection_override_get_dump_buf_size(struct qed_hwfn *p_hwfn,
2993 struct qed_ptt *p_ptt,
2994 u32 *buf_size);
2995/**
2996 * @brief qed_dbg_protection_override_dump - Reads protection override window
2997 * entries and writes the results into the specified buffer.
2998 *
2999 * @param p_hwfn - HW device data
3000 * @param p_ptt - Ptt window used for writing the registers.
3001 * @param dump_buf - Pointer to write the protection override data into.
3002 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3003 * @param num_dumped_dwords - OUT: number of dumped dwords.
3004 *
3005 * @return error if one of the following holds:
3006 * - the version wasn't set
3007 * - the specified buffer is too small
3008 * - DMAE transaction failed
3009 * Otherwise, returns ok.
3010 */
3011enum dbg_status qed_dbg_protection_override_dump(struct qed_hwfn *p_hwfn,
3012 struct qed_ptt *p_ptt,
3013 u32 *dump_buf,
3014 u32 buf_size_in_dwords,
3015 u32 *num_dumped_dwords);
3016/**
3017 * @brief qed_dbg_fw_asserts_get_dump_buf_size - Returns the required buffer
3018 * size for FW Asserts results.
3019 *
3020 * @param p_hwfn - HW device data
3021 * @param p_ptt - Ptt window used for writing the registers.
3022 * @param buf_size - OUT: required buffer size (in dwords) for FW Asserts data.
3023 *
3024 * @return error if one of the following holds:
3025 * - the version wasn't set
3026 * Otherwise, returns ok.
3027 */
3028enum dbg_status qed_dbg_fw_asserts_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3029 struct qed_ptt *p_ptt,
3030 u32 *buf_size);
3031/**
3032 * @brief qed_dbg_fw_asserts_dump - Reads the FW Asserts and writes the results
3033 * into the specified buffer.
3034 *
3035 * @param p_hwfn - HW device data
3036 * @param p_ptt - Ptt window used for writing the registers.
3037 * @param dump_buf - Pointer to write the FW Asserts data into.
3038 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3039 * @param num_dumped_dwords - OUT: number of dumped dwords.
3040 *
3041 * @return error if one of the following holds:
3042 * - the version wasn't set
3043 * - the specified buffer is too small
3044 * Otherwise, returns ok.
3045 */
3046enum dbg_status qed_dbg_fw_asserts_dump(struct qed_hwfn *p_hwfn,
3047 struct qed_ptt *p_ptt,
3048 u32 *dump_buf,
3049 u32 buf_size_in_dwords,
3050 u32 *num_dumped_dwords);
3051/**
3052 * @brief qed_dbg_print_attn - Prints attention registers values in the
3053 * specified results struct.
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003054 *
3055 * @param p_hwfn
3056 * @param results - Pointer to the attention read results
3057 *
3058 * @return error if one of the following holds:
3059 * - the version wasn't set
3060 * Otherwise, returns ok.
3061 */
3062enum dbg_status qed_dbg_print_attn(struct qed_hwfn *p_hwfn,
3063 struct dbg_attn_block_result *results);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003064
Tomer Tayarc965db42016-09-07 16:36:24 +03003065/******************************** Constants **********************************/
3066
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003067#define MAX_NAME_LEN 16
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003068
Tomer Tayarc965db42016-09-07 16:36:24 +03003069/***************************** Public Functions *******************************/
3070/**
3071 * @brief qed_dbg_user_set_bin_ptr - Sets a pointer to the binary data with
3072 * debug arrays.
3073 *
3074 * @param bin_ptr - a pointer to the binary data with debug arrays.
3075 */
3076enum dbg_status qed_dbg_user_set_bin_ptr(const u8 * const bin_ptr);
3077/**
3078 * @brief qed_dbg_get_status_str - Returns a string for the specified status.
3079 *
3080 * @param status - a debug status code.
3081 *
3082 * @return a string for the specified status
3083 */
3084const char *qed_dbg_get_status_str(enum dbg_status status);
3085/**
3086 * @brief qed_get_idle_chk_results_buf_size - Returns the required buffer size
3087 * for idle check results (in bytes).
3088 *
3089 * @param p_hwfn - HW device data
3090 * @param dump_buf - idle check dump buffer.
3091 * @param num_dumped_dwords - number of dwords that were dumped.
3092 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3093 * results.
3094 *
3095 * @return error if the parsing fails, ok otherwise.
3096 */
3097enum dbg_status qed_get_idle_chk_results_buf_size(struct qed_hwfn *p_hwfn,
3098 u32 *dump_buf,
3099 u32 num_dumped_dwords,
3100 u32 *results_buf_size);
3101/**
3102 * @brief qed_print_idle_chk_results - Prints idle check results
3103 *
3104 * @param p_hwfn - HW device data
3105 * @param dump_buf - idle check dump buffer.
3106 * @param num_dumped_dwords - number of dwords that were dumped.
3107 * @param results_buf - buffer for printing the idle check results.
3108 * @param num_errors - OUT: number of errors found in idle check.
3109 * @param num_warnings - OUT: number of warnings found in idle check.
3110 *
3111 * @return error if the parsing fails, ok otherwise.
3112 */
3113enum dbg_status qed_print_idle_chk_results(struct qed_hwfn *p_hwfn,
3114 u32 *dump_buf,
3115 u32 num_dumped_dwords,
3116 char *results_buf,
3117 u32 *num_errors,
3118 u32 *num_warnings);
3119/**
3120 * @brief qed_get_mcp_trace_results_buf_size - Returns the required buffer size
3121 * for MCP Trace results (in bytes).
3122 *
3123 * @param p_hwfn - HW device data
3124 * @param dump_buf - MCP Trace dump buffer.
3125 * @param num_dumped_dwords - number of dwords that were dumped.
3126 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3127 * results.
3128 *
3129 * @return error if the parsing fails, ok otherwise.
3130 */
3131enum dbg_status qed_get_mcp_trace_results_buf_size(struct qed_hwfn *p_hwfn,
3132 u32 *dump_buf,
3133 u32 num_dumped_dwords,
3134 u32 *results_buf_size);
3135/**
3136 * @brief qed_print_mcp_trace_results - Prints MCP Trace results
3137 *
3138 * @param p_hwfn - HW device data
3139 * @param dump_buf - mcp trace dump buffer, starting from the header.
3140 * @param num_dumped_dwords - number of dwords that were dumped.
3141 * @param results_buf - buffer for printing the mcp trace results.
3142 *
3143 * @return error if the parsing fails, ok otherwise.
3144 */
3145enum dbg_status qed_print_mcp_trace_results(struct qed_hwfn *p_hwfn,
3146 u32 *dump_buf,
3147 u32 num_dumped_dwords,
3148 char *results_buf);
3149/**
3150 * @brief qed_get_reg_fifo_results_buf_size - Returns the required buffer size
3151 * for reg_fifo results (in bytes).
3152 *
3153 * @param p_hwfn - HW device data
3154 * @param dump_buf - reg fifo dump buffer.
3155 * @param num_dumped_dwords - number of dwords that were dumped.
3156 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3157 * results.
3158 *
3159 * @return error if the parsing fails, ok otherwise.
3160 */
3161enum dbg_status qed_get_reg_fifo_results_buf_size(struct qed_hwfn *p_hwfn,
3162 u32 *dump_buf,
3163 u32 num_dumped_dwords,
3164 u32 *results_buf_size);
3165/**
3166 * @brief qed_print_reg_fifo_results - Prints reg fifo results
3167 *
3168 * @param p_hwfn - HW device data
3169 * @param dump_buf - reg fifo dump buffer, starting from the header.
3170 * @param num_dumped_dwords - number of dwords that were dumped.
3171 * @param results_buf - buffer for printing the reg fifo results.
3172 *
3173 * @return error if the parsing fails, ok otherwise.
3174 */
3175enum dbg_status qed_print_reg_fifo_results(struct qed_hwfn *p_hwfn,
3176 u32 *dump_buf,
3177 u32 num_dumped_dwords,
3178 char *results_buf);
3179/**
3180 * @brief qed_get_igu_fifo_results_buf_size - Returns the required buffer size
3181 * for igu_fifo results (in bytes).
3182 *
3183 * @param p_hwfn - HW device data
3184 * @param dump_buf - IGU fifo dump buffer.
3185 * @param num_dumped_dwords - number of dwords that were dumped.
3186 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3187 * results.
3188 *
3189 * @return error if the parsing fails, ok otherwise.
3190 */
3191enum dbg_status qed_get_igu_fifo_results_buf_size(struct qed_hwfn *p_hwfn,
3192 u32 *dump_buf,
3193 u32 num_dumped_dwords,
3194 u32 *results_buf_size);
3195/**
3196 * @brief qed_print_igu_fifo_results - Prints IGU fifo results
3197 *
3198 * @param p_hwfn - HW device data
3199 * @param dump_buf - IGU fifo dump buffer, starting from the header.
3200 * @param num_dumped_dwords - number of dwords that were dumped.
3201 * @param results_buf - buffer for printing the IGU fifo results.
3202 *
3203 * @return error if the parsing fails, ok otherwise.
3204 */
3205enum dbg_status qed_print_igu_fifo_results(struct qed_hwfn *p_hwfn,
3206 u32 *dump_buf,
3207 u32 num_dumped_dwords,
3208 char *results_buf);
3209/**
3210 * @brief qed_get_protection_override_results_buf_size - Returns the required
3211 * buffer size for protection override results (in bytes).
3212 *
3213 * @param p_hwfn - HW device data
3214 * @param dump_buf - protection override dump buffer.
3215 * @param num_dumped_dwords - number of dwords that were dumped.
3216 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3217 * results.
3218 *
3219 * @return error if the parsing fails, ok otherwise.
3220 */
3221enum dbg_status
3222qed_get_protection_override_results_buf_size(struct qed_hwfn *p_hwfn,
3223 u32 *dump_buf,
3224 u32 num_dumped_dwords,
3225 u32 *results_buf_size);
3226/**
3227 * @brief qed_print_protection_override_results - Prints protection override
3228 * results.
3229 *
3230 * @param p_hwfn - HW device data
3231 * @param dump_buf - protection override dump buffer, starting from the header.
3232 * @param num_dumped_dwords - number of dwords that were dumped.
3233 * @param results_buf - buffer for printing the reg fifo results.
3234 *
3235 * @return error if the parsing fails, ok otherwise.
3236 */
3237enum dbg_status qed_print_protection_override_results(struct qed_hwfn *p_hwfn,
3238 u32 *dump_buf,
3239 u32 num_dumped_dwords,
3240 char *results_buf);
3241/**
3242 * @brief qed_get_fw_asserts_results_buf_size - Returns the required buffer size
3243 * for FW Asserts results (in bytes).
3244 *
3245 * @param p_hwfn - HW device data
3246 * @param dump_buf - FW Asserts dump buffer.
3247 * @param num_dumped_dwords - number of dwords that were dumped.
3248 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3249 * results.
3250 *
3251 * @return error if the parsing fails, ok otherwise.
3252 */
3253enum dbg_status qed_get_fw_asserts_results_buf_size(struct qed_hwfn *p_hwfn,
3254 u32 *dump_buf,
3255 u32 num_dumped_dwords,
3256 u32 *results_buf_size);
3257/**
3258 * @brief qed_print_fw_asserts_results - Prints FW Asserts results
3259 *
3260 * @param p_hwfn - HW device data
3261 * @param dump_buf - FW Asserts dump buffer, starting from the header.
3262 * @param num_dumped_dwords - number of dwords that were dumped.
3263 * @param results_buf - buffer for printing the FW Asserts results.
3264 *
3265 * @return error if the parsing fails, ok otherwise.
3266 */
3267enum dbg_status qed_print_fw_asserts_results(struct qed_hwfn *p_hwfn,
3268 u32 *dump_buf,
3269 u32 num_dumped_dwords,
3270 char *results_buf);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003271/* Win 2 */
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003272#define GTT_BAR0_MAP_REG_IGU_CMD 0x00f000UL
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003273
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003274/* Win 3 */
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003275#define GTT_BAR0_MAP_REG_TSDM_RAM 0x010000UL
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003276
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003277/* Win 4 */
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003278#define GTT_BAR0_MAP_REG_MSDM_RAM 0x011000UL
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003279
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003280/* Win 5 */
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003281#define GTT_BAR0_MAP_REG_MSDM_RAM_1024 0x012000UL
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003282
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003283/* Win 6 */
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003284#define GTT_BAR0_MAP_REG_USDM_RAM 0x013000UL
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003285
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003286/* Win 7 */
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003287#define GTT_BAR0_MAP_REG_USDM_RAM_1024 0x014000UL
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003288
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003289/* Win 8 */
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003290#define GTT_BAR0_MAP_REG_USDM_RAM_2048 0x015000UL
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003291
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003292/* Win 9 */
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003293#define GTT_BAR0_MAP_REG_XSDM_RAM 0x016000UL
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003294
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003295/* Win 10 */
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003296#define GTT_BAR0_MAP_REG_YSDM_RAM 0x017000UL
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003297
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003298/* Win 11 */
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003299#define GTT_BAR0_MAP_REG_PSDM_RAM 0x018000UL
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003300
3301/**
3302 * @brief qed_qm_pf_mem_size - prepare QM ILT sizes
3303 *
3304 * Returns the required host memory size in 4KB units.
3305 * Must be called before all QM init HSI functions.
3306 *
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003307 * @param pf_id - physical function ID
3308 * @param num_pf_cids - number of connections used by this PF
3309 * @param num_vf_cids - number of connections used by VFs of this PF
3310 * @param num_tids - number of tasks used by this PF
3311 * @param num_pf_pqs - number of PQs used by this PF
3312 * @param num_vf_pqs - number of PQs used by VFs of this PF
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003313 *
3314 * @return The required host memory size in 4KB units.
3315 */
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003316u32 qed_qm_pf_mem_size(u8 pf_id,
3317 u32 num_pf_cids,
3318 u32 num_vf_cids,
3319 u32 num_tids, u16 num_pf_pqs, u16 num_vf_pqs);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003320
3321struct qed_qm_common_rt_init_params {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003322 u8 max_ports_per_engine;
3323 u8 max_phys_tcs_per_port;
3324 bool pf_rl_en;
3325 bool pf_wfq_en;
3326 bool vport_rl_en;
3327 bool vport_wfq_en;
3328 struct init_qm_port_params *port_params;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003329};
3330
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003331int qed_qm_common_rt_init(struct qed_hwfn *p_hwfn,
3332 struct qed_qm_common_rt_init_params *p_params);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003333
3334struct qed_qm_pf_rt_init_params {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003335 u8 port_id;
3336 u8 pf_id;
3337 u8 max_phys_tcs_per_port;
3338 bool is_first_pf;
3339 u32 num_pf_cids;
3340 u32 num_vf_cids;
3341 u32 num_tids;
3342 u16 start_pq;
3343 u16 num_pf_pqs;
3344 u16 num_vf_pqs;
3345 u8 start_vport;
3346 u8 num_vports;
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003347 u16 pf_wfq;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003348 u32 pf_rl;
3349 struct init_qm_pq_params *pq_params;
3350 struct init_qm_vport_params *vport_params;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003351};
3352
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003353int qed_qm_pf_rt_init(struct qed_hwfn *p_hwfn,
3354 struct qed_ptt *p_ptt,
3355 struct qed_qm_pf_rt_init_params *p_params);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003356
3357/**
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003358 * @brief qed_init_pf_wfq - Initializes the WFQ weight of the specified PF
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003359 *
3360 * @param p_hwfn
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003361 * @param p_ptt - ptt window used for writing the registers
3362 * @param pf_id - PF ID
3363 * @param pf_wfq - WFQ weight. Must be non-zero.
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003364 *
3365 * @return 0 on success, -1 on error.
3366 */
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003367int qed_init_pf_wfq(struct qed_hwfn *p_hwfn,
3368 struct qed_ptt *p_ptt, u8 pf_id, u16 pf_wfq);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003369
3370/**
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003371 * @brief qed_init_pf_rl - Initializes the rate limit of the specified PF
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003372 *
3373 * @param p_hwfn
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003374 * @param p_ptt - ptt window used for writing the registers
3375 * @param pf_id - PF ID
3376 * @param pf_rl - rate limit in Mb/sec units
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003377 *
3378 * @return 0 on success, -1 on error.
3379 */
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003380int qed_init_pf_rl(struct qed_hwfn *p_hwfn,
3381 struct qed_ptt *p_ptt, u8 pf_id, u32 pf_rl);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003382
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003383/**
3384 * @brief qed_init_vport_wfq Initializes the WFQ weight of the specified VPORT
3385 *
3386 * @param p_hwfn
3387 * @param p_ptt - ptt window used for writing the registers
3388 * @param first_tx_pq_id- An array containing the first Tx PQ ID associated
3389 * with the VPORT for each TC. This array is filled by
3390 * qed_qm_pf_rt_init
3391 * @param vport_wfq - WFQ weight. Must be non-zero.
3392 *
3393 * @return 0 on success, -1 on error.
3394 */
3395int qed_init_vport_wfq(struct qed_hwfn *p_hwfn,
3396 struct qed_ptt *p_ptt,
3397 u16 first_tx_pq_id[NUM_OF_TCS], u16 vport_wfq);
3398
3399/**
3400 * @brief qed_init_vport_rl - Initializes the rate limit of the specified VPORT
3401 *
3402 * @param p_hwfn
3403 * @param p_ptt - ptt window used for writing the registers
3404 * @param vport_id - VPORT ID
3405 * @param vport_rl - rate limit in Mb/sec units
3406 *
3407 * @return 0 on success, -1 on error.
3408 */
3409int qed_init_vport_rl(struct qed_hwfn *p_hwfn,
3410 struct qed_ptt *p_ptt, u8 vport_id, u32 vport_rl);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003411/**
3412 * @brief qed_send_qm_stop_cmd Sends a stop command to the QM
3413 *
3414 * @param p_hwfn
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003415 * @param p_ptt
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003416 * @param is_release_cmd - true for release, false for stop.
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003417 * @param is_tx_pq - true for Tx PQs, false for Other PQs.
3418 * @param start_pq - first PQ ID to stop
3419 * @param num_pqs - Number of PQs to stop, starting from start_pq.
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003420 *
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003421 * @return bool, true if successful, false if timeout occured while waiting for QM command done.
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003422 */
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003423bool qed_send_qm_stop_cmd(struct qed_hwfn *p_hwfn,
3424 struct qed_ptt *p_ptt,
3425 bool is_release_cmd,
3426 bool is_tx_pq, u16 start_pq, u16 num_pqs);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003427
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003428/**
3429 * @brief qed_set_vxlan_dest_port - initializes vxlan tunnel destination udp port
3430 *
3431 * @param p_ptt - ptt window used for writing the registers.
3432 * @param dest_port - vxlan destination udp port.
3433 */
Manish Chopra464f6642016-04-14 01:38:29 -04003434void qed_set_vxlan_dest_port(struct qed_hwfn *p_hwfn,
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003435 struct qed_ptt *p_ptt, u16 dest_port);
3436
3437/**
3438 * @brief qed_set_vxlan_enable - enable or disable VXLAN tunnel in HW
3439 *
3440 * @param p_ptt - ptt window used for writing the registers.
3441 * @param vxlan_enable - vxlan enable flag.
3442 */
Manish Chopra464f6642016-04-14 01:38:29 -04003443void qed_set_vxlan_enable(struct qed_hwfn *p_hwfn,
3444 struct qed_ptt *p_ptt, bool vxlan_enable);
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003445
3446/**
3447 * @brief qed_set_gre_enable - enable or disable GRE tunnel in HW
3448 *
3449 * @param p_ptt - ptt window used for writing the registers.
3450 * @param eth_gre_enable - eth GRE enable enable flag.
3451 * @param ip_gre_enable - IP GRE enable enable flag.
3452 */
Manish Chopra464f6642016-04-14 01:38:29 -04003453void qed_set_gre_enable(struct qed_hwfn *p_hwfn,
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003454 struct qed_ptt *p_ptt,
3455 bool eth_gre_enable, bool ip_gre_enable);
3456
3457/**
3458 * @brief qed_set_geneve_dest_port - initializes geneve tunnel destination udp port
3459 *
3460 * @param p_ptt - ptt window used for writing the registers.
3461 * @param dest_port - geneve destination udp port.
3462 */
Manish Chopra464f6642016-04-14 01:38:29 -04003463void qed_set_geneve_dest_port(struct qed_hwfn *p_hwfn,
3464 struct qed_ptt *p_ptt, u16 dest_port);
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003465
3466/**
3467 * @brief qed_set_gre_enable - enable or disable GRE tunnel in HW
3468 *
3469 * @param p_ptt - ptt window used for writing the registers.
3470 * @param eth_geneve_enable - eth GENEVE enable enable flag.
3471 * @param ip_geneve_enable - IP GENEVE enable enable flag.
3472 */
Manish Chopra464f6642016-04-14 01:38:29 -04003473void qed_set_geneve_enable(struct qed_hwfn *p_hwfn,
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003474 struct qed_ptt *p_ptt,
3475 bool eth_geneve_enable, bool ip_geneve_enable);
Chopra, Manishd51e4af2017-04-13 04:54:44 -07003476void qed_set_rfs_mode_disable(struct qed_hwfn *p_hwfn,
3477 struct qed_ptt *p_ptt, u16 pf_id);
3478void qed_set_rfs_mode_enable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
3479 u16 pf_id, bool tcp, bool udp,
3480 bool ipv4, bool ipv6);
Manish Chopra464f6642016-04-14 01:38:29 -04003481
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003482#define YSTORM_FLOW_CONTROL_MODE_OFFSET (IRO[0].base)
3483#define YSTORM_FLOW_CONTROL_MODE_SIZE (IRO[0].size)
3484#define TSTORM_PORT_STAT_OFFSET(port_id) \
3485 (IRO[1].base + ((port_id) * IRO[1].m1))
3486#define TSTORM_PORT_STAT_SIZE (IRO[1].size)
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003487#define TSTORM_LL2_PORT_STAT_OFFSET(port_id) \
3488 (IRO[2].base + ((port_id) * IRO[2].m1))
3489#define TSTORM_LL2_PORT_STAT_SIZE (IRO[2].size)
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003490#define USTORM_VF_PF_CHANNEL_READY_OFFSET(vf_id) \
3491 (IRO[3].base + ((vf_id) * IRO[3].m1))
3492#define USTORM_VF_PF_CHANNEL_READY_SIZE (IRO[3].size)
3493#define USTORM_FLR_FINAL_ACK_OFFSET(pf_id) \
3494 (IRO[4].base + (pf_id) * IRO[4].m1)
3495#define USTORM_FLR_FINAL_ACK_SIZE (IRO[4].size)
3496#define USTORM_EQE_CONS_OFFSET(pf_id) \
3497 (IRO[5].base + ((pf_id) * IRO[5].m1))
3498#define USTORM_EQE_CONS_SIZE (IRO[5].size)
3499#define USTORM_ETH_QUEUE_ZONE_OFFSET(queue_zone_id) \
3500 (IRO[6].base + ((queue_zone_id) * IRO[6].m1))
3501#define USTORM_ETH_QUEUE_ZONE_SIZE (IRO[6].size)
3502#define USTORM_COMMON_QUEUE_CONS_OFFSET(queue_zone_id) \
3503 (IRO[7].base + ((queue_zone_id) * IRO[7].m1))
3504#define USTORM_COMMON_QUEUE_CONS_SIZE (IRO[7].size)
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003505#define TSTORM_LL2_RX_PRODS_OFFSET(core_rx_queue_id) \
3506 (IRO[14].base + ((core_rx_queue_id) * IRO[14].m1))
3507#define TSTORM_LL2_RX_PRODS_SIZE (IRO[14].size)
3508#define CORE_LL2_TSTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
3509 (IRO[15].base + ((core_rx_queue_id) * IRO[15].m1))
3510#define CORE_LL2_TSTORM_PER_QUEUE_STAT_SIZE (IRO[15].size)
3511#define CORE_LL2_USTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
3512 (IRO[16].base + ((core_rx_queue_id) * IRO[16].m1))
3513#define CORE_LL2_USTORM_PER_QUEUE_STAT_SIZE (IRO[16].size)
3514#define CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(core_tx_stats_id) \
3515 (IRO[17].base + ((core_tx_stats_id) * IRO[17].m1))
3516#define CORE_LL2_PSTORM_PER_QUEUE_STAT_SIZE (IRO[17]. size)
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003517#define MSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
3518 (IRO[18].base + ((stat_counter_id) * IRO[18].m1))
3519#define MSTORM_QUEUE_STAT_SIZE (IRO[18].size)
3520#define MSTORM_ETH_PF_PRODS_OFFSET(queue_id) \
3521 (IRO[19].base + ((queue_id) * IRO[19].m1))
3522#define MSTORM_ETH_PF_PRODS_SIZE (IRO[19].size)
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003523#define MSTORM_ETH_VF_PRODS_OFFSET(vf_id, vf_queue_id) \
3524 (IRO[20].base + ((vf_id) * IRO[20].m1) + ((vf_queue_id) * IRO[20].m2))
3525#define MSTORM_ETH_VF_PRODS_SIZE (IRO[20].size)
3526#define MSTORM_TPA_TIMEOUT_US_OFFSET (IRO[21].base)
3527#define MSTORM_TPA_TIMEOUT_US_SIZE (IRO[21].size)
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003528#define MSTORM_ETH_PF_STAT_OFFSET(pf_id) \
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003529 (IRO[22].base + ((pf_id) * IRO[22].m1))
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02003530#define MSTORM_ETH_PF_STAT_SIZE (IRO[22].size)
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003531#define USTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003532 (IRO[23].base + ((stat_counter_id) * IRO[23].m1))
3533#define USTORM_QUEUE_STAT_SIZE (IRO[23].size)
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003534#define USTORM_ETH_PF_STAT_OFFSET(pf_id) \
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003535 (IRO[24].base + ((pf_id) * IRO[24].m1))
3536#define USTORM_ETH_PF_STAT_SIZE (IRO[24].size)
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003537#define PSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003538 (IRO[25].base + ((stat_counter_id) * IRO[25].m1))
3539#define PSTORM_QUEUE_STAT_SIZE (IRO[25].size)
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003540#define PSTORM_ETH_PF_STAT_OFFSET(pf_id) \
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003541 (IRO[26].base + ((pf_id) * IRO[26].m1))
3542#define PSTORM_ETH_PF_STAT_SIZE (IRO[26].size)
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003543#define PSTORM_CTL_FRAME_ETHTYPE_OFFSET(ethtype) \
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003544 (IRO[27].base + ((ethtype) * IRO[27].m1))
3545#define PSTORM_CTL_FRAME_ETHTYPE_SIZE (IRO[27].size)
3546#define TSTORM_ETH_PRS_INPUT_OFFSET (IRO[28].base)
3547#define TSTORM_ETH_PRS_INPUT_SIZE (IRO[28].size)
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003548#define ETH_RX_RATE_LIMIT_OFFSET(pf_id) \
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003549 (IRO[29].base + ((pf_id) * IRO[29].m1))
3550#define ETH_RX_RATE_LIMIT_SIZE (IRO[29].size)
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003551#define XSTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) \
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003552 (IRO[30].base + ((queue_id) * IRO[30].m1))
3553#define XSTORM_ETH_QUEUE_ZONE_SIZE (IRO[30].size)
3554#define TSTORM_SCSI_CMDQ_CONS_OFFSET(cmdq_queue_id) \
3555 (IRO[34].base + ((cmdq_queue_id) * IRO[34].m1))
3556#define TSTORM_SCSI_CMDQ_CONS_SIZE (IRO[34].size)
3557#define TSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) \
3558 (IRO[35].base + ((func_id) * IRO[35].m1) + ((bdq_id) * IRO[35].m2))
3559#define TSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[35].size)
3560#define MSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) \
3561 (IRO[36].base + ((func_id) * IRO[36].m1) + ((bdq_id) * IRO[36].m2))
3562#define MSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[36].size)
3563#define TSTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
3564 (IRO[37].base + ((pf_id) * IRO[37].m1))
3565#define TSTORM_ISCSI_RX_STATS_SIZE (IRO[37].size)
3566#define MSTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
3567 (IRO[38].base + ((pf_id) * IRO[38].m1))
3568#define MSTORM_ISCSI_RX_STATS_SIZE (IRO[38].size)
3569#define USTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
3570 (IRO[39].base + ((pf_id) * IRO[39].m1))
3571#define USTORM_ISCSI_RX_STATS_SIZE (IRO[39].size)
3572#define XSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
3573 (IRO[40].base + ((pf_id) * IRO[40].m1))
3574#define XSTORM_ISCSI_TX_STATS_SIZE (IRO[40].size)
3575#define YSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
3576 (IRO[41].base + ((pf_id) * IRO[41].m1))
3577#define YSTORM_ISCSI_TX_STATS_SIZE (IRO[41].size)
3578#define PSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
3579 (IRO[42].base + ((pf_id) * IRO[42].m1))
3580#define PSTORM_ISCSI_TX_STATS_SIZE (IRO[42].size)
3581#define PSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \
3582 (IRO[45].base + ((rdma_stat_counter_id) * IRO[45].m1))
3583#define PSTORM_RDMA_QUEUE_STAT_SIZE (IRO[45].size)
3584#define TSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \
3585 (IRO[46].base + ((rdma_stat_counter_id) * IRO[46].m1))
3586#define TSTORM_RDMA_QUEUE_STAT_SIZE (IRO[46].size)
Arun Easi1e128c82017-02-15 06:28:22 -08003587#define TSTORM_FCOE_RX_STATS_OFFSET(pf_id) \
3588 (IRO[43].base + ((pf_id) * IRO[43].m1))
3589#define PSTORM_FCOE_TX_STATS_OFFSET(pf_id) \
3590 (IRO[44].base + ((pf_id) * IRO[44].m1))
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003591
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003592static const struct iro iro_arr[47] = {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003593 {0x0, 0x0, 0x0, 0x0, 0x8},
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02003594 {0x4cb0, 0x80, 0x0, 0x0, 0x80},
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003595 {0x6318, 0x20, 0x0, 0x0, 0x20},
3596 {0xb00, 0x8, 0x0, 0x0, 0x4},
3597 {0xa80, 0x8, 0x0, 0x0, 0x4},
3598 {0x0, 0x8, 0x0, 0x0, 0x2},
3599 {0x80, 0x8, 0x0, 0x0, 0x4},
3600 {0x84, 0x8, 0x0, 0x0, 0x2},
3601 {0x4bc0, 0x0, 0x0, 0x0, 0x78},
3602 {0x3df0, 0x0, 0x0, 0x0, 0x78},
3603 {0x29b0, 0x0, 0x0, 0x0, 0x78},
3604 {0x4c38, 0x0, 0x0, 0x0, 0x78},
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003605 {0x4990, 0x0, 0x0, 0x0, 0x78},
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003606 {0x7e48, 0x0, 0x0, 0x0, 0x78},
3607 {0xa28, 0x8, 0x0, 0x0, 0x8},
3608 {0x60f8, 0x10, 0x0, 0x0, 0x10},
3609 {0xb820, 0x30, 0x0, 0x0, 0x30},
3610 {0x95b8, 0x30, 0x0, 0x0, 0x30},
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003611 {0x4b60, 0x80, 0x0, 0x0, 0x40},
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003612 {0x1f8, 0x4, 0x0, 0x0, 0x4},
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003613 {0x53a0, 0x80, 0x4, 0x0, 0x4},
3614 {0xc8f0, 0x0, 0x0, 0x0, 0x4},
3615 {0x4ba0, 0x80, 0x0, 0x0, 0x20},
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003616 {0x8050, 0x40, 0x0, 0x0, 0x30},
3617 {0xe770, 0x60, 0x0, 0x0, 0x60},
3618 {0x2b48, 0x80, 0x0, 0x0, 0x38},
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003619 {0xf188, 0x78, 0x0, 0x0, 0x78},
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003620 {0x1f8, 0x4, 0x0, 0x0, 0x4},
3621 {0xacf0, 0x0, 0x0, 0x0, 0xf0},
3622 {0xade0, 0x8, 0x0, 0x0, 0x8},
3623 {0x1f8, 0x8, 0x0, 0x0, 0x8},
3624 {0xac0, 0x8, 0x0, 0x0, 0x8},
3625 {0x2578, 0x8, 0x0, 0x0, 0x8},
3626 {0x24f8, 0x8, 0x0, 0x0, 0x8},
3627 {0x0, 0x8, 0x0, 0x0, 0x8},
3628 {0x200, 0x10, 0x8, 0x0, 0x8},
3629 {0xb78, 0x10, 0x8, 0x0, 0x2},
3630 {0xd888, 0x38, 0x0, 0x0, 0x24},
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003631 {0x12c38, 0x10, 0x0, 0x0, 0x8},
3632 {0x11aa0, 0x38, 0x0, 0x0, 0x18},
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02003633 {0xa8c0, 0x38, 0x0, 0x0, 0x10},
3634 {0x86f8, 0x30, 0x0, 0x0, 0x18},
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003635 {0x101f8, 0x10, 0x0, 0x0, 0x10},
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003636 {0xdd08, 0x48, 0x0, 0x0, 0x38},
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003637 {0x10660, 0x20, 0x0, 0x0, 0x20},
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003638 {0x2b80, 0x80, 0x0, 0x0, 0x10},
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02003639 {0x5020, 0x10, 0x0, 0x0, 0x10},
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003640};
3641
3642/* Runtime array offsets */
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003643#define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET 0
3644#define DORQ_REG_PF_MAX_ICID_1_RT_OFFSET 1
3645#define DORQ_REG_PF_MAX_ICID_2_RT_OFFSET 2
3646#define DORQ_REG_PF_MAX_ICID_3_RT_OFFSET 3
3647#define DORQ_REG_PF_MAX_ICID_4_RT_OFFSET 4
3648#define DORQ_REG_PF_MAX_ICID_5_RT_OFFSET 5
3649#define DORQ_REG_PF_MAX_ICID_6_RT_OFFSET 6
3650#define DORQ_REG_PF_MAX_ICID_7_RT_OFFSET 7
3651#define DORQ_REG_VF_MAX_ICID_0_RT_OFFSET 8
3652#define DORQ_REG_VF_MAX_ICID_1_RT_OFFSET 9
3653#define DORQ_REG_VF_MAX_ICID_2_RT_OFFSET 10
3654#define DORQ_REG_VF_MAX_ICID_3_RT_OFFSET 11
3655#define DORQ_REG_VF_MAX_ICID_4_RT_OFFSET 12
3656#define DORQ_REG_VF_MAX_ICID_5_RT_OFFSET 13
3657#define DORQ_REG_VF_MAX_ICID_6_RT_OFFSET 14
3658#define DORQ_REG_VF_MAX_ICID_7_RT_OFFSET 15
3659#define DORQ_REG_PF_WAKE_ALL_RT_OFFSET 16
3660#define DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET 17
3661#define IGU_REG_PF_CONFIGURATION_RT_OFFSET 18
3662#define IGU_REG_VF_CONFIGURATION_RT_OFFSET 19
3663#define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET 20
3664#define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET 21
3665#define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET 22
3666#define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET 23
3667#define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET 24
3668#define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 761
3669#define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736
3670#define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 761
3671#define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736
3672#define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET 1497
3673#define CAU_REG_SB_ADDR_MEMORY_RT_SIZE 736
3674#define CAU_REG_PI_MEMORY_RT_OFFSET 2233
3675#define CAU_REG_PI_MEMORY_RT_SIZE 4416
3676#define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET 6649
3677#define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET 6650
3678#define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET 6651
3679#define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET 6652
3680#define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET 6653
3681#define PRS_REG_SEARCH_TCP_RT_OFFSET 6654
3682#define PRS_REG_SEARCH_FCOE_RT_OFFSET 6655
3683#define PRS_REG_SEARCH_ROCE_RT_OFFSET 6656
3684#define PRS_REG_ROCE_DEST_QP_MAX_VF_RT_OFFSET 6657
3685#define PRS_REG_ROCE_DEST_QP_MAX_PF_RT_OFFSET 6658
3686#define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET 6659
3687#define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET 6660
3688#define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET 6661
3689#define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET 6662
3690#define PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET 6663
3691#define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET 6664
3692#define SRC_REG_FIRSTFREE_RT_OFFSET 6665
3693#define SRC_REG_FIRSTFREE_RT_SIZE 2
3694#define SRC_REG_LASTFREE_RT_OFFSET 6667
3695#define SRC_REG_LASTFREE_RT_SIZE 2
3696#define SRC_REG_COUNTFREE_RT_OFFSET 6669
3697#define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET 6670
3698#define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET 6671
3699#define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET 6672
3700#define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET 6673
3701#define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET 6674
3702#define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET 6675
3703#define PSWRQ2_REG_TSDM_P_SIZE_RT_OFFSET 6676
3704#define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET 6677
3705#define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET 6678
3706#define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET 6679
3707#define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET 6680
3708#define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET 6681
3709#define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET 6682
3710#define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET 6683
3711#define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET 6684
3712#define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET 6685
3713#define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET 6686
3714#define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET 6687
3715#define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET 6688
3716#define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6689
3717#define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6690
3718#define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6691
3719#define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET 6692
3720#define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET 6693
3721#define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET 6694
3722#define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET 6695
3723#define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET 6696
3724#define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET 6697
3725#define PSWRQ2_REG_VF_BASE_RT_OFFSET 6698
3726#define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET 6699
3727#define PSWRQ2_REG_WR_MBS0_RT_OFFSET 6700
3728#define PSWRQ2_REG_RD_MBS0_RT_OFFSET 6701
3729#define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET 6702
3730#define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET 6703
3731#define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET 6704
3732#define PSWRQ2_REG_ILT_MEMORY_RT_SIZE 22000
3733#define PGLUE_REG_B_VF_BASE_RT_OFFSET 28704
3734#define PGLUE_REG_B_MSDM_OFFSET_MASK_B_RT_OFFSET 28705
3735#define PGLUE_REG_B_MSDM_VF_SHIFT_B_RT_OFFSET 28706
3736#define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET 28707
3737#define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET 28708
3738#define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET 28709
3739#define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET 28710
3740#define TM_REG_VF_ENABLE_CONN_RT_OFFSET 28711
3741#define TM_REG_PF_ENABLE_CONN_RT_OFFSET 28712
3742#define TM_REG_PF_ENABLE_TASK_RT_OFFSET 28713
3743#define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET 28714
3744#define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET 28715
3745#define TM_REG_CONFIG_CONN_MEM_RT_OFFSET 28716
3746#define TM_REG_CONFIG_CONN_MEM_RT_SIZE 416
3747#define TM_REG_CONFIG_TASK_MEM_RT_OFFSET 29132
3748#define TM_REG_CONFIG_TASK_MEM_RT_SIZE 512
3749#define QM_REG_MAXPQSIZE_0_RT_OFFSET 29644
3750#define QM_REG_MAXPQSIZE_1_RT_OFFSET 29645
3751#define QM_REG_MAXPQSIZE_2_RT_OFFSET 29646
3752#define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET 29647
3753#define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET 29648
3754#define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET 29649
3755#define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET 29650
3756#define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET 29651
3757#define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET 29652
3758#define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET 29653
3759#define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET 29654
3760#define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET 29655
3761#define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET 29656
3762#define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET 29657
3763#define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET 29658
3764#define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET 29659
3765#define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET 29660
3766#define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET 29661
3767#define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET 29662
3768#define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET 29663
3769#define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET 29664
3770#define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET 29665
3771#define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET 29666
3772#define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET 29667
3773#define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET 29668
3774#define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET 29669
3775#define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET 29670
3776#define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET 29671
3777#define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET 29672
3778#define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET 29673
3779#define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET 29674
3780#define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET 29675
3781#define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET 29676
3782#define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET 29677
3783#define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET 29678
3784#define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET 29679
3785#define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET 29680
3786#define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET 29681
3787#define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET 29682
3788#define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET 29683
3789#define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET 29684
3790#define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET 29685
3791#define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET 29686
3792#define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET 29687
3793#define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET 29688
3794#define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET 29689
3795#define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET 29690
3796#define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET 29691
3797#define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET 29692
3798#define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET 29693
3799#define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET 29694
3800#define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET 29695
3801#define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET 29696
3802#define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET 29697
3803#define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET 29698
3804#define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET 29699
3805#define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET 29700
3806#define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET 29701
3807#define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET 29702
3808#define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET 29703
3809#define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET 29704
3810#define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET 29705
3811#define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET 29706
3812#define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET 29707
3813#define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET 29708
3814#define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET 29709
3815#define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET 29710
3816#define QM_REG_BASEADDROTHERPQ_RT_OFFSET 29711
3817#define QM_REG_BASEADDROTHERPQ_RT_SIZE 128
3818#define QM_REG_VOQCRDLINE_RT_OFFSET 29839
3819#define QM_REG_VOQCRDLINE_RT_SIZE 20
3820#define QM_REG_VOQINITCRDLINE_RT_OFFSET 29859
3821#define QM_REG_VOQINITCRDLINE_RT_SIZE 20
3822#define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET 29879
3823#define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET 29880
3824#define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET 29881
3825#define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET 29882
3826#define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET 29883
3827#define QM_REG_WRROTHERPQGRP_0_RT_OFFSET 29884
3828#define QM_REG_WRROTHERPQGRP_1_RT_OFFSET 29885
3829#define QM_REG_WRROTHERPQGRP_2_RT_OFFSET 29886
3830#define QM_REG_WRROTHERPQGRP_3_RT_OFFSET 29887
3831#define QM_REG_WRROTHERPQGRP_4_RT_OFFSET 29888
3832#define QM_REG_WRROTHERPQGRP_5_RT_OFFSET 29889
3833#define QM_REG_WRROTHERPQGRP_6_RT_OFFSET 29890
3834#define QM_REG_WRROTHERPQGRP_7_RT_OFFSET 29891
3835#define QM_REG_WRROTHERPQGRP_8_RT_OFFSET 29892
3836#define QM_REG_WRROTHERPQGRP_9_RT_OFFSET 29893
3837#define QM_REG_WRROTHERPQGRP_10_RT_OFFSET 29894
3838#define QM_REG_WRROTHERPQGRP_11_RT_OFFSET 29895
3839#define QM_REG_WRROTHERPQGRP_12_RT_OFFSET 29896
3840#define QM_REG_WRROTHERPQGRP_13_RT_OFFSET 29897
3841#define QM_REG_WRROTHERPQGRP_14_RT_OFFSET 29898
3842#define QM_REG_WRROTHERPQGRP_15_RT_OFFSET 29899
3843#define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET 29900
3844#define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET 29901
3845#define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET 29902
3846#define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET 29903
3847#define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET 29904
3848#define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET 29905
3849#define QM_REG_PQTX2PF_0_RT_OFFSET 29906
3850#define QM_REG_PQTX2PF_1_RT_OFFSET 29907
3851#define QM_REG_PQTX2PF_2_RT_OFFSET 29908
3852#define QM_REG_PQTX2PF_3_RT_OFFSET 29909
3853#define QM_REG_PQTX2PF_4_RT_OFFSET 29910
3854#define QM_REG_PQTX2PF_5_RT_OFFSET 29911
3855#define QM_REG_PQTX2PF_6_RT_OFFSET 29912
3856#define QM_REG_PQTX2PF_7_RT_OFFSET 29913
3857#define QM_REG_PQTX2PF_8_RT_OFFSET 29914
3858#define QM_REG_PQTX2PF_9_RT_OFFSET 29915
3859#define QM_REG_PQTX2PF_10_RT_OFFSET 29916
3860#define QM_REG_PQTX2PF_11_RT_OFFSET 29917
3861#define QM_REG_PQTX2PF_12_RT_OFFSET 29918
3862#define QM_REG_PQTX2PF_13_RT_OFFSET 29919
3863#define QM_REG_PQTX2PF_14_RT_OFFSET 29920
3864#define QM_REG_PQTX2PF_15_RT_OFFSET 29921
3865#define QM_REG_PQTX2PF_16_RT_OFFSET 29922
3866#define QM_REG_PQTX2PF_17_RT_OFFSET 29923
3867#define QM_REG_PQTX2PF_18_RT_OFFSET 29924
3868#define QM_REG_PQTX2PF_19_RT_OFFSET 29925
3869#define QM_REG_PQTX2PF_20_RT_OFFSET 29926
3870#define QM_REG_PQTX2PF_21_RT_OFFSET 29927
3871#define QM_REG_PQTX2PF_22_RT_OFFSET 29928
3872#define QM_REG_PQTX2PF_23_RT_OFFSET 29929
3873#define QM_REG_PQTX2PF_24_RT_OFFSET 29930
3874#define QM_REG_PQTX2PF_25_RT_OFFSET 29931
3875#define QM_REG_PQTX2PF_26_RT_OFFSET 29932
3876#define QM_REG_PQTX2PF_27_RT_OFFSET 29933
3877#define QM_REG_PQTX2PF_28_RT_OFFSET 29934
3878#define QM_REG_PQTX2PF_29_RT_OFFSET 29935
3879#define QM_REG_PQTX2PF_30_RT_OFFSET 29936
3880#define QM_REG_PQTX2PF_31_RT_OFFSET 29937
3881#define QM_REG_PQTX2PF_32_RT_OFFSET 29938
3882#define QM_REG_PQTX2PF_33_RT_OFFSET 29939
3883#define QM_REG_PQTX2PF_34_RT_OFFSET 29940
3884#define QM_REG_PQTX2PF_35_RT_OFFSET 29941
3885#define QM_REG_PQTX2PF_36_RT_OFFSET 29942
3886#define QM_REG_PQTX2PF_37_RT_OFFSET 29943
3887#define QM_REG_PQTX2PF_38_RT_OFFSET 29944
3888#define QM_REG_PQTX2PF_39_RT_OFFSET 29945
3889#define QM_REG_PQTX2PF_40_RT_OFFSET 29946
3890#define QM_REG_PQTX2PF_41_RT_OFFSET 29947
3891#define QM_REG_PQTX2PF_42_RT_OFFSET 29948
3892#define QM_REG_PQTX2PF_43_RT_OFFSET 29949
3893#define QM_REG_PQTX2PF_44_RT_OFFSET 29950
3894#define QM_REG_PQTX2PF_45_RT_OFFSET 29951
3895#define QM_REG_PQTX2PF_46_RT_OFFSET 29952
3896#define QM_REG_PQTX2PF_47_RT_OFFSET 29953
3897#define QM_REG_PQTX2PF_48_RT_OFFSET 29954
3898#define QM_REG_PQTX2PF_49_RT_OFFSET 29955
3899#define QM_REG_PQTX2PF_50_RT_OFFSET 29956
3900#define QM_REG_PQTX2PF_51_RT_OFFSET 29957
3901#define QM_REG_PQTX2PF_52_RT_OFFSET 29958
3902#define QM_REG_PQTX2PF_53_RT_OFFSET 29959
3903#define QM_REG_PQTX2PF_54_RT_OFFSET 29960
3904#define QM_REG_PQTX2PF_55_RT_OFFSET 29961
3905#define QM_REG_PQTX2PF_56_RT_OFFSET 29962
3906#define QM_REG_PQTX2PF_57_RT_OFFSET 29963
3907#define QM_REG_PQTX2PF_58_RT_OFFSET 29964
3908#define QM_REG_PQTX2PF_59_RT_OFFSET 29965
3909#define QM_REG_PQTX2PF_60_RT_OFFSET 29966
3910#define QM_REG_PQTX2PF_61_RT_OFFSET 29967
3911#define QM_REG_PQTX2PF_62_RT_OFFSET 29968
3912#define QM_REG_PQTX2PF_63_RT_OFFSET 29969
3913#define QM_REG_PQOTHER2PF_0_RT_OFFSET 29970
3914#define QM_REG_PQOTHER2PF_1_RT_OFFSET 29971
3915#define QM_REG_PQOTHER2PF_2_RT_OFFSET 29972
3916#define QM_REG_PQOTHER2PF_3_RT_OFFSET 29973
3917#define QM_REG_PQOTHER2PF_4_RT_OFFSET 29974
3918#define QM_REG_PQOTHER2PF_5_RT_OFFSET 29975
3919#define QM_REG_PQOTHER2PF_6_RT_OFFSET 29976
3920#define QM_REG_PQOTHER2PF_7_RT_OFFSET 29977
3921#define QM_REG_PQOTHER2PF_8_RT_OFFSET 29978
3922#define QM_REG_PQOTHER2PF_9_RT_OFFSET 29979
3923#define QM_REG_PQOTHER2PF_10_RT_OFFSET 29980
3924#define QM_REG_PQOTHER2PF_11_RT_OFFSET 29981
3925#define QM_REG_PQOTHER2PF_12_RT_OFFSET 29982
3926#define QM_REG_PQOTHER2PF_13_RT_OFFSET 29983
3927#define QM_REG_PQOTHER2PF_14_RT_OFFSET 29984
3928#define QM_REG_PQOTHER2PF_15_RT_OFFSET 29985
3929#define QM_REG_RLGLBLPERIOD_0_RT_OFFSET 29986
3930#define QM_REG_RLGLBLPERIOD_1_RT_OFFSET 29987
3931#define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET 29988
3932#define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET 29989
3933#define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET 29990
3934#define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET 29991
3935#define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET 29992
3936#define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET 29993
3937#define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET 29994
3938#define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET 29995
3939#define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET 29996
3940#define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET 29997
3941#define QM_REG_RLGLBLINCVAL_RT_OFFSET 29998
3942#define QM_REG_RLGLBLINCVAL_RT_SIZE 256
3943#define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET 30254
3944#define QM_REG_RLGLBLUPPERBOUND_RT_SIZE 256
3945#define QM_REG_RLGLBLCRD_RT_OFFSET 30510
3946#define QM_REG_RLGLBLCRD_RT_SIZE 256
3947#define QM_REG_RLGLBLENABLE_RT_OFFSET 30766
3948#define QM_REG_RLPFPERIOD_RT_OFFSET 30767
3949#define QM_REG_RLPFPERIODTIMER_RT_OFFSET 30768
3950#define QM_REG_RLPFINCVAL_RT_OFFSET 30769
3951#define QM_REG_RLPFINCVAL_RT_SIZE 16
3952#define QM_REG_RLPFUPPERBOUND_RT_OFFSET 30785
3953#define QM_REG_RLPFUPPERBOUND_RT_SIZE 16
3954#define QM_REG_RLPFCRD_RT_OFFSET 30801
3955#define QM_REG_RLPFCRD_RT_SIZE 16
3956#define QM_REG_RLPFENABLE_RT_OFFSET 30817
3957#define QM_REG_RLPFVOQENABLE_RT_OFFSET 30818
3958#define QM_REG_WFQPFWEIGHT_RT_OFFSET 30819
3959#define QM_REG_WFQPFWEIGHT_RT_SIZE 16
3960#define QM_REG_WFQPFUPPERBOUND_RT_OFFSET 30835
3961#define QM_REG_WFQPFUPPERBOUND_RT_SIZE 16
3962#define QM_REG_WFQPFCRD_RT_OFFSET 30851
3963#define QM_REG_WFQPFCRD_RT_SIZE 160
3964#define QM_REG_WFQPFENABLE_RT_OFFSET 31011
3965#define QM_REG_WFQVPENABLE_RT_OFFSET 31012
3966#define QM_REG_BASEADDRTXPQ_RT_OFFSET 31013
3967#define QM_REG_BASEADDRTXPQ_RT_SIZE 512
3968#define QM_REG_TXPQMAP_RT_OFFSET 31525
3969#define QM_REG_TXPQMAP_RT_SIZE 512
3970#define QM_REG_WFQVPWEIGHT_RT_OFFSET 32037
3971#define QM_REG_WFQVPWEIGHT_RT_SIZE 512
3972#define QM_REG_WFQVPCRD_RT_OFFSET 32549
3973#define QM_REG_WFQVPCRD_RT_SIZE 512
3974#define QM_REG_WFQVPMAP_RT_OFFSET 33061
3975#define QM_REG_WFQVPMAP_RT_SIZE 512
3976#define QM_REG_WFQPFCRD_MSB_RT_OFFSET 33573
3977#define QM_REG_WFQPFCRD_MSB_RT_SIZE 160
3978#define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET 33733
3979#define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET 33734
3980#define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET 33735
3981#define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET 33736
3982#define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET 33737
3983#define NIG_REG_OUTER_TAG_VALUE_MASK_RT_OFFSET 33738
3984#define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET 33739
3985#define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET 33740
3986#define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE 4
3987#define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_OFFSET 33744
3988#define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_SIZE 4
3989#define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET 33748
3990#define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE 4
3991#define NIG_REG_LLH_FUNC_NO_TAG_RT_OFFSET 33752
3992#define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET 33753
3993#define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE 32
3994#define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET 33785
3995#define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE 16
3996#define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET 33801
3997#define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE 16
3998#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 33817
3999#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 16
4000#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET 33833
4001#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE 16
4002#define NIG_REG_TX_EDPM_CTRL_RT_OFFSET 33849
4003#define NIG_REG_ROCE_DUPLICATE_TO_HOST_RT_OFFSET 33850
4004#define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET 33851
4005#define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET 33852
4006#define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET 33853
4007#define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET 33854
4008#define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET 33855
4009#define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET 33856
4010#define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 33857
4011#define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET 33858
4012#define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET 33859
4013#define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET 33860
4014#define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 33861
4015#define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET 33862
4016#define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET 33863
4017#define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET 33864
4018#define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET 33865
4019#define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET 33866
4020#define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET 33867
4021#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET 33868
4022#define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET 33869
4023#define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET 33870
4024#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET 33871
4025#define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET 33872
4026#define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET 33873
4027#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET 33874
4028#define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET 33875
4029#define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET 33876
4030#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET 33877
4031#define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET 33878
4032#define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET 33879
4033#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET 33880
4034#define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET 33881
4035#define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET 33882
4036#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET 33883
4037#define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET 33884
4038#define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET 33885
4039#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET 33886
4040#define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET 33887
4041#define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET 33888
4042#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET 33889
4043#define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET 33890
4044#define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET 33891
4045#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET 33892
4046#define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET 33893
4047#define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET 33894
4048#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET 33895
4049#define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET 33896
4050#define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET 33897
4051#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET 33898
4052#define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET 33899
4053#define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET 33900
4054#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET 33901
4055#define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET 33902
4056#define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET 33903
4057#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET 33904
4058#define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET 33905
4059#define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET 33906
4060#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET 33907
4061#define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET 33908
4062#define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET 33909
4063#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET 33910
4064#define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET 33911
4065#define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET 33912
4066#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET 33913
4067#define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET 33914
4068#define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET 33915
4069#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET 33916
4070#define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET 33917
4071#define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET 33918
4072#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET 33919
4073#define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET 33920
4074#define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET 33921
4075#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET 33922
4076#define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET 33923
4077#define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET 33924
4078#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET 33925
4079#define XCM_REG_CON_PHY_Q3_RT_OFFSET 33926
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004080
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004081#define RUNTIME_ARRAY_SIZE 33927
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004082
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05004083/* The eth storm context for the Tstorm */
4084struct tstorm_eth_conn_st_ctx {
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004085 __le32 reserved[4];
4086};
4087
4088/* The eth storm context for the Pstorm */
4089struct pstorm_eth_conn_st_ctx {
4090 __le32 reserved[8];
4091};
4092
4093/* The eth storm context for the Xstorm */
4094struct xstorm_eth_conn_st_ctx {
4095 __le32 reserved[60];
4096};
4097
4098struct xstorm_eth_conn_ag_ctx {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004099 u8 reserved0;
4100 u8 eth_state;
4101 u8 flags0;
4102#define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
4103#define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
4104#define XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK 0x1
4105#define XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT 1
4106#define XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK 0x1
4107#define XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT 2
4108#define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
4109#define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
4110#define XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK 0x1
4111#define XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT 4
4112#define XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK 0x1
4113#define XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT 5
4114#define XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK 0x1
4115#define XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT 6
4116#define XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK 0x1
4117#define XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT 7
4118 u8 flags1;
4119#define XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK 0x1
4120#define XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT 0
4121#define XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK 0x1
4122#define XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT 1
4123#define XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK 0x1
4124#define XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT 2
4125#define XSTORM_ETH_CONN_AG_CTX_BIT11_MASK 0x1
4126#define XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT 3
4127#define XSTORM_ETH_CONN_AG_CTX_BIT12_MASK 0x1
4128#define XSTORM_ETH_CONN_AG_CTX_BIT12_SHIFT 4
4129#define XSTORM_ETH_CONN_AG_CTX_BIT13_MASK 0x1
4130#define XSTORM_ETH_CONN_AG_CTX_BIT13_SHIFT 5
4131#define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
4132#define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
4133#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
4134#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004135 u8 flags2;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004136#define XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
4137#define XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 0
4138#define XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
4139#define XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 2
4140#define XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
4141#define XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 4
4142#define XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
4143#define XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 6
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004144 u8 flags3;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004145#define XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3
4146#define XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 0
4147#define XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3
4148#define XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 2
4149#define XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3
4150#define XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 4
4151#define XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3
4152#define XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 6
4153 u8 flags4;
4154#define XSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3
4155#define XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 0
4156#define XSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3
4157#define XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 2
4158#define XSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3
4159#define XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 4
4160#define XSTORM_ETH_CONN_AG_CTX_CF11_MASK 0x3
4161#define XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT 6
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004162 u8 flags5;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004163#define XSTORM_ETH_CONN_AG_CTX_CF12_MASK 0x3
4164#define XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT 0
4165#define XSTORM_ETH_CONN_AG_CTX_CF13_MASK 0x3
4166#define XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT 2
4167#define XSTORM_ETH_CONN_AG_CTX_CF14_MASK 0x3
4168#define XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT 4
4169#define XSTORM_ETH_CONN_AG_CTX_CF15_MASK 0x3
4170#define XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT 6
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004171 u8 flags6;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004172#define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3
4173#define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0
4174#define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
4175#define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2
4176#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK 0x3
4177#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT 4
4178#define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
4179#define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004180 u8 flags7;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004181#define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
4182#define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
4183#define XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK 0x3
4184#define XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT 2
4185#define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK 0x3
4186#define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT 4
4187#define XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
4188#define XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 6
4189#define XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
4190#define XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 7
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004191 u8 flags8;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004192#define XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
4193#define XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 0
4194#define XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
4195#define XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 1
4196#define XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1
4197#define XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 2
4198#define XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1
4199#define XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 3
4200#define XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1
4201#define XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 4
4202#define XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1
4203#define XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 5
4204#define XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1
4205#define XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 6
4206#define XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1
4207#define XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 7
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004208 u8 flags9;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004209#define XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1
4210#define XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 0
4211#define XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK 0x1
4212#define XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT 1
4213#define XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK 0x1
4214#define XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT 2
4215#define XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK 0x1
4216#define XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT 3
4217#define XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK 0x1
4218#define XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT 4
4219#define XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK 0x1
4220#define XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT 5
4221#define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1
4222#define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6
4223#define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
4224#define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004225 u8 flags10;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004226#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
4227#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
4228#define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
4229#define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
4230#define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
4231#define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
4232#define XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK 0x1
4233#define XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT 3
4234#define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
4235#define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
4236#define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004237#define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004238#define XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK 0x1
4239#define XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT 6
4240#define XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK 0x1
4241#define XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT 7
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004242 u8 flags11;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004243#define XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK 0x1
4244#define XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT 0
4245#define XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK 0x1
4246#define XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT 1
4247#define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
4248#define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
4249#define XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
4250#define XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 3
4251#define XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1
4252#define XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 4
4253#define XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
4254#define XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 5
4255#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
4256#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
4257#define XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK 0x1
4258#define XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT 7
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004259 u8 flags12;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004260#define XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK 0x1
4261#define XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT 0
4262#define XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK 0x1
4263#define XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT 1
4264#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
4265#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
4266#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
4267#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
4268#define XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK 0x1
4269#define XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT 4
4270#define XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK 0x1
4271#define XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT 5
4272#define XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK 0x1
4273#define XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT 6
4274#define XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK 0x1
4275#define XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT 7
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004276 u8 flags13;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004277#define XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK 0x1
4278#define XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT 0
4279#define XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK 0x1
4280#define XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT 1
4281#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
4282#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
4283#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
4284#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
4285#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
4286#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
4287#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
4288#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
4289#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
4290#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
4291#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
4292#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004293 u8 flags14;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004294#define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1
4295#define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0
4296#define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1
4297#define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1
4298#define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1
4299#define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2
4300#define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1
4301#define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3
4302#define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1
4303#define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4
4304#define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
4305#define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
4306#define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK 0x3
4307#define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT 6
4308 u8 edpm_event_id;
4309 __le16 physical_q0;
4310 __le16 quota;
4311 __le16 edpm_num_bds;
4312 __le16 tx_bd_cons;
4313 __le16 tx_bd_prod;
4314 __le16 tx_class;
4315 __le16 conn_dpi;
4316 u8 byte3;
4317 u8 byte4;
4318 u8 byte5;
4319 u8 byte6;
4320 __le32 reg0;
4321 __le32 reg1;
4322 __le32 reg2;
4323 __le32 reg3;
4324 __le32 reg4;
4325 __le32 reg5;
4326 __le32 reg6;
4327 __le16 word7;
4328 __le16 word8;
4329 __le16 word9;
4330 __le16 word10;
4331 __le32 reg7;
4332 __le32 reg8;
4333 __le32 reg9;
4334 u8 byte7;
4335 u8 byte8;
4336 u8 byte9;
4337 u8 byte10;
4338 u8 byte11;
4339 u8 byte12;
4340 u8 byte13;
4341 u8 byte14;
4342 u8 byte15;
4343 u8 byte16;
4344 __le16 word11;
4345 __le32 reg10;
4346 __le32 reg11;
4347 __le32 reg12;
4348 __le32 reg13;
4349 __le32 reg14;
4350 __le32 reg15;
4351 __le32 reg16;
4352 __le32 reg17;
4353 __le32 reg18;
4354 __le32 reg19;
4355 __le16 word12;
4356 __le16 word13;
4357 __le16 word14;
4358 __le16 word15;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004359};
4360
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05004361/* The eth storm context for the Ystorm */
4362struct ystorm_eth_conn_st_ctx {
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004363 __le32 reserved[8];
4364};
4365
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05004366struct ystorm_eth_conn_ag_ctx {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004367 u8 byte0;
4368 u8 state;
4369 u8 flags0;
4370#define YSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
4371#define YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
4372#define YSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
4373#define YSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
4374#define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3
4375#define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 2
4376#define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK 0x3
4377#define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_SHIFT 4
4378#define YSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
4379#define YSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004380 u8 flags1;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004381#define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1
4382#define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 0
4383#define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK 0x1
4384#define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_SHIFT 1
4385#define YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
4386#define YSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
4387#define YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
4388#define YSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3
4389#define YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
4390#define YSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4
4391#define YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
4392#define YSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5
4393#define YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
4394#define YSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6
4395#define YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
4396#define YSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7
4397 u8 tx_q0_int_coallecing_timeset;
4398 u8 byte3;
4399 __le16 word0;
4400 __le32 terminate_spqe;
4401 __le32 reg1;
4402 __le16 tx_bd_cons_upd;
4403 __le16 word2;
4404 __le16 word3;
4405 __le16 word4;
4406 __le32 reg2;
4407 __le32 reg3;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004408};
4409
4410struct tstorm_eth_conn_ag_ctx {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004411 u8 byte0;
4412 u8 byte1;
4413 u8 flags0;
4414#define TSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
4415#define TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
4416#define TSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
4417#define TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
4418#define TSTORM_ETH_CONN_AG_CTX_BIT2_MASK 0x1
4419#define TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT 2
4420#define TSTORM_ETH_CONN_AG_CTX_BIT3_MASK 0x1
4421#define TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT 3
4422#define TSTORM_ETH_CONN_AG_CTX_BIT4_MASK 0x1
4423#define TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT 4
4424#define TSTORM_ETH_CONN_AG_CTX_BIT5_MASK 0x1
4425#define TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT 5
4426#define TSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
4427#define TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 6
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004428 u8 flags1;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004429#define TSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
4430#define TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 0
4431#define TSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
4432#define TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 2
4433#define TSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
4434#define TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 4
4435#define TSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3
4436#define TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 6
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004437 u8 flags2;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004438#define TSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3
4439#define TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 0
4440#define TSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3
4441#define TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 2
4442#define TSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3
4443#define TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 4
4444#define TSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3
4445#define TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 6
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004446 u8 flags3;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004447#define TSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3
4448#define TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 0
4449#define TSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3
4450#define TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 2
4451#define TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
4452#define TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 4
4453#define TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
4454#define TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 5
4455#define TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
4456#define TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 6
4457#define TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
4458#define TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 7
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004459 u8 flags4;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004460#define TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1
4461#define TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 0
4462#define TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1
4463#define TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 1
4464#define TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1
4465#define TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 2
4466#define TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1
4467#define TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 3
4468#define TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1
4469#define TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 4
4470#define TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1
4471#define TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 5
4472#define TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1
4473#define TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 6
4474#define TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
4475#define TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004476 u8 flags5;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004477#define TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
4478#define TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
4479#define TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
4480#define TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1
4481#define TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
4482#define TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2
4483#define TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
4484#define TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3
4485#define TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
4486#define TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4
4487#define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK 0x1
4488#define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT 5
4489#define TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
4490#define TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6
4491#define TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1
4492#define TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7
4493 __le32 reg0;
4494 __le32 reg1;
4495 __le32 reg2;
4496 __le32 reg3;
4497 __le32 reg4;
4498 __le32 reg5;
4499 __le32 reg6;
4500 __le32 reg7;
4501 __le32 reg8;
4502 u8 byte2;
4503 u8 byte3;
4504 __le16 rx_bd_cons;
4505 u8 byte4;
4506 u8 byte5;
4507 __le16 rx_bd_prod;
4508 __le16 word2;
4509 __le16 word3;
4510 __le32 reg9;
4511 __le32 reg10;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004512};
4513
4514struct ustorm_eth_conn_ag_ctx {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004515 u8 byte0;
4516 u8 byte1;
4517 u8 flags0;
4518#define USTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
4519#define USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
4520#define USTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
4521#define USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
4522#define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK 0x3
4523#define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_SHIFT 2
4524#define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK 0x3
4525#define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_SHIFT 4
4526#define USTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
4527#define USTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004528 u8 flags1;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004529#define USTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
4530#define USTORM_ETH_CONN_AG_CTX_CF3_SHIFT 0
4531#define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK 0x3
4532#define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT 2
4533#define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK 0x3
4534#define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT 4
4535#define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3
4536#define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 6
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004537 u8 flags2;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004538#define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK 0x1
4539#define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT 0
4540#define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK 0x1
4541#define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_SHIFT 1
4542#define USTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
4543#define USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
4544#define USTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
4545#define USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 3
4546#define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK 0x1
4547#define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT 4
4548#define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK 0x1
4549#define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT 5
4550#define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1
4551#define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 6
4552#define USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
4553#define USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004554 u8 flags3;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004555#define USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
4556#define USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
4557#define USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
4558#define USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1
4559#define USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
4560#define USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2
4561#define USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
4562#define USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3
4563#define USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
4564#define USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4
4565#define USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1
4566#define USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 5
4567#define USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
4568#define USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6
4569#define USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1
4570#define USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7
4571 u8 byte2;
4572 u8 byte3;
4573 __le16 word0;
4574 __le16 tx_bd_cons;
4575 __le32 reg0;
4576 __le32 reg1;
4577 __le32 reg2;
4578 __le32 tx_int_coallecing_timeset;
4579 __le16 tx_drv_bd_cons;
4580 __le16 rx_drv_cqe_cons;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004581};
4582
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05004583/* The eth storm context for the Ustorm */
4584struct ustorm_eth_conn_st_ctx {
4585 __le32 reserved[40];
4586};
4587
4588/* The eth storm context for the Mstorm */
4589struct mstorm_eth_conn_st_ctx {
4590 __le32 reserved[8];
4591};
4592
4593/* eth connection context */
4594struct eth_conn_context {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004595 struct tstorm_eth_conn_st_ctx tstorm_st_context;
4596 struct regpair tstorm_st_padding[2];
4597 struct pstorm_eth_conn_st_ctx pstorm_st_context;
4598 struct xstorm_eth_conn_st_ctx xstorm_st_context;
4599 struct xstorm_eth_conn_ag_ctx xstorm_ag_context;
4600 struct ystorm_eth_conn_st_ctx ystorm_st_context;
4601 struct ystorm_eth_conn_ag_ctx ystorm_ag_context;
4602 struct tstorm_eth_conn_ag_ctx tstorm_ag_context;
4603 struct ustorm_eth_conn_ag_ctx ustorm_ag_context;
4604 struct ustorm_eth_conn_st_ctx ustorm_st_context;
4605 struct mstorm_eth_conn_st_ctx mstorm_st_context;
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05004606};
4607
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004608enum eth_error_code {
4609 ETH_OK = 0x00,
4610 ETH_FILTERS_MAC_ADD_FAIL_FULL,
4611 ETH_FILTERS_MAC_ADD_FAIL_FULL_MTT2,
4612 ETH_FILTERS_MAC_ADD_FAIL_DUP_MTT2,
4613 ETH_FILTERS_MAC_ADD_FAIL_DUP_STT2,
4614 ETH_FILTERS_MAC_DEL_FAIL_NOF,
4615 ETH_FILTERS_MAC_DEL_FAIL_NOF_MTT2,
4616 ETH_FILTERS_MAC_DEL_FAIL_NOF_STT2,
4617 ETH_FILTERS_MAC_ADD_FAIL_ZERO_MAC,
4618 ETH_FILTERS_VLAN_ADD_FAIL_FULL,
4619 ETH_FILTERS_VLAN_ADD_FAIL_DUP,
4620 ETH_FILTERS_VLAN_DEL_FAIL_NOF,
4621 ETH_FILTERS_VLAN_DEL_FAIL_NOF_TT1,
4622 ETH_FILTERS_PAIR_ADD_FAIL_DUP,
4623 ETH_FILTERS_PAIR_ADD_FAIL_FULL,
4624 ETH_FILTERS_PAIR_ADD_FAIL_FULL_MAC,
4625 ETH_FILTERS_PAIR_DEL_FAIL_NOF,
4626 ETH_FILTERS_PAIR_DEL_FAIL_NOF_TT1,
4627 ETH_FILTERS_PAIR_ADD_FAIL_ZERO_MAC,
4628 ETH_FILTERS_VNI_ADD_FAIL_FULL,
4629 ETH_FILTERS_VNI_ADD_FAIL_DUP,
4630 MAX_ETH_ERROR_CODE
4631};
4632
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004633enum eth_event_opcode {
4634 ETH_EVENT_UNUSED,
4635 ETH_EVENT_VPORT_START,
4636 ETH_EVENT_VPORT_UPDATE,
4637 ETH_EVENT_VPORT_STOP,
4638 ETH_EVENT_TX_QUEUE_START,
4639 ETH_EVENT_TX_QUEUE_STOP,
4640 ETH_EVENT_RX_QUEUE_START,
4641 ETH_EVENT_RX_QUEUE_UPDATE,
4642 ETH_EVENT_RX_QUEUE_STOP,
4643 ETH_EVENT_FILTERS_UPDATE,
4644 ETH_EVENT_RESERVED,
4645 ETH_EVENT_RESERVED2,
4646 ETH_EVENT_RESERVED3,
4647 ETH_EVENT_RX_ADD_UDP_FILTER,
4648 ETH_EVENT_RX_DELETE_UDP_FILTER,
4649 ETH_EVENT_RESERVED4,
4650 ETH_EVENT_RESERVED5,
4651 MAX_ETH_EVENT_OPCODE
4652};
4653
4654/* Classify rule types in E2/E3 */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05004655enum eth_filter_action {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004656 ETH_FILTER_ACTION_UNUSED,
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05004657 ETH_FILTER_ACTION_REMOVE,
4658 ETH_FILTER_ACTION_ADD,
4659 ETH_FILTER_ACTION_REMOVE_ALL,
4660 MAX_ETH_FILTER_ACTION
4661};
4662
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004663/* Command for adding/removing a classification rule $$KEEP_ENDIANNESS$$ */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05004664struct eth_filter_cmd {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004665 u8 type;
4666 u8 vport_id;
4667 u8 action;
4668 u8 reserved0;
4669 __le32 vni;
4670 __le16 mac_lsb;
4671 __le16 mac_mid;
4672 __le16 mac_msb;
4673 __le16 vlan_id;
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05004674};
4675
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004676/* $$KEEP_ENDIANNESS$$ */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05004677struct eth_filter_cmd_header {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004678 u8 rx;
4679 u8 tx;
4680 u8 cmd_cnt;
4681 u8 assert_on_error;
4682 u8 reserved1[4];
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05004683};
4684
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004685/* Ethernet filter types: mac/vlan/pair */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05004686enum eth_filter_type {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004687 ETH_FILTER_TYPE_UNUSED,
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05004688 ETH_FILTER_TYPE_MAC,
4689 ETH_FILTER_TYPE_VLAN,
4690 ETH_FILTER_TYPE_PAIR,
4691 ETH_FILTER_TYPE_INNER_MAC,
4692 ETH_FILTER_TYPE_INNER_VLAN,
4693 ETH_FILTER_TYPE_INNER_PAIR,
4694 ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR,
4695 ETH_FILTER_TYPE_MAC_VNI_PAIR,
4696 ETH_FILTER_TYPE_VNI,
4697 MAX_ETH_FILTER_TYPE
4698};
4699
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004700enum eth_ipv4_frag_type {
4701 ETH_IPV4_NOT_FRAG,
4702 ETH_IPV4_FIRST_FRAG,
4703 ETH_IPV4_NON_FIRST_FRAG,
4704 MAX_ETH_IPV4_FRAG_TYPE
4705};
4706
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02004707enum eth_ip_type {
4708 ETH_IPV4,
4709 ETH_IPV6,
4710 MAX_ETH_IP_TYPE
4711};
4712
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05004713enum eth_ramrod_cmd_id {
4714 ETH_RAMROD_UNUSED,
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004715 ETH_RAMROD_VPORT_START,
4716 ETH_RAMROD_VPORT_UPDATE,
4717 ETH_RAMROD_VPORT_STOP,
4718 ETH_RAMROD_RX_QUEUE_START,
4719 ETH_RAMROD_RX_QUEUE_STOP,
4720 ETH_RAMROD_TX_QUEUE_START,
4721 ETH_RAMROD_TX_QUEUE_STOP,
4722 ETH_RAMROD_FILTERS_UPDATE,
4723 ETH_RAMROD_RX_QUEUE_UPDATE,
4724 ETH_RAMROD_RX_CREATE_OPENFLOW_ACTION,
4725 ETH_RAMROD_RX_ADD_OPENFLOW_FILTER,
4726 ETH_RAMROD_RX_DELETE_OPENFLOW_FILTER,
4727 ETH_RAMROD_RX_ADD_UDP_FILTER,
4728 ETH_RAMROD_RX_DELETE_UDP_FILTER,
4729 ETH_RAMROD_RX_CREATE_GFT_ACTION,
4730 ETH_RAMROD_GFT_UPDATE_FILTER,
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05004731 MAX_ETH_RAMROD_CMD_ID
4732};
4733
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004734/* return code from eth sp ramrods */
4735struct eth_return_code {
4736 u8 value;
4737#define ETH_RETURN_CODE_ERR_CODE_MASK 0x1F
4738#define ETH_RETURN_CODE_ERR_CODE_SHIFT 0
4739#define ETH_RETURN_CODE_RESERVED_MASK 0x3
4740#define ETH_RETURN_CODE_RESERVED_SHIFT 5
4741#define ETH_RETURN_CODE_RX_TX_MASK 0x1
4742#define ETH_RETURN_CODE_RX_TX_SHIFT 7
4743};
4744
4745/* What to do in case an error occurs */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05004746enum eth_tx_err {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004747 ETH_TX_ERR_DROP,
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05004748 ETH_TX_ERR_ASSERT_MALICIOUS,
4749 MAX_ETH_TX_ERR
4750};
4751
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004752/* Array of the different error type behaviors */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05004753struct eth_tx_err_vals {
4754 __le16 values;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004755#define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_MASK 0x1
4756#define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_SHIFT 0
4757#define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_MASK 0x1
4758#define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_SHIFT 1
4759#define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_MASK 0x1
4760#define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_SHIFT 2
4761#define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_MASK 0x1
4762#define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_SHIFT 3
4763#define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_MASK 0x1
4764#define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_SHIFT 4
4765#define ETH_TX_ERR_VALS_MTU_VIOLATION_MASK 0x1
4766#define ETH_TX_ERR_VALS_MTU_VIOLATION_SHIFT 5
4767#define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_MASK 0x1
4768#define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_SHIFT 6
4769#define ETH_TX_ERR_VALS_RESERVED_MASK 0x1FF
4770#define ETH_TX_ERR_VALS_RESERVED_SHIFT 7
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05004771};
4772
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004773/* vport rss configuration data */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05004774struct eth_vport_rss_config {
4775 __le16 capabilities;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004776#define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_MASK 0x1
4777#define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_SHIFT 0
4778#define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_MASK 0x1
4779#define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_SHIFT 1
4780#define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_MASK 0x1
4781#define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_SHIFT 2
4782#define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_MASK 0x1
4783#define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_SHIFT 3
4784#define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_MASK 0x1
4785#define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_SHIFT 4
4786#define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_MASK 0x1
4787#define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_SHIFT 5
4788#define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_MASK 0x1
4789#define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_SHIFT 6
4790#define ETH_VPORT_RSS_CONFIG_RESERVED0_MASK 0x1FF
4791#define ETH_VPORT_RSS_CONFIG_RESERVED0_SHIFT 7
4792 u8 rss_id;
4793 u8 rss_mode;
4794 u8 update_rss_key;
4795 u8 update_rss_ind_table;
4796 u8 update_rss_capabilities;
4797 u8 tbl_size;
4798 __le32 reserved2[2];
4799 __le16 indirection_table[ETH_RSS_IND_TABLE_ENTRIES_NUM];
4800
4801 __le32 rss_key[ETH_RSS_KEY_SIZE_REGS];
4802 __le32 reserved3[2];
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05004803};
4804
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004805/* eth vport RSS mode */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05004806enum eth_vport_rss_mode {
4807 ETH_VPORT_RSS_MODE_DISABLED,
4808 ETH_VPORT_RSS_MODE_REGULAR,
4809 MAX_ETH_VPORT_RSS_MODE
4810};
4811
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004812/* Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05004813struct eth_vport_rx_mode {
4814 __le16 state;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004815#define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_MASK 0x1
4816#define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_SHIFT 0
4817#define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_MASK 0x1
4818#define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_SHIFT 1
4819#define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_MASK 0x1
4820#define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_SHIFT 2
4821#define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_MASK 0x1
4822#define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_SHIFT 3
4823#define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_MASK 0x1
4824#define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_SHIFT 4
4825#define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_MASK 0x1
4826#define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_SHIFT 5
4827#define ETH_VPORT_RX_MODE_RESERVED1_MASK 0x3FF
4828#define ETH_VPORT_RX_MODE_RESERVED1_SHIFT 6
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05004829 __le16 reserved2[3];
4830};
4831
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004832/* Command for setting tpa parameters */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05004833struct eth_vport_tpa_param {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004834 u8 tpa_ipv4_en_flg;
4835 u8 tpa_ipv6_en_flg;
4836 u8 tpa_ipv4_tunn_en_flg;
4837 u8 tpa_ipv6_tunn_en_flg;
4838 u8 tpa_pkt_split_flg;
4839 u8 tpa_hdr_data_split_flg;
4840 u8 tpa_gro_consistent_flg;
4841
4842 u8 tpa_max_aggs_num;
4843
4844 __le16 tpa_max_size;
4845 __le16 tpa_min_size_to_start;
4846
4847 __le16 tpa_min_size_to_cont;
4848 u8 max_buff_num;
4849 u8 reserved;
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05004850};
4851
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004852/* Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05004853struct eth_vport_tx_mode {
4854 __le16 state;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004855#define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_MASK 0x1
4856#define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_SHIFT 0
4857#define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_MASK 0x1
4858#define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_SHIFT 1
4859#define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_MASK 0x1
4860#define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_SHIFT 2
4861#define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_MASK 0x1
4862#define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_SHIFT 3
4863#define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_MASK 0x1
4864#define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_SHIFT 4
4865#define ETH_VPORT_TX_MODE_RESERVED1_MASK 0x7FF
4866#define ETH_VPORT_TX_MODE_RESERVED1_SHIFT 5
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05004867 __le16 reserved2[3];
4868};
4869
Chopra, Manishd51e4af2017-04-13 04:54:44 -07004870enum gft_filter_update_action {
4871 GFT_ADD_FILTER,
4872 GFT_DELETE_FILTER,
4873 MAX_GFT_FILTER_UPDATE_ACTION
4874};
4875
4876enum gft_logic_filter_type {
4877 GFT_FILTER_TYPE,
4878 RFS_FILTER_TYPE,
4879 MAX_GFT_LOGIC_FILTER_TYPE
4880};
4881
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004882/* Ramrod data for rx queue start ramrod */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05004883struct rx_queue_start_ramrod_data {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004884 __le16 rx_queue_id;
4885 __le16 num_of_pbl_pages;
4886 __le16 bd_max_bytes;
4887 __le16 sb_id;
4888 u8 sb_index;
4889 u8 vport_id;
4890 u8 default_rss_queue_flg;
4891 u8 complete_cqe_flg;
4892 u8 complete_event_flg;
4893 u8 stats_counter_id;
4894 u8 pin_context;
4895 u8 pxp_tph_valid_bd;
4896 u8 pxp_tph_valid_pkt;
4897 u8 pxp_st_hint;
4898
4899 __le16 pxp_st_index;
4900 u8 pmd_mode;
4901
4902 u8 notify_en;
4903 u8 toggle_val;
4904
4905 u8 vf_rx_prod_index;
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004906 u8 vf_rx_prod_use_zone_a;
4907 u8 reserved[5];
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004908 __le16 reserved1;
4909 struct regpair cqe_pbl_addr;
4910 struct regpair bd_base;
4911 struct regpair reserved2;
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05004912};
4913
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004914/* Ramrod data for rx queue start ramrod */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05004915struct rx_queue_stop_ramrod_data {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004916 __le16 rx_queue_id;
4917 u8 complete_cqe_flg;
4918 u8 complete_event_flg;
4919 u8 vport_id;
4920 u8 reserved[3];
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05004921};
4922
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004923/* Ramrod data for rx queue update ramrod */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05004924struct rx_queue_update_ramrod_data {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004925 __le16 rx_queue_id;
4926 u8 complete_cqe_flg;
4927 u8 complete_event_flg;
4928 u8 vport_id;
4929 u8 reserved[4];
4930 u8 reserved1;
4931 u8 reserved2;
4932 u8 reserved3;
4933 __le16 reserved4;
4934 __le16 reserved5;
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05004935 struct regpair reserved6;
4936};
4937
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004938/* Ramrod data for rx Add UDP Filter */
4939struct rx_udp_filter_data {
4940 __le16 action_icid;
4941 __le16 vlan_id;
4942 u8 ip_type;
4943 u8 tenant_id_exists;
4944 __le16 reserved1;
4945 __le32 ip_dst_addr[4];
4946 __le32 ip_src_addr[4];
4947 __le16 udp_dst_port;
4948 __le16 udp_src_port;
4949 __le32 tenant_id;
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05004950};
4951
Chopra, Manishd51e4af2017-04-13 04:54:44 -07004952struct rx_update_gft_filter_data {
4953 struct regpair pkt_hdr_addr;
4954 __le16 pkt_hdr_length;
4955 __le16 rx_qid_or_action_icid;
4956 u8 vport_id;
4957 u8 filter_type;
4958 u8 filter_action;
4959 u8 reserved;
4960};
4961
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004962/* Ramrod data for rx queue start ramrod */
4963struct tx_queue_start_ramrod_data {
4964 __le16 sb_id;
4965 u8 sb_index;
4966 u8 vport_id;
4967 u8 reserved0;
4968 u8 stats_counter_id;
4969 __le16 qm_pq_id;
4970 u8 flags;
4971#define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_MASK 0x1
4972#define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_SHIFT 0
4973#define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_MASK 0x1
4974#define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_SHIFT 1
4975#define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_MASK 0x1
4976#define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_SHIFT 2
4977#define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_MASK 0x1
4978#define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_SHIFT 3
4979#define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_MASK 0x1
4980#define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_SHIFT 4
4981#define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_MASK 0x1
4982#define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_SHIFT 5
4983#define TX_QUEUE_START_RAMROD_DATA_RESERVED1_MASK 0x3
4984#define TX_QUEUE_START_RAMROD_DATA_RESERVED1_SHIFT 6
4985 u8 pxp_st_hint;
4986 u8 pxp_tph_valid_bd;
4987 u8 pxp_tph_valid_pkt;
4988 __le16 pxp_st_index;
4989 __le16 comp_agg_size;
4990 __le16 queue_zone_id;
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004991 __le16 reserved2;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004992 __le16 pbl_size;
4993 __le16 tx_queue_id;
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004994 __le16 same_as_last_id;
4995 __le16 reserved[3];
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004996 struct regpair pbl_base_addr;
4997 struct regpair bd_cons_address;
4998};
4999
5000/* Ramrod data for tx queue stop ramrod */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005001struct tx_queue_stop_ramrod_data {
5002 __le16 reserved[4];
5003};
5004
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005005/* Ramrod data for vport update ramrod */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005006struct vport_filter_update_ramrod_data {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005007 struct eth_filter_cmd_header filter_cmd_hdr;
5008 struct eth_filter_cmd filter_cmds[ETH_FILTER_RULES_COUNT];
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005009};
5010
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005011/* Ramrod data for vport start ramrod */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005012struct vport_start_ramrod_data {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005013 u8 vport_id;
5014 u8 sw_fid;
5015 __le16 mtu;
5016 u8 drop_ttl0_en;
5017 u8 inner_vlan_removal_en;
5018 struct eth_vport_rx_mode rx_mode;
5019 struct eth_vport_tx_mode tx_mode;
5020 struct eth_vport_tpa_param tpa_param;
5021 __le16 default_vlan;
5022 u8 tx_switching_en;
5023 u8 anti_spoofing_en;
5024
5025 u8 default_vlan_en;
5026
5027 u8 handle_ptp_pkts;
5028 u8 silent_vlan_removal_en;
5029 u8 untagged;
5030 struct eth_tx_err_vals tx_err_behav;
5031
5032 u8 zero_placement_offset;
5033 u8 ctl_frame_mac_check_en;
5034 u8 ctl_frame_ethtype_check_en;
5035 u8 reserved[5];
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005036};
5037
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005038/* Ramrod data for vport stop ramrod */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005039struct vport_stop_ramrod_data {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005040 u8 vport_id;
5041 u8 reserved[7];
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005042};
5043
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005044/* Ramrod data for vport update ramrod */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005045struct vport_update_ramrod_data_cmn {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005046 u8 vport_id;
5047 u8 update_rx_active_flg;
5048 u8 rx_active_flg;
5049 u8 update_tx_active_flg;
5050 u8 tx_active_flg;
5051 u8 update_rx_mode_flg;
5052 u8 update_tx_mode_flg;
5053 u8 update_approx_mcast_flg;
5054
5055 u8 update_rss_flg;
5056 u8 update_inner_vlan_removal_en_flg;
5057
5058 u8 inner_vlan_removal_en;
5059 u8 update_tpa_param_flg;
5060 u8 update_tpa_en_flg;
5061 u8 update_tx_switching_en_flg;
5062
5063 u8 tx_switching_en;
5064 u8 update_anti_spoofing_en_flg;
5065
5066 u8 anti_spoofing_en;
5067 u8 update_handle_ptp_pkts;
5068
5069 u8 handle_ptp_pkts;
5070 u8 update_default_vlan_en_flg;
5071
5072 u8 default_vlan_en;
5073
5074 u8 update_default_vlan_flg;
5075
5076 __le16 default_vlan;
5077 u8 update_accept_any_vlan_flg;
5078
5079 u8 accept_any_vlan;
5080 u8 silent_vlan_removal_en;
5081 u8 update_mtu_flg;
5082
5083 __le16 mtu;
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02005084 u8 update_ctl_frame_checks_en_flg;
5085 u8 ctl_frame_mac_check_en;
5086 u8 ctl_frame_ethtype_check_en;
5087 u8 reserved[15];
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005088};
5089
5090struct vport_update_ramrod_mcast {
5091 __le32 bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
5092};
5093
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005094/* Ramrod data for vport update ramrod */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005095struct vport_update_ramrod_data {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005096 struct vport_update_ramrod_data_cmn common;
5097
5098 struct eth_vport_rx_mode rx_mode;
5099 struct eth_vport_tx_mode tx_mode;
5100 struct eth_vport_tpa_param tpa_param;
5101 struct vport_update_ramrod_mcast approx_mcast;
5102 struct eth_vport_rss_config rss_config;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02005103};
5104
Chopra, Manishd51e4af2017-04-13 04:54:44 -07005105struct gft_cam_line {
5106 __le32 camline;
5107#define GFT_CAM_LINE_VALID_MASK 0x1
5108#define GFT_CAM_LINE_VALID_SHIFT 0
5109#define GFT_CAM_LINE_DATA_MASK 0x3FFF
5110#define GFT_CAM_LINE_DATA_SHIFT 1
5111#define GFT_CAM_LINE_MASK_BITS_MASK 0x3FFF
5112#define GFT_CAM_LINE_MASK_BITS_SHIFT 15
5113#define GFT_CAM_LINE_RESERVED1_MASK 0x7
5114#define GFT_CAM_LINE_RESERVED1_SHIFT 29
5115};
5116
5117struct gft_cam_line_mapped {
5118 __le32 camline;
5119#define GFT_CAM_LINE_MAPPED_VALID_MASK 0x1
5120#define GFT_CAM_LINE_MAPPED_VALID_SHIFT 0
5121#define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK 0x1
5122#define GFT_CAM_LINE_MAPPED_IP_VERSION_SHIFT 1
5123#define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK 0x1
5124#define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_SHIFT 2
5125#define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK 0xF
5126#define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_SHIFT 3
5127#define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK 0xF
5128#define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_SHIFT 7
5129#define GFT_CAM_LINE_MAPPED_PF_ID_MASK 0xF
5130#define GFT_CAM_LINE_MAPPED_PF_ID_SHIFT 11
5131#define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_MASK 0x1
5132#define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_SHIFT 15
5133#define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_MASK 0x1
5134#define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_SHIFT 16
5135#define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_MASK 0xF
5136#define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_SHIFT 17
5137#define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_MASK 0xF
5138#define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_SHIFT 21
5139#define GFT_CAM_LINE_MAPPED_PF_ID_MASK_MASK 0xF
5140#define GFT_CAM_LINE_MAPPED_PF_ID_MASK_SHIFT 25
5141#define GFT_CAM_LINE_MAPPED_RESERVED1_MASK 0x7
5142#define GFT_CAM_LINE_MAPPED_RESERVED1_SHIFT 29
5143};
5144
5145union gft_cam_line_union {
5146 struct gft_cam_line cam_line;
5147 struct gft_cam_line_mapped cam_line_mapped;
5148};
5149
5150enum gft_profile_ip_version {
5151 GFT_PROFILE_IPV4 = 0,
5152 GFT_PROFILE_IPV6 = 1,
5153 MAX_GFT_PROFILE_IP_VERSION
5154};
5155
5156enum gft_profile_upper_protocol_type {
5157 GFT_PROFILE_ROCE_PROTOCOL = 0,
5158 GFT_PROFILE_RROCE_PROTOCOL = 1,
5159 GFT_PROFILE_FCOE_PROTOCOL = 2,
5160 GFT_PROFILE_ICMP_PROTOCOL = 3,
5161 GFT_PROFILE_ARP_PROTOCOL = 4,
5162 GFT_PROFILE_USER_TCP_SRC_PORT_1_INNER = 5,
5163 GFT_PROFILE_USER_TCP_DST_PORT_1_INNER = 6,
5164 GFT_PROFILE_TCP_PROTOCOL = 7,
5165 GFT_PROFILE_USER_UDP_DST_PORT_1_INNER = 8,
5166 GFT_PROFILE_USER_UDP_DST_PORT_2_OUTER = 9,
5167 GFT_PROFILE_UDP_PROTOCOL = 10,
5168 GFT_PROFILE_USER_IP_1_INNER = 11,
5169 GFT_PROFILE_USER_IP_2_OUTER = 12,
5170 GFT_PROFILE_USER_ETH_1_INNER = 13,
5171 GFT_PROFILE_USER_ETH_2_OUTER = 14,
5172 GFT_PROFILE_RAW = 15,
5173 MAX_GFT_PROFILE_UPPER_PROTOCOL_TYPE
5174};
5175
5176struct gft_ram_line {
5177 __le32 low32bits;
5178#define GFT_RAM_LINE_VLAN_SELECT_MASK 0x3
5179#define GFT_RAM_LINE_VLAN_SELECT_SHIFT 0
5180#define GFT_RAM_LINE_TUNNEL_ENTROPHY_MASK 0x1
5181#define GFT_RAM_LINE_TUNNEL_ENTROPHY_SHIFT 2
5182#define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_MASK 0x1
5183#define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_SHIFT 3
5184#define GFT_RAM_LINE_TUNNEL_TTL_MASK 0x1
5185#define GFT_RAM_LINE_TUNNEL_TTL_SHIFT 4
5186#define GFT_RAM_LINE_TUNNEL_ETHERTYPE_MASK 0x1
5187#define GFT_RAM_LINE_TUNNEL_ETHERTYPE_SHIFT 5
5188#define GFT_RAM_LINE_TUNNEL_DST_PORT_MASK 0x1
5189#define GFT_RAM_LINE_TUNNEL_DST_PORT_SHIFT 6
5190#define GFT_RAM_LINE_TUNNEL_SRC_PORT_MASK 0x1
5191#define GFT_RAM_LINE_TUNNEL_SRC_PORT_SHIFT 7
5192#define GFT_RAM_LINE_TUNNEL_DSCP_MASK 0x1
5193#define GFT_RAM_LINE_TUNNEL_DSCP_SHIFT 8
5194#define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_MASK 0x1
5195#define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_SHIFT 9
5196#define GFT_RAM_LINE_TUNNEL_DST_IP_MASK 0x1
5197#define GFT_RAM_LINE_TUNNEL_DST_IP_SHIFT 10
5198#define GFT_RAM_LINE_TUNNEL_SRC_IP_MASK 0x1
5199#define GFT_RAM_LINE_TUNNEL_SRC_IP_SHIFT 11
5200#define GFT_RAM_LINE_TUNNEL_PRIORITY_MASK 0x1
5201#define GFT_RAM_LINE_TUNNEL_PRIORITY_SHIFT 12
5202#define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_MASK 0x1
5203#define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_SHIFT 13
5204#define GFT_RAM_LINE_TUNNEL_VLAN_MASK 0x1
5205#define GFT_RAM_LINE_TUNNEL_VLAN_SHIFT 14
5206#define GFT_RAM_LINE_TUNNEL_DST_MAC_MASK 0x1
5207#define GFT_RAM_LINE_TUNNEL_DST_MAC_SHIFT 15
5208#define GFT_RAM_LINE_TUNNEL_SRC_MAC_MASK 0x1
5209#define GFT_RAM_LINE_TUNNEL_SRC_MAC_SHIFT 16
5210#define GFT_RAM_LINE_TTL_EQUAL_ONE_MASK 0x1
5211#define GFT_RAM_LINE_TTL_EQUAL_ONE_SHIFT 17
5212#define GFT_RAM_LINE_TTL_MASK 0x1
5213#define GFT_RAM_LINE_TTL_SHIFT 18
5214#define GFT_RAM_LINE_ETHERTYPE_MASK 0x1
5215#define GFT_RAM_LINE_ETHERTYPE_SHIFT 19
5216#define GFT_RAM_LINE_RESERVED0_MASK 0x1
5217#define GFT_RAM_LINE_RESERVED0_SHIFT 20
5218#define GFT_RAM_LINE_TCP_FLAG_FIN_MASK 0x1
5219#define GFT_RAM_LINE_TCP_FLAG_FIN_SHIFT 21
5220#define GFT_RAM_LINE_TCP_FLAG_SYN_MASK 0x1
5221#define GFT_RAM_LINE_TCP_FLAG_SYN_SHIFT 22
5222#define GFT_RAM_LINE_TCP_FLAG_RST_MASK 0x1
5223#define GFT_RAM_LINE_TCP_FLAG_RST_SHIFT 23
5224#define GFT_RAM_LINE_TCP_FLAG_PSH_MASK 0x1
5225#define GFT_RAM_LINE_TCP_FLAG_PSH_SHIFT 24
5226#define GFT_RAM_LINE_TCP_FLAG_ACK_MASK 0x1
5227#define GFT_RAM_LINE_TCP_FLAG_ACK_SHIFT 25
5228#define GFT_RAM_LINE_TCP_FLAG_URG_MASK 0x1
5229#define GFT_RAM_LINE_TCP_FLAG_URG_SHIFT 26
5230#define GFT_RAM_LINE_TCP_FLAG_ECE_MASK 0x1
5231#define GFT_RAM_LINE_TCP_FLAG_ECE_SHIFT 27
5232#define GFT_RAM_LINE_TCP_FLAG_CWR_MASK 0x1
5233#define GFT_RAM_LINE_TCP_FLAG_CWR_SHIFT 28
5234#define GFT_RAM_LINE_TCP_FLAG_NS_MASK 0x1
5235#define GFT_RAM_LINE_TCP_FLAG_NS_SHIFT 29
5236#define GFT_RAM_LINE_DST_PORT_MASK 0x1
5237#define GFT_RAM_LINE_DST_PORT_SHIFT 30
5238#define GFT_RAM_LINE_SRC_PORT_MASK 0x1
5239#define GFT_RAM_LINE_SRC_PORT_SHIFT 31
5240 __le32 high32bits;
5241#define GFT_RAM_LINE_DSCP_MASK 0x1
5242#define GFT_RAM_LINE_DSCP_SHIFT 0
5243#define GFT_RAM_LINE_OVER_IP_PROTOCOL_MASK 0x1
5244#define GFT_RAM_LINE_OVER_IP_PROTOCOL_SHIFT 1
5245#define GFT_RAM_LINE_DST_IP_MASK 0x1
5246#define GFT_RAM_LINE_DST_IP_SHIFT 2
5247#define GFT_RAM_LINE_SRC_IP_MASK 0x1
5248#define GFT_RAM_LINE_SRC_IP_SHIFT 3
5249#define GFT_RAM_LINE_PRIORITY_MASK 0x1
5250#define GFT_RAM_LINE_PRIORITY_SHIFT 4
5251#define GFT_RAM_LINE_PROVIDER_VLAN_MASK 0x1
5252#define GFT_RAM_LINE_PROVIDER_VLAN_SHIFT 5
5253#define GFT_RAM_LINE_VLAN_MASK 0x1
5254#define GFT_RAM_LINE_VLAN_SHIFT 6
5255#define GFT_RAM_LINE_DST_MAC_MASK 0x1
5256#define GFT_RAM_LINE_DST_MAC_SHIFT 7
5257#define GFT_RAM_LINE_SRC_MAC_MASK 0x1
5258#define GFT_RAM_LINE_SRC_MAC_SHIFT 8
5259#define GFT_RAM_LINE_TENANT_ID_MASK 0x1
5260#define GFT_RAM_LINE_TENANT_ID_SHIFT 9
5261#define GFT_RAM_LINE_RESERVED1_MASK 0x3FFFFF
5262#define GFT_RAM_LINE_RESERVED1_SHIFT 10
5263};
5264
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02005265struct mstorm_eth_conn_ag_ctx {
5266 u8 byte0;
5267 u8 byte1;
5268 u8 flags0;
5269#define MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
5270#define MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
5271#define MSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
5272#define MSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
5273#define MSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
5274#define MSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 2
5275#define MSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
5276#define MSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 4
5277#define MSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
5278#define MSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
5279 u8 flags1;
5280#define MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
5281#define MSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 0
5282#define MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
5283#define MSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 1
5284#define MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
5285#define MSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
5286#define MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
5287#define MSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3
5288#define MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
5289#define MSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4
5290#define MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
5291#define MSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5
5292#define MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
5293#define MSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6
5294#define MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
5295#define MSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7
5296 __le16 word0;
5297 __le16 word1;
5298 __le32 reg0;
5299 __le32 reg1;
5300};
5301
5302struct xstorm_eth_conn_agctxdq_ext_ldpart {
5303 u8 reserved0;
5304 u8 eth_state;
5305 u8 flags0;
5306#define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1
5307#define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0
5308#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_MASK 0x1
5309#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_SHIFT 1
5310#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_MASK 0x1
5311#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_SHIFT 2
5312#define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1
5313#define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3
5314#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_MASK 0x1
5315#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_SHIFT 4
5316#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_MASK 0x1
5317#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_SHIFT 5
5318#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_MASK 0x1
5319#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_SHIFT 6
5320#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_MASK 0x1
5321#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_SHIFT 7
5322 u8 flags1;
5323#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_MASK 0x1
5324#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_SHIFT 0
5325#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_MASK 0x1
5326#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_SHIFT 1
5327#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_MASK 0x1
5328#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_SHIFT 2
5329#define XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_MASK 0x1
5330#define XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_SHIFT 3
5331#define XSTORMETHCONNAGCTXDQEXTLDPART_BIT12_MASK 0x1
5332#define XSTORMETHCONNAGCTXDQEXTLDPART_BIT12_SHIFT 4
5333#define XSTORMETHCONNAGCTXDQEXTLDPART_BIT13_MASK 0x1
5334#define XSTORMETHCONNAGCTXDQEXTLDPART_BIT13_SHIFT 5
5335#define XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_MASK 0x1
5336#define XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_SHIFT 6
5337#define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_MASK 0x1
5338#define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_SHIFT 7
5339 u8 flags2;
5340#define XSTORMETHCONNAGCTXDQEXTLDPART_CF0_MASK 0x3
5341#define XSTORMETHCONNAGCTXDQEXTLDPART_CF0_SHIFT 0
5342#define XSTORMETHCONNAGCTXDQEXTLDPART_CF1_MASK 0x3
5343#define XSTORMETHCONNAGCTXDQEXTLDPART_CF1_SHIFT 2
5344#define XSTORMETHCONNAGCTXDQEXTLDPART_CF2_MASK 0x3
5345#define XSTORMETHCONNAGCTXDQEXTLDPART_CF2_SHIFT 4
5346#define XSTORMETHCONNAGCTXDQEXTLDPART_CF3_MASK 0x3
5347#define XSTORMETHCONNAGCTXDQEXTLDPART_CF3_SHIFT 6
5348 u8 flags3;
5349#define XSTORMETHCONNAGCTXDQEXTLDPART_CF4_MASK 0x3
5350#define XSTORMETHCONNAGCTXDQEXTLDPART_CF4_SHIFT 0
5351#define XSTORMETHCONNAGCTXDQEXTLDPART_CF5_MASK 0x3
5352#define XSTORMETHCONNAGCTXDQEXTLDPART_CF5_SHIFT 2
5353#define XSTORMETHCONNAGCTXDQEXTLDPART_CF6_MASK 0x3
5354#define XSTORMETHCONNAGCTXDQEXTLDPART_CF6_SHIFT 4
5355#define XSTORMETHCONNAGCTXDQEXTLDPART_CF7_MASK 0x3
5356#define XSTORMETHCONNAGCTXDQEXTLDPART_CF7_SHIFT 6
5357 u8 flags4;
5358#define XSTORMETHCONNAGCTXDQEXTLDPART_CF8_MASK 0x3
5359#define XSTORMETHCONNAGCTXDQEXTLDPART_CF8_SHIFT 0
5360#define XSTORMETHCONNAGCTXDQEXTLDPART_CF9_MASK 0x3
5361#define XSTORMETHCONNAGCTXDQEXTLDPART_CF9_SHIFT 2
5362#define XSTORMETHCONNAGCTXDQEXTLDPART_CF10_MASK 0x3
5363#define XSTORMETHCONNAGCTXDQEXTLDPART_CF10_SHIFT 4
5364#define XSTORMETHCONNAGCTXDQEXTLDPART_CF11_MASK 0x3
5365#define XSTORMETHCONNAGCTXDQEXTLDPART_CF11_SHIFT 6
5366 u8 flags5;
5367#define XSTORMETHCONNAGCTXDQEXTLDPART_CF12_MASK 0x3
5368#define XSTORMETHCONNAGCTXDQEXTLDPART_CF12_SHIFT 0
5369#define XSTORMETHCONNAGCTXDQEXTLDPART_CF13_MASK 0x3
5370#define XSTORMETHCONNAGCTXDQEXTLDPART_CF13_SHIFT 2
5371#define XSTORMETHCONNAGCTXDQEXTLDPART_CF14_MASK 0x3
5372#define XSTORMETHCONNAGCTXDQEXTLDPART_CF14_SHIFT 4
5373#define XSTORMETHCONNAGCTXDQEXTLDPART_CF15_MASK 0x3
5374#define XSTORMETHCONNAGCTXDQEXTLDPART_CF15_SHIFT 6
5375 u8 flags6;
5376#define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_MASK 0x3
5377#define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_SHIFT 0
5378#define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_MASK 0x3
5379#define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_SHIFT 2
5380#define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_MASK 0x3
5381#define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_SHIFT 4
5382#define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_MASK 0x3
5383#define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_SHIFT 6
5384 u8 flags7;
5385#define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_MASK 0x3
5386#define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_SHIFT 0
5387#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_MASK 0x3
5388#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_SHIFT 2
5389#define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3
5390#define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4
5391#define XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1
5392#define XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6
5393#define XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1
5394#define XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7
5395 u8 flags8;
5396#define XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1
5397#define XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0
5398#define XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1
5399#define XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1
5400#define XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1
5401#define XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2
5402#define XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1
5403#define XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3
5404#define XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1
5405#define XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4
5406#define XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_MASK 0x1
5407#define XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_SHIFT 5
5408#define XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1
5409#define XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6
5410#define XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1
5411#define XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7
5412 u8 flags9;
5413#define XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1
5414#define XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0
5415#define XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1
5416#define XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1
5417#define XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1
5418#define XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2
5419#define XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1
5420#define XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3
5421#define XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1
5422#define XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4
5423#define XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1
5424#define XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5
5425#define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_MASK 0x1
5426#define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_SHIFT 6
5427#define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_MASK 0x1
5428#define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_SHIFT 7
5429 u8 flags10;
5430#define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_MASK 0x1
5431#define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_SHIFT 0
5432#define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_MASK 0x1
5433#define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_SHIFT 1
5434#define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_MASK 0x1
5435#define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_SHIFT 2
5436#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_MASK 0x1
5437#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_SHIFT 3
5438#define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1
5439#define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4
5440#define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_MASK 0x1
5441#define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_SHIFT 5
5442#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_MASK 0x1
5443#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_SHIFT 6
5444#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_MASK 0x1
5445#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_SHIFT 7
5446 u8 flags11;
5447#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_MASK 0x1
5448#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_SHIFT 0
5449#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_MASK 0x1
5450#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_SHIFT 1
5451#define XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_MASK 0x1
5452#define XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_SHIFT 2
5453#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1
5454#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3
5455#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1
5456#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4
5457#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1
5458#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5
5459#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1
5460#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6
5461#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1
5462#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7
5463 u8 flags12;
5464#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1
5465#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0
5466#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1
5467#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1
5468#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1
5469#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2
5470#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1
5471#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3
5472#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1
5473#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4
5474#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1
5475#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5
5476#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1
5477#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6
5478#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1
5479#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7
5480 u8 flags13;
5481#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1
5482#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0
5483#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1
5484#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1
5485#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1
5486#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2
5487#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1
5488#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3
5489#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1
5490#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4
5491#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1
5492#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5
5493#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1
5494#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6
5495#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1
5496#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7
5497 u8 flags14;
5498#define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_MASK 0x1
5499#define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_SHIFT 0
5500#define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_MASK 0x1
5501#define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_SHIFT 1
5502#define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_MASK 0x1
5503#define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_SHIFT 2
5504#define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_MASK 0x1
5505#define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_SHIFT 3
5506#define XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_MASK 0x1
5507#define XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_SHIFT 4
5508#define XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1
5509#define XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5
5510#define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_MASK 0x3
5511#define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_SHIFT 6
5512 u8 edpm_event_id;
5513 __le16 physical_q0;
5514 __le16 quota;
5515 __le16 edpm_num_bds;
5516 __le16 tx_bd_cons;
5517 __le16 tx_bd_prod;
5518 __le16 tx_class;
5519 __le16 conn_dpi;
5520 u8 byte3;
5521 u8 byte4;
5522 u8 byte5;
5523 u8 byte6;
5524 __le32 reg0;
5525 __le32 reg1;
5526 __le32 reg2;
5527 __le32 reg3;
5528 __le32 reg4;
5529};
5530
5531struct xstorm_eth_hw_conn_ag_ctx {
5532 u8 reserved0;
5533 u8 eth_state;
5534 u8 flags0;
5535#define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
5536#define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
5537#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK 0x1
5538#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_SHIFT 1
5539#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK 0x1
5540#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_SHIFT 2
5541#define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
5542#define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
5543#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK 0x1
5544#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_SHIFT 4
5545#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK 0x1
5546#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_SHIFT 5
5547#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK 0x1
5548#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_SHIFT 6
5549#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK 0x1
5550#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_SHIFT 7
5551 u8 flags1;
5552#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK 0x1
5553#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_SHIFT 0
5554#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK 0x1
5555#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_SHIFT 1
5556#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK 0x1
5557#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_SHIFT 2
5558#define XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK 0x1
5559#define XSTORM_ETH_HW_CONN_AG_CTX_BIT11_SHIFT 3
5560#define XSTORM_ETH_HW_CONN_AG_CTX_BIT12_MASK 0x1
5561#define XSTORM_ETH_HW_CONN_AG_CTX_BIT12_SHIFT 4
5562#define XSTORM_ETH_HW_CONN_AG_CTX_BIT13_MASK 0x1
5563#define XSTORM_ETH_HW_CONN_AG_CTX_BIT13_SHIFT 5
5564#define XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
5565#define XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
5566#define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
5567#define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
5568 u8 flags2;
5569#define XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK 0x3
5570#define XSTORM_ETH_HW_CONN_AG_CTX_CF0_SHIFT 0
5571#define XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK 0x3
5572#define XSTORM_ETH_HW_CONN_AG_CTX_CF1_SHIFT 2
5573#define XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK 0x3
5574#define XSTORM_ETH_HW_CONN_AG_CTX_CF2_SHIFT 4
5575#define XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK 0x3
5576#define XSTORM_ETH_HW_CONN_AG_CTX_CF3_SHIFT 6
5577 u8 flags3;
5578#define XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK 0x3
5579#define XSTORM_ETH_HW_CONN_AG_CTX_CF4_SHIFT 0
5580#define XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK 0x3
5581#define XSTORM_ETH_HW_CONN_AG_CTX_CF5_SHIFT 2
5582#define XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK 0x3
5583#define XSTORM_ETH_HW_CONN_AG_CTX_CF6_SHIFT 4
5584#define XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK 0x3
5585#define XSTORM_ETH_HW_CONN_AG_CTX_CF7_SHIFT 6
5586 u8 flags4;
5587#define XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK 0x3
5588#define XSTORM_ETH_HW_CONN_AG_CTX_CF8_SHIFT 0
5589#define XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK 0x3
5590#define XSTORM_ETH_HW_CONN_AG_CTX_CF9_SHIFT 2
5591#define XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK 0x3
5592#define XSTORM_ETH_HW_CONN_AG_CTX_CF10_SHIFT 4
5593#define XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK 0x3
5594#define XSTORM_ETH_HW_CONN_AG_CTX_CF11_SHIFT 6
5595 u8 flags5;
5596#define XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK 0x3
5597#define XSTORM_ETH_HW_CONN_AG_CTX_CF12_SHIFT 0
5598#define XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK 0x3
5599#define XSTORM_ETH_HW_CONN_AG_CTX_CF13_SHIFT 2
5600#define XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK 0x3
5601#define XSTORM_ETH_HW_CONN_AG_CTX_CF14_SHIFT 4
5602#define XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK 0x3
5603#define XSTORM_ETH_HW_CONN_AG_CTX_CF15_SHIFT 6
5604 u8 flags6;
5605#define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3
5606#define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0
5607#define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
5608#define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2
5609#define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK 0x3
5610#define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_SHIFT 4
5611#define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
5612#define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
5613 u8 flags7;
5614#define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
5615#define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
5616#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK 0x3
5617#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_SHIFT 2
5618#define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK 0x3
5619#define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_SHIFT 4
5620#define XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK 0x1
5621#define XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_SHIFT 6
5622#define XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK 0x1
5623#define XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_SHIFT 7
5624 u8 flags8;
5625#define XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK 0x1
5626#define XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_SHIFT 0
5627#define XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK 0x1
5628#define XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_SHIFT 1
5629#define XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK 0x1
5630#define XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_SHIFT 2
5631#define XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK 0x1
5632#define XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_SHIFT 3
5633#define XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK 0x1
5634#define XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_SHIFT 4
5635#define XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK 0x1
5636#define XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_SHIFT 5
5637#define XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK 0x1
5638#define XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_SHIFT 6
5639#define XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK 0x1
5640#define XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_SHIFT 7
5641 u8 flags9;
5642#define XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK 0x1
5643#define XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_SHIFT 0
5644#define XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK 0x1
5645#define XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_SHIFT 1
5646#define XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK 0x1
5647#define XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_SHIFT 2
5648#define XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK 0x1
5649#define XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_SHIFT 3
5650#define XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK 0x1
5651#define XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_SHIFT 4
5652#define XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK 0x1
5653#define XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_SHIFT 5
5654#define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1
5655#define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6
5656#define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
5657#define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7
5658 u8 flags10;
5659#define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
5660#define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
5661#define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
5662#define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
5663#define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
5664#define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
5665#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK 0x1
5666#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_SHIFT 3
5667#define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
5668#define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
5669#define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1
5670#define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
5671#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK 0x1
5672#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_SHIFT 6
5673#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK 0x1
5674#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_SHIFT 7
5675 u8 flags11;
5676#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK 0x1
5677#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_SHIFT 0
5678#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK 0x1
5679#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_SHIFT 1
5680#define XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
5681#define XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
5682#define XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK 0x1
5683#define XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_SHIFT 3
5684#define XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK 0x1
5685#define XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_SHIFT 4
5686#define XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK 0x1
5687#define XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_SHIFT 5
5688#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
5689#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
5690#define XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK 0x1
5691#define XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_SHIFT 7
5692 u8 flags12;
5693#define XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK 0x1
5694#define XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_SHIFT 0
5695#define XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK 0x1
5696#define XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_SHIFT 1
5697#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
5698#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
5699#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
5700#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
5701#define XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK 0x1
5702#define XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_SHIFT 4
5703#define XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK 0x1
5704#define XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_SHIFT 5
5705#define XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK 0x1
5706#define XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_SHIFT 6
5707#define XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK 0x1
5708#define XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_SHIFT 7
5709 u8 flags13;
5710#define XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK 0x1
5711#define XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_SHIFT 0
5712#define XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK 0x1
5713#define XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_SHIFT 1
5714#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
5715#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
5716#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
5717#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
5718#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
5719#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
5720#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
5721#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
5722#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
5723#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
5724#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
5725#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
5726 u8 flags14;
5727#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1
5728#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0
5729#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1
5730#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1
5731#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1
5732#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2
5733#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1
5734#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3
5735#define XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1
5736#define XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4
5737#define XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
5738#define XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
5739#define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK 0x3
5740#define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_SHIFT 6
5741 u8 edpm_event_id;
5742 __le16 physical_q0;
5743 __le16 quota;
5744 __le16 edpm_num_bds;
5745 __le16 tx_bd_cons;
5746 __le16 tx_bd_prod;
5747 __le16 tx_class;
5748 __le16 conn_dpi;
5749};
5750
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03005751struct mstorm_rdma_task_st_ctx {
5752 struct regpair temp[4];
5753};
5754
5755struct rdma_close_func_ramrod_data {
5756 u8 cnq_start_offset;
5757 u8 num_cnqs;
5758 u8 vf_id;
5759 u8 vf_valid;
5760 u8 reserved[4];
5761};
5762
5763struct rdma_cnq_params {
5764 __le16 sb_num;
5765 u8 sb_index;
5766 u8 num_pbl_pages;
5767 __le32 reserved;
5768 struct regpair pbl_base_addr;
5769 __le16 queue_zone_num;
5770 u8 reserved1[6];
5771};
5772
5773struct rdma_create_cq_ramrod_data {
5774 struct regpair cq_handle;
5775 struct regpair pbl_addr;
5776 __le32 max_cqes;
5777 __le16 pbl_num_pages;
5778 __le16 dpi;
5779 u8 is_two_level_pbl;
5780 u8 cnq_id;
5781 u8 pbl_log_page_size;
5782 u8 toggle_bit;
5783 __le16 int_timeout;
5784 __le16 reserved1;
5785};
5786
5787struct rdma_deregister_tid_ramrod_data {
5788 __le32 itid;
5789 __le32 reserved;
5790};
5791
5792struct rdma_destroy_cq_output_params {
5793 __le16 cnq_num;
5794 __le16 reserved0;
5795 __le32 reserved1;
5796};
5797
5798struct rdma_destroy_cq_ramrod_data {
5799 struct regpair output_params_addr;
5800};
5801
5802enum rdma_event_opcode {
5803 RDMA_EVENT_UNUSED,
5804 RDMA_EVENT_FUNC_INIT,
5805 RDMA_EVENT_FUNC_CLOSE,
5806 RDMA_EVENT_REGISTER_MR,
5807 RDMA_EVENT_DEREGISTER_MR,
5808 RDMA_EVENT_CREATE_CQ,
5809 RDMA_EVENT_RESIZE_CQ,
5810 RDMA_EVENT_DESTROY_CQ,
5811 RDMA_EVENT_CREATE_SRQ,
5812 RDMA_EVENT_MODIFY_SRQ,
5813 RDMA_EVENT_DESTROY_SRQ,
5814 MAX_RDMA_EVENT_OPCODE
5815};
5816
5817enum rdma_fw_return_code {
5818 RDMA_RETURN_OK = 0,
5819 RDMA_RETURN_REGISTER_MR_BAD_STATE_ERR,
5820 RDMA_RETURN_DEREGISTER_MR_BAD_STATE_ERR,
5821 RDMA_RETURN_RESIZE_CQ_ERR,
5822 RDMA_RETURN_NIG_DRAIN_REQ,
5823 MAX_RDMA_FW_RETURN_CODE
5824};
5825
5826struct rdma_init_func_hdr {
5827 u8 cnq_start_offset;
5828 u8 num_cnqs;
5829 u8 cq_ring_mode;
5830 u8 cnp_vlan_priority;
5831 __le32 cnp_send_timeout;
5832 u8 cnp_dscp;
5833 u8 vf_id;
5834 u8 vf_valid;
5835 u8 reserved[5];
5836};
5837
5838struct rdma_init_func_ramrod_data {
5839 struct rdma_init_func_hdr params_header;
5840 struct rdma_cnq_params cnq_params[NUM_OF_GLOBAL_QUEUES];
5841};
5842
5843enum rdma_ramrod_cmd_id {
5844 RDMA_RAMROD_UNUSED,
5845 RDMA_RAMROD_FUNC_INIT,
5846 RDMA_RAMROD_FUNC_CLOSE,
5847 RDMA_RAMROD_REGISTER_MR,
5848 RDMA_RAMROD_DEREGISTER_MR,
5849 RDMA_RAMROD_CREATE_CQ,
5850 RDMA_RAMROD_RESIZE_CQ,
5851 RDMA_RAMROD_DESTROY_CQ,
5852 RDMA_RAMROD_CREATE_SRQ,
5853 RDMA_RAMROD_MODIFY_SRQ,
5854 RDMA_RAMROD_DESTROY_SRQ,
5855 MAX_RDMA_RAMROD_CMD_ID
5856};
5857
5858struct rdma_register_tid_ramrod_data {
5859 __le32 flags;
5860#define RDMA_REGISTER_TID_RAMROD_DATA_MAX_ID_MASK 0x3FFFF
5861#define RDMA_REGISTER_TID_RAMROD_DATA_MAX_ID_SHIFT 0
5862#define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_MASK 0x1F
5863#define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_SHIFT 18
5864#define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_MASK 0x1
5865#define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_SHIFT 23
5866#define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_MASK 0x1
5867#define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_SHIFT 24
5868#define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_MASK 0x1
5869#define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_SHIFT 25
5870#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_MASK 0x1
5871#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_SHIFT 26
5872#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_MASK 0x1
5873#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_SHIFT 27
5874#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_MASK 0x1
5875#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_SHIFT 28
5876#define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_MASK 0x1
5877#define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_SHIFT 29
5878#define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_MASK 0x1
5879#define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_SHIFT 30
5880#define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_MASK 0x1
5881#define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_SHIFT 31
5882 u8 flags1;
5883#define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_MASK 0x1F
5884#define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_SHIFT 0
5885#define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_MASK 0x7
5886#define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_SHIFT 5
5887 u8 flags2;
5888#define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_MASK 0x1
5889#define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_SHIFT 0
5890#define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_MASK 0x1
5891#define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_SHIFT 1
5892#define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_MASK 0x3F
5893#define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_SHIFT 2
5894 u8 key;
5895 u8 length_hi;
5896 u8 vf_id;
5897 u8 vf_valid;
5898 __le16 pd;
5899 __le32 length_lo;
5900 __le32 itid;
5901 __le32 reserved2;
5902 struct regpair va;
5903 struct regpair pbl_base;
5904 struct regpair dif_error_addr;
5905 struct regpair dif_runt_addr;
5906 __le32 reserved3[2];
5907};
5908
5909struct rdma_resize_cq_output_params {
5910 __le32 old_cq_cons;
5911 __le32 old_cq_prod;
5912};
5913
5914struct rdma_resize_cq_ramrod_data {
5915 u8 flags;
5916#define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_MASK 0x1
5917#define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_SHIFT 0
5918#define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_MASK 0x1
5919#define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_SHIFT 1
5920#define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_MASK 0x3F
5921#define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_SHIFT 2
5922 u8 pbl_log_page_size;
5923 __le16 pbl_num_pages;
5924 __le32 max_cqes;
5925 struct regpair pbl_addr;
5926 struct regpair output_params_addr;
5927};
5928
5929struct rdma_srq_context {
5930 struct regpair temp[8];
5931};
5932
5933struct rdma_srq_create_ramrod_data {
5934 struct regpair pbl_base_addr;
5935 __le16 pages_in_srq_pbl;
5936 __le16 pd_id;
5937 struct rdma_srq_id srq_id;
5938 __le16 page_size;
5939 __le16 reserved1;
5940 __le32 reserved2;
5941 struct regpair producers_addr;
5942};
5943
5944struct rdma_srq_destroy_ramrod_data {
5945 struct rdma_srq_id srq_id;
5946 __le32 reserved;
5947};
5948
5949struct rdma_srq_modify_ramrod_data {
5950 struct rdma_srq_id srq_id;
5951 __le32 wqe_limit;
5952};
5953
5954struct ystorm_rdma_task_st_ctx {
5955 struct regpair temp[4];
5956};
5957
5958struct ystorm_rdma_task_ag_ctx {
5959 u8 reserved;
5960 u8 byte1;
5961 __le16 msem_ctx_upd_seq;
5962 u8 flags0;
5963#define YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
5964#define YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
5965#define YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
5966#define YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
5967#define YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
5968#define YSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
5969#define YSTORM_RDMA_TASK_AG_CTX_VALID_MASK 0x1
5970#define YSTORM_RDMA_TASK_AG_CTX_VALID_SHIFT 6
5971#define YSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1
5972#define YSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7
5973 u8 flags1;
5974#define YSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
5975#define YSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0
5976#define YSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
5977#define YSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2
5978#define YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK 0x3
5979#define YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_SHIFT 4
5980#define YSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
5981#define YSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6
5982#define YSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
5983#define YSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7
5984 u8 flags2;
5985#define YSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1
5986#define YSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0
5987#define YSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
5988#define YSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1
5989#define YSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
5990#define YSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2
5991#define YSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
5992#define YSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3
5993#define YSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
5994#define YSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4
5995#define YSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
5996#define YSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5
5997#define YSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
5998#define YSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6
5999#define YSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
6000#define YSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7
6001 u8 key;
6002 __le32 mw_cnt;
6003 u8 ref_cnt_seq;
6004 u8 ctx_upd_seq;
6005 __le16 dif_flags;
6006 __le16 tx_ref_count;
6007 __le16 last_used_ltid;
6008 __le16 parent_mr_lo;
6009 __le16 parent_mr_hi;
6010 __le32 fbo_lo;
6011 __le32 fbo_hi;
6012};
6013
6014struct mstorm_rdma_task_ag_ctx {
6015 u8 reserved;
6016 u8 byte1;
6017 __le16 icid;
6018 u8 flags0;
6019#define MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
6020#define MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
6021#define MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
6022#define MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
6023#define MSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
6024#define MSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
6025#define MSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1
6026#define MSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6
6027#define MSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1
6028#define MSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7
6029 u8 flags1;
6030#define MSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
6031#define MSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0
6032#define MSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
6033#define MSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2
6034#define MSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3
6035#define MSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 4
6036#define MSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
6037#define MSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6
6038#define MSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
6039#define MSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7
6040 u8 flags2;
6041#define MSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1
6042#define MSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 0
6043#define MSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
6044#define MSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1
6045#define MSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
6046#define MSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2
6047#define MSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
6048#define MSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3
6049#define MSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
6050#define MSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4
6051#define MSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
6052#define MSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5
6053#define MSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
6054#define MSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6
6055#define MSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
6056#define MSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7
6057 u8 key;
6058 __le32 mw_cnt;
6059 u8 ref_cnt_seq;
6060 u8 ctx_upd_seq;
6061 __le16 dif_flags;
6062 __le16 tx_ref_count;
6063 __le16 last_used_ltid;
6064 __le16 parent_mr_lo;
6065 __le16 parent_mr_hi;
6066 __le32 fbo_lo;
6067 __le32 fbo_hi;
6068};
6069
6070struct ustorm_rdma_task_st_ctx {
6071 struct regpair temp[2];
6072};
6073
6074struct ustorm_rdma_task_ag_ctx {
6075 u8 reserved;
6076 u8 byte1;
6077 __le16 icid;
6078 u8 flags0;
6079#define USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
6080#define USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
6081#define USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
6082#define USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
6083#define USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_MASK 0x1
6084#define USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_SHIFT 5
6085#define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK 0x3
6086#define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_SHIFT 6
6087 u8 flags1;
6088#define USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK 0x3
6089#define USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_SHIFT 0
6090#define USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK 0x3
6091#define USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_SHIFT 2
6092#define USTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3
6093#define USTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 4
6094#define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3
6095#define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6
6096 u8 flags2;
6097#define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_MASK 0x1
6098#define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_SHIFT 0
6099#define USTORM_RDMA_TASK_AG_CTX_RESERVED2_MASK 0x1
6100#define USTORM_RDMA_TASK_AG_CTX_RESERVED2_SHIFT 1
6101#define USTORM_RDMA_TASK_AG_CTX_RESERVED3_MASK 0x1
6102#define USTORM_RDMA_TASK_AG_CTX_RESERVED3_SHIFT 2
6103#define USTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1
6104#define USTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 3
6105#define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
6106#define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
6107#define USTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
6108#define USTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 5
6109#define USTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
6110#define USTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 6
6111#define USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
6112#define USTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 7
6113 u8 flags3;
6114#define USTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
6115#define USTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 0
6116#define USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
6117#define USTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 1
6118#define USTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
6119#define USTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 2
6120#define USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
6121#define USTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 3
6122#define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
6123#define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
6124 __le32 dif_err_intervals;
6125 __le32 dif_error_1st_interval;
6126 __le32 reg2;
6127 __le32 dif_runt_value;
6128 __le32 reg4;
6129 __le32 reg5;
6130};
6131
6132struct rdma_task_context {
6133 struct ystorm_rdma_task_st_ctx ystorm_st_context;
6134 struct ystorm_rdma_task_ag_ctx ystorm_ag_context;
6135 struct tdif_task_context tdif_context;
6136 struct mstorm_rdma_task_ag_ctx mstorm_ag_context;
6137 struct mstorm_rdma_task_st_ctx mstorm_st_context;
6138 struct rdif_task_context rdif_context;
6139 struct ustorm_rdma_task_st_ctx ustorm_st_context;
6140 struct regpair ustorm_st_padding[2];
6141 struct ustorm_rdma_task_ag_ctx ustorm_ag_context;
6142};
6143
6144enum rdma_tid_type {
6145 RDMA_TID_REGISTERED_MR,
6146 RDMA_TID_FMR,
6147 RDMA_TID_MW_TYPE1,
6148 RDMA_TID_MW_TYPE2A,
6149 MAX_RDMA_TID_TYPE
6150};
6151
6152struct mstorm_rdma_conn_ag_ctx {
6153 u8 byte0;
6154 u8 byte1;
6155 u8 flags0;
6156#define MSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1
6157#define MSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0
6158#define MSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1
6159#define MSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
6160#define MSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3
6161#define MSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2
6162#define MSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
6163#define MSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4
6164#define MSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
6165#define MSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6
6166 u8 flags1;
6167#define MSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1
6168#define MSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0
6169#define MSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
6170#define MSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1
6171#define MSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
6172#define MSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2
6173#define MSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1
6174#define MSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3
6175#define MSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1
6176#define MSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4
6177#define MSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
6178#define MSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5
6179#define MSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
6180#define MSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6
6181#define MSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
6182#define MSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7
6183 __le16 word0;
6184 __le16 word1;
6185 __le32 reg0;
6186 __le32 reg1;
6187};
6188
6189struct tstorm_rdma_conn_ag_ctx {
6190 u8 reserved0;
6191 u8 byte1;
6192 u8 flags0;
6193#define TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
6194#define TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
6195#define TSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1
6196#define TSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
6197#define TSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1
6198#define TSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2
6199#define TSTORM_RDMA_CONN_AG_CTX_BIT3_MASK 0x1
6200#define TSTORM_RDMA_CONN_AG_CTX_BIT3_SHIFT 3
6201#define TSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1
6202#define TSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4
6203#define TSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1
6204#define TSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5
6205#define TSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3
6206#define TSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 6
6207 u8 flags1;
6208#define TSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
6209#define TSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 0
6210#define TSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
6211#define TSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 2
6212#define TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
6213#define TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4
6214#define TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
6215#define TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
6216 u8 flags2;
6217#define TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
6218#define TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
6219#define TSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3
6220#define TSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 2
6221#define TSTORM_RDMA_CONN_AG_CTX_CF7_MASK 0x3
6222#define TSTORM_RDMA_CONN_AG_CTX_CF7_SHIFT 4
6223#define TSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3
6224#define TSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 6
6225 u8 flags3;
6226#define TSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3
6227#define TSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 0
6228#define TSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3
6229#define TSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 2
6230#define TSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1
6231#define TSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 4
6232#define TSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
6233#define TSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 5
6234#define TSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
6235#define TSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 6
6236#define TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
6237#define TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
6238 u8 flags4;
6239#define TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
6240#define TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
6241#define TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
6242#define TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1
6243#define TSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1
6244#define TSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 2
6245#define TSTORM_RDMA_CONN_AG_CTX_CF7EN_MASK 0x1
6246#define TSTORM_RDMA_CONN_AG_CTX_CF7EN_SHIFT 3
6247#define TSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1
6248#define TSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 4
6249#define TSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1
6250#define TSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 5
6251#define TSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1
6252#define TSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 6
6253#define TSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1
6254#define TSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 7
6255 u8 flags5;
6256#define TSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1
6257#define TSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 0
6258#define TSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
6259#define TSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1
6260#define TSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
6261#define TSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2
6262#define TSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
6263#define TSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3
6264#define TSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1
6265#define TSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4
6266#define TSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1
6267#define TSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5
6268#define TSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1
6269#define TSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6
6270#define TSTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1
6271#define TSTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7
6272 __le32 reg0;
6273 __le32 reg1;
6274 __le32 reg2;
6275 __le32 reg3;
6276 __le32 reg4;
6277 __le32 reg5;
6278 __le32 reg6;
6279 __le32 reg7;
6280 __le32 reg8;
6281 u8 byte2;
6282 u8 byte3;
6283 __le16 word0;
6284 u8 byte4;
6285 u8 byte5;
6286 __le16 word1;
6287 __le16 word2;
6288 __le16 word3;
6289 __le32 reg9;
6290 __le32 reg10;
6291};
6292
6293struct tstorm_rdma_task_ag_ctx {
6294 u8 byte0;
6295 u8 byte1;
6296 __le16 word0;
6297 u8 flags0;
6298#define TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_MASK 0xF
6299#define TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_SHIFT 0
6300#define TSTORM_RDMA_TASK_AG_CTX_BIT0_MASK 0x1
6301#define TSTORM_RDMA_TASK_AG_CTX_BIT0_SHIFT 4
6302#define TSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
6303#define TSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
6304#define TSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1
6305#define TSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6
6306#define TSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1
6307#define TSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7
6308 u8 flags1;
6309#define TSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1
6310#define TSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0
6311#define TSTORM_RDMA_TASK_AG_CTX_BIT5_MASK 0x1
6312#define TSTORM_RDMA_TASK_AG_CTX_BIT5_SHIFT 1
6313#define TSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
6314#define TSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 2
6315#define TSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
6316#define TSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 4
6317#define TSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3
6318#define TSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 6
6319 u8 flags2;
6320#define TSTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3
6321#define TSTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 0
6322#define TSTORM_RDMA_TASK_AG_CTX_CF4_MASK 0x3
6323#define TSTORM_RDMA_TASK_AG_CTX_CF4_SHIFT 2
6324#define TSTORM_RDMA_TASK_AG_CTX_CF5_MASK 0x3
6325#define TSTORM_RDMA_TASK_AG_CTX_CF5_SHIFT 4
6326#define TSTORM_RDMA_TASK_AG_CTX_CF6_MASK 0x3
6327#define TSTORM_RDMA_TASK_AG_CTX_CF6_SHIFT 6
6328 u8 flags3;
6329#define TSTORM_RDMA_TASK_AG_CTX_CF7_MASK 0x3
6330#define TSTORM_RDMA_TASK_AG_CTX_CF7_SHIFT 0
6331#define TSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
6332#define TSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 2
6333#define TSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
6334#define TSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 3
6335#define TSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1
6336#define TSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 4
6337#define TSTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1
6338#define TSTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 5
6339#define TSTORM_RDMA_TASK_AG_CTX_CF4EN_MASK 0x1
6340#define TSTORM_RDMA_TASK_AG_CTX_CF4EN_SHIFT 6
6341#define TSTORM_RDMA_TASK_AG_CTX_CF5EN_MASK 0x1
6342#define TSTORM_RDMA_TASK_AG_CTX_CF5EN_SHIFT 7
6343 u8 flags4;
6344#define TSTORM_RDMA_TASK_AG_CTX_CF6EN_MASK 0x1
6345#define TSTORM_RDMA_TASK_AG_CTX_CF6EN_SHIFT 0
6346#define TSTORM_RDMA_TASK_AG_CTX_CF7EN_MASK 0x1
6347#define TSTORM_RDMA_TASK_AG_CTX_CF7EN_SHIFT 1
6348#define TSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
6349#define TSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 2
6350#define TSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
6351#define TSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 3
6352#define TSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
6353#define TSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 4
6354#define TSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
6355#define TSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 5
6356#define TSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
6357#define TSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 6
6358#define TSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
6359#define TSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 7
6360 u8 byte2;
6361 __le16 word1;
6362 __le32 reg0;
6363 u8 byte3;
6364 u8 byte4;
6365 __le16 word2;
6366 __le16 word3;
6367 __le16 word4;
6368 __le32 reg1;
6369 __le32 reg2;
6370};
6371
6372struct ustorm_rdma_conn_ag_ctx {
6373 u8 reserved;
6374 u8 byte1;
6375 u8 flags0;
6376#define USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
6377#define USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
6378#define USTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1
6379#define USTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
6380#define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
6381#define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 2
6382#define USTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
6383#define USTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4
6384#define USTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
6385#define USTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6
6386 u8 flags1;
6387#define USTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3
6388#define USTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 0
6389#define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3
6390#define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2
6391#define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3
6392#define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4
6393#define USTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3
6394#define USTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 6
6395 u8 flags2;
6396#define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
6397#define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
6398#define USTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
6399#define USTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1
6400#define USTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
6401#define USTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2
6402#define USTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1
6403#define USTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 3
6404#define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1
6405#define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4
6406#define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1
6407#define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5
6408#define USTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1
6409#define USTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 6
6410#define USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_MASK 0x1
6411#define USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_SHIFT 7
6412 u8 flags3;
6413#define USTORM_RDMA_CONN_AG_CTX_CQ_EN_MASK 0x1
6414#define USTORM_RDMA_CONN_AG_CTX_CQ_EN_SHIFT 0
6415#define USTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
6416#define USTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1
6417#define USTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
6418#define USTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2
6419#define USTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
6420#define USTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3
6421#define USTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1
6422#define USTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4
6423#define USTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1
6424#define USTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5
6425#define USTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1
6426#define USTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6
6427#define USTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1
6428#define USTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7
6429 u8 byte2;
6430 u8 byte3;
6431 __le16 conn_dpi;
6432 __le16 word1;
6433 __le32 cq_cons;
6434 __le32 cq_se_prod;
6435 __le32 cq_prod;
6436 __le32 reg3;
6437 __le16 int_timeout;
6438 __le16 word3;
6439};
6440
6441struct xstorm_roce_conn_ag_ctx_dq_ext_ld_part {
6442 u8 reserved0;
6443 u8 state;
6444 u8 flags0;
6445#define XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1
6446#define XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0
6447#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_MASK 0x1
6448#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_SHIFT 1
6449#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_MASK 0x1
6450#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_SHIFT 2
6451#define XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1
6452#define XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3
6453#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_MASK 0x1
6454#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_SHIFT 4
6455#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_MASK 0x1
6456#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_SHIFT 5
6457#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_MASK 0x1
6458#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_SHIFT 6
6459#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_MASK 0x1
6460#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_SHIFT 7
6461 u8 flags1;
6462#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_MASK 0x1
6463#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_SHIFT 0
6464#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_MASK 0x1
6465#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_SHIFT 1
6466#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_MASK 0x1
6467#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_SHIFT 2
6468#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK 0x1
6469#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_SHIFT 3
6470#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_MASK 0x1
6471#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_SHIFT 4
6472#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT13_MASK 0x1
6473#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT13_SHIFT 5
6474#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_MASK 0x1
6475#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_SHIFT 6
6476#define XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK 0x1
6477#define XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_SHIFT 7
6478 u8 flags2;
6479#define XSTORMROCECONNAGCTXDQEXTLDPART_CF0_MASK 0x3
6480#define XSTORMROCECONNAGCTXDQEXTLDPART_CF0_SHIFT 0
6481#define XSTORMROCECONNAGCTXDQEXTLDPART_CF1_MASK 0x3
6482#define XSTORMROCECONNAGCTXDQEXTLDPART_CF1_SHIFT 2
6483#define XSTORMROCECONNAGCTXDQEXTLDPART_CF2_MASK 0x3
6484#define XSTORMROCECONNAGCTXDQEXTLDPART_CF2_SHIFT 4
6485#define XSTORMROCECONNAGCTXDQEXTLDPART_CF3_MASK 0x3
6486#define XSTORMROCECONNAGCTXDQEXTLDPART_CF3_SHIFT 6
6487 u8 flags3;
6488#define XSTORMROCECONNAGCTXDQEXTLDPART_CF4_MASK 0x3
6489#define XSTORMROCECONNAGCTXDQEXTLDPART_CF4_SHIFT 0
6490#define XSTORMROCECONNAGCTXDQEXTLDPART_CF5_MASK 0x3
6491#define XSTORMROCECONNAGCTXDQEXTLDPART_CF5_SHIFT 2
6492#define XSTORMROCECONNAGCTXDQEXTLDPART_CF6_MASK 0x3
6493#define XSTORMROCECONNAGCTXDQEXTLDPART_CF6_SHIFT 4
6494#define XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_MASK 0x3
6495#define XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_SHIFT 6
6496 u8 flags4;
6497#define XSTORMROCECONNAGCTXDQEXTLDPART_CF8_MASK 0x3
6498#define XSTORMROCECONNAGCTXDQEXTLDPART_CF8_SHIFT 0
6499#define XSTORMROCECONNAGCTXDQEXTLDPART_CF9_MASK 0x3
6500#define XSTORMROCECONNAGCTXDQEXTLDPART_CF9_SHIFT 2
6501#define XSTORMROCECONNAGCTXDQEXTLDPART_CF10_MASK 0x3
6502#define XSTORMROCECONNAGCTXDQEXTLDPART_CF10_SHIFT 4
6503#define XSTORMROCECONNAGCTXDQEXTLDPART_CF11_MASK 0x3
6504#define XSTORMROCECONNAGCTXDQEXTLDPART_CF11_SHIFT 6
6505 u8 flags5;
6506#define XSTORMROCECONNAGCTXDQEXTLDPART_CF12_MASK 0x3
6507#define XSTORMROCECONNAGCTXDQEXTLDPART_CF12_SHIFT 0
6508#define XSTORMROCECONNAGCTXDQEXTLDPART_CF13_MASK 0x3
6509#define XSTORMROCECONNAGCTXDQEXTLDPART_CF13_SHIFT 2
6510#define XSTORMROCECONNAGCTXDQEXTLDPART_CF14_MASK 0x3
6511#define XSTORMROCECONNAGCTXDQEXTLDPART_CF14_SHIFT 4
6512#define XSTORMROCECONNAGCTXDQEXTLDPART_CF15_MASK 0x3
6513#define XSTORMROCECONNAGCTXDQEXTLDPART_CF15_SHIFT 6
6514 u8 flags6;
6515#define XSTORMROCECONNAGCTXDQEXTLDPART_CF16_MASK 0x3
6516#define XSTORMROCECONNAGCTXDQEXTLDPART_CF16_SHIFT 0
6517#define XSTORMROCECONNAGCTXDQEXTLDPART_CF17_MASK 0x3
6518#define XSTORMROCECONNAGCTXDQEXTLDPART_CF17_SHIFT 2
6519#define XSTORMROCECONNAGCTXDQEXTLDPART_CF18_MASK 0x3
6520#define XSTORMROCECONNAGCTXDQEXTLDPART_CF18_SHIFT 4
6521#define XSTORMROCECONNAGCTXDQEXTLDPART_CF19_MASK 0x3
6522#define XSTORMROCECONNAGCTXDQEXTLDPART_CF19_SHIFT 6
6523 u8 flags7;
6524#define XSTORMROCECONNAGCTXDQEXTLDPART_CF20_MASK 0x3
6525#define XSTORMROCECONNAGCTXDQEXTLDPART_CF20_SHIFT 0
6526#define XSTORMROCECONNAGCTXDQEXTLDPART_CF21_MASK 0x3
6527#define XSTORMROCECONNAGCTXDQEXTLDPART_CF21_SHIFT 2
6528#define XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3
6529#define XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4
6530#define XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1
6531#define XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6
6532#define XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1
6533#define XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7
6534 u8 flags8;
6535#define XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1
6536#define XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0
6537#define XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1
6538#define XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1
6539#define XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1
6540#define XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2
6541#define XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1
6542#define XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3
6543#define XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1
6544#define XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4
6545#define XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_MASK 0x1
6546#define XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_SHIFT 5
6547#define XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1
6548#define XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6
6549#define XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1
6550#define XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7
6551 u8 flags9;
6552#define XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1
6553#define XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0
6554#define XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1
6555#define XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1
6556#define XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1
6557#define XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2
6558#define XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1
6559#define XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3
6560#define XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1
6561#define XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4
6562#define XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1
6563#define XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5
6564#define XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_MASK 0x1
6565#define XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_SHIFT 6
6566#define XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_MASK 0x1
6567#define XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_SHIFT 7
6568 u8 flags10;
6569#define XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_MASK 0x1
6570#define XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_SHIFT 0
6571#define XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_MASK 0x1
6572#define XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_SHIFT 1
6573#define XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_MASK 0x1
6574#define XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_SHIFT 2
6575#define XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_MASK 0x1
6576#define XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_SHIFT 3
6577#define XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1
6578#define XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4
6579#define XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_MASK 0x1
6580#define XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_SHIFT 5
6581#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_MASK 0x1
6582#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_SHIFT 6
6583#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_MASK 0x1
6584#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_SHIFT 7
6585 u8 flags11;
6586#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_MASK 0x1
6587#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_SHIFT 0
6588#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_MASK 0x1
6589#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_SHIFT 1
6590#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_MASK 0x1
6591#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_SHIFT 2
6592#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1
6593#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3
6594#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1
6595#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4
6596#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1
6597#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5
6598#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1
6599#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6
6600#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1
6601#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7
6602 u8 flags12;
6603#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1
6604#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0
6605#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1
6606#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1
6607#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1
6608#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2
6609#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1
6610#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3
6611#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1
6612#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4
6613#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1
6614#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5
6615#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1
6616#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6
6617#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1
6618#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7
6619 u8 flags13;
6620#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1
6621#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0
6622#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1
6623#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1
6624#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1
6625#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2
6626#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1
6627#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3
6628#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1
6629#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4
6630#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1
6631#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5
6632#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1
6633#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6
6634#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1
6635#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7
6636 u8 flags14;
6637#define XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_MASK 0x1
6638#define XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_SHIFT 0
6639#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_MASK 0x1
6640#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_SHIFT 1
6641#define XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_MASK 0x3
6642#define XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_SHIFT 2
6643#define XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_MASK 0x1
6644#define XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_SHIFT 4
6645#define XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1
6646#define XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5
6647#define XSTORMROCECONNAGCTXDQEXTLDPART_CF23_MASK 0x3
6648#define XSTORMROCECONNAGCTXDQEXTLDPART_CF23_SHIFT 6
6649 u8 byte2;
6650 __le16 physical_q0;
6651 __le16 word1;
6652 __le16 word2;
6653 __le16 word3;
6654 __le16 word4;
6655 __le16 word5;
6656 __le16 conn_dpi;
6657 u8 byte3;
6658 u8 byte4;
6659 u8 byte5;
6660 u8 byte6;
6661 __le32 reg0;
6662 __le32 reg1;
6663 __le32 reg2;
6664 __le32 snd_nxt_psn;
6665 __le32 reg4;
6666};
6667
6668struct xstorm_rdma_conn_ag_ctx {
6669 u8 reserved0;
6670 u8 state;
6671 u8 flags0;
6672#define XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
6673#define XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
6674#define XSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1
6675#define XSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
6676#define XSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1
6677#define XSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2
6678#define XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
6679#define XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
6680#define XSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1
6681#define XSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4
6682#define XSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1
6683#define XSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5
6684#define XSTORM_RDMA_CONN_AG_CTX_BIT6_MASK 0x1
6685#define XSTORM_RDMA_CONN_AG_CTX_BIT6_SHIFT 6
6686#define XSTORM_RDMA_CONN_AG_CTX_BIT7_MASK 0x1
6687#define XSTORM_RDMA_CONN_AG_CTX_BIT7_SHIFT 7
6688 u8 flags1;
6689#define XSTORM_RDMA_CONN_AG_CTX_BIT8_MASK 0x1
6690#define XSTORM_RDMA_CONN_AG_CTX_BIT8_SHIFT 0
6691#define XSTORM_RDMA_CONN_AG_CTX_BIT9_MASK 0x1
6692#define XSTORM_RDMA_CONN_AG_CTX_BIT9_SHIFT 1
6693#define XSTORM_RDMA_CONN_AG_CTX_BIT10_MASK 0x1
6694#define XSTORM_RDMA_CONN_AG_CTX_BIT10_SHIFT 2
6695#define XSTORM_RDMA_CONN_AG_CTX_BIT11_MASK 0x1
6696#define XSTORM_RDMA_CONN_AG_CTX_BIT11_SHIFT 3
6697#define XSTORM_RDMA_CONN_AG_CTX_BIT12_MASK 0x1
6698#define XSTORM_RDMA_CONN_AG_CTX_BIT12_SHIFT 4
6699#define XSTORM_RDMA_CONN_AG_CTX_BIT13_MASK 0x1
6700#define XSTORM_RDMA_CONN_AG_CTX_BIT13_SHIFT 5
6701#define XSTORM_RDMA_CONN_AG_CTX_BIT14_MASK 0x1
6702#define XSTORM_RDMA_CONN_AG_CTX_BIT14_SHIFT 6
6703#define XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
6704#define XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7
6705 u8 flags2;
6706#define XSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3
6707#define XSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 0
6708#define XSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
6709#define XSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 2
6710#define XSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
6711#define XSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 4
6712#define XSTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3
6713#define XSTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 6
6714 u8 flags3;
6715#define XSTORM_RDMA_CONN_AG_CTX_CF4_MASK 0x3
6716#define XSTORM_RDMA_CONN_AG_CTX_CF4_SHIFT 0
6717#define XSTORM_RDMA_CONN_AG_CTX_CF5_MASK 0x3
6718#define XSTORM_RDMA_CONN_AG_CTX_CF5_SHIFT 2
6719#define XSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3
6720#define XSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 4
6721#define XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
6722#define XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
6723 u8 flags4;
6724#define XSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3
6725#define XSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 0
6726#define XSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3
6727#define XSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 2
6728#define XSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3
6729#define XSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 4
6730#define XSTORM_RDMA_CONN_AG_CTX_CF11_MASK 0x3
6731#define XSTORM_RDMA_CONN_AG_CTX_CF11_SHIFT 6
6732 u8 flags5;
6733#define XSTORM_RDMA_CONN_AG_CTX_CF12_MASK 0x3
6734#define XSTORM_RDMA_CONN_AG_CTX_CF12_SHIFT 0
6735#define XSTORM_RDMA_CONN_AG_CTX_CF13_MASK 0x3
6736#define XSTORM_RDMA_CONN_AG_CTX_CF13_SHIFT 2
6737#define XSTORM_RDMA_CONN_AG_CTX_CF14_MASK 0x3
6738#define XSTORM_RDMA_CONN_AG_CTX_CF14_SHIFT 4
6739#define XSTORM_RDMA_CONN_AG_CTX_CF15_MASK 0x3
6740#define XSTORM_RDMA_CONN_AG_CTX_CF15_SHIFT 6
6741 u8 flags6;
6742#define XSTORM_RDMA_CONN_AG_CTX_CF16_MASK 0x3
6743#define XSTORM_RDMA_CONN_AG_CTX_CF16_SHIFT 0
6744#define XSTORM_RDMA_CONN_AG_CTX_CF17_MASK 0x3
6745#define XSTORM_RDMA_CONN_AG_CTX_CF17_SHIFT 2
6746#define XSTORM_RDMA_CONN_AG_CTX_CF18_MASK 0x3
6747#define XSTORM_RDMA_CONN_AG_CTX_CF18_SHIFT 4
6748#define XSTORM_RDMA_CONN_AG_CTX_CF19_MASK 0x3
6749#define XSTORM_RDMA_CONN_AG_CTX_CF19_SHIFT 6
6750 u8 flags7;
6751#define XSTORM_RDMA_CONN_AG_CTX_CF20_MASK 0x3
6752#define XSTORM_RDMA_CONN_AG_CTX_CF20_SHIFT 0
6753#define XSTORM_RDMA_CONN_AG_CTX_CF21_MASK 0x3
6754#define XSTORM_RDMA_CONN_AG_CTX_CF21_SHIFT 2
6755#define XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_MASK 0x3
6756#define XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_SHIFT 4
6757#define XSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1
6758#define XSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 6
6759#define XSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
6760#define XSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 7
6761 u8 flags8;
6762#define XSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
6763#define XSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 0
6764#define XSTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1
6765#define XSTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 1
6766#define XSTORM_RDMA_CONN_AG_CTX_CF4EN_MASK 0x1
6767#define XSTORM_RDMA_CONN_AG_CTX_CF4EN_SHIFT 2
6768#define XSTORM_RDMA_CONN_AG_CTX_CF5EN_MASK 0x1
6769#define XSTORM_RDMA_CONN_AG_CTX_CF5EN_SHIFT 3
6770#define XSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1
6771#define XSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 4
6772#define XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
6773#define XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
6774#define XSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1
6775#define XSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 6
6776#define XSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1
6777#define XSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 7
6778 u8 flags9;
6779#define XSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1
6780#define XSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 0
6781#define XSTORM_RDMA_CONN_AG_CTX_CF11EN_MASK 0x1
6782#define XSTORM_RDMA_CONN_AG_CTX_CF11EN_SHIFT 1
6783#define XSTORM_RDMA_CONN_AG_CTX_CF12EN_MASK 0x1
6784#define XSTORM_RDMA_CONN_AG_CTX_CF12EN_SHIFT 2
6785#define XSTORM_RDMA_CONN_AG_CTX_CF13EN_MASK 0x1
6786#define XSTORM_RDMA_CONN_AG_CTX_CF13EN_SHIFT 3
6787#define XSTORM_RDMA_CONN_AG_CTX_CF14EN_MASK 0x1
6788#define XSTORM_RDMA_CONN_AG_CTX_CF14EN_SHIFT 4
6789#define XSTORM_RDMA_CONN_AG_CTX_CF15EN_MASK 0x1
6790#define XSTORM_RDMA_CONN_AG_CTX_CF15EN_SHIFT 5
6791#define XSTORM_RDMA_CONN_AG_CTX_CF16EN_MASK 0x1
6792#define XSTORM_RDMA_CONN_AG_CTX_CF16EN_SHIFT 6
6793#define XSTORM_RDMA_CONN_AG_CTX_CF17EN_MASK 0x1
6794#define XSTORM_RDMA_CONN_AG_CTX_CF17EN_SHIFT 7
6795 u8 flags10;
6796#define XSTORM_RDMA_CONN_AG_CTX_CF18EN_MASK 0x1
6797#define XSTORM_RDMA_CONN_AG_CTX_CF18EN_SHIFT 0
6798#define XSTORM_RDMA_CONN_AG_CTX_CF19EN_MASK 0x1
6799#define XSTORM_RDMA_CONN_AG_CTX_CF19EN_SHIFT 1
6800#define XSTORM_RDMA_CONN_AG_CTX_CF20EN_MASK 0x1
6801#define XSTORM_RDMA_CONN_AG_CTX_CF20EN_SHIFT 2
6802#define XSTORM_RDMA_CONN_AG_CTX_CF21EN_MASK 0x1
6803#define XSTORM_RDMA_CONN_AG_CTX_CF21EN_SHIFT 3
6804#define XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
6805#define XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
6806#define XSTORM_RDMA_CONN_AG_CTX_CF23EN_MASK 0x1
6807#define XSTORM_RDMA_CONN_AG_CTX_CF23EN_SHIFT 5
6808#define XSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1
6809#define XSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 6
6810#define XSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1
6811#define XSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 7
6812 u8 flags11;
6813#define XSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
6814#define XSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 0
6815#define XSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
6816#define XSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 1
6817#define XSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
6818#define XSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 2
6819#define XSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1
6820#define XSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 3
6821#define XSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1
6822#define XSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 4
6823#define XSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1
6824#define XSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 5
6825#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
6826#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
6827#define XSTORM_RDMA_CONN_AG_CTX_RULE9EN_MASK 0x1
6828#define XSTORM_RDMA_CONN_AG_CTX_RULE9EN_SHIFT 7
6829 u8 flags12;
6830#define XSTORM_RDMA_CONN_AG_CTX_RULE10EN_MASK 0x1
6831#define XSTORM_RDMA_CONN_AG_CTX_RULE10EN_SHIFT 0
6832#define XSTORM_RDMA_CONN_AG_CTX_RULE11EN_MASK 0x1
6833#define XSTORM_RDMA_CONN_AG_CTX_RULE11EN_SHIFT 1
6834#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
6835#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
6836#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
6837#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
6838#define XSTORM_RDMA_CONN_AG_CTX_RULE14EN_MASK 0x1
6839#define XSTORM_RDMA_CONN_AG_CTX_RULE14EN_SHIFT 4
6840#define XSTORM_RDMA_CONN_AG_CTX_RULE15EN_MASK 0x1
6841#define XSTORM_RDMA_CONN_AG_CTX_RULE15EN_SHIFT 5
6842#define XSTORM_RDMA_CONN_AG_CTX_RULE16EN_MASK 0x1
6843#define XSTORM_RDMA_CONN_AG_CTX_RULE16EN_SHIFT 6
6844#define XSTORM_RDMA_CONN_AG_CTX_RULE17EN_MASK 0x1
6845#define XSTORM_RDMA_CONN_AG_CTX_RULE17EN_SHIFT 7
6846 u8 flags13;
6847#define XSTORM_RDMA_CONN_AG_CTX_RULE18EN_MASK 0x1
6848#define XSTORM_RDMA_CONN_AG_CTX_RULE18EN_SHIFT 0
6849#define XSTORM_RDMA_CONN_AG_CTX_RULE19EN_MASK 0x1
6850#define XSTORM_RDMA_CONN_AG_CTX_RULE19EN_SHIFT 1
6851#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
6852#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
6853#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
6854#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
6855#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
6856#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
6857#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
6858#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
6859#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
6860#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
6861#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
6862#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
6863 u8 flags14;
6864#define XSTORM_RDMA_CONN_AG_CTX_MIGRATION_MASK 0x1
6865#define XSTORM_RDMA_CONN_AG_CTX_MIGRATION_SHIFT 0
6866#define XSTORM_RDMA_CONN_AG_CTX_BIT17_MASK 0x1
6867#define XSTORM_RDMA_CONN_AG_CTX_BIT17_SHIFT 1
6868#define XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3
6869#define XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2
6870#define XSTORM_RDMA_CONN_AG_CTX_RESERVED_MASK 0x1
6871#define XSTORM_RDMA_CONN_AG_CTX_RESERVED_SHIFT 4
6872#define XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
6873#define XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
6874#define XSTORM_RDMA_CONN_AG_CTX_CF23_MASK 0x3
6875#define XSTORM_RDMA_CONN_AG_CTX_CF23_SHIFT 6
6876 u8 byte2;
6877 __le16 physical_q0;
6878 __le16 word1;
6879 __le16 word2;
6880 __le16 word3;
6881 __le16 word4;
6882 __le16 word5;
6883 __le16 conn_dpi;
6884 u8 byte3;
6885 u8 byte4;
6886 u8 byte5;
6887 u8 byte6;
6888 __le32 reg0;
6889 __le32 reg1;
6890 __le32 reg2;
6891 __le32 snd_nxt_psn;
6892 __le32 reg4;
6893 __le32 reg5;
6894 __le32 reg6;
6895};
6896
6897struct ystorm_rdma_conn_ag_ctx {
6898 u8 byte0;
6899 u8 byte1;
6900 u8 flags0;
6901#define YSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1
6902#define YSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0
6903#define YSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1
6904#define YSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
6905#define YSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3
6906#define YSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2
6907#define YSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
6908#define YSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4
6909#define YSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
6910#define YSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6
6911 u8 flags1;
6912#define YSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1
6913#define YSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0
6914#define YSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
6915#define YSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1
6916#define YSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
6917#define YSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2
6918#define YSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1
6919#define YSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3
6920#define YSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1
6921#define YSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4
6922#define YSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
6923#define YSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5
6924#define YSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
6925#define YSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6
6926#define YSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
6927#define YSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7
6928 u8 byte2;
6929 u8 byte3;
6930 __le16 word0;
6931 __le32 reg0;
6932 __le32 reg1;
6933 __le16 word1;
6934 __le16 word2;
6935 __le16 word3;
6936 __le16 word4;
6937 __le32 reg2;
6938 __le32 reg3;
6939};
6940
6941struct mstorm_roce_conn_st_ctx {
6942 struct regpair temp[6];
6943};
6944
6945struct pstorm_roce_conn_st_ctx {
6946 struct regpair temp[16];
6947};
6948
6949struct ystorm_roce_conn_st_ctx {
6950 struct regpair temp[2];
6951};
6952
6953struct xstorm_roce_conn_st_ctx {
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02006954 struct regpair temp[24];
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03006955};
6956
6957struct tstorm_roce_conn_st_ctx {
6958 struct regpair temp[30];
6959};
6960
6961struct ustorm_roce_conn_st_ctx {
6962 struct regpair temp[12];
6963};
6964
6965struct roce_conn_context {
6966 struct ystorm_roce_conn_st_ctx ystorm_st_context;
6967 struct regpair ystorm_st_padding[2];
6968 struct pstorm_roce_conn_st_ctx pstorm_st_context;
6969 struct xstorm_roce_conn_st_ctx xstorm_st_context;
6970 struct regpair xstorm_st_padding[2];
6971 struct xstorm_rdma_conn_ag_ctx xstorm_ag_context;
6972 struct tstorm_rdma_conn_ag_ctx tstorm_ag_context;
6973 struct timers_context timer_context;
6974 struct ustorm_rdma_conn_ag_ctx ustorm_ag_context;
6975 struct tstorm_roce_conn_st_ctx tstorm_st_context;
6976 struct mstorm_roce_conn_st_ctx mstorm_st_context;
6977 struct ustorm_roce_conn_st_ctx ustorm_st_context;
6978 struct regpair ustorm_st_padding[2];
6979};
6980
6981struct roce_create_qp_req_ramrod_data {
6982 __le16 flags;
6983#define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3
6984#define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0
6985#define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1
6986#define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT 2
6987#define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_MASK 0x1
6988#define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_SHIFT 3
6989#define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_MASK 0x7
6990#define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_SHIFT 4
6991#define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_MASK 0x1
6992#define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_SHIFT 7
6993#define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF
6994#define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT 8
6995#define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF
6996#define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT 12
6997 u8 max_ord;
6998 u8 traffic_class;
6999 u8 hop_limit;
7000 u8 orq_num_pages;
7001 __le16 p_key;
7002 __le32 flow_label;
7003 __le32 dst_qp_id;
7004 __le32 ack_timeout_val;
7005 __le32 initial_psn;
7006 __le16 mtu;
7007 __le16 pd;
7008 __le16 sq_num_pages;
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02007009 __le16 low_latency_phy_queue;
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007010 struct regpair sq_pbl_addr;
7011 struct regpair orq_pbl_addr;
7012 __le16 local_mac_addr[3];
7013 __le16 remote_mac_addr[3];
7014 __le16 vlan_id;
7015 __le16 udp_src_port;
7016 __le32 src_gid[4];
7017 __le32 dst_gid[4];
7018 struct regpair qp_handle_for_cqe;
7019 struct regpair qp_handle_for_async;
7020 u8 stats_counter_id;
7021 u8 reserved3[7];
7022 __le32 cq_cid;
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02007023 __le16 regular_latency_phy_queue;
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007024 __le16 dpi;
7025};
7026
7027struct roce_create_qp_resp_ramrod_data {
7028 __le16 flags;
7029#define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3
7030#define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0
7031#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
7032#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT 2
7033#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
7034#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT 3
7035#define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
7036#define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT 4
7037#define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_MASK 0x1
7038#define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_SHIFT 5
7039#define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_MASK 0x1
7040#define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_SHIFT 6
Yuval Mintz05fafbf2016-08-19 09:33:31 +03007041#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_MASK 0x1
7042#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007043#define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_MASK 0x7
7044#define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_SHIFT 8
7045#define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F
7046#define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 11
7047 u8 max_ird;
7048 u8 traffic_class;
7049 u8 hop_limit;
7050 u8 irq_num_pages;
7051 __le16 p_key;
7052 __le32 flow_label;
7053 __le32 dst_qp_id;
7054 u8 stats_counter_id;
7055 u8 reserved1;
7056 __le16 mtu;
7057 __le32 initial_psn;
7058 __le16 pd;
7059 __le16 rq_num_pages;
7060 struct rdma_srq_id srq_id;
7061 struct regpair rq_pbl_addr;
7062 struct regpair irq_pbl_addr;
7063 __le16 local_mac_addr[3];
7064 __le16 remote_mac_addr[3];
7065 __le16 vlan_id;
7066 __le16 udp_src_port;
7067 __le32 src_gid[4];
7068 __le32 dst_gid[4];
7069 struct regpair qp_handle_for_cqe;
7070 struct regpair qp_handle_for_async;
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02007071 __le16 low_latency_phy_queue;
7072 u8 reserved2[6];
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007073 __le32 cq_cid;
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02007074 __le16 regular_latency_phy_queue;
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007075 __le16 dpi;
7076};
7077
7078struct roce_destroy_qp_req_output_params {
7079 __le32 num_bound_mw;
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02007080 __le32 cq_prod;
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007081};
7082
7083struct roce_destroy_qp_req_ramrod_data {
7084 struct regpair output_params_addr;
7085};
7086
7087struct roce_destroy_qp_resp_output_params {
7088 __le32 num_invalidated_mw;
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02007089 __le32 cq_prod;
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007090};
7091
7092struct roce_destroy_qp_resp_ramrod_data {
7093 struct regpair output_params_addr;
7094};
7095
7096enum roce_event_opcode {
7097 ROCE_EVENT_CREATE_QP = 11,
7098 ROCE_EVENT_MODIFY_QP,
7099 ROCE_EVENT_QUERY_QP,
7100 ROCE_EVENT_DESTROY_QP,
7101 MAX_ROCE_EVENT_OPCODE
7102};
7103
Yuval Mintz05fafbf2016-08-19 09:33:31 +03007104struct roce_init_func_ramrod_data {
7105 struct rdma_init_func_ramrod_data rdma;
7106};
7107
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007108struct roce_modify_qp_req_ramrod_data {
7109 __le16 flags;
7110#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1
7111#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0
7112#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_MASK 0x1
7113#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_SHIFT 1
7114#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_MASK 0x1
7115#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_SHIFT 2
7116#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_MASK 0x1
7117#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_SHIFT 3
7118#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1
7119#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT 4
7120#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_MASK 0x1
7121#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_SHIFT 5
7122#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_MASK 0x1
7123#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_SHIFT 6
7124#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_MASK 0x1
7125#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_SHIFT 7
7126#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_MASK 0x1
7127#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_SHIFT 8
7128#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_MASK 0x1
7129#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_SHIFT 9
7130#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_MASK 0x7
7131#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_SHIFT 10
7132#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_MASK 0x7
7133#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_SHIFT 13
7134 u8 fields;
7135#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF
7136#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT 0
7137#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF
7138#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT 4
7139 u8 max_ord;
7140 u8 traffic_class;
7141 u8 hop_limit;
7142 __le16 p_key;
7143 __le32 flow_label;
7144 __le32 ack_timeout_val;
7145 __le16 mtu;
7146 __le16 reserved2;
7147 __le32 reserved3[3];
7148 __le32 src_gid[4];
7149 __le32 dst_gid[4];
7150};
7151
7152struct roce_modify_qp_resp_ramrod_data {
7153 __le16 flags;
7154#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1
7155#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0
7156#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
7157#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT 1
7158#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
7159#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT 2
7160#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
7161#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT 3
7162#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_MASK 0x1
7163#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_SHIFT 4
7164#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1
7165#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT 5
7166#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_MASK 0x1
7167#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_SHIFT 6
7168#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_MASK 0x1
7169#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_SHIFT 7
7170#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_MASK 0x1
7171#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_SHIFT 8
7172#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1
7173#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT 9
7174#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_MASK 0x3F
7175#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_SHIFT 10
7176 u8 fields;
7177#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_MASK 0x7
7178#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_SHIFT 0
7179#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F
7180#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 3
7181 u8 max_ird;
7182 u8 traffic_class;
7183 u8 hop_limit;
7184 __le16 p_key;
7185 __le32 flow_label;
7186 __le16 mtu;
7187 __le16 reserved2;
7188 __le32 src_gid[4];
7189 __le32 dst_gid[4];
7190};
7191
7192struct roce_query_qp_req_output_params {
7193 __le32 psn;
7194 __le32 flags;
7195#define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_MASK 0x1
7196#define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_SHIFT 0
7197#define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_MASK 0x1
7198#define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_SHIFT 1
7199#define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_MASK 0x3FFFFFFF
7200#define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_SHIFT 2
7201};
7202
7203struct roce_query_qp_req_ramrod_data {
7204 struct regpair output_params_addr;
7205};
7206
7207struct roce_query_qp_resp_output_params {
7208 __le32 psn;
7209 __le32 err_flag;
7210#define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_MASK 0x1
7211#define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0
7212#define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_MASK 0x7FFFFFFF
7213#define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_SHIFT 1
7214};
7215
7216struct roce_query_qp_resp_ramrod_data {
7217 struct regpair output_params_addr;
7218};
7219
7220enum roce_ramrod_cmd_id {
7221 ROCE_RAMROD_CREATE_QP = 11,
7222 ROCE_RAMROD_MODIFY_QP,
7223 ROCE_RAMROD_QUERY_QP,
7224 ROCE_RAMROD_DESTROY_QP,
7225 MAX_ROCE_RAMROD_CMD_ID
7226};
7227
7228struct mstorm_roce_req_conn_ag_ctx {
7229 u8 byte0;
7230 u8 byte1;
7231 u8 flags0;
7232#define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
7233#define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
7234#define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
7235#define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1
7236#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
7237#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2
7238#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
7239#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4
7240#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
7241#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6
7242 u8 flags1;
7243#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
7244#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
7245#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
7246#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1
7247#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
7248#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2
7249#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
7250#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3
7251#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
7252#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4
7253#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
7254#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5
7255#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
7256#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6
7257#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
7258#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7
7259 __le16 word0;
7260 __le16 word1;
7261 __le32 reg0;
7262 __le32 reg1;
7263};
7264
7265struct mstorm_roce_resp_conn_ag_ctx {
7266 u8 byte0;
7267 u8 byte1;
7268 u8 flags0;
7269#define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
7270#define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
7271#define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
7272#define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1
7273#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
7274#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2
7275#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
7276#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4
7277#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
7278#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6
7279 u8 flags1;
7280#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
7281#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
7282#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
7283#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1
7284#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
7285#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2
7286#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
7287#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3
7288#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
7289#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4
7290#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
7291#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5
7292#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
7293#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6
7294#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
7295#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7
7296 __le16 word0;
7297 __le16 word1;
7298 __le32 reg0;
7299 __le32 reg1;
7300};
7301
7302enum roce_flavor {
7303 PLAIN_ROCE /* RoCE v1 */ ,
7304 RROCE_IPV4 /* RoCE v2 (Routable RoCE) over ipv4 */ ,
7305 RROCE_IPV6 /* RoCE v2 (Routable RoCE) over ipv6 */ ,
7306 MAX_ROCE_FLAVOR
7307};
7308
7309struct tstorm_roce_req_conn_ag_ctx {
7310 u8 reserved0;
7311 u8 state;
7312 u8 flags0;
7313#define TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
7314#define TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
7315#define TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURED_MASK 0x1
7316#define TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURED_SHIFT 1
7317#define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURED_MASK 0x1
7318#define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURED_SHIFT 2
7319#define TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_MASK 0x1
7320#define TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_SHIFT 3
7321#define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1
7322#define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4
7323#define TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_MASK 0x1
7324#define TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_SHIFT 5
7325#define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_MASK 0x3
7326#define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_SHIFT 6
7327 u8 flags1;
7328#define TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
7329#define TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 0
7330#define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_MASK 0x3
7331#define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_SHIFT 2
7332#define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
7333#define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4
7334#define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
7335#define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
7336 u8 flags2;
7337#define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
7338#define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
7339#define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_MASK 0x3
7340#define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_SHIFT 2
7341#define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_MASK 0x3
7342#define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_SHIFT 4
7343#define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_MASK 0x3
7344#define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_SHIFT 6
7345 u8 flags3;
7346#define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_MASK 0x3
7347#define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_SHIFT 0
7348#define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_MASK 0x3
7349#define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_SHIFT 2
7350#define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_MASK 0x1
7351#define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_SHIFT 4
7352#define TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
7353#define TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 5
7354#define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_MASK 0x1
7355#define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_SHIFT 6
7356#define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
7357#define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
7358 u8 flags4;
7359#define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
7360#define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
7361#define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
7362#define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1
7363#define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_MASK 0x1
7364#define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_SHIFT 2
7365#define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_MASK 0x1
7366#define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_SHIFT 3
7367#define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_MASK 0x1
7368#define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_SHIFT 4
7369#define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_MASK 0x1
7370#define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_SHIFT 5
7371#define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_MASK 0x1
7372#define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_SHIFT 6
7373#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
7374#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7
7375 u8 flags5;
7376#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
7377#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0
7378#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
7379#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1
7380#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
7381#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2
7382#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
7383#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3
7384#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
7385#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4
7386#define TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_MASK 0x1
7387#define TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_SHIFT 5
7388#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1
7389#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6
7390#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1
7391#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7
7392 __le32 reg0;
7393 __le32 snd_nxt_psn;
7394 __le32 snd_max_psn;
7395 __le32 orq_prod;
7396 __le32 reg4;
7397 __le32 reg5;
7398 __le32 reg6;
7399 __le32 reg7;
7400 __le32 reg8;
7401 u8 tx_cqe_error_type;
7402 u8 orq_cache_idx;
7403 __le16 snd_sq_cons_th;
7404 u8 byte4;
7405 u8 byte5;
7406 __le16 snd_sq_cons;
7407 __le16 word2;
7408 __le16 word3;
7409 __le32 reg9;
7410 __le32 reg10;
7411};
7412
7413struct tstorm_roce_resp_conn_ag_ctx {
7414 u8 byte0;
7415 u8 state;
7416 u8 flags0;
7417#define TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
7418#define TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
7419#define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
7420#define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1
7421#define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_MASK 0x1
7422#define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_SHIFT 2
7423#define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_MASK 0x1
7424#define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_SHIFT 3
7425#define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1
7426#define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4
7427#define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_MASK 0x1
7428#define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_SHIFT 5
7429#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
7430#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 6
7431 u8 flags1;
7432#define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
7433#define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 0
7434#define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_MASK 0x3
7435#define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_SHIFT 2
7436#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
7437#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 4
7438#define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
7439#define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
7440 u8 flags2;
7441#define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
7442#define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
7443#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3
7444#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 2
7445#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_MASK 0x3
7446#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_SHIFT 4
7447#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3
7448#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 6
7449 u8 flags3;
7450#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3
7451#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 0
7452#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3
7453#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 2
7454#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
7455#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 4
7456#define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
7457#define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 5
7458#define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_MASK 0x1
7459#define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_SHIFT 6
7460#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
7461#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 7
7462 u8 flags4;
7463#define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
7464#define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
7465#define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
7466#define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1
7467#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1
7468#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 2
7469#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_MASK 0x1
7470#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_SHIFT 3
7471#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1
7472#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 4
7473#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1
7474#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 5
7475#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1
7476#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 6
7477#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
7478#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7
7479 u8 flags5;
7480#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
7481#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0
7482#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
7483#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1
7484#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
7485#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2
7486#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
7487#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3
7488#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
7489#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4
7490#define TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_MASK 0x1
7491#define TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_SHIFT 5
7492#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
7493#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6
7494#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1
7495#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7
7496 __le32 psn_and_rxmit_id_echo;
7497 __le32 reg1;
7498 __le32 reg2;
7499 __le32 reg3;
7500 __le32 reg4;
7501 __le32 reg5;
7502 __le32 reg6;
7503 __le32 reg7;
7504 __le32 reg8;
7505 u8 tx_async_error_type;
7506 u8 byte3;
7507 __le16 rq_cons;
7508 u8 byte4;
7509 u8 byte5;
7510 __le16 rq_prod;
7511 __le16 conn_dpi;
7512 __le16 irq_cons;
7513 __le32 num_invlidated_mw;
7514 __le32 reg10;
7515};
7516
7517struct ustorm_roce_req_conn_ag_ctx {
7518 u8 byte0;
7519 u8 byte1;
7520 u8 flags0;
7521#define USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
7522#define USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
7523#define USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
7524#define USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1
7525#define USTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
7526#define USTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2
7527#define USTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
7528#define USTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4
7529#define USTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
7530#define USTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6
7531 u8 flags1;
7532#define USTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3
7533#define USTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 0
7534#define USTORM_ROCE_REQ_CONN_AG_CTX_CF4_MASK 0x3
7535#define USTORM_ROCE_REQ_CONN_AG_CTX_CF4_SHIFT 2
7536#define USTORM_ROCE_REQ_CONN_AG_CTX_CF5_MASK 0x3
7537#define USTORM_ROCE_REQ_CONN_AG_CTX_CF5_SHIFT 4
7538#define USTORM_ROCE_REQ_CONN_AG_CTX_CF6_MASK 0x3
7539#define USTORM_ROCE_REQ_CONN_AG_CTX_CF6_SHIFT 6
7540 u8 flags2;
7541#define USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
7542#define USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
7543#define USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
7544#define USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1
7545#define USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
7546#define USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2
7547#define USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1
7548#define USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 3
7549#define USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_MASK 0x1
7550#define USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_SHIFT 4
7551#define USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_MASK 0x1
7552#define USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_SHIFT 5
7553#define USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_MASK 0x1
7554#define USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_SHIFT 6
7555#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
7556#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7
7557 u8 flags3;
7558#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
7559#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0
7560#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
7561#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1
7562#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
7563#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2
7564#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
7565#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3
7566#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
7567#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4
7568#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1
7569#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 5
7570#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1
7571#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6
7572#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1
7573#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7
7574 u8 byte2;
7575 u8 byte3;
7576 __le16 word0;
7577 __le16 word1;
7578 __le32 reg0;
7579 __le32 reg1;
7580 __le32 reg2;
7581 __le32 reg3;
7582 __le16 word2;
7583 __le16 word3;
7584};
7585
7586struct ustorm_roce_resp_conn_ag_ctx {
7587 u8 byte0;
7588 u8 byte1;
7589 u8 flags0;
7590#define USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
7591#define USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
7592#define USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
7593#define USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1
7594#define USTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
7595#define USTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2
7596#define USTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
7597#define USTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4
7598#define USTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
7599#define USTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6
7600 u8 flags1;
7601#define USTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
7602#define USTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 0
7603#define USTORM_ROCE_RESP_CONN_AG_CTX_CF4_MASK 0x3
7604#define USTORM_ROCE_RESP_CONN_AG_CTX_CF4_SHIFT 2
7605#define USTORM_ROCE_RESP_CONN_AG_CTX_CF5_MASK 0x3
7606#define USTORM_ROCE_RESP_CONN_AG_CTX_CF5_SHIFT 4
7607#define USTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3
7608#define USTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 6
7609 u8 flags2;
7610#define USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
7611#define USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
7612#define USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
7613#define USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1
7614#define USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
7615#define USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2
7616#define USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
7617#define USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 3
7618#define USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_MASK 0x1
7619#define USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_SHIFT 4
7620#define USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_MASK 0x1
7621#define USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_SHIFT 5
7622#define USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1
7623#define USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 6
7624#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
7625#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7
7626 u8 flags3;
7627#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
7628#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0
7629#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
7630#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1
7631#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
7632#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2
7633#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
7634#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3
7635#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
7636#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4
7637#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1
7638#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 5
7639#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
7640#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6
7641#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1
7642#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7
7643 u8 byte2;
7644 u8 byte3;
7645 __le16 word0;
7646 __le16 word1;
7647 __le32 reg0;
7648 __le32 reg1;
7649 __le32 reg2;
7650 __le32 reg3;
7651 __le16 word2;
7652 __le16 word3;
7653};
7654
7655struct xstorm_roce_req_conn_ag_ctx {
7656 u8 reserved0;
7657 u8 state;
7658 u8 flags0;
7659#define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
7660#define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
7661#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_MASK 0x1
7662#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_SHIFT 1
7663#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_MASK 0x1
7664#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_SHIFT 2
7665#define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
7666#define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
7667#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_MASK 0x1
7668#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_SHIFT 4
7669#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_MASK 0x1
7670#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_SHIFT 5
7671#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_MASK 0x1
7672#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_SHIFT 6
7673#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_MASK 0x1
7674#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_SHIFT 7
7675 u8 flags1;
7676#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_MASK 0x1
7677#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_SHIFT 0
7678#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_MASK 0x1
7679#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_SHIFT 1
7680#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_MASK 0x1
7681#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_SHIFT 2
7682#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_MASK 0x1
7683#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_SHIFT 3
7684#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_MASK 0x1
7685#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_SHIFT 4
7686#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_MASK 0x1
7687#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_SHIFT 5
7688#define XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_MASK 0x1
7689#define XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_SHIFT 6
7690#define XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
7691#define XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7
7692 u8 flags2;
7693#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
7694#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 0
7695#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
7696#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 2
7697#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
7698#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 4
7699#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3
7700#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 6
7701 u8 flags3;
7702#define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3
7703#define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 0
7704#define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
7705#define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2
7706#define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_MASK 0x3
7707#define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_SHIFT 4
7708#define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
7709#define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
7710 u8 flags4;
7711#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_MASK 0x3
7712#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_SHIFT 0
7713#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_MASK 0x3
7714#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_SHIFT 2
7715#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_MASK 0x3
7716#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_SHIFT 4
7717#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_MASK 0x3
7718#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_SHIFT 6
7719 u8 flags5;
7720#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_MASK 0x3
7721#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_SHIFT 0
7722#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_MASK 0x3
7723#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_SHIFT 2
7724#define XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_MASK 0x3
7725#define XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_SHIFT 4
7726#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_MASK 0x3
7727#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_SHIFT 6
7728 u8 flags6;
7729#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_MASK 0x3
7730#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_SHIFT 0
7731#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_MASK 0x3
7732#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_SHIFT 2
7733#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_MASK 0x3
7734#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_SHIFT 4
7735#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_MASK 0x3
7736#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_SHIFT 6
7737 u8 flags7;
7738#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_MASK 0x3
7739#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_SHIFT 0
7740#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_MASK 0x3
7741#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_SHIFT 2
7742#define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_MASK 0x3
7743#define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_SHIFT 4
7744#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
7745#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 6
7746#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
7747#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 7
7748 u8 flags8;
7749#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
7750#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 0
7751#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1
7752#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 1
7753#define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1
7754#define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 2
7755#define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
7756#define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3
7757#define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_MASK 0x1
7758#define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_SHIFT 4
7759#define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
7760#define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
7761#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_MASK 0x1
7762#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_SHIFT 6
7763#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_MASK 0x1
7764#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_SHIFT 7
7765 u8 flags9;
7766#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_MASK 0x1
7767#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_SHIFT 0
7768#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_MASK 0x1
7769#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_SHIFT 1
7770#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_MASK 0x1
7771#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_SHIFT 2
7772#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_MASK 0x1
7773#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_SHIFT 3
7774#define XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_MASK 0x1
7775#define XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_SHIFT 4
7776#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_MASK 0x1
7777#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_SHIFT 5
7778#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_MASK 0x1
7779#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_SHIFT 6
7780#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_MASK 0x1
7781#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_SHIFT 7
7782 u8 flags10;
7783#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_MASK 0x1
7784#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_SHIFT 0
7785#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_MASK 0x1
7786#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_SHIFT 1
7787#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_MASK 0x1
7788#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_SHIFT 2
7789#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_MASK 0x1
7790#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_SHIFT 3
7791#define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
7792#define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
7793#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_MASK 0x1
7794#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_SHIFT 5
7795#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
7796#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 6
7797#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
7798#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 7
7799 u8 flags11;
7800#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
7801#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 0
7802#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
7803#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 1
7804#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
7805#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 2
7806#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
7807#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 3
7808#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1
7809#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 4
7810#define XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_MASK 0x1
7811#define XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_SHIFT 5
7812#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
7813#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
7814#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_MASK 0x1
7815#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_SHIFT 7
7816 u8 flags12;
7817#define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_MASK 0x1
7818#define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_SHIFT 0
7819#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_MASK 0x1
7820#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_SHIFT 1
7821#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
7822#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
7823#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
7824#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
7825#define XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_MASK 0x1
7826#define XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_SHIFT 4
7827#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_MASK 0x1
7828#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_SHIFT 5
7829#define XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_MASK 0x1
7830#define XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_SHIFT 6
7831#define XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_MASK 0x1
7832#define XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_SHIFT 7
7833 u8 flags13;
7834#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_MASK 0x1
7835#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_SHIFT 0
7836#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_MASK 0x1
7837#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_SHIFT 1
7838#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
7839#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
7840#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
7841#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
7842#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
7843#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
7844#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
7845#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
7846#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
7847#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
7848#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
7849#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
7850 u8 flags14;
7851#define XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_MASK 0x1
7852#define XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_SHIFT 0
7853#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_MASK 0x1
7854#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_SHIFT 1
7855#define XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3
7856#define XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2
7857#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_MASK 0x1
7858#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_SHIFT 4
7859#define XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
7860#define XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
7861#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_MASK 0x3
7862#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_SHIFT 6
7863 u8 byte2;
7864 __le16 physical_q0;
7865 __le16 word1;
7866 __le16 sq_cmp_cons;
7867 __le16 sq_cons;
7868 __le16 sq_prod;
7869 __le16 word5;
7870 __le16 conn_dpi;
7871 u8 byte3;
7872 u8 byte4;
7873 u8 byte5;
7874 u8 byte6;
7875 __le32 lsn;
7876 __le32 ssn;
7877 __le32 snd_una_psn;
7878 __le32 snd_nxt_psn;
7879 __le32 reg4;
7880 __le32 orq_cons_th;
7881 __le32 orq_cons;
7882};
7883
7884struct xstorm_roce_resp_conn_ag_ctx {
7885 u8 reserved0;
7886 u8 state;
7887 u8 flags0;
7888#define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
7889#define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
7890#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_MASK 0x1
7891#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_SHIFT 1
7892#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_MASK 0x1
7893#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_SHIFT 2
7894#define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
7895#define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
7896#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_MASK 0x1
7897#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_SHIFT 4
7898#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_MASK 0x1
7899#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_SHIFT 5
7900#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_MASK 0x1
7901#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_SHIFT 6
7902#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_MASK 0x1
7903#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_SHIFT 7
7904 u8 flags1;
7905#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_MASK 0x1
7906#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_SHIFT 0
7907#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_MASK 0x1
7908#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_SHIFT 1
7909#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_MASK 0x1
7910#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_SHIFT 2
7911#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_MASK 0x1
7912#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_SHIFT 3
7913#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_MASK 0x1
7914#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_SHIFT 4
7915#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_MASK 0x1
7916#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_SHIFT 5
7917#define XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_MASK 0x1
7918#define XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_SHIFT 6
7919#define XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
7920#define XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7
7921 u8 flags2;
7922#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
7923#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 0
7924#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
7925#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 2
7926#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
7927#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 4
7928#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
7929#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 6
7930 u8 flags3;
7931#define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_MASK 0x3
7932#define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_SHIFT 0
7933#define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
7934#define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2
7935#define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_MASK 0x3
7936#define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_SHIFT 4
7937#define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
7938#define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
7939 u8 flags4;
7940#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3
7941#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 0
7942#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3
7943#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 2
7944#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3
7945#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 4
7946#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_MASK 0x3
7947#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_SHIFT 6
7948 u8 flags5;
7949#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_MASK 0x3
7950#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_SHIFT 0
7951#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_MASK 0x3
7952#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_SHIFT 2
7953#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_MASK 0x3
7954#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_SHIFT 4
7955#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_MASK 0x3
7956#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_SHIFT 6
7957 u8 flags6;
7958#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_MASK 0x3
7959#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_SHIFT 0
7960#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_MASK 0x3
7961#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_SHIFT 2
7962#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_MASK 0x3
7963#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_SHIFT 4
7964#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_MASK 0x3
7965#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_SHIFT 6
7966 u8 flags7;
7967#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_MASK 0x3
7968#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_SHIFT 0
7969#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_MASK 0x3
7970#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_SHIFT 2
7971#define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_MASK 0x3
7972#define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_SHIFT 4
7973#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
7974#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 6
7975#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
7976#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 7
7977 u8 flags8;
7978#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
7979#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 0
7980#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
7981#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 1
7982#define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_MASK 0x1
7983#define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_SHIFT 2
7984#define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
7985#define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3
7986#define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_MASK 0x1
7987#define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_SHIFT 4
7988#define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
7989#define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
7990#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1
7991#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 6
7992#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1
7993#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 7
7994 u8 flags9;
7995#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1
7996#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 0
7997#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_MASK 0x1
7998#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_SHIFT 1
7999#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_MASK 0x1
8000#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_SHIFT 2
8001#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_MASK 0x1
8002#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_SHIFT 3
8003#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_MASK 0x1
8004#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_SHIFT 4
8005#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_MASK 0x1
8006#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_SHIFT 5
8007#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_MASK 0x1
8008#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_SHIFT 6
8009#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_MASK 0x1
8010#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_SHIFT 7
8011 u8 flags10;
8012#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_MASK 0x1
8013#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_SHIFT 0
8014#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_MASK 0x1
8015#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_SHIFT 1
8016#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_MASK 0x1
8017#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_SHIFT 2
8018#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_MASK 0x1
8019#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_SHIFT 3
8020#define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
8021#define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
8022#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_MASK 0x1
8023#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_SHIFT 5
8024#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
8025#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 6
8026#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
8027#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 7
8028 u8 flags11;
8029#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
8030#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 0
8031#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
8032#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 1
8033#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
8034#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 2
8035#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
8036#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 3
8037#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1
8038#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 4
8039#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
8040#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 5
8041#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
8042#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
8043#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_MASK 0x1
8044#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_SHIFT 7
8045 u8 flags12;
8046#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE10EN_MASK 0x1
8047#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE10EN_SHIFT 0
8048#define XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_MASK 0x1
8049#define XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_SHIFT 1
8050#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
8051#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
8052#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
8053#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
8054#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_MASK 0x1
8055#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_SHIFT 4
8056#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_MASK 0x1
8057#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_SHIFT 5
8058#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_MASK 0x1
8059#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_SHIFT 6
8060#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_MASK 0x1
8061#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_SHIFT 7
8062 u8 flags13;
8063#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_MASK 0x1
8064#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_SHIFT 0
8065#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_MASK 0x1
8066#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_SHIFT 1
8067#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
8068#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
8069#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
8070#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
8071#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
8072#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
8073#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
8074#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
8075#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
8076#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
8077#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
8078#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
8079 u8 flags14;
8080#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_MASK 0x1
8081#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_SHIFT 0
8082#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_MASK 0x1
8083#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_SHIFT 1
8084#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_MASK 0x1
8085#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_SHIFT 2
8086#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_MASK 0x1
8087#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_SHIFT 3
8088#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_MASK 0x1
8089#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_SHIFT 4
8090#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_MASK 0x1
8091#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_SHIFT 5
8092#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_MASK 0x3
8093#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_SHIFT 6
8094 u8 byte2;
8095 __le16 physical_q0;
8096 __le16 word1;
8097 __le16 irq_prod;
8098 __le16 word3;
8099 __le16 word4;
8100 __le16 word5;
8101 __le16 irq_cons;
8102 u8 rxmit_opcode;
8103 u8 byte4;
8104 u8 byte5;
8105 u8 byte6;
8106 __le32 rxmit_psn_and_id;
8107 __le32 rxmit_bytes_length;
8108 __le32 psn;
8109 __le32 reg3;
8110 __le32 reg4;
8111 __le32 reg5;
8112 __le32 msn_and_syndrome;
8113};
8114
8115struct ystorm_roce_req_conn_ag_ctx {
8116 u8 byte0;
8117 u8 byte1;
8118 u8 flags0;
8119#define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
8120#define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
8121#define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
8122#define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1
8123#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
8124#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2
8125#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
8126#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4
8127#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
8128#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6
8129 u8 flags1;
8130#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
8131#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
8132#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
8133#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1
8134#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
8135#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2
8136#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
8137#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3
8138#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
8139#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4
8140#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
8141#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5
8142#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
8143#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6
8144#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
8145#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7
8146 u8 byte2;
8147 u8 byte3;
8148 __le16 word0;
8149 __le32 reg0;
8150 __le32 reg1;
8151 __le16 word1;
8152 __le16 word2;
8153 __le16 word3;
8154 __le16 word4;
8155 __le32 reg2;
8156 __le32 reg3;
8157};
8158
8159struct ystorm_roce_resp_conn_ag_ctx {
8160 u8 byte0;
8161 u8 byte1;
8162 u8 flags0;
8163#define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
8164#define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
8165#define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
8166#define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1
8167#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
8168#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2
8169#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
8170#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4
8171#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
8172#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6
8173 u8 flags1;
8174#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
8175#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
8176#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
8177#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1
8178#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
8179#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2
8180#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
8181#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3
8182#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
8183#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4
8184#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
8185#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5
8186#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
8187#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6
8188#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
8189#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7
8190 u8 byte2;
8191 u8 byte3;
8192 __le16 word0;
8193 __le32 reg0;
8194 __le32 reg1;
8195 __le16 word1;
8196 __le16 word2;
8197 __le16 word3;
8198 __le16 word4;
8199 __le32 reg2;
8200 __le32 reg3;
8201};
8202
Arun Easi1e128c82017-02-15 06:28:22 -08008203struct ystorm_fcoe_conn_st_ctx {
8204 u8 func_mode;
8205 u8 cos;
8206 u8 conf_version;
8207 u8 eth_hdr_size;
8208 __le16 stat_ram_addr;
8209 __le16 mtu;
8210 __le16 max_fc_payload_len;
8211 __le16 tx_max_fc_pay_len;
8212 u8 fcp_cmd_size;
8213 u8 fcp_rsp_size;
8214 __le16 mss;
8215 struct regpair reserved;
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02008216 __le16 min_frame_size;
Arun Easi1e128c82017-02-15 06:28:22 -08008217 u8 protection_info_flags;
8218#define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1
8219#define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT 0
8220#define YSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1
8221#define YSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT 1
8222#define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_MASK 0x3F
8223#define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_SHIFT 2
8224 u8 dst_protection_per_mss;
8225 u8 src_protection_per_mss;
8226 u8 ptu_log_page_size;
8227 u8 flags;
8228#define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1
8229#define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 0
8230#define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1
8231#define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT 1
8232#define YSTORM_FCOE_CONN_ST_CTX_RSRV_MASK 0x3F
8233#define YSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT 2
8234 u8 fcp_xfer_size;
Arun Easi1e128c82017-02-15 06:28:22 -08008235};
8236
8237struct fcoe_vlan_fields {
8238 __le16 fields;
8239#define FCOE_VLAN_FIELDS_VID_MASK 0xFFF
8240#define FCOE_VLAN_FIELDS_VID_SHIFT 0
8241#define FCOE_VLAN_FIELDS_CLI_MASK 0x1
8242#define FCOE_VLAN_FIELDS_CLI_SHIFT 12
8243#define FCOE_VLAN_FIELDS_PRI_MASK 0x7
8244#define FCOE_VLAN_FIELDS_PRI_SHIFT 13
8245};
8246
8247union fcoe_vlan_field_union {
8248 struct fcoe_vlan_fields fields;
8249 __le16 val;
8250};
8251
8252union fcoe_vlan_vif_field_union {
8253 union fcoe_vlan_field_union vlan;
8254 __le16 vif;
8255};
8256
8257struct pstorm_fcoe_eth_context_section {
8258 u8 remote_addr_3;
8259 u8 remote_addr_2;
8260 u8 remote_addr_1;
8261 u8 remote_addr_0;
8262 u8 local_addr_1;
8263 u8 local_addr_0;
8264 u8 remote_addr_5;
8265 u8 remote_addr_4;
8266 u8 local_addr_5;
8267 u8 local_addr_4;
8268 u8 local_addr_3;
8269 u8 local_addr_2;
8270 union fcoe_vlan_vif_field_union vif_outer_vlan;
8271 __le16 vif_outer_eth_type;
8272 union fcoe_vlan_vif_field_union inner_vlan;
8273 __le16 inner_eth_type;
8274};
8275
8276struct pstorm_fcoe_conn_st_ctx {
8277 u8 func_mode;
8278 u8 cos;
8279 u8 conf_version;
8280 u8 rsrv;
8281 __le16 stat_ram_addr;
8282 __le16 mss;
8283 struct regpair abts_cleanup_addr;
8284 struct pstorm_fcoe_eth_context_section eth;
8285 u8 sid_2;
8286 u8 sid_1;
8287 u8 sid_0;
8288 u8 flags;
8289#define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_MASK 0x1
8290#define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_SHIFT 0
8291#define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_MASK 0x1
8292#define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_SHIFT 1
8293#define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1
8294#define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 2
8295#define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1
8296#define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT 3
8297#define PSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK 0xF
8298#define PSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT 4
8299 u8 did_2;
8300 u8 did_1;
8301 u8 did_0;
8302 u8 src_mac_index;
8303 __le16 rec_rr_tov_val;
8304 u8 q_relative_offset;
8305 u8 reserved1;
8306};
8307
8308struct xstorm_fcoe_conn_st_ctx {
8309 u8 func_mode;
8310 u8 src_mac_index;
8311 u8 conf_version;
8312 u8 cached_wqes_avail;
8313 __le16 stat_ram_addr;
8314 u8 flags;
8315#define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_MASK 0x1
8316#define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_SHIFT 0
8317#define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1
8318#define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 1
8319#define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_MASK 0x1
8320#define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_SHIFT 2
8321#define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_MASK 0x3
8322#define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_SHIFT 3
8323#define XSTORM_FCOE_CONN_ST_CTX_RSRV_MASK 0x7
8324#define XSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT 5
8325 u8 cached_wqes_offset;
8326 u8 reserved2;
8327 u8 eth_hdr_size;
8328 u8 seq_id;
8329 u8 max_conc_seqs;
8330 __le16 num_pages_in_pbl;
8331 __le16 reserved;
8332 struct regpair sq_pbl_addr;
8333 struct regpair sq_curr_page_addr;
8334 struct regpair sq_next_page_addr;
8335 struct regpair xferq_pbl_addr;
8336 struct regpair xferq_curr_page_addr;
8337 struct regpair xferq_next_page_addr;
8338 struct regpair respq_pbl_addr;
8339 struct regpair respq_curr_page_addr;
8340 struct regpair respq_next_page_addr;
8341 __le16 mtu;
8342 __le16 tx_max_fc_pay_len;
8343 __le16 max_fc_payload_len;
8344 __le16 min_frame_size;
8345 __le16 sq_pbl_next_index;
8346 __le16 respq_pbl_next_index;
8347 u8 fcp_cmd_byte_credit;
8348 u8 fcp_rsp_byte_credit;
8349 __le16 protection_info;
8350#define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_MASK 0x1
8351#define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_SHIFT 0
8352#define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1
8353#define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT 1
8354#define XSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1
8355#define XSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT 2
8356#define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_MASK 0x1
8357#define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_SHIFT 3
8358#define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_MASK 0xF
8359#define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_SHIFT 4
8360#define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_MASK 0xFF
8361#define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_SHIFT 8
8362 __le16 xferq_pbl_next_index;
8363 __le16 page_size;
8364 u8 mid_seq;
8365 u8 fcp_xfer_byte_credit;
8366 u8 reserved1[2];
8367 struct fcoe_wqe cached_wqes[16];
8368};
8369
8370struct xstorm_fcoe_conn_ag_ctx {
8371 u8 reserved0;
8372 u8 fcoe_state;
8373 u8 flags0;
8374#define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
8375#define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
8376#define XSTORM_FCOE_CONN_AG_CTX_RESERVED1_MASK 0x1
8377#define XSTORM_FCOE_CONN_AG_CTX_RESERVED1_SHIFT 1
8378#define XSTORM_FCOE_CONN_AG_CTX_RESERVED2_MASK 0x1
8379#define XSTORM_FCOE_CONN_AG_CTX_RESERVED2_SHIFT 2
8380#define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
8381#define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
8382#define XSTORM_FCOE_CONN_AG_CTX_RESERVED3_MASK 0x1
8383#define XSTORM_FCOE_CONN_AG_CTX_RESERVED3_SHIFT 4
8384#define XSTORM_FCOE_CONN_AG_CTX_RESERVED4_MASK 0x1
8385#define XSTORM_FCOE_CONN_AG_CTX_RESERVED4_SHIFT 5
8386#define XSTORM_FCOE_CONN_AG_CTX_RESERVED5_MASK 0x1
8387#define XSTORM_FCOE_CONN_AG_CTX_RESERVED5_SHIFT 6
8388#define XSTORM_FCOE_CONN_AG_CTX_RESERVED6_MASK 0x1
8389#define XSTORM_FCOE_CONN_AG_CTX_RESERVED6_SHIFT 7
8390 u8 flags1;
8391#define XSTORM_FCOE_CONN_AG_CTX_RESERVED7_MASK 0x1
8392#define XSTORM_FCOE_CONN_AG_CTX_RESERVED7_SHIFT 0
8393#define XSTORM_FCOE_CONN_AG_CTX_RESERVED8_MASK 0x1
8394#define XSTORM_FCOE_CONN_AG_CTX_RESERVED8_SHIFT 1
8395#define XSTORM_FCOE_CONN_AG_CTX_RESERVED9_MASK 0x1
8396#define XSTORM_FCOE_CONN_AG_CTX_RESERVED9_SHIFT 2
8397#define XSTORM_FCOE_CONN_AG_CTX_BIT11_MASK 0x1
8398#define XSTORM_FCOE_CONN_AG_CTX_BIT11_SHIFT 3
8399#define XSTORM_FCOE_CONN_AG_CTX_BIT12_MASK 0x1
8400#define XSTORM_FCOE_CONN_AG_CTX_BIT12_SHIFT 4
8401#define XSTORM_FCOE_CONN_AG_CTX_BIT13_MASK 0x1
8402#define XSTORM_FCOE_CONN_AG_CTX_BIT13_SHIFT 5
8403#define XSTORM_FCOE_CONN_AG_CTX_BIT14_MASK 0x1
8404#define XSTORM_FCOE_CONN_AG_CTX_BIT14_SHIFT 6
8405#define XSTORM_FCOE_CONN_AG_CTX_BIT15_MASK 0x1
8406#define XSTORM_FCOE_CONN_AG_CTX_BIT15_SHIFT 7
8407 u8 flags2;
8408#define XSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
8409#define XSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 0
8410#define XSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
8411#define XSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 2
8412#define XSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
8413#define XSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 4
8414#define XSTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3
8415#define XSTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 6
8416 u8 flags3;
8417#define XSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
8418#define XSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 0
8419#define XSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
8420#define XSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 2
8421#define XSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
8422#define XSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 4
8423#define XSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3
8424#define XSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT 6
8425 u8 flags4;
8426#define XSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3
8427#define XSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 0
8428#define XSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3
8429#define XSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 2
8430#define XSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3
8431#define XSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT 4
8432#define XSTORM_FCOE_CONN_AG_CTX_CF11_MASK 0x3
8433#define XSTORM_FCOE_CONN_AG_CTX_CF11_SHIFT 6
8434 u8 flags5;
8435#define XSTORM_FCOE_CONN_AG_CTX_CF12_MASK 0x3
8436#define XSTORM_FCOE_CONN_AG_CTX_CF12_SHIFT 0
8437#define XSTORM_FCOE_CONN_AG_CTX_CF13_MASK 0x3
8438#define XSTORM_FCOE_CONN_AG_CTX_CF13_SHIFT 2
8439#define XSTORM_FCOE_CONN_AG_CTX_CF14_MASK 0x3
8440#define XSTORM_FCOE_CONN_AG_CTX_CF14_SHIFT 4
8441#define XSTORM_FCOE_CONN_AG_CTX_CF15_MASK 0x3
8442#define XSTORM_FCOE_CONN_AG_CTX_CF15_SHIFT 6
8443 u8 flags6;
8444#define XSTORM_FCOE_CONN_AG_CTX_CF16_MASK 0x3
8445#define XSTORM_FCOE_CONN_AG_CTX_CF16_SHIFT 0
8446#define XSTORM_FCOE_CONN_AG_CTX_CF17_MASK 0x3
8447#define XSTORM_FCOE_CONN_AG_CTX_CF17_SHIFT 2
8448#define XSTORM_FCOE_CONN_AG_CTX_CF18_MASK 0x3
8449#define XSTORM_FCOE_CONN_AG_CTX_CF18_SHIFT 4
8450#define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_MASK 0x3
8451#define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_SHIFT 6
8452 u8 flags7;
8453#define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
8454#define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
8455#define XSTORM_FCOE_CONN_AG_CTX_RESERVED10_MASK 0x3
8456#define XSTORM_FCOE_CONN_AG_CTX_RESERVED10_SHIFT 2
8457#define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
8458#define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_SHIFT 4
8459#define XSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
8460#define XSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 6
8461#define XSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
8462#define XSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 7
8463 u8 flags8;
8464#define XSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
8465#define XSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 0
8466#define XSTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1
8467#define XSTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT 1
8468#define XSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
8469#define XSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 2
8470#define XSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
8471#define XSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 3
8472#define XSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
8473#define XSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 4
8474#define XSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1
8475#define XSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT 5
8476#define XSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1
8477#define XSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT 6
8478#define XSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1
8479#define XSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT 7
8480 u8 flags9;
8481#define XSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1
8482#define XSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 0
8483#define XSTORM_FCOE_CONN_AG_CTX_CF11EN_MASK 0x1
8484#define XSTORM_FCOE_CONN_AG_CTX_CF11EN_SHIFT 1
8485#define XSTORM_FCOE_CONN_AG_CTX_CF12EN_MASK 0x1
8486#define XSTORM_FCOE_CONN_AG_CTX_CF12EN_SHIFT 2
8487#define XSTORM_FCOE_CONN_AG_CTX_CF13EN_MASK 0x1
8488#define XSTORM_FCOE_CONN_AG_CTX_CF13EN_SHIFT 3
8489#define XSTORM_FCOE_CONN_AG_CTX_CF14EN_MASK 0x1
8490#define XSTORM_FCOE_CONN_AG_CTX_CF14EN_SHIFT 4
8491#define XSTORM_FCOE_CONN_AG_CTX_CF15EN_MASK 0x1
8492#define XSTORM_FCOE_CONN_AG_CTX_CF15EN_SHIFT 5
8493#define XSTORM_FCOE_CONN_AG_CTX_CF16EN_MASK 0x1
8494#define XSTORM_FCOE_CONN_AG_CTX_CF16EN_SHIFT 6
8495#define XSTORM_FCOE_CONN_AG_CTX_CF17EN_MASK 0x1
8496#define XSTORM_FCOE_CONN_AG_CTX_CF17EN_SHIFT 7
8497 u8 flags10;
8498#define XSTORM_FCOE_CONN_AG_CTX_CF18EN_MASK 0x1
8499#define XSTORM_FCOE_CONN_AG_CTX_CF18EN_SHIFT 0
8500#define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
8501#define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_SHIFT 1
8502#define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
8503#define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
8504#define XSTORM_FCOE_CONN_AG_CTX_RESERVED11_MASK 0x1
8505#define XSTORM_FCOE_CONN_AG_CTX_RESERVED11_SHIFT 3
8506#define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
8507#define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
8508#define XSTORM_FCOE_CONN_AG_CTX_CF23EN_MASK 0x1
8509#define XSTORM_FCOE_CONN_AG_CTX_CF23EN_SHIFT 5
8510#define XSTORM_FCOE_CONN_AG_CTX_RESERVED12_MASK 0x1
8511#define XSTORM_FCOE_CONN_AG_CTX_RESERVED12_SHIFT 6
8512#define XSTORM_FCOE_CONN_AG_CTX_RESERVED13_MASK 0x1
8513#define XSTORM_FCOE_CONN_AG_CTX_RESERVED13_SHIFT 7
8514 u8 flags11;
8515#define XSTORM_FCOE_CONN_AG_CTX_RESERVED14_MASK 0x1
8516#define XSTORM_FCOE_CONN_AG_CTX_RESERVED14_SHIFT 0
8517#define XSTORM_FCOE_CONN_AG_CTX_RESERVED15_MASK 0x1
8518#define XSTORM_FCOE_CONN_AG_CTX_RESERVED15_SHIFT 1
8519#define XSTORM_FCOE_CONN_AG_CTX_RESERVED16_MASK 0x1
8520#define XSTORM_FCOE_CONN_AG_CTX_RESERVED16_SHIFT 2
8521#define XSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
8522#define XSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 3
8523#define XSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
8524#define XSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 4
8525#define XSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
8526#define XSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 5
8527#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
8528#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
8529#define XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_MASK 0x1
8530#define XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_SHIFT 7
8531 u8 flags12;
8532#define XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_MASK 0x1
8533#define XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_SHIFT 0
8534#define XSTORM_FCOE_CONN_AG_CTX_RULE11EN_MASK 0x1
8535#define XSTORM_FCOE_CONN_AG_CTX_RULE11EN_SHIFT 1
8536#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
8537#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
8538#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
8539#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
8540#define XSTORM_FCOE_CONN_AG_CTX_RULE14EN_MASK 0x1
8541#define XSTORM_FCOE_CONN_AG_CTX_RULE14EN_SHIFT 4
8542#define XSTORM_FCOE_CONN_AG_CTX_RULE15EN_MASK 0x1
8543#define XSTORM_FCOE_CONN_AG_CTX_RULE15EN_SHIFT 5
8544#define XSTORM_FCOE_CONN_AG_CTX_RULE16EN_MASK 0x1
8545#define XSTORM_FCOE_CONN_AG_CTX_RULE16EN_SHIFT 6
8546#define XSTORM_FCOE_CONN_AG_CTX_RULE17EN_MASK 0x1
8547#define XSTORM_FCOE_CONN_AG_CTX_RULE17EN_SHIFT 7
8548 u8 flags13;
8549#define XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_MASK 0x1
8550#define XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_SHIFT 0
8551#define XSTORM_FCOE_CONN_AG_CTX_RULE19EN_MASK 0x1
8552#define XSTORM_FCOE_CONN_AG_CTX_RULE19EN_SHIFT 1
8553#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
8554#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
8555#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
8556#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
8557#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
8558#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
8559#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
8560#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
8561#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
8562#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
8563#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
8564#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
8565 u8 flags14;
8566#define XSTORM_FCOE_CONN_AG_CTX_BIT16_MASK 0x1
8567#define XSTORM_FCOE_CONN_AG_CTX_BIT16_SHIFT 0
8568#define XSTORM_FCOE_CONN_AG_CTX_BIT17_MASK 0x1
8569#define XSTORM_FCOE_CONN_AG_CTX_BIT17_SHIFT 1
8570#define XSTORM_FCOE_CONN_AG_CTX_BIT18_MASK 0x1
8571#define XSTORM_FCOE_CONN_AG_CTX_BIT18_SHIFT 2
8572#define XSTORM_FCOE_CONN_AG_CTX_BIT19_MASK 0x1
8573#define XSTORM_FCOE_CONN_AG_CTX_BIT19_SHIFT 3
8574#define XSTORM_FCOE_CONN_AG_CTX_BIT20_MASK 0x1
8575#define XSTORM_FCOE_CONN_AG_CTX_BIT20_SHIFT 4
8576#define XSTORM_FCOE_CONN_AG_CTX_BIT21_MASK 0x1
8577#define XSTORM_FCOE_CONN_AG_CTX_BIT21_SHIFT 5
8578#define XSTORM_FCOE_CONN_AG_CTX_CF23_MASK 0x3
8579#define XSTORM_FCOE_CONN_AG_CTX_CF23_SHIFT 6
8580 u8 byte2;
8581 __le16 physical_q0;
8582 __le16 word1;
8583 __le16 word2;
8584 __le16 sq_cons;
8585 __le16 sq_prod;
8586 __le16 xferq_prod;
8587 __le16 xferq_cons;
8588 u8 byte3;
8589 u8 byte4;
8590 u8 byte5;
8591 u8 byte6;
8592 __le32 remain_io;
8593 __le32 reg1;
8594 __le32 reg2;
8595 __le32 reg3;
8596 __le32 reg4;
8597 __le32 reg5;
8598 __le32 reg6;
8599 __le16 respq_prod;
8600 __le16 respq_cons;
8601 __le16 word9;
8602 __le16 word10;
8603 __le32 reg7;
8604 __le32 reg8;
8605};
8606
8607struct ustorm_fcoe_conn_st_ctx {
8608 struct regpair respq_pbl_addr;
8609 __le16 num_pages_in_pbl;
8610 u8 ptu_log_page_size;
8611 u8 log_page_size;
8612 __le16 respq_prod;
8613 u8 reserved[2];
8614};
8615
8616struct tstorm_fcoe_conn_ag_ctx {
8617 u8 reserved0;
8618 u8 fcoe_state;
8619 u8 flags0;
8620#define TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
8621#define TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
8622#define TSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
8623#define TSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
8624#define TSTORM_FCOE_CONN_AG_CTX_BIT2_MASK 0x1
8625#define TSTORM_FCOE_CONN_AG_CTX_BIT2_SHIFT 2
8626#define TSTORM_FCOE_CONN_AG_CTX_BIT3_MASK 0x1
8627#define TSTORM_FCOE_CONN_AG_CTX_BIT3_SHIFT 3
8628#define TSTORM_FCOE_CONN_AG_CTX_BIT4_MASK 0x1
8629#define TSTORM_FCOE_CONN_AG_CTX_BIT4_SHIFT 4
8630#define TSTORM_FCOE_CONN_AG_CTX_BIT5_MASK 0x1
8631#define TSTORM_FCOE_CONN_AG_CTX_BIT5_SHIFT 5
8632#define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_MASK 0x3
8633#define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_SHIFT 6
8634 u8 flags1;
8635#define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
8636#define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 0
8637#define TSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
8638#define TSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 2
8639#define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
8640#define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4
8641#define TSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
8642#define TSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 6
8643 u8 flags2;
8644#define TSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
8645#define TSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 0
8646#define TSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
8647#define TSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 2
8648#define TSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3
8649#define TSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT 4
8650#define TSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3
8651#define TSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 6
8652 u8 flags3;
8653#define TSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3
8654#define TSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 0
8655#define TSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3
8656#define TSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT 2
8657#define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_MASK 0x1
8658#define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_SHIFT 4
8659#define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
8660#define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
8661#define TSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
8662#define TSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 6
8663#define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
8664#define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
8665 u8 flags4;
8666#define TSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
8667#define TSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 0
8668#define TSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
8669#define TSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 1
8670#define TSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
8671#define TSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 2
8672#define TSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1
8673#define TSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT 3
8674#define TSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1
8675#define TSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT 4
8676#define TSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1
8677#define TSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT 5
8678#define TSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1
8679#define TSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 6
8680#define TSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
8681#define TSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7
8682 u8 flags5;
8683#define TSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
8684#define TSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0
8685#define TSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
8686#define TSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1
8687#define TSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
8688#define TSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2
8689#define TSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
8690#define TSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3
8691#define TSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
8692#define TSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4
8693#define TSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
8694#define TSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5
8695#define TSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
8696#define TSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6
8697#define TSTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1
8698#define TSTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7
8699 __le32 reg0;
8700 __le32 reg1;
8701};
8702
8703struct ustorm_fcoe_conn_ag_ctx {
8704 u8 byte0;
8705 u8 byte1;
8706 u8 flags0;
8707#define USTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
8708#define USTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0
8709#define USTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
8710#define USTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
8711#define USTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
8712#define USTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2
8713#define USTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
8714#define USTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4
8715#define USTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
8716#define USTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6
8717 u8 flags1;
8718#define USTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3
8719#define USTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 0
8720#define USTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
8721#define USTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 2
8722#define USTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
8723#define USTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 4
8724#define USTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
8725#define USTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 6
8726 u8 flags2;
8727#define USTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
8728#define USTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0
8729#define USTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
8730#define USTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1
8731#define USTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
8732#define USTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2
8733#define USTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1
8734#define USTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT 3
8735#define USTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
8736#define USTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 4
8737#define USTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
8738#define USTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 5
8739#define USTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
8740#define USTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 6
8741#define USTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
8742#define USTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7
8743 u8 flags3;
8744#define USTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
8745#define USTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0
8746#define USTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
8747#define USTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1
8748#define USTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
8749#define USTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2
8750#define USTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
8751#define USTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3
8752#define USTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
8753#define USTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4
8754#define USTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
8755#define USTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5
8756#define USTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
8757#define USTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6
8758#define USTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1
8759#define USTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7
8760 u8 byte2;
8761 u8 byte3;
8762 __le16 word0;
8763 __le16 word1;
8764 __le32 reg0;
8765 __le32 reg1;
8766 __le32 reg2;
8767 __le32 reg3;
8768 __le16 word2;
8769 __le16 word3;
8770};
8771
8772struct tstorm_fcoe_conn_st_ctx {
8773 __le16 stat_ram_addr;
8774 __le16 rx_max_fc_payload_len;
8775 __le16 e_d_tov_val;
8776 u8 flags;
8777#define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_MASK 0x1
8778#define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_SHIFT 0
8779#define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_MASK 0x1
8780#define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_SHIFT 1
8781#define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_MASK 0x3F
8782#define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_SHIFT 2
8783 u8 timers_cleanup_invocation_cnt;
8784 __le32 reserved1[2];
8785 __le32 dst_mac_address_bytes0to3;
8786 __le16 dst_mac_address_bytes4to5;
8787 __le16 ramrod_echo;
8788 u8 flags1;
8789#define TSTORM_FCOE_CONN_ST_CTX_MODE_MASK 0x3
8790#define TSTORM_FCOE_CONN_ST_CTX_MODE_SHIFT 0
8791#define TSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK 0x3F
8792#define TSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT 2
8793 u8 q_relative_offset;
8794 u8 bdq_resource_id;
8795 u8 reserved0[5];
8796};
8797
8798struct mstorm_fcoe_conn_ag_ctx {
8799 u8 byte0;
8800 u8 byte1;
8801 u8 flags0;
8802#define MSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
8803#define MSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0
8804#define MSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
8805#define MSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
8806#define MSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
8807#define MSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2
8808#define MSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
8809#define MSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4
8810#define MSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
8811#define MSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6
8812 u8 flags1;
8813#define MSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
8814#define MSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0
8815#define MSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
8816#define MSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1
8817#define MSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
8818#define MSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2
8819#define MSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
8820#define MSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3
8821#define MSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
8822#define MSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4
8823#define MSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
8824#define MSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5
8825#define MSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
8826#define MSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6
8827#define MSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
8828#define MSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7
8829 __le16 word0;
8830 __le16 word1;
8831 __le32 reg0;
8832 __le32 reg1;
8833};
8834
8835struct fcoe_mstorm_fcoe_conn_st_ctx_fp {
8836 __le16 xfer_prod;
8837 __le16 reserved1;
8838 u8 protection_info;
8839#define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_MASK 0x1
8840#define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_SHIFT 0
8841#define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_VALID_MASK 0x1
8842#define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_VALID_SHIFT 1
8843#define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_RESERVED0_MASK 0x3F
8844#define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_RESERVED0_SHIFT 2
8845 u8 q_relative_offset;
8846 u8 reserved2[2];
8847};
8848
8849struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp {
8850 __le16 conn_id;
8851 __le16 stat_ram_addr;
8852 __le16 num_pages_in_pbl;
8853 u8 ptu_log_page_size;
8854 u8 log_page_size;
8855 __le16 unsolicited_cq_count;
8856 __le16 cmdq_count;
8857 u8 bdq_resource_id;
8858 u8 reserved0[3];
8859 struct regpair xferq_pbl_addr;
8860 struct regpair reserved1;
8861 struct regpair reserved2[3];
8862};
8863
8864struct mstorm_fcoe_conn_st_ctx {
8865 struct fcoe_mstorm_fcoe_conn_st_ctx_fp fp;
8866 struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp non_fp;
8867};
8868
8869struct fcoe_conn_context {
8870 struct ystorm_fcoe_conn_st_ctx ystorm_st_context;
8871 struct pstorm_fcoe_conn_st_ctx pstorm_st_context;
8872 struct regpair pstorm_st_padding[2];
8873 struct xstorm_fcoe_conn_st_ctx xstorm_st_context;
8874 struct xstorm_fcoe_conn_ag_ctx xstorm_ag_context;
8875 struct regpair xstorm_ag_padding[6];
8876 struct ustorm_fcoe_conn_st_ctx ustorm_st_context;
8877 struct regpair ustorm_st_padding[2];
8878 struct tstorm_fcoe_conn_ag_ctx tstorm_ag_context;
8879 struct regpair tstorm_ag_padding[2];
8880 struct timers_context timer_context;
8881 struct ustorm_fcoe_conn_ag_ctx ustorm_ag_context;
8882 struct tstorm_fcoe_conn_st_ctx tstorm_st_context;
8883 struct mstorm_fcoe_conn_ag_ctx mstorm_ag_context;
8884 struct mstorm_fcoe_conn_st_ctx mstorm_st_context;
8885};
8886
8887struct fcoe_conn_offload_ramrod_params {
8888 struct fcoe_conn_offload_ramrod_data offload_ramrod_data;
8889};
8890
8891struct fcoe_conn_terminate_ramrod_params {
8892 struct fcoe_conn_terminate_ramrod_data terminate_ramrod_data;
8893};
8894
8895enum fcoe_event_type {
8896 FCOE_EVENT_INIT_FUNC,
8897 FCOE_EVENT_DESTROY_FUNC,
8898 FCOE_EVENT_STAT_FUNC,
8899 FCOE_EVENT_OFFLOAD_CONN,
8900 FCOE_EVENT_TERMINATE_CONN,
8901 FCOE_EVENT_ERROR,
8902 MAX_FCOE_EVENT_TYPE
8903};
8904
8905struct fcoe_init_ramrod_params {
8906 struct fcoe_init_func_ramrod_data init_ramrod_data;
8907};
8908
8909enum fcoe_ramrod_cmd_id {
8910 FCOE_RAMROD_CMD_ID_INIT_FUNC,
8911 FCOE_RAMROD_CMD_ID_DESTROY_FUNC,
8912 FCOE_RAMROD_CMD_ID_STAT_FUNC,
8913 FCOE_RAMROD_CMD_ID_OFFLOAD_CONN,
8914 FCOE_RAMROD_CMD_ID_TERMINATE_CONN,
8915 MAX_FCOE_RAMROD_CMD_ID
8916};
8917
8918struct fcoe_stat_ramrod_params {
8919 struct fcoe_stat_ramrod_data stat_ramrod_data;
8920};
8921
8922struct ystorm_fcoe_conn_ag_ctx {
8923 u8 byte0;
8924 u8 byte1;
8925 u8 flags0;
8926#define YSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
8927#define YSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0
8928#define YSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
8929#define YSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
8930#define YSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
8931#define YSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2
8932#define YSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
8933#define YSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4
8934#define YSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
8935#define YSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6
8936 u8 flags1;
8937#define YSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
8938#define YSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0
8939#define YSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
8940#define YSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1
8941#define YSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
8942#define YSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2
8943#define YSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
8944#define YSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3
8945#define YSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
8946#define YSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4
8947#define YSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
8948#define YSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5
8949#define YSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
8950#define YSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6
8951#define YSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
8952#define YSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7
8953 u8 byte2;
8954 u8 byte3;
8955 __le16 word0;
8956 __le32 reg0;
8957 __le32 reg1;
8958 __le16 word1;
8959 __le16 word2;
8960 __le16 word3;
8961 __le16 word4;
8962 __le32 reg2;
8963 __le32 reg3;
8964};
8965
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008966struct ystorm_iscsi_conn_st_ctx {
8967 __le32 reserved[4];
8968};
8969
8970struct pstorm_iscsi_tcp_conn_st_ctx {
8971 __le32 tcp[32];
8972 __le32 iscsi[4];
8973};
8974
8975struct xstorm_iscsi_tcp_conn_st_ctx {
8976 __le32 reserved_iscsi[40];
8977 __le32 reserved_tcp[4];
8978};
8979
8980struct xstorm_iscsi_conn_ag_ctx {
8981 u8 cdu_validation;
8982 u8 state;
8983 u8 flags0;
8984#define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
8985#define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
8986#define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1
8987#define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_SHIFT 1
8988#define XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_MASK 0x1
8989#define XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_SHIFT 2
8990#define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
8991#define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
8992#define XSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1
8993#define XSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT 4
8994#define XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_MASK 0x1
8995#define XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_SHIFT 5
8996#define XSTORM_ISCSI_CONN_AG_CTX_BIT6_MASK 0x1
8997#define XSTORM_ISCSI_CONN_AG_CTX_BIT6_SHIFT 6
8998#define XSTORM_ISCSI_CONN_AG_CTX_BIT7_MASK 0x1
8999#define XSTORM_ISCSI_CONN_AG_CTX_BIT7_SHIFT 7
9000 u8 flags1;
9001#define XSTORM_ISCSI_CONN_AG_CTX_BIT8_MASK 0x1
9002#define XSTORM_ISCSI_CONN_AG_CTX_BIT8_SHIFT 0
9003#define XSTORM_ISCSI_CONN_AG_CTX_BIT9_MASK 0x1
9004#define XSTORM_ISCSI_CONN_AG_CTX_BIT9_SHIFT 1
9005#define XSTORM_ISCSI_CONN_AG_CTX_BIT10_MASK 0x1
9006#define XSTORM_ISCSI_CONN_AG_CTX_BIT10_SHIFT 2
9007#define XSTORM_ISCSI_CONN_AG_CTX_BIT11_MASK 0x1
9008#define XSTORM_ISCSI_CONN_AG_CTX_BIT11_SHIFT 3
9009#define XSTORM_ISCSI_CONN_AG_CTX_BIT12_MASK 0x1
9010#define XSTORM_ISCSI_CONN_AG_CTX_BIT12_SHIFT 4
9011#define XSTORM_ISCSI_CONN_AG_CTX_BIT13_MASK 0x1
9012#define XSTORM_ISCSI_CONN_AG_CTX_BIT13_SHIFT 5
9013#define XSTORM_ISCSI_CONN_AG_CTX_BIT14_MASK 0x1
9014#define XSTORM_ISCSI_CONN_AG_CTX_BIT14_SHIFT 6
9015#define XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_MASK 0x1
9016#define XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_SHIFT 7
9017 u8 flags2;
9018#define XSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
9019#define XSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 0
9020#define XSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
9021#define XSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 2
9022#define XSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
9023#define XSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 4
9024#define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
9025#define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 6
9026 u8 flags3;
9027#define XSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
9028#define XSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 0
9029#define XSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
9030#define XSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 2
9031#define XSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
9032#define XSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 4
9033#define XSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3
9034#define XSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT 6
9035 u8 flags4;
9036#define XSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3
9037#define XSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT 0
9038#define XSTORM_ISCSI_CONN_AG_CTX_CF9_MASK 0x3
9039#define XSTORM_ISCSI_CONN_AG_CTX_CF9_SHIFT 2
9040#define XSTORM_ISCSI_CONN_AG_CTX_CF10_MASK 0x3
9041#define XSTORM_ISCSI_CONN_AG_CTX_CF10_SHIFT 4
9042#define XSTORM_ISCSI_CONN_AG_CTX_CF11_MASK 0x3
9043#define XSTORM_ISCSI_CONN_AG_CTX_CF11_SHIFT 6
9044 u8 flags5;
9045#define XSTORM_ISCSI_CONN_AG_CTX_CF12_MASK 0x3
9046#define XSTORM_ISCSI_CONN_AG_CTX_CF12_SHIFT 0
9047#define XSTORM_ISCSI_CONN_AG_CTX_CF13_MASK 0x3
9048#define XSTORM_ISCSI_CONN_AG_CTX_CF13_SHIFT 2
9049#define XSTORM_ISCSI_CONN_AG_CTX_CF14_MASK 0x3
9050#define XSTORM_ISCSI_CONN_AG_CTX_CF14_SHIFT 4
9051#define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_MASK 0x3
9052#define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_SHIFT 6
9053 u8 flags6;
9054#define XSTORM_ISCSI_CONN_AG_CTX_CF16_MASK 0x3
9055#define XSTORM_ISCSI_CONN_AG_CTX_CF16_SHIFT 0
9056#define XSTORM_ISCSI_CONN_AG_CTX_CF17_MASK 0x3
9057#define XSTORM_ISCSI_CONN_AG_CTX_CF17_SHIFT 2
9058#define XSTORM_ISCSI_CONN_AG_CTX_CF18_MASK 0x3
9059#define XSTORM_ISCSI_CONN_AG_CTX_CF18_SHIFT 4
9060#define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_MASK 0x3
9061#define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_SHIFT 6
9062 u8 flags7;
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02009063#define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_MASK 0x3
9064#define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_SHIFT 0
9065#define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_MASK 0x3
9066#define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_SHIFT 2
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03009067#define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_MASK 0x3
9068#define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_SHIFT 4
9069#define XSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
9070#define XSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 6
9071#define XSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
9072#define XSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 7
9073 u8 flags8;
9074#define XSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
9075#define XSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 0
9076#define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
9077#define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 1
9078#define XSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
9079#define XSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 2
9080#define XSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
9081#define XSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 3
9082#define XSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
9083#define XSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 4
9084#define XSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK 0x1
9085#define XSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT 5
9086#define XSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK 0x1
9087#define XSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT 6
9088#define XSTORM_ISCSI_CONN_AG_CTX_CF9EN_MASK 0x1
9089#define XSTORM_ISCSI_CONN_AG_CTX_CF9EN_SHIFT 7
9090 u8 flags9;
9091#define XSTORM_ISCSI_CONN_AG_CTX_CF10EN_MASK 0x1
9092#define XSTORM_ISCSI_CONN_AG_CTX_CF10EN_SHIFT 0
9093#define XSTORM_ISCSI_CONN_AG_CTX_CF11EN_MASK 0x1
9094#define XSTORM_ISCSI_CONN_AG_CTX_CF11EN_SHIFT 1
9095#define XSTORM_ISCSI_CONN_AG_CTX_CF12EN_MASK 0x1
9096#define XSTORM_ISCSI_CONN_AG_CTX_CF12EN_SHIFT 2
9097#define XSTORM_ISCSI_CONN_AG_CTX_CF13EN_MASK 0x1
9098#define XSTORM_ISCSI_CONN_AG_CTX_CF13EN_SHIFT 3
9099#define XSTORM_ISCSI_CONN_AG_CTX_CF14EN_MASK 0x1
9100#define XSTORM_ISCSI_CONN_AG_CTX_CF14EN_SHIFT 4
9101#define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_MASK 0x1
9102#define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_SHIFT 5
9103#define XSTORM_ISCSI_CONN_AG_CTX_CF16EN_MASK 0x1
9104#define XSTORM_ISCSI_CONN_AG_CTX_CF16EN_SHIFT 6
9105#define XSTORM_ISCSI_CONN_AG_CTX_CF17EN_MASK 0x1
9106#define XSTORM_ISCSI_CONN_AG_CTX_CF17EN_SHIFT 7
9107 u8 flags10;
9108#define XSTORM_ISCSI_CONN_AG_CTX_CF18EN_MASK 0x1
9109#define XSTORM_ISCSI_CONN_AG_CTX_CF18EN_SHIFT 0
9110#define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1
9111#define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT 1
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02009112#define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_MASK 0x1
9113#define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_SHIFT 2
9114#define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_MASK 0x1
9115#define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_SHIFT 3
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03009116#define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
9117#define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
9118#define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_MASK 0x1
9119#define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_SHIFT 5
9120#define XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
9121#define XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 6
9122#define XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_MASK 0x1
9123#define XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_SHIFT 7
9124 u8 flags11;
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02009125#define XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1
9126#define XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03009127#define XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
9128#define XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 1
9129#define XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_MASK 0x1
9130#define XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_SHIFT 2
9131#define XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
9132#define XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 3
9133#define XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
9134#define XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 4
9135#define XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
9136#define XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 5
9137#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
9138#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
9139#define XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_MASK 0x1
9140#define XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_SHIFT 7
9141 u8 flags12;
9142#define XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_MASK 0x1
9143#define XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_SHIFT 0
9144#define XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_MASK 0x1
9145#define XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_SHIFT 1
9146#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
9147#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
9148#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
9149#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
9150#define XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_MASK 0x1
9151#define XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_SHIFT 4
9152#define XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_MASK 0x1
9153#define XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_SHIFT 5
9154#define XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_MASK 0x1
9155#define XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_SHIFT 6
9156#define XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_MASK 0x1
9157#define XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_SHIFT 7
9158 u8 flags13;
9159#define XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_MASK 0x1
9160#define XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_SHIFT 0
9161#define XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_MASK 0x1
9162#define XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_SHIFT 1
9163#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
9164#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
9165#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
9166#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
9167#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
9168#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
9169#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
9170#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
9171#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
9172#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
9173#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
9174#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
9175 u8 flags14;
9176#define XSTORM_ISCSI_CONN_AG_CTX_BIT16_MASK 0x1
9177#define XSTORM_ISCSI_CONN_AG_CTX_BIT16_SHIFT 0
9178#define XSTORM_ISCSI_CONN_AG_CTX_BIT17_MASK 0x1
9179#define XSTORM_ISCSI_CONN_AG_CTX_BIT17_SHIFT 1
9180#define XSTORM_ISCSI_CONN_AG_CTX_BIT18_MASK 0x1
9181#define XSTORM_ISCSI_CONN_AG_CTX_BIT18_SHIFT 2
9182#define XSTORM_ISCSI_CONN_AG_CTX_BIT19_MASK 0x1
9183#define XSTORM_ISCSI_CONN_AG_CTX_BIT19_SHIFT 3
9184#define XSTORM_ISCSI_CONN_AG_CTX_BIT20_MASK 0x1
9185#define XSTORM_ISCSI_CONN_AG_CTX_BIT20_SHIFT 4
9186#define XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_MASK 0x1
9187#define XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_SHIFT 5
9188#define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_MASK 0x3
9189#define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_SHIFT 6
9190 u8 byte2;
9191 __le16 physical_q0;
9192 __le16 physical_q1;
9193 __le16 dummy_dorq_var;
9194 __le16 sq_cons;
9195 __le16 sq_prod;
9196 __le16 word5;
9197 __le16 slow_io_total_data_tx_update;
9198 u8 byte3;
9199 u8 byte4;
9200 u8 byte5;
9201 u8 byte6;
9202 __le32 reg0;
9203 __le32 reg1;
9204 __le32 reg2;
9205 __le32 more_to_send_seq;
9206 __le32 reg4;
9207 __le32 reg5;
9208 __le32 hq_scan_next_relevant_ack;
9209 __le16 r2tq_prod;
9210 __le16 r2tq_cons;
9211 __le16 hq_prod;
9212 __le16 hq_cons;
9213 __le32 remain_seq;
9214 __le32 bytes_to_next_pdu;
9215 __le32 hq_tcp_seq;
9216 u8 byte7;
9217 u8 byte8;
9218 u8 byte9;
9219 u8 byte10;
9220 u8 byte11;
9221 u8 byte12;
9222 u8 byte13;
9223 u8 byte14;
9224 u8 byte15;
9225 u8 byte16;
9226 __le16 word11;
9227 __le32 reg10;
9228 __le32 reg11;
9229 __le32 exp_stat_sn;
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02009230 __le32 ongoing_fast_rxmit_seq;
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03009231 __le32 reg14;
9232 __le32 reg15;
9233 __le32 reg16;
9234 __le32 reg17;
9235};
9236
9237struct tstorm_iscsi_conn_ag_ctx {
9238 u8 reserved0;
9239 u8 state;
9240 u8 flags0;
9241#define TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
9242#define TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
9243#define TSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
9244#define TSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
9245#define TSTORM_ISCSI_CONN_AG_CTX_BIT2_MASK 0x1
9246#define TSTORM_ISCSI_CONN_AG_CTX_BIT2_SHIFT 2
9247#define TSTORM_ISCSI_CONN_AG_CTX_BIT3_MASK 0x1
9248#define TSTORM_ISCSI_CONN_AG_CTX_BIT3_SHIFT 3
9249#define TSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1
9250#define TSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT 4
9251#define TSTORM_ISCSI_CONN_AG_CTX_BIT5_MASK 0x1
9252#define TSTORM_ISCSI_CONN_AG_CTX_BIT5_SHIFT 5
9253#define TSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
9254#define TSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 6
9255 u8 flags1;
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02009256#define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_MASK 0x3
9257#define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_SHIFT 0
9258#define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_MASK 0x3
9259#define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_SHIFT 2
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03009260#define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
9261#define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 4
9262#define TSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
9263#define TSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 6
9264 u8 flags2;
9265#define TSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
9266#define TSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 0
9267#define TSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
9268#define TSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 2
9269#define TSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3
9270#define TSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT 4
9271#define TSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3
9272#define TSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT 6
9273 u8 flags3;
9274#define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
9275#define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
9276#define TSTORM_ISCSI_CONN_AG_CTX_CF10_MASK 0x3
9277#define TSTORM_ISCSI_CONN_AG_CTX_CF10_SHIFT 2
9278#define TSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
9279#define TSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 4
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02009280#define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_MASK 0x1
9281#define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_SHIFT 5
9282#define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_MASK 0x1
9283#define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03009284#define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
9285#define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7
9286 u8 flags4;
9287#define TSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
9288#define TSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 0
9289#define TSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
9290#define TSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 1
9291#define TSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
9292#define TSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 2
9293#define TSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK 0x1
9294#define TSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT 3
9295#define TSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK 0x1
9296#define TSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT 4
9297#define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
9298#define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 5
9299#define TSTORM_ISCSI_CONN_AG_CTX_CF10EN_MASK 0x1
9300#define TSTORM_ISCSI_CONN_AG_CTX_CF10EN_SHIFT 6
9301#define TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
9302#define TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 7
9303 u8 flags5;
9304#define TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
9305#define TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 0
9306#define TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
9307#define TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 1
9308#define TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
9309#define TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 2
9310#define TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
9311#define TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 3
9312#define TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
9313#define TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 4
9314#define TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
9315#define TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 5
9316#define TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
9317#define TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 6
9318#define TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK 0x1
9319#define TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT 7
9320 __le32 reg0;
9321 __le32 reg1;
9322 __le32 reg2;
9323 __le32 reg3;
9324 __le32 reg4;
9325 __le32 reg5;
9326 __le32 reg6;
9327 __le32 reg7;
9328 __le32 reg8;
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02009329 u8 cid_offload_cnt;
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03009330 u8 byte3;
9331 __le16 word0;
9332};
9333
9334struct ustorm_iscsi_conn_ag_ctx {
9335 u8 byte0;
9336 u8 byte1;
9337 u8 flags0;
9338#define USTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
9339#define USTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0
9340#define USTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
9341#define USTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
9342#define USTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
9343#define USTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2
9344#define USTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
9345#define USTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4
9346#define USTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
9347#define USTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6
9348 u8 flags1;
9349#define USTORM_ISCSI_CONN_AG_CTX_CF3_MASK 0x3
9350#define USTORM_ISCSI_CONN_AG_CTX_CF3_SHIFT 0
9351#define USTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
9352#define USTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 2
9353#define USTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
9354#define USTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 4
9355#define USTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
9356#define USTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 6
9357 u8 flags2;
9358#define USTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
9359#define USTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0
9360#define USTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
9361#define USTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1
9362#define USTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
9363#define USTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2
9364#define USTORM_ISCSI_CONN_AG_CTX_CF3EN_MASK 0x1
9365#define USTORM_ISCSI_CONN_AG_CTX_CF3EN_SHIFT 3
9366#define USTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
9367#define USTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 4
9368#define USTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
9369#define USTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 5
9370#define USTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
9371#define USTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 6
9372#define USTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
9373#define USTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 7
9374 u8 flags3;
9375#define USTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
9376#define USTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 0
9377#define USTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
9378#define USTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 1
9379#define USTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
9380#define USTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 2
9381#define USTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
9382#define USTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 3
9383#define USTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
9384#define USTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 4
9385#define USTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
9386#define USTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 5
9387#define USTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
9388#define USTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 6
9389#define USTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK 0x1
9390#define USTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT 7
9391 u8 byte2;
9392 u8 byte3;
9393 __le16 word0;
9394 __le16 word1;
9395 __le32 reg0;
9396 __le32 reg1;
9397 __le32 reg2;
9398 __le32 reg3;
9399 __le16 word2;
9400 __le16 word3;
9401};
9402
9403struct tstorm_iscsi_conn_st_ctx {
9404 __le32 reserved[40];
9405};
9406
9407struct mstorm_iscsi_conn_ag_ctx {
9408 u8 reserved;
9409 u8 state;
9410 u8 flags0;
9411#define MSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
9412#define MSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0
9413#define MSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
9414#define MSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
9415#define MSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
9416#define MSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2
9417#define MSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
9418#define MSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4
9419#define MSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
9420#define MSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6
9421 u8 flags1;
9422#define MSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
9423#define MSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0
9424#define MSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
9425#define MSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1
9426#define MSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
9427#define MSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2
9428#define MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
9429#define MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 3
9430#define MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
9431#define MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 4
9432#define MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
9433#define MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 5
9434#define MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
9435#define MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 6
9436#define MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
9437#define MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 7
9438 __le16 word0;
9439 __le16 word1;
9440 __le32 reg0;
9441 __le32 reg1;
9442};
9443
9444struct mstorm_iscsi_tcp_conn_st_ctx {
9445 __le32 reserved_tcp[20];
9446 __le32 reserved_iscsi[8];
9447};
9448
9449struct ustorm_iscsi_conn_st_ctx {
9450 __le32 reserved[52];
9451};
9452
9453struct iscsi_conn_context {
9454 struct ystorm_iscsi_conn_st_ctx ystorm_st_context;
9455 struct regpair ystorm_st_padding[2];
9456 struct pstorm_iscsi_tcp_conn_st_ctx pstorm_st_context;
9457 struct regpair pstorm_st_padding[2];
9458 struct pb_context xpb2_context;
9459 struct xstorm_iscsi_tcp_conn_st_ctx xstorm_st_context;
9460 struct regpair xstorm_st_padding[2];
9461 struct xstorm_iscsi_conn_ag_ctx xstorm_ag_context;
9462 struct tstorm_iscsi_conn_ag_ctx tstorm_ag_context;
9463 struct regpair tstorm_ag_padding[2];
9464 struct timers_context timer_context;
9465 struct ustorm_iscsi_conn_ag_ctx ustorm_ag_context;
9466 struct pb_context upb_context;
9467 struct tstorm_iscsi_conn_st_ctx tstorm_st_context;
9468 struct regpair tstorm_st_padding[2];
9469 struct mstorm_iscsi_conn_ag_ctx mstorm_ag_context;
9470 struct mstorm_iscsi_tcp_conn_st_ctx mstorm_st_context;
9471 struct ustorm_iscsi_conn_st_ctx ustorm_st_context;
9472};
9473
9474struct iscsi_init_ramrod_params {
9475 struct iscsi_spe_func_init iscsi_init_spe;
9476 struct tcp_init_params tcp_init;
9477};
9478
9479struct ystorm_iscsi_conn_ag_ctx {
9480 u8 byte0;
9481 u8 byte1;
9482 u8 flags0;
9483#define YSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
9484#define YSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0
9485#define YSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
9486#define YSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
9487#define YSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
9488#define YSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2
9489#define YSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
9490#define YSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4
9491#define YSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
9492#define YSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6
9493 u8 flags1;
9494#define YSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
9495#define YSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0
9496#define YSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
9497#define YSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1
9498#define YSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
9499#define YSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2
9500#define YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
9501#define YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 3
9502#define YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
9503#define YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 4
9504#define YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
9505#define YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 5
9506#define YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
9507#define YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 6
9508#define YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
9509#define YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 7
9510 u8 byte2;
9511 u8 byte3;
9512 __le16 word0;
9513 __le32 reg0;
9514 __le32 reg1;
9515 __le16 word1;
9516 __le16 word2;
9517 __le16 word3;
9518 __le16 word4;
9519 __le32 reg2;
9520 __le32 reg3;
9521};
Tomer Tayarc965db42016-09-07 16:36:24 +03009522
9523#define MFW_TRACE_SIGNATURE 0x25071946
9524
9525/* The trace in the buffer */
9526#define MFW_TRACE_EVENTID_MASK 0x00ffff
9527#define MFW_TRACE_PRM_SIZE_MASK 0x0f0000
9528#define MFW_TRACE_PRM_SIZE_SHIFT 16
9529#define MFW_TRACE_ENTRY_SIZE 3
9530
9531struct mcp_trace {
9532 u32 signature; /* Help to identify that the trace is valid */
9533 u32 size; /* the size of the trace buffer in bytes */
9534 u32 curr_level; /* 2 - all will be written to the buffer
9535 * 1 - debug trace will not be written
9536 * 0 - just errors will be written to the buffer
9537 */
9538 u32 modules_mask[2]; /* a bit per module, 1 means write it, 0 means
9539 * mask it.
9540 */
9541
9542 /* Warning: the following pointers are assumed to be 32bits as they are
9543 * used only in the MFW.
9544 */
9545 u32 trace_prod; /* The next trace will be written to this offset */
9546 u32 trace_oldest; /* The oldest valid trace starts at this offset
9547 * (usually very close after the current producer).
9548 */
9549};
9550
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009551#define VF_MAX_STATIC 192
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009552
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009553#define MCP_GLOB_PATH_MAX 2
9554#define MCP_PORT_MAX 2
9555#define MCP_GLOB_PORT_MAX 4
9556#define MCP_GLOB_FUNC_MAX 16
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009557
Tomer Tayarc965db42016-09-07 16:36:24 +03009558typedef u32 offsize_t; /* In DWORDS !!! */
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009559/* Offset from the beginning of the MCP scratchpad */
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009560#define OFFSIZE_OFFSET_SHIFT 0
9561#define OFFSIZE_OFFSET_MASK 0x0000ffff
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009562/* Size of specific element (not the whole array if any) */
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009563#define OFFSIZE_SIZE_SHIFT 16
9564#define OFFSIZE_SIZE_MASK 0xffff0000
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009565
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009566#define SECTION_OFFSET(_offsize) ((((_offsize & \
9567 OFFSIZE_OFFSET_MASK) >> \
9568 OFFSIZE_OFFSET_SHIFT) << 2))
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009569
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009570#define QED_SECTION_SIZE(_offsize) (((_offsize & \
9571 OFFSIZE_SIZE_MASK) >> \
9572 OFFSIZE_SIZE_SHIFT) << 2)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009573
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009574#define SECTION_ADDR(_offsize, idx) (MCP_REG_SCRATCH + \
9575 SECTION_OFFSET(_offsize) + \
9576 (QED_SECTION_SIZE(_offsize) * idx))
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009577
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009578#define SECTION_OFFSIZE_ADDR(_pub_base, _section) \
9579 (_pub_base + offsetof(struct mcp_public_data, sections[_section]))
9580
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009581/* PHY configuration */
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009582struct eth_phy_cfg {
9583 u32 speed;
9584#define ETH_SPEED_AUTONEG 0
9585#define ETH_SPEED_SMARTLINQ 0x8
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009586
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009587 u32 pause;
9588#define ETH_PAUSE_NONE 0x0
9589#define ETH_PAUSE_AUTONEG 0x1
9590#define ETH_PAUSE_RX 0x2
9591#define ETH_PAUSE_TX 0x4
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009592
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009593 u32 adv_speed;
9594 u32 loopback_mode;
9595#define ETH_LOOPBACK_NONE (0)
9596#define ETH_LOOPBACK_INT_PHY (1)
9597#define ETH_LOOPBACK_EXT_PHY (2)
9598#define ETH_LOOPBACK_EXT (3)
9599#define ETH_LOOPBACK_MAC (4)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009600
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009601 u32 feature_config_flags;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009602#define ETH_EEE_MODE_ADV_LPI (1 << 0)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009603};
9604
9605struct port_mf_cfg {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009606 u32 dynamic_cfg;
9607#define PORT_MF_CFG_OV_TAG_MASK 0x0000ffff
9608#define PORT_MF_CFG_OV_TAG_SHIFT 0
9609#define PORT_MF_CFG_OV_TAG_DEFAULT PORT_MF_CFG_OV_TAG_MASK
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009610
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009611 u32 reserved[1];
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009612};
9613
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009614struct eth_stats {
9615 u64 r64;
9616 u64 r127;
9617 u64 r255;
9618 u64 r511;
9619 u64 r1023;
9620 u64 r1518;
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02009621
9622 union {
9623 struct {
9624 u64 r1522;
9625 u64 r2047;
9626 u64 r4095;
9627 u64 r9216;
9628 u64 r16383;
9629 } bb0;
9630 struct {
9631 u64 unused1;
9632 u64 r1519_to_max;
9633 u64 unused2;
9634 u64 unused3;
9635 u64 unused4;
9636 } ah0;
9637 } u0;
9638
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009639 u64 rfcs;
9640 u64 rxcf;
9641 u64 rxpf;
9642 u64 rxpp;
9643 u64 raln;
9644 u64 rfcr;
9645 u64 rovr;
9646 u64 rjbr;
9647 u64 rund;
9648 u64 rfrg;
9649 u64 t64;
9650 u64 t127;
9651 u64 t255;
9652 u64 t511;
9653 u64 t1023;
9654 u64 t1518;
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02009655
9656 union {
9657 struct {
9658 u64 t2047;
9659 u64 t4095;
9660 u64 t9216;
9661 u64 t16383;
9662 } bb1;
9663 struct {
9664 u64 t1519_to_max;
9665 u64 unused6;
9666 u64 unused7;
9667 u64 unused8;
9668 } ah1;
9669 } u1;
9670
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009671 u64 txpf;
9672 u64 txpp;
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02009673
9674 union {
9675 struct {
9676 u64 tlpiec;
9677 u64 tncl;
9678 } bb2;
9679 struct {
9680 u64 unused9;
9681 u64 unused10;
9682 } ah2;
9683 } u2;
9684
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009685 u64 rbyte;
9686 u64 rxuca;
9687 u64 rxmca;
9688 u64 rxbca;
9689 u64 rxpok;
9690 u64 tbyte;
9691 u64 txuca;
9692 u64 txmca;
9693 u64 txbca;
9694 u64 txcf;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009695};
9696
9697struct brb_stats {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009698 u64 brb_truncate[8];
9699 u64 brb_discard[8];
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009700};
9701
9702struct port_stats {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009703 struct brb_stats brb;
9704 struct eth_stats eth;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009705};
9706
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009707struct couple_mode_teaming {
9708 u8 port_cmt[MCP_GLOB_PORT_MAX];
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009709#define PORT_CMT_IN_TEAM (1 << 0)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009710
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009711#define PORT_CMT_PORT_ROLE (1 << 1)
9712#define PORT_CMT_PORT_INACTIVE (0 << 1)
9713#define PORT_CMT_PORT_ACTIVE (1 << 1)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009714
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009715#define PORT_CMT_TEAM_MASK (1 << 2)
9716#define PORT_CMT_TEAM0 (0 << 2)
9717#define PORT_CMT_TEAM1 (1 << 2)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009718};
9719
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009720#define LLDP_CHASSIS_ID_STAT_LEN 4
9721#define LLDP_PORT_ID_STAT_LEN 4
9722#define DCBX_MAX_APP_PROTOCOL 32
9723#define MAX_SYSTEM_LLDP_TLV_DATA 32
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009724
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009725enum _lldp_agent {
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009726 LLDP_NEAREST_BRIDGE = 0,
9727 LLDP_NEAREST_NON_TPMR_BRIDGE,
9728 LLDP_NEAREST_CUSTOMER_BRIDGE,
9729 LLDP_MAX_LLDP_AGENTS
9730};
9731
9732struct lldp_config_params_s {
9733 u32 config;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009734#define LLDP_CONFIG_TX_INTERVAL_MASK 0x000000ff
9735#define LLDP_CONFIG_TX_INTERVAL_SHIFT 0
9736#define LLDP_CONFIG_HOLD_MASK 0x00000f00
9737#define LLDP_CONFIG_HOLD_SHIFT 8
9738#define LLDP_CONFIG_MAX_CREDIT_MASK 0x0000f000
9739#define LLDP_CONFIG_MAX_CREDIT_SHIFT 12
9740#define LLDP_CONFIG_ENABLE_RX_MASK 0x40000000
9741#define LLDP_CONFIG_ENABLE_RX_SHIFT 30
9742#define LLDP_CONFIG_ENABLE_TX_MASK 0x80000000
9743#define LLDP_CONFIG_ENABLE_TX_SHIFT 31
9744 u32 local_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
9745 u32 local_port_id[LLDP_PORT_ID_STAT_LEN];
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009746};
9747
9748struct lldp_status_params_s {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009749 u32 prefix_seq_num;
9750 u32 status;
9751 u32 peer_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
9752 u32 peer_port_id[LLDP_PORT_ID_STAT_LEN];
9753 u32 suffix_seq_num;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009754};
9755
9756struct dcbx_ets_feature {
9757 u32 flags;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009758#define DCBX_ETS_ENABLED_MASK 0x00000001
9759#define DCBX_ETS_ENABLED_SHIFT 0
9760#define DCBX_ETS_WILLING_MASK 0x00000002
9761#define DCBX_ETS_WILLING_SHIFT 1
9762#define DCBX_ETS_ERROR_MASK 0x00000004
9763#define DCBX_ETS_ERROR_SHIFT 2
9764#define DCBX_ETS_CBS_MASK 0x00000008
9765#define DCBX_ETS_CBS_SHIFT 3
9766#define DCBX_ETS_MAX_TCS_MASK 0x000000f0
9767#define DCBX_ETS_MAX_TCS_SHIFT 4
Ariel Eliorb5a9ee72017-04-03 12:21:09 +03009768#define DCBX_OOO_TC_MASK 0x00000f00
9769#define DCBX_OOO_TC_SHIFT 8
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009770 u32 pri_tc_tbl[1];
Ariel Eliorb5a9ee72017-04-03 12:21:09 +03009771#define DCBX_TCP_OOO_TC (4)
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009772
Ariel Eliorb5a9ee72017-04-03 12:21:09 +03009773#define NIG_ETS_ISCSI_OOO_CLIENT_OFFSET (DCBX_TCP_OOO_TC + 1)
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009774#define DCBX_CEE_STRICT_PRIORITY 0xf
9775 u32 tc_bw_tbl[2];
9776 u32 tc_tsa_tbl[2];
9777#define DCBX_ETS_TSA_STRICT 0
9778#define DCBX_ETS_TSA_CBS 1
9779#define DCBX_ETS_TSA_ETS 2
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009780};
9781
Ariel Eliorb5a9ee72017-04-03 12:21:09 +03009782#define DCBX_TCP_OOO_TC (4)
9783#define DCBX_TCP_OOO_K2_4PORT_TC (3)
9784
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009785struct dcbx_app_priority_entry {
9786 u32 entry;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009787#define DCBX_APP_PRI_MAP_MASK 0x000000ff
9788#define DCBX_APP_PRI_MAP_SHIFT 0
9789#define DCBX_APP_PRI_0 0x01
9790#define DCBX_APP_PRI_1 0x02
9791#define DCBX_APP_PRI_2 0x04
9792#define DCBX_APP_PRI_3 0x08
9793#define DCBX_APP_PRI_4 0x10
9794#define DCBX_APP_PRI_5 0x20
9795#define DCBX_APP_PRI_6 0x40
9796#define DCBX_APP_PRI_7 0x80
9797#define DCBX_APP_SF_MASK 0x00000300
9798#define DCBX_APP_SF_SHIFT 8
9799#define DCBX_APP_SF_ETHTYPE 0
9800#define DCBX_APP_SF_PORT 1
Sudarsana Reddy Kallurufb9ea8a2016-08-08 21:57:41 -04009801#define DCBX_APP_SF_IEEE_MASK 0x0000f000
9802#define DCBX_APP_SF_IEEE_SHIFT 12
9803#define DCBX_APP_SF_IEEE_RESERVED 0
9804#define DCBX_APP_SF_IEEE_ETHTYPE 1
9805#define DCBX_APP_SF_IEEE_TCP_PORT 2
9806#define DCBX_APP_SF_IEEE_UDP_PORT 3
9807#define DCBX_APP_SF_IEEE_TCP_UDP_PORT 4
9808
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009809#define DCBX_APP_PROTOCOL_ID_MASK 0xffff0000
9810#define DCBX_APP_PROTOCOL_ID_SHIFT 16
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009811};
9812
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009813struct dcbx_app_priority_feature {
9814 u32 flags;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009815#define DCBX_APP_ENABLED_MASK 0x00000001
9816#define DCBX_APP_ENABLED_SHIFT 0
9817#define DCBX_APP_WILLING_MASK 0x00000002
9818#define DCBX_APP_WILLING_SHIFT 1
9819#define DCBX_APP_ERROR_MASK 0x00000004
9820#define DCBX_APP_ERROR_SHIFT 2
9821#define DCBX_APP_MAX_TCS_MASK 0x0000f000
9822#define DCBX_APP_MAX_TCS_SHIFT 12
9823#define DCBX_APP_NUM_ENTRIES_MASK 0x00ff0000
9824#define DCBX_APP_NUM_ENTRIES_SHIFT 16
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009825 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
9826};
9827
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009828struct dcbx_features {
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009829 struct dcbx_ets_feature ets;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009830 u32 pfc;
9831#define DCBX_PFC_PRI_EN_BITMAP_MASK 0x000000ff
9832#define DCBX_PFC_PRI_EN_BITMAP_SHIFT 0
9833#define DCBX_PFC_PRI_EN_BITMAP_PRI_0 0x01
9834#define DCBX_PFC_PRI_EN_BITMAP_PRI_1 0x02
9835#define DCBX_PFC_PRI_EN_BITMAP_PRI_2 0x04
9836#define DCBX_PFC_PRI_EN_BITMAP_PRI_3 0x08
9837#define DCBX_PFC_PRI_EN_BITMAP_PRI_4 0x10
9838#define DCBX_PFC_PRI_EN_BITMAP_PRI_5 0x20
9839#define DCBX_PFC_PRI_EN_BITMAP_PRI_6 0x40
9840#define DCBX_PFC_PRI_EN_BITMAP_PRI_7 0x80
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009841
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009842#define DCBX_PFC_FLAGS_MASK 0x0000ff00
9843#define DCBX_PFC_FLAGS_SHIFT 8
9844#define DCBX_PFC_CAPS_MASK 0x00000f00
9845#define DCBX_PFC_CAPS_SHIFT 8
9846#define DCBX_PFC_MBC_MASK 0x00004000
9847#define DCBX_PFC_MBC_SHIFT 14
9848#define DCBX_PFC_WILLING_MASK 0x00008000
9849#define DCBX_PFC_WILLING_SHIFT 15
9850#define DCBX_PFC_ENABLED_MASK 0x00010000
9851#define DCBX_PFC_ENABLED_SHIFT 16
9852#define DCBX_PFC_ERROR_MASK 0x00020000
9853#define DCBX_PFC_ERROR_SHIFT 17
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009854
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009855 struct dcbx_app_priority_feature app;
9856};
9857
9858struct dcbx_local_params {
9859 u32 config;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009860#define DCBX_CONFIG_VERSION_MASK 0x00000007
9861#define DCBX_CONFIG_VERSION_SHIFT 0
9862#define DCBX_CONFIG_VERSION_DISABLED 0
9863#define DCBX_CONFIG_VERSION_IEEE 1
9864#define DCBX_CONFIG_VERSION_CEE 2
9865#define DCBX_CONFIG_VERSION_STATIC 4
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009866
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009867 u32 flags;
9868 struct dcbx_features features;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009869};
9870
9871struct dcbx_mib {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009872 u32 prefix_seq_num;
9873 u32 flags;
9874 struct dcbx_features features;
9875 u32 suffix_seq_num;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009876};
9877
9878struct lldp_system_tlvs_buffer_s {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009879 u16 valid;
9880 u16 length;
9881 u32 data[MAX_SYSTEM_LLDP_TLV_DATA];
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009882};
9883
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009884struct dcb_dscp_map {
9885 u32 flags;
9886#define DCB_DSCP_ENABLE_MASK 0x1
9887#define DCB_DSCP_ENABLE_SHIFT 0
9888#define DCB_DSCP_ENABLE 1
9889 u32 dscp_pri_map[8];
9890};
9891
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009892struct public_global {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009893 u32 max_path;
9894 u32 max_ports;
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02009895#define MODE_1P 1
9896#define MODE_2P 2
9897#define MODE_3P 3
9898#define MODE_4P 4
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009899 u32 debug_mb_offset;
9900 u32 phymod_dbg_mb_offset;
9901 struct couple_mode_teaming cmt;
9902 s32 internal_temperature;
9903 u32 mfw_ver;
9904 u32 running_bundle_id;
9905 s32 external_temperature;
9906 u32 mdump_reason;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009907};
9908
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009909struct fw_flr_mb {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009910 u32 aggint;
9911 u32 opgen_addr;
9912 u32 accum_ack;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009913};
9914
9915struct public_path {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009916 struct fw_flr_mb flr_mb;
9917 u32 mcp_vf_disabled[VF_MAX_STATIC / 32];
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009918
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009919 u32 process_kill;
9920#define PROCESS_KILL_COUNTER_MASK 0x0000ffff
9921#define PROCESS_KILL_COUNTER_SHIFT 0
9922#define PROCESS_KILL_GLOB_AEU_BIT_MASK 0xffff0000
9923#define PROCESS_KILL_GLOB_AEU_BIT_SHIFT 16
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009924#define GLOBAL_AEU_BIT(aeu_reg_id, aeu_bit) (aeu_reg_id * 32 + aeu_bit)
9925};
9926
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009927struct public_port {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009928 u32 validity_map;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009929
9930 u32 link_status;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009931#define LINK_STATUS_LINK_UP 0x00000001
9932#define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001e
9933#define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (1 << 1)
9934#define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (2 << 1)
9935#define LINK_STATUS_SPEED_AND_DUPLEX_10G (3 << 1)
9936#define LINK_STATUS_SPEED_AND_DUPLEX_20G (4 << 1)
9937#define LINK_STATUS_SPEED_AND_DUPLEX_40G (5 << 1)
9938#define LINK_STATUS_SPEED_AND_DUPLEX_50G (6 << 1)
9939#define LINK_STATUS_SPEED_AND_DUPLEX_100G (7 << 1)
9940#define LINK_STATUS_SPEED_AND_DUPLEX_25G (8 << 1)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009941
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009942#define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009943
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009944#define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
9945#define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009946
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009947#define LINK_STATUS_PFC_ENABLED 0x00000100
9948#define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
9949#define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
9950#define LINK_STATUS_LINK_PARTNER_10G_CAPABLE 0x00000800
9951#define LINK_STATUS_LINK_PARTNER_20G_CAPABLE 0x00001000
9952#define LINK_STATUS_LINK_PARTNER_40G_CAPABLE 0x00002000
9953#define LINK_STATUS_LINK_PARTNER_50G_CAPABLE 0x00004000
9954#define LINK_STATUS_LINK_PARTNER_100G_CAPABLE 0x00008000
9955#define LINK_STATUS_LINK_PARTNER_25G_CAPABLE 0x00010000
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009956
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009957#define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
9958#define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0 << 18)
9959#define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1 << 18)
9960#define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2 << 18)
9961#define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3 << 18)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009962
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009963#define LINK_STATUS_SFP_TX_FAULT 0x00100000
9964#define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00200000
9965#define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00400000
9966#define LINK_STATUS_RX_SIGNAL_PRESENT 0x00800000
9967#define LINK_STATUS_MAC_LOCAL_FAULT 0x01000000
9968#define LINK_STATUS_MAC_REMOTE_FAULT 0x02000000
9969#define LINK_STATUS_UNSUPPORTED_SPD_REQ 0x04000000
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009970
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009971 u32 link_status1;
9972 u32 ext_phy_fw_version;
9973 u32 drv_phy_cfg_addr;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009974
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009975 u32 port_stx;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009976
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009977 u32 stat_nig_timer;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009978
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009979 struct port_mf_cfg port_mf_config;
9980 struct port_stats stats;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009981
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009982 u32 media_type;
9983#define MEDIA_UNSPECIFIED 0x0
9984#define MEDIA_SFPP_10G_FIBER 0x1
9985#define MEDIA_XFP_FIBER 0x2
9986#define MEDIA_DA_TWINAX 0x3
9987#define MEDIA_BASE_T 0x4
9988#define MEDIA_SFP_1G_FIBER 0x5
9989#define MEDIA_MODULE_FIBER 0x6
9990#define MEDIA_KR 0xf0
9991#define MEDIA_NOT_PRESENT 0xff
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009992
9993 u32 lfa_status;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009994 u32 link_change_count;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009995
Yuval Mintz351a4ded2016-06-02 10:23:29 +03009996 struct lldp_config_params_s lldp_config_params[LLDP_MAX_LLDP_AGENTS];
9997 struct lldp_status_params_s lldp_status_params[LLDP_MAX_LLDP_AGENTS];
9998 struct lldp_system_tlvs_buffer_s system_lldp_tlvs_buf;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02009999
10000 /* DCBX related MIB */
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010001 struct dcbx_local_params local_admin_dcbx_mib;
10002 struct dcbx_mib remote_dcbx_mib;
10003 struct dcbx_mib operational_dcbx_mib;
Yuval Mintzfc48b7a2016-02-15 13:22:35 -050010004
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010005 u32 reserved[2];
10006 u32 transceiver_data;
10007#define ETH_TRANSCEIVER_STATE_MASK 0x000000FF
10008#define ETH_TRANSCEIVER_STATE_SHIFT 0x00000000
10009#define ETH_TRANSCEIVER_STATE_UNPLUGGED 0x00000000
10010#define ETH_TRANSCEIVER_STATE_PRESENT 0x00000001
10011#define ETH_TRANSCEIVER_STATE_VALID 0x00000003
10012#define ETH_TRANSCEIVER_STATE_UPDATING 0x00000008
10013
10014 u32 wol_info;
10015 u32 wol_pkt_len;
10016 u32 wol_pkt_details;
10017 struct dcb_dscp_map dcb_dscp_map;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010018};
10019
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010020struct public_func {
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010021 u32 reserved0[2];
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010022
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010023 u32 mtu_size;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010024
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010025 u32 reserved[7];
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010026
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010027 u32 config;
10028#define FUNC_MF_CFG_FUNC_HIDE 0x00000001
10029#define FUNC_MF_CFG_PAUSE_ON_HOST_RING 0x00000002
10030#define FUNC_MF_CFG_PAUSE_ON_HOST_RING_SHIFT 0x00000001
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010031
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010032#define FUNC_MF_CFG_PROTOCOL_MASK 0x000000f0
10033#define FUNC_MF_CFG_PROTOCOL_SHIFT 4
10034#define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000000
Yuval Mintzc5ac9312016-06-03 14:35:34 +030010035#define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000010
Arun Easi1e128c82017-02-15 06:28:22 -080010036#define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000020
Yuval Mintzc5ac9312016-06-03 14:35:34 +030010037#define FUNC_MF_CFG_PROTOCOL_ROCE 0x00000030
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010038#define FUNC_MF_CFG_PROTOCOL_MAX 0x00000030
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010039
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010040#define FUNC_MF_CFG_MIN_BW_MASK 0x0000ff00
10041#define FUNC_MF_CFG_MIN_BW_SHIFT 8
10042#define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
10043#define FUNC_MF_CFG_MAX_BW_MASK 0x00ff0000
10044#define FUNC_MF_CFG_MAX_BW_SHIFT 16
10045#define FUNC_MF_CFG_MAX_BW_DEFAULT 0x00640000
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010046
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010047 u32 status;
10048#define FUNC_STATUS_VLINK_DOWN 0x00000001
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010049
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010050 u32 mac_upper;
10051#define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
10052#define FUNC_MF_CFG_UPPERMAC_SHIFT 0
10053#define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK
10054 u32 mac_lower;
10055#define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010056
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010057 u32 fcoe_wwn_port_name_upper;
10058 u32 fcoe_wwn_port_name_lower;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010059
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010060 u32 fcoe_wwn_node_name_upper;
10061 u32 fcoe_wwn_node_name_lower;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010062
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010063 u32 ovlan_stag;
10064#define FUNC_MF_CFG_OV_STAG_MASK 0x0000ffff
10065#define FUNC_MF_CFG_OV_STAG_SHIFT 0
10066#define FUNC_MF_CFG_OV_STAG_DEFAULT FUNC_MF_CFG_OV_STAG_MASK
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010067
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010068 u32 pf_allocation;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010069
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010070 u32 preserve_data;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010071
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010072 u32 driver_last_activity_ts;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010073
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010074 u32 drv_ack_vf_disabled[VF_MAX_STATIC / 32];
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010075
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010076 u32 drv_id;
10077#define DRV_ID_PDA_COMP_VER_MASK 0x0000ffff
10078#define DRV_ID_PDA_COMP_VER_SHIFT 0
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010079
Tomer Tayar5d24bcf2017-03-28 15:12:52 +030010080#define LOAD_REQ_HSI_VERSION 2
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010081#define DRV_ID_MCP_HSI_VER_MASK 0x00ff0000
10082#define DRV_ID_MCP_HSI_VER_SHIFT 16
Tomer Tayar5d24bcf2017-03-28 15:12:52 +030010083#define DRV_ID_MCP_HSI_VER_CURRENT (LOAD_REQ_HSI_VERSION << \
10084 DRV_ID_MCP_HSI_VER_SHIFT)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010085
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010086#define DRV_ID_DRV_TYPE_MASK 0x7f000000
10087#define DRV_ID_DRV_TYPE_SHIFT 24
10088#define DRV_ID_DRV_TYPE_UNKNOWN (0 << DRV_ID_DRV_TYPE_SHIFT)
10089#define DRV_ID_DRV_TYPE_LINUX (1 << DRV_ID_DRV_TYPE_SHIFT)
Yuval Mintzfc48b7a2016-02-15 13:22:35 -050010090
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010091#define DRV_ID_DRV_INIT_HW_MASK 0x80000000
10092#define DRV_ID_DRV_INIT_HW_SHIFT 31
10093#define DRV_ID_DRV_INIT_HW_FLAG (1 << DRV_ID_DRV_INIT_HW_SHIFT)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010094};
10095
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010096struct mcp_mac {
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010097 u32 mac_upper;
10098 u32 mac_lower;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010099};
10100
10101struct mcp_val64 {
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010102 u32 lo;
10103 u32 hi;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010104};
10105
10106struct mcp_file_att {
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010107 u32 nvm_start_addr;
10108 u32 len;
10109};
10110
10111struct bist_nvm_image_att {
10112 u32 return_code;
10113 u32 image_type;
10114 u32 nvm_start_addr;
10115 u32 len;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010116};
10117
10118#define MCP_DRV_VER_STR_SIZE 16
10119#define MCP_DRV_VER_STR_SIZE_DWORD (MCP_DRV_VER_STR_SIZE / sizeof(u32))
10120#define MCP_DRV_NVM_BUF_LEN 32
10121struct drv_version_stc {
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010122 u32 version;
10123 u8 name[MCP_DRV_VER_STR_SIZE - 4];
10124};
10125
10126struct lan_stats_stc {
10127 u64 ucast_rx_pkts;
10128 u64 ucast_tx_pkts;
10129 u32 fcs_err;
10130 u32 rserved;
10131};
10132
Arun Easi1e128c82017-02-15 06:28:22 -080010133struct fcoe_stats_stc {
10134 u64 rx_pkts;
10135 u64 tx_pkts;
10136 u32 fcs_err;
10137 u32 login_failure;
10138};
10139
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010140struct ocbb_data_stc {
10141 u32 ocbb_host_addr;
10142 u32 ocsd_host_addr;
10143 u32 ocsd_req_update_interval;
10144};
10145
10146#define MAX_NUM_OF_SENSORS 7
10147struct temperature_status_stc {
10148 u32 num_of_sensors;
10149 u32 sensor[MAX_NUM_OF_SENSORS];
10150};
10151
10152/* crash dump configuration header */
10153struct mdump_config_stc {
10154 u32 version;
10155 u32 config;
10156 u32 epoc;
10157 u32 num_of_logs;
10158 u32 valid_logs;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010159};
10160
Tomer Tayar2edbff82016-10-31 07:14:27 +020010161enum resource_id_enum {
10162 RESOURCE_NUM_SB_E = 0,
10163 RESOURCE_NUM_L2_QUEUE_E = 1,
10164 RESOURCE_NUM_VPORT_E = 2,
10165 RESOURCE_NUM_VMQ_E = 3,
10166 RESOURCE_FACTOR_NUM_RSS_PF_E = 4,
10167 RESOURCE_FACTOR_RSS_PER_VF_E = 5,
10168 RESOURCE_NUM_RL_E = 6,
10169 RESOURCE_NUM_PQ_E = 7,
10170 RESOURCE_NUM_VF_E = 8,
10171 RESOURCE_VFC_FILTER_E = 9,
10172 RESOURCE_ILT_E = 10,
10173 RESOURCE_CQS_E = 11,
10174 RESOURCE_GFT_PROFILES_E = 12,
10175 RESOURCE_NUM_TC_E = 13,
10176 RESOURCE_NUM_RSS_ENGINES_E = 14,
10177 RESOURCE_LL2_QUEUE_E = 15,
10178 RESOURCE_RDMA_STATS_QUEUE_E = 16,
Tomer Tayar9c8517c2017-03-28 15:12:55 +030010179 RESOURCE_BDQ_E = 17,
Tomer Tayar2edbff82016-10-31 07:14:27 +020010180 RESOURCE_MAX_NUM,
10181 RESOURCE_NUM_INVALID = 0xFFFFFFFF
10182};
10183
10184/* Resource ID is to be filled by the driver in the MB request
10185 * Size, offset & flags to be filled by the MFW in the MB response
10186 */
10187struct resource_info {
10188 enum resource_id_enum res_id;
10189 u32 size; /* number of allocated resources */
10190 u32 offset; /* Offset of the 1st resource */
10191 u32 vf_size;
10192 u32 vf_offset;
10193 u32 flags;
10194#define RESOURCE_ELEMENT_STRICT (1 << 0)
10195};
10196
Tomer Tayar5d24bcf2017-03-28 15:12:52 +030010197#define DRV_ROLE_NONE 0
10198#define DRV_ROLE_PREBOOT 1
10199#define DRV_ROLE_OS 2
10200#define DRV_ROLE_KDUMP 3
10201
10202struct load_req_stc {
10203 u32 drv_ver_0;
10204 u32 drv_ver_1;
10205 u32 fw_ver;
10206 u32 misc0;
10207#define LOAD_REQ_ROLE_MASK 0x000000FF
10208#define LOAD_REQ_ROLE_SHIFT 0
10209#define LOAD_REQ_LOCK_TO_MASK 0x0000FF00
10210#define LOAD_REQ_LOCK_TO_SHIFT 8
10211#define LOAD_REQ_LOCK_TO_DEFAULT 0
10212#define LOAD_REQ_LOCK_TO_NONE 255
10213#define LOAD_REQ_FORCE_MASK 0x000F0000
10214#define LOAD_REQ_FORCE_SHIFT 16
10215#define LOAD_REQ_FORCE_NONE 0
10216#define LOAD_REQ_FORCE_PF 1
10217#define LOAD_REQ_FORCE_ALL 2
10218#define LOAD_REQ_FLAGS0_MASK 0x00F00000
10219#define LOAD_REQ_FLAGS0_SHIFT 20
10220#define LOAD_REQ_FLAGS0_AVOID_RESET (0x1 << 0)
10221};
10222
10223struct load_rsp_stc {
10224 u32 drv_ver_0;
10225 u32 drv_ver_1;
10226 u32 fw_ver;
10227 u32 misc0;
10228#define LOAD_RSP_ROLE_MASK 0x000000FF
10229#define LOAD_RSP_ROLE_SHIFT 0
10230#define LOAD_RSP_HSI_MASK 0x0000FF00
10231#define LOAD_RSP_HSI_SHIFT 8
10232#define LOAD_RSP_FLAGS0_MASK 0x000F0000
10233#define LOAD_RSP_FLAGS0_SHIFT 16
10234#define LOAD_RSP_FLAGS0_DRV_EXISTS (0x1 << 0)
10235};
10236
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010237union drv_union_data {
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010238 u32 ver_str[MCP_DRV_VER_STR_SIZE_DWORD];
10239 struct mcp_mac wol_mac;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010240
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010241 struct eth_phy_cfg drv_phy_cfg;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010242
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010243 struct mcp_val64 val64;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010244
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010245 u8 raw_data[MCP_DRV_NVM_BUF_LEN];
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010246
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010247 struct mcp_file_att file_att;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010248
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010249 u32 ack_vf_disabled[VF_MAX_STATIC / 32];
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010250
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010251 struct drv_version_stc drv_version;
10252
10253 struct lan_stats_stc lan_stats;
Arun Easi1e128c82017-02-15 06:28:22 -080010254 struct fcoe_stats_stc fcoe_stats;
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010255 struct ocbb_data_stc ocbb_info;
10256 struct temperature_status_stc temp_info;
Tomer Tayar2edbff82016-10-31 07:14:27 +020010257 struct resource_info resource;
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010258 struct bist_nvm_image_att nvm_image_att;
10259 struct mdump_config_stc mdump_config;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010260};
10261
10262struct public_drv_mb {
10263 u32 drv_mb_header;
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010264#define DRV_MSG_CODE_MASK 0xffff0000
10265#define DRV_MSG_CODE_LOAD_REQ 0x10000000
10266#define DRV_MSG_CODE_LOAD_DONE 0x11000000
10267#define DRV_MSG_CODE_INIT_HW 0x12000000
Tomer Tayar5d24bcf2017-03-28 15:12:52 +030010268#define DRV_MSG_CODE_CANCEL_LOAD_REQ 0x13000000
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010269#define DRV_MSG_CODE_UNLOAD_REQ 0x20000000
10270#define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
10271#define DRV_MSG_CODE_INIT_PHY 0x22000000
10272#define DRV_MSG_CODE_LINK_RESET 0x23000000
10273#define DRV_MSG_CODE_SET_DCBX 0x25000000
Sudarsana Kalluru0fefbfb2016-10-31 07:14:21 +020010274#define DRV_MSG_CODE_OV_UPDATE_CURR_CFG 0x26000000
10275#define DRV_MSG_CODE_OV_UPDATE_BUS_NUM 0x27000000
10276#define DRV_MSG_CODE_OV_UPDATE_BOOT_PROGRESS 0x28000000
10277#define DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER 0x29000000
10278#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE 0x31000000
10279#define DRV_MSG_CODE_BW_UPDATE_ACK 0x32000000
10280#define DRV_MSG_CODE_OV_UPDATE_MTU 0x33000000
Tomer Tayar9c8517c2017-03-28 15:12:55 +030010281#define DRV_MSG_GET_RESOURCE_ALLOC_MSG 0x34000000
10282#define DRV_MSG_SET_RESOURCE_VALUE_MSG 0x35000000
Sudarsana Kalluru0fefbfb2016-10-31 07:14:21 +020010283#define DRV_MSG_CODE_OV_UPDATE_WOL 0x38000000
10284#define DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE 0x39000000
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010285
Manish Chopra4b01e512016-04-26 10:56:09 -040010286#define DRV_MSG_CODE_BW_UPDATE_ACK 0x32000000
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010287#define DRV_MSG_CODE_NIG_DRAIN 0x30000000
Mintz, Yuval18a69e32017-03-28 15:12:53 +030010288#define DRV_MSG_CODE_INITIATE_PF_FLR 0x02010000
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010289#define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000
10290#define DRV_MSG_CODE_CFG_VF_MSIX 0xc0010000
Tomer Tayarc965db42016-09-07 16:36:24 +030010291#define DRV_MSG_CODE_NVM_GET_FILE_ATT 0x00030000
10292#define DRV_MSG_CODE_NVM_READ_NVRAM 0x00050000
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010293#define DRV_MSG_CODE_MCP_RESET 0x00090000
10294#define DRV_MSG_CODE_SET_VERSION 0x000f0000
Tomer Tayar41024262016-09-05 14:35:10 +030010295#define DRV_MSG_CODE_MCP_HALT 0x00100000
Sudarsana Kalluru0fefbfb2016-10-31 07:14:21 +020010296#define DRV_MSG_CODE_SET_VMAC 0x00110000
10297#define DRV_MSG_CODE_GET_VMAC 0x00120000
10298#define DRV_MSG_CODE_VMAC_TYPE_SHIFT 4
10299#define DRV_MSG_CODE_VMAC_TYPE_MASK 0x30
10300#define DRV_MSG_CODE_VMAC_TYPE_MAC 1
10301#define DRV_MSG_CODE_VMAC_TYPE_WWNN 2
10302#define DRV_MSG_CODE_VMAC_TYPE_WWPN 3
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010303
Sudarsana Reddy Kalluru6c754242016-08-16 10:51:03 -040010304#define DRV_MSG_CODE_GET_STATS 0x00130000
10305#define DRV_MSG_CODE_STATS_TYPE_LAN 1
10306#define DRV_MSG_CODE_STATS_TYPE_FCOE 2
10307#define DRV_MSG_CODE_STATS_TYPE_ISCSI 3
10308#define DRV_MSG_CODE_STATS_TYPE_RDMA 4
10309
Tomer Tayar41024262016-09-05 14:35:10 +030010310#define DRV_MSG_CODE_MASK_PARITIES 0x001a0000
10311
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010312#define DRV_MSG_CODE_BIST_TEST 0x001e0000
10313#define DRV_MSG_CODE_SET_LED_MODE 0x00200000
Tomer Tayar95691c92017-03-28 15:12:54 +030010314#define DRV_MSG_CODE_RESOURCE_CMD 0x00230000
10315
10316#define RESOURCE_CMD_REQ_RESC_MASK 0x0000001F
10317#define RESOURCE_CMD_REQ_RESC_SHIFT 0
10318#define RESOURCE_CMD_REQ_OPCODE_MASK 0x000000E0
10319#define RESOURCE_CMD_REQ_OPCODE_SHIFT 5
10320#define RESOURCE_OPCODE_REQ 1
10321#define RESOURCE_OPCODE_REQ_WO_AGING 2
10322#define RESOURCE_OPCODE_REQ_W_AGING 3
10323#define RESOURCE_OPCODE_RELEASE 4
10324#define RESOURCE_OPCODE_FORCE_RELEASE 5
10325#define RESOURCE_CMD_REQ_AGE_MASK 0x0000FF00
10326#define RESOURCE_CMD_REQ_AGE_SHIFT 8
10327
10328#define RESOURCE_CMD_RSP_OWNER_MASK 0x000000FF
10329#define RESOURCE_CMD_RSP_OWNER_SHIFT 0
10330#define RESOURCE_CMD_RSP_OPCODE_MASK 0x00000700
10331#define RESOURCE_CMD_RSP_OPCODE_SHIFT 8
10332#define RESOURCE_OPCODE_GNT 1
10333#define RESOURCE_OPCODE_BUSY 2
10334#define RESOURCE_OPCODE_RELEASED 3
10335#define RESOURCE_OPCODE_RELEASED_PREVIOUS 4
10336#define RESOURCE_OPCODE_WRONG_OWNER 5
10337#define RESOURCE_OPCODE_UNKNOWN_CMD 255
10338
10339#define RESOURCE_DUMP 0
10340
Mintz, Yuval6927e822016-10-31 07:14:25 +020010341#define DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL 0x002b0000
Mintz, Yuval14d39642016-10-31 07:14:23 +020010342#define DRV_MSG_CODE_OS_WOL 0x002e0000
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010343
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010344#define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010345
10346 u32 drv_mb_param;
Sudarsana Kalluru0fefbfb2016-10-31 07:14:21 +020010347#define DRV_MB_PARAM_UNLOAD_WOL_UNKNOWN 0x00000000
10348#define DRV_MB_PARAM_UNLOAD_WOL_MCP 0x00000001
10349#define DRV_MB_PARAM_UNLOAD_WOL_DISABLED 0x00000002
10350#define DRV_MB_PARAM_UNLOAD_WOL_ENABLED 0x00000003
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010351#define DRV_MB_PARAM_DCBX_NOTIFY_MASK 0x000000FF
10352#define DRV_MB_PARAM_DCBX_NOTIFY_SHIFT 3
Tomer Tayarc965db42016-09-07 16:36:24 +030010353
10354#define DRV_MB_PARAM_NVM_LEN_SHIFT 24
10355
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010356#define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT 0
10357#define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK 0x000000FF
10358#define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT 8
10359#define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK 0x0000FF00
Sudarsana Reddy Kalluru6ad8c632016-06-08 06:22:10 -040010360#define DRV_MB_PARAM_LLDP_SEND_MASK 0x00000001
10361#define DRV_MB_PARAM_LLDP_SEND_SHIFT 0
10362
Sudarsana Kalluru0fefbfb2016-10-31 07:14:21 +020010363#define DRV_MB_PARAM_OV_CURR_CFG_SHIFT 0
10364#define DRV_MB_PARAM_OV_CURR_CFG_MASK 0x0000000F
10365#define DRV_MB_PARAM_OV_CURR_CFG_NONE 0
10366#define DRV_MB_PARAM_OV_CURR_CFG_OS 1
10367#define DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC 2
10368#define DRV_MB_PARAM_OV_CURR_CFG_OTHER 3
10369
10370#define DRV_MB_PARAM_OV_STORM_FW_VER_SHIFT 0
10371#define DRV_MB_PARAM_OV_STORM_FW_VER_MASK 0xFFFFFFFF
10372#define DRV_MB_PARAM_OV_STORM_FW_VER_MAJOR_MASK 0xFF000000
10373#define DRV_MB_PARAM_OV_STORM_FW_VER_MINOR_MASK 0x00FF0000
10374#define DRV_MB_PARAM_OV_STORM_FW_VER_BUILD_MASK 0x0000FF00
10375#define DRV_MB_PARAM_OV_STORM_FW_VER_DROP_MASK 0x000000FF
10376
10377#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_SHIFT 0
10378#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_MASK 0xF
10379#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_UNKNOWN 0x1
10380#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED 0x2
10381#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_LOADING 0x3
10382#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED 0x4
10383#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE 0x5
10384
10385#define DRV_MB_PARAM_OV_MTU_SIZE_SHIFT 0
10386#define DRV_MB_PARAM_OV_MTU_SIZE_MASK 0xFFFFFFFF
10387
10388#define DRV_MB_PARAM_WOL_MASK (DRV_MB_PARAM_WOL_DEFAULT | \
10389 DRV_MB_PARAM_WOL_DISABLED | \
10390 DRV_MB_PARAM_WOL_ENABLED)
10391#define DRV_MB_PARAM_WOL_DEFAULT DRV_MB_PARAM_UNLOAD_WOL_MCP
10392#define DRV_MB_PARAM_WOL_DISABLED DRV_MB_PARAM_UNLOAD_WOL_DISABLED
10393#define DRV_MB_PARAM_WOL_ENABLED DRV_MB_PARAM_UNLOAD_WOL_ENABLED
10394
10395#define DRV_MB_PARAM_ESWITCH_MODE_MASK (DRV_MB_PARAM_ESWITCH_MODE_NONE | \
10396 DRV_MB_PARAM_ESWITCH_MODE_VEB | \
10397 DRV_MB_PARAM_ESWITCH_MODE_VEPA)
10398#define DRV_MB_PARAM_ESWITCH_MODE_NONE 0x0
10399#define DRV_MB_PARAM_ESWITCH_MODE_VEB 0x1
10400#define DRV_MB_PARAM_ESWITCH_MODE_VEPA 0x2
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010401
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010402#define DRV_MB_PARAM_SET_LED_MODE_OPER 0x0
10403#define DRV_MB_PARAM_SET_LED_MODE_ON 0x1
10404#define DRV_MB_PARAM_SET_LED_MODE_OFF 0x2
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010405
Tomer Tayar2edbff82016-10-31 07:14:27 +020010406 /* Resource Allocation params - Driver version support */
10407#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000
10408#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 16
10409#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF
10410#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0
10411
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010412#define DRV_MB_PARAM_BIST_REGISTER_TEST 1
10413#define DRV_MB_PARAM_BIST_CLOCK_TEST 2
Mintz, Yuval7a4b21b2016-10-31 07:14:22 +020010414#define DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES 3
10415#define DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX 4
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010416
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010417#define DRV_MB_PARAM_BIST_RC_UNKNOWN 0
10418#define DRV_MB_PARAM_BIST_RC_PASSED 1
10419#define DRV_MB_PARAM_BIST_RC_FAILED 2
10420#define DRV_MB_PARAM_BIST_RC_INVALID_PARAMETER 3
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010421
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010422#define DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT 0
10423#define DRV_MB_PARAM_BIST_TEST_INDEX_MASK 0x000000FF
Mintz, Yuval7a4b21b2016-10-31 07:14:22 +020010424#define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT 8
10425#define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_MASK 0x0000FF00
Sudarsana Reddy Kalluru03dc76c2016-04-28 20:20:52 -040010426
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010427 u32 fw_mb_header;
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010428#define FW_MSG_CODE_MASK 0xffff0000
Tomer Tayar95691c92017-03-28 15:12:54 +030010429#define FW_MSG_CODE_UNSUPPORTED 0x00000000
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010430#define FW_MSG_CODE_DRV_LOAD_ENGINE 0x10100000
10431#define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000
10432#define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000
10433#define FW_MSG_CODE_DRV_LOAD_REFUSED_PDA 0x10200000
Tomer Tayar5d24bcf2017-03-28 15:12:52 +030010434#define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1 0x10210000
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010435#define FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG 0x10220000
Tomer Tayar5d24bcf2017-03-28 15:12:52 +030010436#define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI 0x10230000
10437#define FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE 0x10300000
10438#define FW_MSG_CODE_DRV_LOAD_REFUSED_REJECT 0x10310000
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010439#define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000
10440#define FW_MSG_CODE_DRV_UNLOAD_ENGINE 0x20110000
10441#define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20120000
10442#define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20130000
10443#define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
Tomer Tayar2edbff82016-10-31 07:14:27 +020010444#define FW_MSG_CODE_RESOURCE_ALLOC_OK 0x34000000
10445#define FW_MSG_CODE_RESOURCE_ALLOC_UNKNOWN 0x35000000
10446#define FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED 0x36000000
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010447#define FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE 0xb0010000
Tomer Tayarc965db42016-09-07 16:36:24 +030010448
10449#define FW_MSG_CODE_NVM_OK 0x00010000
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010450#define FW_MSG_CODE_OK 0x00160000
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010451
Mintz, Yuval14d39642016-10-31 07:14:23 +020010452#define FW_MSG_CODE_OS_WOL_SUPPORTED 0x00800000
10453#define FW_MSG_CODE_OS_WOL_NOT_SUPPORTED 0x00810000
10454
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010455#define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010456
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010457 u32 fw_mb_param;
Tomer Tayar9c8517c2017-03-28 15:12:55 +030010458#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000
10459#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 16
10460#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF
10461#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010462
Mintz, Yuval6927e822016-10-31 07:14:25 +020010463 /* get pf rdma protocol command responce */
10464#define FW_MB_PARAM_GET_PF_RDMA_NONE 0x0
10465#define FW_MB_PARAM_GET_PF_RDMA_ROCE 0x1
10466#define FW_MB_PARAM_GET_PF_RDMA_IWARP 0x2
10467#define FW_MB_PARAM_GET_PF_RDMA_BOTH 0x3
10468
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010469 u32 drv_pulse_mb;
10470#define DRV_PULSE_SEQ_MASK 0x00007fff
10471#define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
10472#define DRV_PULSE_ALWAYS_ALIVE 0x00008000
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010473
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010474 u32 mcp_pulse_mb;
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010475#define MCP_PULSE_SEQ_MASK 0x00007fff
10476#define MCP_PULSE_ALWAYS_ALIVE 0x00008000
10477#define MCP_EVENT_MASK 0xffff0000
10478#define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010479
10480 union drv_union_data union_data;
10481};
10482
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010483enum MFW_DRV_MSG_TYPE {
10484 MFW_DRV_MSG_LINK_CHANGE,
10485 MFW_DRV_MSG_FLR_FW_ACK_FAILED,
10486 MFW_DRV_MSG_VF_DISABLED,
10487 MFW_DRV_MSG_LLDP_DATA_UPDATED,
10488 MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED,
10489 MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED,
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010490 MFW_DRV_MSG_RESERVED4,
Zvi Nachmani334c03b2016-03-09 09:16:25 +020010491 MFW_DRV_MSG_BW_UPDATE,
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010492 MFW_DRV_MSG_BW_UPDATE5,
Sudarsana Reddy Kalluru6c754242016-08-16 10:51:03 -040010493 MFW_DRV_MSG_GET_LAN_STATS,
10494 MFW_DRV_MSG_GET_FCOE_STATS,
10495 MFW_DRV_MSG_GET_ISCSI_STATS,
10496 MFW_DRV_MSG_GET_RDMA_STATS,
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010497 MFW_DRV_MSG_BW_UPDATE10,
Zvi Nachmani334c03b2016-03-09 09:16:25 +020010498 MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE,
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010499 MFW_DRV_MSG_BW_UPDATE11,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010500 MFW_DRV_MSG_MAX
10501};
10502
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010503#define MFW_DRV_MSG_MAX_DWORDS(msgs) (((msgs - 1) >> 2) + 1)
10504#define MFW_DRV_MSG_DWORD(msg_id) (msg_id >> 2)
10505#define MFW_DRV_MSG_OFFSET(msg_id) ((msg_id & 0x3) << 3)
10506#define MFW_DRV_MSG_MASK(msg_id) (0xff << MFW_DRV_MSG_OFFSET(msg_id))
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010507
10508struct public_mfw_mb {
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010509 u32 sup_msgs;
10510 u32 msg[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
10511 u32 ack[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010512};
10513
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010514enum public_sections {
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010515 PUBLIC_DRV_MB,
10516 PUBLIC_MFW_MB,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010517 PUBLIC_GLOBAL,
10518 PUBLIC_PATH,
10519 PUBLIC_PORT,
10520 PUBLIC_FUNC,
10521 PUBLIC_MAX_SECTIONS
10522};
10523
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010524struct mcp_public_data {
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010525 u32 num_sections;
10526 u32 sections[PUBLIC_MAX_SECTIONS];
10527 struct public_drv_mb drv_mb[MCP_GLOB_FUNC_MAX];
10528 struct public_mfw_mb mfw_mb[MCP_GLOB_FUNC_MAX];
10529 struct public_global global;
10530 struct public_path path[MCP_GLOB_PATH_MAX];
10531 struct public_port port[MCP_GLOB_PORT_MAX];
10532 struct public_func func[MCP_GLOB_FUNC_MAX];
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010533};
10534
10535struct nvm_cfg_mac_address {
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010536 u32 mac_addr_hi;
10537#define NVM_CFG_MAC_ADDRESS_HI_MASK 0x0000FFFF
10538#define NVM_CFG_MAC_ADDRESS_HI_OFFSET 0
10539 u32 mac_addr_lo;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010540};
10541
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010542struct nvm_cfg1_glob {
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010543 u32 generic_cont0;
10544#define NVM_CFG1_GLOB_MF_MODE_MASK 0x00000FF0
10545#define NVM_CFG1_GLOB_MF_MODE_OFFSET 4
10546#define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED 0x0
10547#define NVM_CFG1_GLOB_MF_MODE_DEFAULT 0x1
10548#define NVM_CFG1_GLOB_MF_MODE_SPIO4 0x2
10549#define NVM_CFG1_GLOB_MF_MODE_NPAR1_0 0x3
10550#define NVM_CFG1_GLOB_MF_MODE_NPAR1_5 0x4
10551#define NVM_CFG1_GLOB_MF_MODE_NPAR2_0 0x5
10552#define NVM_CFG1_GLOB_MF_MODE_BD 0x6
10553#define NVM_CFG1_GLOB_MF_MODE_UFP 0x7
10554 u32 engineering_change[3];
10555 u32 manufacturing_id;
10556 u32 serial_number[4];
10557 u32 pcie_cfg;
10558 u32 mgmt_traffic;
10559 u32 core_cfg;
10560#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK 0x000000FF
10561#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET 0
10562#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G 0x0
10563#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G 0x1
10564#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G 0x2
10565#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F 0x3
10566#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E 0x4
10567#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G 0x5
10568#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G 0xB
10569#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G 0xC
10570#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G 0xD
10571#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G 0xE
Mintz, Yuval9c79dda2017-03-14 16:23:54 +020010572#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G 0xF
10573
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010574 u32 e_lane_cfg1;
10575 u32 e_lane_cfg2;
10576 u32 f_lane_cfg1;
10577 u32 f_lane_cfg2;
10578 u32 mps10_preemphasis;
10579 u32 mps10_driver_current;
10580 u32 mps25_preemphasis;
10581 u32 mps25_driver_current;
10582 u32 pci_id;
10583 u32 pci_subsys_id;
10584 u32 bar;
10585 u32 mps10_txfir_main;
10586 u32 mps10_txfir_post;
10587 u32 mps25_txfir_main;
10588 u32 mps25_txfir_post;
10589 u32 manufacture_ver;
10590 u32 manufacture_time;
10591 u32 led_global_settings;
10592 u32 generic_cont1;
10593 u32 mbi_version;
10594 u32 mbi_date;
10595 u32 misc_sig;
10596 u32 device_capabilities;
10597#define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET 0x1
Arun Easi1e128c82017-02-15 06:28:22 -080010598#define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE 0x2
Yuval Mintzc5ac9312016-06-03 14:35:34 +030010599#define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI 0x4
10600#define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE 0x8
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010601 u32 power_dissipated;
10602 u32 power_consumed;
10603 u32 efi_version;
10604 u32 multi_network_modes_capability;
10605 u32 reserved[41];
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010606};
10607
10608struct nvm_cfg1_path {
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010609 u32 reserved[30];
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010610};
10611
10612struct nvm_cfg1_port {
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010613 u32 reserved__m_relocated_to_option_123;
10614 u32 reserved__m_relocated_to_option_124;
10615 u32 generic_cont0;
10616#define NVM_CFG1_PORT_DCBX_MODE_MASK 0x000F0000
10617#define NVM_CFG1_PORT_DCBX_MODE_OFFSET 16
10618#define NVM_CFG1_PORT_DCBX_MODE_DISABLED 0x0
10619#define NVM_CFG1_PORT_DCBX_MODE_IEEE 0x1
10620#define NVM_CFG1_PORT_DCBX_MODE_CEE 0x2
10621#define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC 0x3
10622#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK 0x00F00000
10623#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_OFFSET 20
10624#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET 0x1
10625#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_FCOE 0x2
10626#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ISCSI 0x4
10627 u32 pcie_cfg;
10628 u32 features;
10629 u32 speed_cap_mask;
10630#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF
10631#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
10632#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G 0x1
10633#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G 0x2
10634#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G 0x8
10635#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G 0x10
10636#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G 0x20
10637#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40
10638 u32 link_settings;
10639#define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK 0x0000000F
10640#define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET 0
10641#define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG 0x0
10642#define NVM_CFG1_PORT_DRV_LINK_SPEED_1G 0x1
10643#define NVM_CFG1_PORT_DRV_LINK_SPEED_10G 0x2
10644#define NVM_CFG1_PORT_DRV_LINK_SPEED_25G 0x4
10645#define NVM_CFG1_PORT_DRV_LINK_SPEED_40G 0x5
10646#define NVM_CFG1_PORT_DRV_LINK_SPEED_50G 0x6
10647#define NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G 0x7
10648#define NVM_CFG1_PORT_DRV_LINK_SPEED_SMARTLINQ 0x8
10649#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK 0x00000070
10650#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET 4
10651#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG 0x1
10652#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX 0x2
10653#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX 0x4
10654 u32 phy_cfg;
10655 u32 mgmt_traffic;
10656 u32 ext_phy;
10657 u32 mba_cfg1;
10658 u32 mba_cfg2;
10659 u32 vf_cfg;
10660 struct nvm_cfg_mac_address lldp_mac_address;
10661 u32 led_port_settings;
10662 u32 transceiver_00;
10663 u32 device_ids;
10664 u32 board_cfg;
10665 u32 mnm_10g_cap;
10666 u32 mnm_10g_ctrl;
10667 u32 mnm_10g_misc;
10668 u32 mnm_25g_cap;
10669 u32 mnm_25g_ctrl;
10670 u32 mnm_25g_misc;
10671 u32 mnm_40g_cap;
10672 u32 mnm_40g_ctrl;
10673 u32 mnm_40g_misc;
10674 u32 mnm_50g_cap;
10675 u32 mnm_50g_ctrl;
10676 u32 mnm_50g_misc;
10677 u32 mnm_100g_cap;
10678 u32 mnm_100g_ctrl;
10679 u32 mnm_100g_misc;
10680 u32 reserved[116];
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010681};
10682
10683struct nvm_cfg1_func {
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010684 struct nvm_cfg_mac_address mac_address;
10685 u32 rsrv1;
10686 u32 rsrv2;
10687 u32 device_id;
10688 u32 cmn_cfg;
10689 u32 pci_cfg;
10690 struct nvm_cfg_mac_address fcoe_node_wwn_mac_addr;
10691 struct nvm_cfg_mac_address fcoe_port_wwn_mac_addr;
10692 u32 preboot_generic_cfg;
10693 u32 reserved[8];
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010694};
10695
10696struct nvm_cfg1 {
Yuval Mintz351a4ded2016-06-02 10:23:29 +030010697 struct nvm_cfg1_glob glob;
10698 struct nvm_cfg1_path path[MCP_GLOB_PATH_MAX];
10699 struct nvm_cfg1_port port[MCP_GLOB_PORT_MAX];
10700 struct nvm_cfg1_func func[MCP_GLOB_FUNC_MAX];
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010701};
Tomer Tayarc965db42016-09-07 16:36:24 +030010702
10703enum spad_sections {
10704 SPAD_SECTION_TRACE,
10705 SPAD_SECTION_NVM_CFG,
10706 SPAD_SECTION_PUBLIC,
10707 SPAD_SECTION_PRIVATE,
10708 SPAD_SECTION_MAX
10709};
10710
10711#define MCP_TRACE_SIZE 2048 /* 2kb */
10712
10713/* This section is located at a fixed location in the beginning of the
10714 * scratchpad, to ensure that the MCP trace is not run over during MFW upgrade.
10715 * All the rest of data has a floating location which differs from version to
10716 * version, and is pointed by the mcp_meta_data below.
10717 * Moreover, the spad_layout section is part of the MFW firmware, and is loaded
10718 * with it from nvram in order to clear this portion.
10719 */
10720struct static_init {
10721 u32 num_sections;
10722 offsize_t sections[SPAD_SECTION_MAX];
10723#define SECTION(_sec_) (*((offsize_t *)(STRUCT_OFFSET(sections[_sec_]))))
10724
10725 struct mcp_trace trace;
10726#define MCP_TRACE_P ((struct mcp_trace *)(STRUCT_OFFSET(trace)))
10727 u8 trace_buffer[MCP_TRACE_SIZE];
10728#define MCP_TRACE_BUF ((u8 *)(STRUCT_OFFSET(trace_buffer)))
10729 /* running_mfw has the same definition as in nvm_map.h.
10730 * This bit indicate both the running dir, and the running bundle.
10731 * It is set once when the LIM is loaded.
10732 */
10733 u32 running_mfw;
10734#define RUNNING_MFW (*((u32 *)(STRUCT_OFFSET(running_mfw))))
10735 u32 build_time;
10736#define MFW_BUILD_TIME (*((u32 *)(STRUCT_OFFSET(build_time))))
10737 u32 reset_type;
10738#define RESET_TYPE (*((u32 *)(STRUCT_OFFSET(reset_type))))
10739 u32 mfw_secure_mode;
10740#define MFW_SECURE_MODE (*((u32 *)(STRUCT_OFFSET(mfw_secure_mode))))
10741 u16 pme_status_pf_bitmap;
10742#define PME_STATUS_PF_BITMAP (*((u16 *)(STRUCT_OFFSET(pme_status_pf_bitmap))))
10743 u16 pme_enable_pf_bitmap;
10744#define PME_ENABLE_PF_BITMAP (*((u16 *)(STRUCT_OFFSET(pme_enable_pf_bitmap))))
10745 u32 mim_nvm_addr;
10746 u32 mim_start_addr;
10747 u32 ah_pcie_link_params;
10748#define AH_PCIE_LINK_PARAMS_LINK_SPEED_MASK (0x000000ff)
10749#define AH_PCIE_LINK_PARAMS_LINK_SPEED_SHIFT (0)
10750#define AH_PCIE_LINK_PARAMS_LINK_WIDTH_MASK (0x0000ff00)
10751#define AH_PCIE_LINK_PARAMS_LINK_WIDTH_SHIFT (8)
10752#define AH_PCIE_LINK_PARAMS_ASPM_MODE_MASK (0x00ff0000)
10753#define AH_PCIE_LINK_PARAMS_ASPM_MODE_SHIFT (16)
10754#define AH_PCIE_LINK_PARAMS_ASPM_CAP_MASK (0xff000000)
10755#define AH_PCIE_LINK_PARAMS_ASPM_CAP_SHIFT (24)
10756#define AH_PCIE_LINK_PARAMS (*((u32 *)(STRUCT_OFFSET(ah_pcie_link_params))))
10757
10758 u32 rsrv_persist[5]; /* Persist reserved for MFW upgrades */
10759};
10760
10761enum nvm_image_type {
10762 NVM_TYPE_TIM1 = 0x01,
10763 NVM_TYPE_TIM2 = 0x02,
10764 NVM_TYPE_MIM1 = 0x03,
10765 NVM_TYPE_MIM2 = 0x04,
10766 NVM_TYPE_MBA = 0x05,
10767 NVM_TYPE_MODULES_PN = 0x06,
10768 NVM_TYPE_VPD = 0x07,
10769 NVM_TYPE_MFW_TRACE1 = 0x08,
10770 NVM_TYPE_MFW_TRACE2 = 0x09,
10771 NVM_TYPE_NVM_CFG1 = 0x0a,
10772 NVM_TYPE_L2B = 0x0b,
10773 NVM_TYPE_DIR1 = 0x0c,
10774 NVM_TYPE_EAGLE_FW1 = 0x0d,
10775 NVM_TYPE_FALCON_FW1 = 0x0e,
10776 NVM_TYPE_PCIE_FW1 = 0x0f,
10777 NVM_TYPE_HW_SET = 0x10,
10778 NVM_TYPE_LIM = 0x11,
10779 NVM_TYPE_AVS_FW1 = 0x12,
10780 NVM_TYPE_DIR2 = 0x13,
10781 NVM_TYPE_CCM = 0x14,
10782 NVM_TYPE_EAGLE_FW2 = 0x15,
10783 NVM_TYPE_FALCON_FW2 = 0x16,
10784 NVM_TYPE_PCIE_FW2 = 0x17,
10785 NVM_TYPE_AVS_FW2 = 0x18,
10786 NVM_TYPE_INIT_HW = 0x19,
10787 NVM_TYPE_DEFAULT_CFG = 0x1a,
10788 NVM_TYPE_MDUMP = 0x1b,
10789 NVM_TYPE_META = 0x1c,
10790 NVM_TYPE_ISCSI_CFG = 0x1d,
10791 NVM_TYPE_FCOE_CFG = 0x1f,
10792 NVM_TYPE_ETH_PHY_FW1 = 0x20,
10793 NVM_TYPE_ETH_PHY_FW2 = 0x21,
10794 NVM_TYPE_MAX,
10795};
10796
10797#define DIR_ID_1 (0)
10798
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020010799#endif