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Jiri Pirko56ade8f2015-10-16 14:01:37 +02001/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.h
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#ifndef _MLXSW_SPECTRUM_H
38#define _MLXSW_SPECTRUM_H
39
40#include <linux/types.h>
41#include <linux/netdevice.h>
42#include <linux/bitops.h>
43#include <linux/if_vlan.h>
Ido Schimmel7f71eb42015-12-15 16:03:37 +010044#include <linux/list.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020045#include <net/switchdev.h>
Jiri Pirkoc4745502016-02-26 17:32:26 +010046#include <net/devlink.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020047
Elad Raz3a49b4f2016-01-10 21:06:28 +010048#include "port.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020049#include "core.h"
50
51#define MLXSW_SP_VFID_BASE VLAN_N_VID
Ido Schimmel7f71eb42015-12-15 16:03:37 +010052#define MLXSW_SP_VFID_PORT_MAX 512 /* Non-bridged VLAN interfaces */
Ido Schimmelb555cf42016-04-05 10:20:02 +020053#define MLXSW_SP_VFID_BR_MAX 6144 /* Bridged VLAN interfaces */
Ido Schimmel7f71eb42015-12-15 16:03:37 +010054#define MLXSW_SP_VFID_MAX (MLXSW_SP_VFID_PORT_MAX + MLXSW_SP_VFID_BR_MAX)
55
Jiri Pirko0d65fc12015-12-03 12:12:28 +010056#define MLXSW_SP_LAG_MAX 64
57#define MLXSW_SP_PORT_PER_LAG_MAX 16
Jiri Pirko56ade8f2015-10-16 14:01:37 +020058
Elad Raz53ae6282016-01-10 21:06:26 +010059#define MLXSW_SP_MID_MAX 7000
60
Ido Schimmel18f1e702016-02-26 17:32:31 +010061#define MLXSW_SP_PORTS_PER_CLUSTER_MAX 4
62
63#define MLXSW_SP_PORT_BASE_SPEED 25000 /* Mb/s */
64
Ido Schimmel1a198442016-04-06 17:10:02 +020065#define MLXSW_SP_BYTES_PER_CELL 96
66
67#define MLXSW_SP_BYTES_TO_CELLS(b) DIV_ROUND_UP(b, MLXSW_SP_BYTES_PER_CELL)
68
Jiri Pirko56ade8f2015-10-16 14:01:37 +020069struct mlxsw_sp_port;
70
Jiri Pirko0d65fc12015-12-03 12:12:28 +010071struct mlxsw_sp_upper {
72 struct net_device *dev;
73 unsigned int ref_count;
74};
75
Ido Schimmel7f71eb42015-12-15 16:03:37 +010076struct mlxsw_sp_vfid {
77 struct list_head list;
78 u16 nr_vports;
79 u16 vfid; /* Starting at 0 */
Ido Schimmel26f0e7f2015-12-15 16:03:44 +010080 struct net_device *br_dev;
Ido Schimmel7f71eb42015-12-15 16:03:37 +010081 u16 vid;
82};
83
Elad Raz3a49b4f2016-01-10 21:06:28 +010084struct mlxsw_sp_mid {
85 struct list_head list;
86 unsigned char addr[ETH_ALEN];
87 u16 vid;
88 u16 mid;
89 unsigned int ref_count;
90};
91
Ido Schimmel7f71eb42015-12-15 16:03:37 +010092static inline u16 mlxsw_sp_vfid_to_fid(u16 vfid)
93{
94 return MLXSW_SP_VFID_BASE + vfid;
95}
96
Ido Schimmelaac78a42015-12-15 16:03:42 +010097static inline u16 mlxsw_sp_fid_to_vfid(u16 fid)
98{
99 return fid - MLXSW_SP_VFID_BASE;
100}
101
102static inline bool mlxsw_sp_fid_is_vfid(u16 fid)
103{
104 return fid >= MLXSW_SP_VFID_BASE;
105}
106
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200107struct mlxsw_sp {
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100108 struct {
109 struct list_head list;
110 unsigned long mapped[BITS_TO_LONGS(MLXSW_SP_VFID_PORT_MAX)];
111 } port_vfids;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +0100112 struct {
113 struct list_head list;
114 unsigned long mapped[BITS_TO_LONGS(MLXSW_SP_VFID_BR_MAX)];
115 } br_vfids;
Elad Raz3a49b4f2016-01-10 21:06:28 +0100116 struct {
117 struct list_head list;
118 unsigned long mapped[BITS_TO_LONGS(MLXSW_SP_MID_MAX)];
119 } br_mids;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200120 unsigned long active_fids[BITS_TO_LONGS(VLAN_N_VID)];
121 struct mlxsw_sp_port **ports;
122 struct mlxsw_core *core;
123 const struct mlxsw_bus_info *bus_info;
124 unsigned char base_mac[ETH_ALEN];
125 struct {
126 struct delayed_work dw;
127#define MLXSW_SP_DEFAULT_LEARNING_INTERVAL 100
128 unsigned int interval; /* ms */
129 } fdb_notify;
Ido Schimmel869f63a2016-03-08 12:59:33 -0800130#define MLXSW_SP_MIN_AGEING_TIME 10
131#define MLXSW_SP_MAX_AGEING_TIME 1000000
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200132#define MLXSW_SP_DEFAULT_AGEING_TIME 300
133 u32 ageing_time;
Jiri Pirko0d65fc12015-12-03 12:12:28 +0100134 struct mlxsw_sp_upper master_bridge;
135 struct mlxsw_sp_upper lags[MLXSW_SP_LAG_MAX];
Ido Schimmel558c2d52016-02-26 17:32:29 +0100136 u8 port_to_module[MLXSW_PORT_MAX_PORTS];
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200137};
138
Jiri Pirko0d65fc12015-12-03 12:12:28 +0100139static inline struct mlxsw_sp_upper *
140mlxsw_sp_lag_get(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
141{
142 return &mlxsw_sp->lags[lag_id];
143}
144
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200145struct mlxsw_sp_port_pcpu_stats {
146 u64 rx_packets;
147 u64 rx_bytes;
148 u64 tx_packets;
149 u64 tx_bytes;
150 struct u64_stats_sync syncp;
151 u32 tx_dropped;
152};
153
154struct mlxsw_sp_port {
155 struct net_device *dev;
156 struct mlxsw_sp_port_pcpu_stats __percpu *pcpu_stats;
157 struct mlxsw_sp *mlxsw_sp;
158 u8 local_port;
159 u8 stp_state;
Jiri Pirko0d9b9702015-10-28 10:16:56 +0100160 u8 learning:1,
161 learning_sync:1,
Ido Schimmel02930382015-10-28 10:16:58 +0100162 uc_flood:1,
Jiri Pirko0d65fc12015-12-03 12:12:28 +0100163 bridged:1,
Ido Schimmel18f1e702016-02-26 17:32:31 +0100164 lagged:1,
165 split:1;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200166 u16 pvid;
Jiri Pirko0d65fc12015-12-03 12:12:28 +0100167 u16 lag_id;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100168 struct {
169 struct list_head list;
170 struct mlxsw_sp_vfid *vfid;
171 u16 vid;
172 } vport;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200173 /* 802.1Q bridge VLANs */
Ido Schimmelbd40e9d2015-12-15 16:03:36 +0100174 unsigned long *active_vlans;
Elad Razfc1273a2016-01-06 13:01:11 +0100175 unsigned long *untagged_vlans;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200176 /* VLAN interfaces */
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100177 struct list_head vports_list;
Jiri Pirkoc4745502016-02-26 17:32:26 +0100178 struct devlink_port devlink_port;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200179};
180
Jiri Pirko0d65fc12015-12-03 12:12:28 +0100181static inline struct mlxsw_sp_port *
182mlxsw_sp_port_lagged_get(struct mlxsw_sp *mlxsw_sp, u16 lag_id, u8 port_index)
183{
184 struct mlxsw_sp_port *mlxsw_sp_port;
185 u8 local_port;
186
187 local_port = mlxsw_core_lag_mapping_get(mlxsw_sp->core,
188 lag_id, port_index);
189 mlxsw_sp_port = mlxsw_sp->ports[local_port];
190 return mlxsw_sp_port && mlxsw_sp_port->lagged ? mlxsw_sp_port : NULL;
191}
192
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100193static inline bool
194mlxsw_sp_port_is_vport(const struct mlxsw_sp_port *mlxsw_sp_port)
195{
196 return mlxsw_sp_port->vport.vfid;
197}
198
Ido Schimmel26f0e7f2015-12-15 16:03:44 +0100199static inline struct net_device *
200mlxsw_sp_vport_br_get(const struct mlxsw_sp_port *mlxsw_sp_vport)
201{
202 return mlxsw_sp_vport->vport.vfid->br_dev;
203}
204
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100205static inline u16
206mlxsw_sp_vport_vid_get(const struct mlxsw_sp_port *mlxsw_sp_vport)
207{
208 return mlxsw_sp_vport->vport.vid;
209}
210
211static inline u16
212mlxsw_sp_vport_vfid_get(const struct mlxsw_sp_port *mlxsw_sp_vport)
213{
214 return mlxsw_sp_vport->vport.vfid->vfid;
215}
216
217static inline struct mlxsw_sp_port *
218mlxsw_sp_port_vport_find(const struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
219{
220 struct mlxsw_sp_port *mlxsw_sp_vport;
221
222 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
223 vport.list) {
224 if (mlxsw_sp_vport_vid_get(mlxsw_sp_vport) == vid)
225 return mlxsw_sp_vport;
226 }
227
228 return NULL;
229}
230
Ido Schimmelaac78a42015-12-15 16:03:42 +0100231static inline struct mlxsw_sp_port *
232mlxsw_sp_port_vport_find_by_vfid(const struct mlxsw_sp_port *mlxsw_sp_port,
233 u16 vfid)
234{
235 struct mlxsw_sp_port *mlxsw_sp_vport;
236
237 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
238 vport.list) {
239 if (mlxsw_sp_vport_vfid_get(mlxsw_sp_vport) == vfid)
240 return mlxsw_sp_vport;
241 }
242
243 return NULL;
244}
245
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200246enum mlxsw_sp_flood_table {
247 MLXSW_SP_FLOOD_TABLE_UC,
248 MLXSW_SP_FLOOD_TABLE_BM,
249};
250
251int mlxsw_sp_buffers_init(struct mlxsw_sp *mlxsw_sp);
252int mlxsw_sp_port_buffers_init(struct mlxsw_sp_port *mlxsw_sp_port);
253
254int mlxsw_sp_switchdev_init(struct mlxsw_sp *mlxsw_sp);
255void mlxsw_sp_switchdev_fini(struct mlxsw_sp *mlxsw_sp);
256int mlxsw_sp_port_vlan_init(struct mlxsw_sp_port *mlxsw_sp_port);
257void mlxsw_sp_port_switchdev_init(struct mlxsw_sp_port *mlxsw_sp_port);
258void mlxsw_sp_port_switchdev_fini(struct mlxsw_sp_port *mlxsw_sp_port);
259int mlxsw_sp_port_vid_to_fid_set(struct mlxsw_sp_port *mlxsw_sp_port,
260 enum mlxsw_reg_svfa_mt mt, bool valid, u16 fid,
261 u16 vid);
262int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
263 u16 vid_end, bool is_member, bool untagged);
264int mlxsw_sp_port_add_vid(struct net_device *dev, __be16 __always_unused proto,
265 u16 vid);
266int mlxsw_sp_port_kill_vid(struct net_device *dev,
267 __be16 __always_unused proto, u16 vid);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100268int mlxsw_sp_vport_flood_set(struct mlxsw_sp_port *mlxsw_sp_vport, u16 vfid,
Ido Schimmel19ae6122015-12-15 16:03:39 +0100269 bool set, bool only_uc);
Ido Schimmel4dc236c2016-01-27 15:20:16 +0100270void mlxsw_sp_port_active_vlans_del(struct mlxsw_sp_port *mlxsw_sp_port);
Ido Schimmel28a01d22016-02-18 11:30:02 +0100271int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200272
273#endif