blob: 21760f497b32157fad4bef939f997e361befe4c4 [file] [log] [blame]
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001/* QLogic qed NIC Driver
Mintz, Yuvale8f1cb52017-01-01 13:57:00 +02002 * Copyright (c) 2015-2017 QLogic Corporation
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003 *
Mintz, Yuvale8f1cb52017-01-01 13:57:00 +02004 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020031 */
32
33#ifndef _QED_HSI_H
34#define _QED_HSI_H
35
36#include <linux/types.h>
37#include <linux/io.h>
38#include <linux/bitops.h>
39#include <linux/delay.h>
40#include <linux/kernel.h>
41#include <linux/list.h>
42#include <linux/slab.h>
43#include <linux/qed/common_hsi.h>
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030044#include <linux/qed/storage_common.h>
45#include <linux/qed/tcp_common.h>
Arun Easi1e128c82017-02-15 06:28:22 -080046#include <linux/qed/fcoe_common.h>
Yuval Mintz25c089d2015-10-26 11:02:26 +020047#include <linux/qed/eth_common.h>
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030048#include <linux/qed/iscsi_common.h>
Kalderon, Michal67b40dc2017-07-02 10:29:22 +030049#include <linux/qed/iwarp_common.h>
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030050#include <linux/qed/rdma_common.h>
51#include <linux/qed/roce_common.h>
Arun Easi1e128c82017-02-15 06:28:22 -080052#include <linux/qed/qed_fcoe_if.h>
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020053
54struct qed_hwfn;
55struct qed_ptt;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020056
Tomer Tayara2e76992017-12-27 19:30:05 +020057/* Opcodes for the event ring */
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020058enum common_event_opcode {
59 COMMON_EVENT_PF_START,
60 COMMON_EVENT_PF_STOP,
Yuval Mintz1408cc1f2016-05-11 16:36:14 +030061 COMMON_EVENT_VF_START,
Yuval Mintz0b55e272016-05-11 16:36:15 +030062 COMMON_EVENT_VF_STOP,
Yuval Mintz37bff2b2016-05-11 16:36:13 +030063 COMMON_EVENT_VF_PF_CHANNEL,
Yuval Mintz351a4ded2016-06-02 10:23:29 +030064 COMMON_EVENT_VF_FLR,
65 COMMON_EVENT_PF_UPDATE,
66 COMMON_EVENT_MALICIOUS_VF,
67 COMMON_EVENT_RL_UPDATE,
Yuval Mintzfc48b7a2016-02-15 13:22:35 -050068 COMMON_EVENT_EMPTY,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020069 MAX_COMMON_EVENT_OPCODE
70};
71
72/* Common Ramrod Command IDs */
73enum common_ramrod_cmd_id {
74 COMMON_RAMROD_UNUSED,
Yuval Mintz351a4ded2016-06-02 10:23:29 +030075 COMMON_RAMROD_PF_START,
76 COMMON_RAMROD_PF_STOP,
Yuval Mintz1408cc1f2016-05-11 16:36:14 +030077 COMMON_RAMROD_VF_START,
Yuval Mintz0b55e272016-05-11 16:36:15 +030078 COMMON_RAMROD_VF_STOP,
Manish Chopra464f6642016-04-14 01:38:29 -040079 COMMON_RAMROD_PF_UPDATE,
Yuval Mintz351a4ded2016-06-02 10:23:29 +030080 COMMON_RAMROD_RL_UPDATE,
Yuval Mintzfc48b7a2016-02-15 13:22:35 -050081 COMMON_RAMROD_EMPTY,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020082 MAX_COMMON_RAMROD_CMD_ID
83};
84
Tomer Tayara2e76992017-12-27 19:30:05 +020085/* How ll2 should deal with packet upon errors */
86enum core_error_handle {
87 LL2_DROP_PACKET,
88 LL2_DO_NOTHING,
89 LL2_ASSERT,
90 MAX_CORE_ERROR_HANDLE
91};
92
93/* Opcodes for the event ring */
94enum core_event_opcode {
95 CORE_EVENT_TX_QUEUE_START,
96 CORE_EVENT_TX_QUEUE_STOP,
97 CORE_EVENT_RX_QUEUE_START,
98 CORE_EVENT_RX_QUEUE_STOP,
99 CORE_EVENT_RX_QUEUE_FLUSH,
100 MAX_CORE_EVENT_OPCODE
101};
102
103/* The L4 pseudo checksum mode for Core */
104enum core_l4_pseudo_checksum_mode {
105 CORE_L4_PSEUDO_CSUM_CORRECT_LENGTH,
106 CORE_L4_PSEUDO_CSUM_ZERO_LENGTH,
107 MAX_CORE_L4_PSEUDO_CHECKSUM_MODE
108};
109
110/* Light-L2 RX Producers in Tstorm RAM */
111struct core_ll2_port_stats {
112 struct regpair gsi_invalid_hdr;
113 struct regpair gsi_invalid_pkt_length;
114 struct regpair gsi_unsupported_pkt_typ;
115 struct regpair gsi_crcchksm_error;
116};
117
118/* Ethernet TX Per Queue Stats */
119struct core_ll2_pstorm_per_queue_stat {
120 struct regpair sent_ucast_bytes;
121 struct regpair sent_mcast_bytes;
122 struct regpair sent_bcast_bytes;
123 struct regpair sent_ucast_pkts;
124 struct regpair sent_mcast_pkts;
125 struct regpair sent_bcast_pkts;
126};
127
128/* Light-L2 RX Producers in Tstorm RAM */
129struct core_ll2_rx_prod {
130 __le16 bd_prod;
131 __le16 cqe_prod;
132 __le32 reserved;
133};
134
135struct core_ll2_tstorm_per_queue_stat {
136 struct regpair packet_too_big_discard;
137 struct regpair no_buff_discard;
138};
139
140struct core_ll2_ustorm_per_queue_stat {
141 struct regpair rcv_ucast_bytes;
142 struct regpair rcv_mcast_bytes;
143 struct regpair rcv_bcast_bytes;
144 struct regpair rcv_ucast_pkts;
145 struct regpair rcv_mcast_pkts;
146 struct regpair rcv_bcast_pkts;
147};
148
149/* Core Ramrod Command IDs (light L2) */
150enum core_ramrod_cmd_id {
151 CORE_RAMROD_UNUSED,
152 CORE_RAMROD_RX_QUEUE_START,
153 CORE_RAMROD_TX_QUEUE_START,
154 CORE_RAMROD_RX_QUEUE_STOP,
155 CORE_RAMROD_TX_QUEUE_STOP,
156 CORE_RAMROD_RX_QUEUE_FLUSH,
157 MAX_CORE_RAMROD_CMD_ID
158};
159
160/* Core RX CQE Type for Light L2 */
161enum core_roce_flavor_type {
162 CORE_ROCE,
163 CORE_RROCE,
164 MAX_CORE_ROCE_FLAVOR_TYPE
165};
166
167/* Specifies how ll2 should deal with packets errors: packet_too_big and
168 * no_buff.
169 */
170struct core_rx_action_on_error {
171 u8 error_type;
172#define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_MASK 0x3
173#define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_SHIFT 0
174#define CORE_RX_ACTION_ON_ERROR_NO_BUFF_MASK 0x3
175#define CORE_RX_ACTION_ON_ERROR_NO_BUFF_SHIFT 2
176#define CORE_RX_ACTION_ON_ERROR_RESERVED_MASK 0xF
177#define CORE_RX_ACTION_ON_ERROR_RESERVED_SHIFT 4
178};
179
180/* Core RX BD for Light L2 */
181struct core_rx_bd {
182 struct regpair addr;
183 __le16 reserved[4];
184};
185
186/* Core RX CM offload BD for Light L2 */
187struct core_rx_bd_with_buff_len {
188 struct regpair addr;
189 __le16 buff_length;
190 __le16 reserved[3];
191};
192
193/* Core RX CM offload BD for Light L2 */
194union core_rx_bd_union {
195 struct core_rx_bd rx_bd;
196 struct core_rx_bd_with_buff_len rx_bd_with_len;
197};
198
199/* Opaque Data for Light L2 RX CQE */
200struct core_rx_cqe_opaque_data {
201 __le32 data[2];
202};
203
204/* Core RX CQE Type for Light L2 */
205enum core_rx_cqe_type {
206 CORE_RX_CQE_ILLEGAL_TYPE,
207 CORE_RX_CQE_TYPE_REGULAR,
208 CORE_RX_CQE_TYPE_GSI_OFFLOAD,
209 CORE_RX_CQE_TYPE_SLOW_PATH,
210 MAX_CORE_RX_CQE_TYPE
211};
212
213/* Core RX CQE for Light L2 */
214struct core_rx_fast_path_cqe {
215 u8 type;
216 u8 placement_offset;
217 struct parsing_and_err_flags parse_flags;
218 __le16 packet_length;
219 __le16 vlan;
220 struct core_rx_cqe_opaque_data opaque_data;
221 struct parsing_err_flags err_flags;
222 __le16 reserved0;
223 __le32 reserved1[3];
224};
225
226/* Core Rx CM offload CQE */
227struct core_rx_gsi_offload_cqe {
228 u8 type;
229 u8 data_length_error;
230 struct parsing_and_err_flags parse_flags;
231 __le16 data_length;
232 __le16 vlan;
233 __le32 src_mac_addrhi;
234 __le16 src_mac_addrlo;
235 __le16 qp_id;
236 __le32 gid_dst[4];
237};
238
239/* Core RX CQE for Light L2 */
240struct core_rx_slow_path_cqe {
241 u8 type;
242 u8 ramrod_cmd_id;
243 __le16 echo;
244 struct core_rx_cqe_opaque_data opaque_data;
245 __le32 reserved1[5];
246};
247
248/* Core RX CM offload BD for Light L2 */
249union core_rx_cqe_union {
250 struct core_rx_fast_path_cqe rx_cqe_fp;
251 struct core_rx_gsi_offload_cqe rx_cqe_gsi;
252 struct core_rx_slow_path_cqe rx_cqe_sp;
253};
254
255/* Ramrod data for rx queue start ramrod */
256struct core_rx_start_ramrod_data {
257 struct regpair bd_base;
258 struct regpair cqe_pbl_addr;
259 __le16 mtu;
260 __le16 sb_id;
261 u8 sb_index;
262 u8 complete_cqe_flg;
263 u8 complete_event_flg;
264 u8 drop_ttl0_flg;
265 __le16 num_of_pbl_pages;
266 u8 inner_vlan_removal_en;
267 u8 queue_id;
268 u8 main_func_queue;
269 u8 mf_si_bcast_accept_all;
270 u8 mf_si_mcast_accept_all;
271 struct core_rx_action_on_error action_on_error;
272 u8 gsi_offload_flag;
273 u8 reserved[7];
274};
275
276/* Ramrod data for rx queue stop ramrod */
277struct core_rx_stop_ramrod_data {
278 u8 complete_cqe_flg;
279 u8 complete_event_flg;
280 u8 queue_id;
281 u8 reserved1;
282 __le16 reserved2[2];
283};
284
285/* Flags for Core TX BD */
286struct core_tx_bd_data {
287 __le16 as_bitfield;
288#define CORE_TX_BD_DATA_FORCE_VLAN_MODE_MASK 0x1
289#define CORE_TX_BD_DATA_FORCE_VLAN_MODE_SHIFT 0
290#define CORE_TX_BD_DATA_VLAN_INSERTION_MASK 0x1
291#define CORE_TX_BD_DATA_VLAN_INSERTION_SHIFT 1
292#define CORE_TX_BD_DATA_START_BD_MASK 0x1
293#define CORE_TX_BD_DATA_START_BD_SHIFT 2
294#define CORE_TX_BD_DATA_IP_CSUM_MASK 0x1
295#define CORE_TX_BD_DATA_IP_CSUM_SHIFT 3
296#define CORE_TX_BD_DATA_L4_CSUM_MASK 0x1
297#define CORE_TX_BD_DATA_L4_CSUM_SHIFT 4
298#define CORE_TX_BD_DATA_IPV6_EXT_MASK 0x1
299#define CORE_TX_BD_DATA_IPV6_EXT_SHIFT 5
300#define CORE_TX_BD_DATA_L4_PROTOCOL_MASK 0x1
301#define CORE_TX_BD_DATA_L4_PROTOCOL_SHIFT 6
302#define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_MASK 0x1
303#define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_SHIFT 7
304#define CORE_TX_BD_DATA_NBDS_MASK 0xF
305#define CORE_TX_BD_DATA_NBDS_SHIFT 8
306#define CORE_TX_BD_DATA_ROCE_FLAV_MASK 0x1
307#define CORE_TX_BD_DATA_ROCE_FLAV_SHIFT 12
308#define CORE_TX_BD_DATA_IP_LEN_MASK 0x1
309#define CORE_TX_BD_DATA_IP_LEN_SHIFT 13
310#define CORE_TX_BD_DATA_RESERVED0_MASK 0x3
311#define CORE_TX_BD_DATA_RESERVED0_SHIFT 14
312};
313
314/* Core TX BD for Light L2 */
315struct core_tx_bd {
316 struct regpair addr;
317 __le16 nbytes;
318 __le16 nw_vlan_or_lb_echo;
319 struct core_tx_bd_data bd_data;
320 __le16 bitfield1;
321#define CORE_TX_BD_L4_HDR_OFFSET_W_MASK 0x3FFF
322#define CORE_TX_BD_L4_HDR_OFFSET_W_SHIFT 0
323#define CORE_TX_BD_TX_DST_MASK 0x3
324#define CORE_TX_BD_TX_DST_SHIFT 14
325};
326
327/* Light L2 TX Destination */
328enum core_tx_dest {
329 CORE_TX_DEST_NW,
330 CORE_TX_DEST_LB,
331 CORE_TX_DEST_RESERVED,
332 CORE_TX_DEST_DROP,
333 MAX_CORE_TX_DEST
334};
335
336/* Ramrod data for tx queue start ramrod */
337struct core_tx_start_ramrod_data {
338 struct regpair pbl_base_addr;
339 __le16 mtu;
340 __le16 sb_id;
341 u8 sb_index;
342 u8 stats_en;
343 u8 stats_id;
344 u8 conn_type;
345 __le16 pbl_size;
346 __le16 qm_pq_id;
347 u8 gsi_offload_flag;
348 u8 resrved[3];
349};
350
351/* Ramrod data for tx queue stop ramrod */
352struct core_tx_stop_ramrod_data {
353 __le32 reserved0[2];
354};
355
356/* Enum flag for what type of dcb data to update */
357enum dcb_dscp_update_mode {
358 DONT_UPDATE_DCB_DSCP,
359 UPDATE_DCB,
360 UPDATE_DSCP,
361 UPDATE_DCB_DSCP,
362 MAX_DCB_DSCP_UPDATE_MODE
363};
364
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200365/* The core storm context for the Ystorm */
366struct ystorm_core_conn_st_ctx {
367 __le32 reserved[4];
368};
369
370/* The core storm context for the Pstorm */
371struct pstorm_core_conn_st_ctx {
372 __le32 reserved[4];
373};
374
375/* Core Slowpath Connection storm context of Xstorm */
376struct xstorm_core_conn_st_ctx {
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300377 __le32 spq_base_lo;
378 __le32 spq_base_hi;
379 struct regpair consolid_base_addr;
380 __le16 spq_cons;
381 __le16 consolid_cons;
382 __le32 reserved0[55];
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200383};
384
Tomer Tayar21dd79e2017-12-27 19:30:06 +0200385struct e4_xstorm_core_conn_ag_ctx {
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300386 u8 reserved0;
387 u8 core_state;
388 u8 flags0;
Tomer Tayar21dd79e2017-12-27 19:30:06 +0200389#define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
390#define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
391#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK 0x1
392#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED1_SHIFT 1
393#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK 0x1
394#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED2_SHIFT 2
395#define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
396#define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
397#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK 0x1
398#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED3_SHIFT 4
399#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK 0x1
400#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED4_SHIFT 5
401#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK 0x1
402#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED5_SHIFT 6
403#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK 0x1
404#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED6_SHIFT 7
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200405 u8 flags1;
Tomer Tayar21dd79e2017-12-27 19:30:06 +0200406#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK 0x1
407#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT 0
408#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK 0x1
409#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED8_SHIFT 1
410#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK 0x1
411#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED9_SHIFT 2
412#define E4_XSTORM_CORE_CONN_AG_CTX_BIT11_MASK 0x1
413#define E4_XSTORM_CORE_CONN_AG_CTX_BIT11_SHIFT 3
414#define E4_XSTORM_CORE_CONN_AG_CTX_BIT12_MASK 0x1
415#define E4_XSTORM_CORE_CONN_AG_CTX_BIT12_SHIFT 4
416#define E4_XSTORM_CORE_CONN_AG_CTX_BIT13_MASK 0x1
417#define E4_XSTORM_CORE_CONN_AG_CTX_BIT13_SHIFT 5
418#define E4_XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
419#define E4_XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
420#define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
421#define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200422 u8 flags2;
Tomer Tayar21dd79e2017-12-27 19:30:06 +0200423#define E4_XSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
424#define E4_XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 0
425#define E4_XSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
426#define E4_XSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 2
427#define E4_XSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
428#define E4_XSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 4
429#define E4_XSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
430#define E4_XSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 6
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200431 u8 flags3;
Tomer Tayar21dd79e2017-12-27 19:30:06 +0200432#define E4_XSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
433#define E4_XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 0
434#define E4_XSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
435#define E4_XSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 2
436#define E4_XSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
437#define E4_XSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 4
438#define E4_XSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3
439#define E4_XSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 6
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200440 u8 flags4;
Tomer Tayar21dd79e2017-12-27 19:30:06 +0200441#define E4_XSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3
442#define E4_XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 0
443#define E4_XSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3
444#define E4_XSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 2
445#define E4_XSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3
446#define E4_XSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 4
447#define E4_XSTORM_CORE_CONN_AG_CTX_CF11_MASK 0x3
448#define E4_XSTORM_CORE_CONN_AG_CTX_CF11_SHIFT 6
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200449 u8 flags5;
Tomer Tayar21dd79e2017-12-27 19:30:06 +0200450#define E4_XSTORM_CORE_CONN_AG_CTX_CF12_MASK 0x3
451#define E4_XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT 0
452#define E4_XSTORM_CORE_CONN_AG_CTX_CF13_MASK 0x3
453#define E4_XSTORM_CORE_CONN_AG_CTX_CF13_SHIFT 2
454#define E4_XSTORM_CORE_CONN_AG_CTX_CF14_MASK 0x3
455#define E4_XSTORM_CORE_CONN_AG_CTX_CF14_SHIFT 4
456#define E4_XSTORM_CORE_CONN_AG_CTX_CF15_MASK 0x3
457#define E4_XSTORM_CORE_CONN_AG_CTX_CF15_SHIFT 6
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200458 u8 flags6;
Tomer Tayar21dd79e2017-12-27 19:30:06 +0200459#define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK 0x3
460#define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT 0
461#define E4_XSTORM_CORE_CONN_AG_CTX_CF17_MASK 0x3
462#define E4_XSTORM_CORE_CONN_AG_CTX_CF17_SHIFT 2
463#define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK 0x3
464#define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_SHIFT 4
465#define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
466#define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200467 u8 flags7;
Tomer Tayar21dd79e2017-12-27 19:30:06 +0200468#define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
469#define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
470#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK 0x3
471#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED10_SHIFT 2
472#define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
473#define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_SHIFT 4
474#define E4_XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
475#define E4_XSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 6
476#define E4_XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
477#define E4_XSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 7
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200478 u8 flags8;
Tomer Tayar21dd79e2017-12-27 19:30:06 +0200479#define E4_XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
480#define E4_XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 0
481#define E4_XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
482#define E4_XSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 1
483#define E4_XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
484#define E4_XSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 2
485#define E4_XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
486#define E4_XSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 3
487#define E4_XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
488#define E4_XSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 4
489#define E4_XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1
490#define E4_XSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 5
491#define E4_XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1
492#define E4_XSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 6
493#define E4_XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1
494#define E4_XSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 7
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200495 u8 flags9;
Tomer Tayar21dd79e2017-12-27 19:30:06 +0200496#define E4_XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1
497#define E4_XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 0
498#define E4_XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK 0x1
499#define E4_XSTORM_CORE_CONN_AG_CTX_CF11EN_SHIFT 1
500#define E4_XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK 0x1
501#define E4_XSTORM_CORE_CONN_AG_CTX_CF12EN_SHIFT 2
502#define E4_XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK 0x1
503#define E4_XSTORM_CORE_CONN_AG_CTX_CF13EN_SHIFT 3
504#define E4_XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK 0x1
505#define E4_XSTORM_CORE_CONN_AG_CTX_CF14EN_SHIFT 4
506#define E4_XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK 0x1
507#define E4_XSTORM_CORE_CONN_AG_CTX_CF15EN_SHIFT 5
508#define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK 0x1
509#define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_SHIFT 6
510#define E4_XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK 0x1
511#define E4_XSTORM_CORE_CONN_AG_CTX_CF17EN_SHIFT 7
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200512 u8 flags10;
Tomer Tayar21dd79e2017-12-27 19:30:06 +0200513#define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
514#define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
515#define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
516#define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
517#define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
518#define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
519#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK 0x1
520#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED11_SHIFT 3
521#define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
522#define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
523#define E4_XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK 0x1
524#define E4_XSTORM_CORE_CONN_AG_CTX_CF23EN_SHIFT 5
525#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK 0x1
526#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED12_SHIFT 6
527#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK 0x1
528#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED13_SHIFT 7
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200529 u8 flags11;
Tomer Tayar21dd79e2017-12-27 19:30:06 +0200530#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK 0x1
531#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT 0
532#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK 0x1
533#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED15_SHIFT 1
534#define E4_XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
535#define E4_XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
536#define E4_XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
537#define E4_XSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 3
538#define E4_XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
539#define E4_XSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 4
540#define E4_XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
541#define E4_XSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 5
542#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
543#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
544#define E4_XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK 0x1
545#define E4_XSTORM_CORE_CONN_AG_CTX_RULE9EN_SHIFT 7
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200546 u8 flags12;
Tomer Tayar21dd79e2017-12-27 19:30:06 +0200547#define E4_XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK 0x1
548#define E4_XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT 0
549#define E4_XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK 0x1
550#define E4_XSTORM_CORE_CONN_AG_CTX_RULE11EN_SHIFT 1
551#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
552#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
553#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
554#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
555#define E4_XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK 0x1
556#define E4_XSTORM_CORE_CONN_AG_CTX_RULE14EN_SHIFT 4
557#define E4_XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK 0x1
558#define E4_XSTORM_CORE_CONN_AG_CTX_RULE15EN_SHIFT 5
559#define E4_XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK 0x1
560#define E4_XSTORM_CORE_CONN_AG_CTX_RULE16EN_SHIFT 6
561#define E4_XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK 0x1
562#define E4_XSTORM_CORE_CONN_AG_CTX_RULE17EN_SHIFT 7
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200563 u8 flags13;
Tomer Tayar21dd79e2017-12-27 19:30:06 +0200564#define E4_XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK 0x1
565#define E4_XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT 0
566#define E4_XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK 0x1
567#define E4_XSTORM_CORE_CONN_AG_CTX_RULE19EN_SHIFT 1
568#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
569#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
570#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
571#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
572#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
573#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
574#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
575#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
576#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
577#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
578#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
579#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200580 u8 flags14;
Tomer Tayar21dd79e2017-12-27 19:30:06 +0200581#define E4_XSTORM_CORE_CONN_AG_CTX_BIT16_MASK 0x1
582#define E4_XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT 0
583#define E4_XSTORM_CORE_CONN_AG_CTX_BIT17_MASK 0x1
584#define E4_XSTORM_CORE_CONN_AG_CTX_BIT17_SHIFT 1
585#define E4_XSTORM_CORE_CONN_AG_CTX_BIT18_MASK 0x1
586#define E4_XSTORM_CORE_CONN_AG_CTX_BIT18_SHIFT 2
587#define E4_XSTORM_CORE_CONN_AG_CTX_BIT19_MASK 0x1
588#define E4_XSTORM_CORE_CONN_AG_CTX_BIT19_SHIFT 3
589#define E4_XSTORM_CORE_CONN_AG_CTX_BIT20_MASK 0x1
590#define E4_XSTORM_CORE_CONN_AG_CTX_BIT20_SHIFT 4
591#define E4_XSTORM_CORE_CONN_AG_CTX_BIT21_MASK 0x1
592#define E4_XSTORM_CORE_CONN_AG_CTX_BIT21_SHIFT 5
593#define E4_XSTORM_CORE_CONN_AG_CTX_CF23_MASK 0x3
594#define E4_XSTORM_CORE_CONN_AG_CTX_CF23_SHIFT 6
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300595 u8 byte2;
596 __le16 physical_q0;
597 __le16 consolid_prod;
598 __le16 reserved16;
599 __le16 tx_bd_cons;
600 __le16 tx_bd_or_spq_prod;
601 __le16 word5;
602 __le16 conn_dpi;
603 u8 byte3;
604 u8 byte4;
605 u8 byte5;
606 u8 byte6;
607 __le32 reg0;
608 __le32 reg1;
609 __le32 reg2;
610 __le32 reg3;
611 __le32 reg4;
612 __le32 reg5;
613 __le32 reg6;
614 __le16 word7;
615 __le16 word8;
616 __le16 word9;
617 __le16 word10;
618 __le32 reg7;
619 __le32 reg8;
620 __le32 reg9;
621 u8 byte7;
622 u8 byte8;
623 u8 byte9;
624 u8 byte10;
625 u8 byte11;
626 u8 byte12;
627 u8 byte13;
628 u8 byte14;
629 u8 byte15;
Mintz, Yuval7b6859f2017-05-18 19:41:04 +0300630 u8 e5_reserved;
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300631 __le16 word11;
632 __le32 reg10;
633 __le32 reg11;
634 __le32 reg12;
635 __le32 reg13;
636 __le32 reg14;
637 __le32 reg15;
638 __le32 reg16;
639 __le32 reg17;
640 __le32 reg18;
641 __le32 reg19;
642 __le16 word12;
643 __le16 word13;
644 __le16 word14;
645 __le16 word15;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200646};
647
Tomer Tayar21dd79e2017-12-27 19:30:06 +0200648struct e4_tstorm_core_conn_ag_ctx {
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300649 u8 byte0;
650 u8 byte1;
651 u8 flags0;
Tomer Tayar21dd79e2017-12-27 19:30:06 +0200652#define E4_TSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
653#define E4_TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
654#define E4_TSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
655#define E4_TSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
656#define E4_TSTORM_CORE_CONN_AG_CTX_BIT2_MASK 0x1
657#define E4_TSTORM_CORE_CONN_AG_CTX_BIT2_SHIFT 2
658#define E4_TSTORM_CORE_CONN_AG_CTX_BIT3_MASK 0x1
659#define E4_TSTORM_CORE_CONN_AG_CTX_BIT3_SHIFT 3
660#define E4_TSTORM_CORE_CONN_AG_CTX_BIT4_MASK 0x1
661#define E4_TSTORM_CORE_CONN_AG_CTX_BIT4_SHIFT 4
662#define E4_TSTORM_CORE_CONN_AG_CTX_BIT5_MASK 0x1
663#define E4_TSTORM_CORE_CONN_AG_CTX_BIT5_SHIFT 5
664#define E4_TSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
665#define E4_TSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 6
Yuval Mintzfc48b7a2016-02-15 13:22:35 -0500666 u8 flags1;
Tomer Tayar21dd79e2017-12-27 19:30:06 +0200667#define E4_TSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
668#define E4_TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 0
669#define E4_TSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
670#define E4_TSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 2
671#define E4_TSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
672#define E4_TSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 4
673#define E4_TSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
674#define E4_TSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 6
Yuval Mintzfc48b7a2016-02-15 13:22:35 -0500675 u8 flags2;
Tomer Tayar21dd79e2017-12-27 19:30:06 +0200676#define E4_TSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
677#define E4_TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 0
678#define E4_TSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
679#define E4_TSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 2
680#define E4_TSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3
681#define E4_TSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 4
682#define E4_TSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3
683#define E4_TSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 6
Yuval Mintzfc48b7a2016-02-15 13:22:35 -0500684 u8 flags3;
Tomer Tayar21dd79e2017-12-27 19:30:06 +0200685#define E4_TSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3
686#define E4_TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 0
687#define E4_TSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3
688#define E4_TSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 2
689#define E4_TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
690#define E4_TSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 4
691#define E4_TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
692#define E4_TSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 5
693#define E4_TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
694#define E4_TSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 6
695#define E4_TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
696#define E4_TSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 7
Yuval Mintzfc48b7a2016-02-15 13:22:35 -0500697 u8 flags4;
Tomer Tayar21dd79e2017-12-27 19:30:06 +0200698#define E4_TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
699#define E4_TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 0
700#define E4_TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
701#define E4_TSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 1
702#define E4_TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
703#define E4_TSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 2
704#define E4_TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1
705#define E4_TSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 3
706#define E4_TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1
707#define E4_TSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 4
708#define E4_TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1
709#define E4_TSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 5
710#define E4_TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1
711#define E4_TSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 6
712#define E4_TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
713#define E4_TSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
Yuval Mintzfc48b7a2016-02-15 13:22:35 -0500714 u8 flags5;
Tomer Tayar21dd79e2017-12-27 19:30:06 +0200715#define E4_TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
716#define E4_TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
717#define E4_TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
718#define E4_TSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
719#define E4_TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
720#define E4_TSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
721#define E4_TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
722#define E4_TSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
723#define E4_TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
724#define E4_TSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
725#define E4_TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
726#define E4_TSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
727#define E4_TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
728#define E4_TSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
729#define E4_TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1
730#define E4_TSTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300731 __le32 reg0;
732 __le32 reg1;
733 __le32 reg2;
734 __le32 reg3;
735 __le32 reg4;
736 __le32 reg5;
737 __le32 reg6;
738 __le32 reg7;
739 __le32 reg8;
740 u8 byte2;
741 u8 byte3;
742 __le16 word0;
743 u8 byte4;
744 u8 byte5;
745 __le16 word1;
746 __le16 word2;
747 __le16 word3;
748 __le32 reg9;
749 __le32 reg10;
Yuval Mintzfc48b7a2016-02-15 13:22:35 -0500750};
751
Tomer Tayar21dd79e2017-12-27 19:30:06 +0200752struct e4_ustorm_core_conn_ag_ctx {
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300753 u8 reserved;
754 u8 byte1;
755 u8 flags0;
Tomer Tayar21dd79e2017-12-27 19:30:06 +0200756#define E4_USTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
757#define E4_USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
758#define E4_USTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
759#define E4_USTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
760#define E4_USTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
761#define E4_USTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
762#define E4_USTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
763#define E4_USTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
764#define E4_USTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
765#define E4_USTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
Yuval Mintzfc48b7a2016-02-15 13:22:35 -0500766 u8 flags1;
Tomer Tayar21dd79e2017-12-27 19:30:06 +0200767#define E4_USTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
768#define E4_USTORM_CORE_CONN_AG_CTX_CF3_SHIFT 0
769#define E4_USTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
770#define E4_USTORM_CORE_CONN_AG_CTX_CF4_SHIFT 2
771#define E4_USTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
772#define E4_USTORM_CORE_CONN_AG_CTX_CF5_SHIFT 4
773#define E4_USTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
774#define E4_USTORM_CORE_CONN_AG_CTX_CF6_SHIFT 6
Yuval Mintzfc48b7a2016-02-15 13:22:35 -0500775 u8 flags2;
Tomer Tayar21dd79e2017-12-27 19:30:06 +0200776#define E4_USTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
777#define E4_USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
778#define E4_USTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
779#define E4_USTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
780#define E4_USTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
781#define E4_USTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
782#define E4_USTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
783#define E4_USTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 3
784#define E4_USTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
785#define E4_USTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 4
786#define E4_USTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
787#define E4_USTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 5
788#define E4_USTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
789#define E4_USTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 6
790#define E4_USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
791#define E4_USTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
Yuval Mintzfc48b7a2016-02-15 13:22:35 -0500792 u8 flags3;
Tomer Tayar21dd79e2017-12-27 19:30:06 +0200793#define E4_USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
794#define E4_USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
795#define E4_USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
796#define E4_USTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
797#define E4_USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
798#define E4_USTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
799#define E4_USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
800#define E4_USTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
801#define E4_USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
802#define E4_USTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
803#define E4_USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
804#define E4_USTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
805#define E4_USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
806#define E4_USTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
807#define E4_USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1
808#define E4_USTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300809 u8 byte2;
810 u8 byte3;
811 __le16 word0;
812 __le16 word1;
813 __le32 rx_producers;
814 __le32 reg1;
815 __le32 reg2;
816 __le32 reg3;
817 __le16 word2;
818 __le16 word3;
Yuval Mintzfc48b7a2016-02-15 13:22:35 -0500819};
820
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200821/* The core storm context for the Mstorm */
822struct mstorm_core_conn_st_ctx {
823 __le32 reserved[24];
824};
825
826/* The core storm context for the Ustorm */
827struct ustorm_core_conn_st_ctx {
828 __le32 reserved[4];
829};
830
831/* core connection context */
Tomer Tayar21dd79e2017-12-27 19:30:06 +0200832struct e4_core_conn_context {
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300833 struct ystorm_core_conn_st_ctx ystorm_st_context;
834 struct regpair ystorm_st_padding[2];
835 struct pstorm_core_conn_st_ctx pstorm_st_context;
836 struct regpair pstorm_st_padding[2];
837 struct xstorm_core_conn_st_ctx xstorm_st_context;
Tomer Tayar21dd79e2017-12-27 19:30:06 +0200838 struct e4_xstorm_core_conn_ag_ctx xstorm_ag_context;
839 struct e4_tstorm_core_conn_ag_ctx tstorm_ag_context;
840 struct e4_ustorm_core_conn_ag_ctx ustorm_ag_context;
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300841 struct mstorm_core_conn_st_ctx mstorm_st_context;
842 struct ustorm_core_conn_st_ctx ustorm_st_context;
843 struct regpair ustorm_st_padding[2];
844};
845
846struct eth_mstorm_per_pf_stat {
847 struct regpair gre_discard_pkts;
848 struct regpair vxlan_discard_pkts;
849 struct regpair geneve_discard_pkts;
850 struct regpair lb_discard_pkts;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200851};
852
Manish Chopra9df2ed02015-10-26 11:02:33 +0200853struct eth_mstorm_per_queue_stat {
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300854 struct regpair ttl0_discard;
855 struct regpair packet_too_big_discard;
856 struct regpair no_buff_discard;
857 struct regpair not_active_discard;
858 struct regpair tpa_coalesced_pkts;
859 struct regpair tpa_coalesced_events;
860 struct regpair tpa_aborts_num;
861 struct regpair tpa_coalesced_bytes;
Manish Chopra9df2ed02015-10-26 11:02:33 +0200862};
863
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300864/* Ethernet TX Per PF */
865struct eth_pstorm_per_pf_stat {
866 struct regpair sent_lb_ucast_bytes;
867 struct regpair sent_lb_mcast_bytes;
868 struct regpair sent_lb_bcast_bytes;
869 struct regpair sent_lb_ucast_pkts;
870 struct regpair sent_lb_mcast_pkts;
871 struct regpair sent_lb_bcast_pkts;
872 struct regpair sent_gre_bytes;
873 struct regpair sent_vxlan_bytes;
874 struct regpair sent_geneve_bytes;
875 struct regpair sent_gre_pkts;
876 struct regpair sent_vxlan_pkts;
877 struct regpair sent_geneve_pkts;
878 struct regpair gre_drop_pkts;
879 struct regpair vxlan_drop_pkts;
880 struct regpair geneve_drop_pkts;
881};
882
883/* Ethernet TX Per Queue Stats */
Manish Chopra9df2ed02015-10-26 11:02:33 +0200884struct eth_pstorm_per_queue_stat {
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300885 struct regpair sent_ucast_bytes;
886 struct regpair sent_mcast_bytes;
887 struct regpair sent_bcast_bytes;
888 struct regpair sent_ucast_pkts;
889 struct regpair sent_mcast_pkts;
890 struct regpair sent_bcast_pkts;
891 struct regpair error_drop_pkts;
892};
893
894/* ETH Rx producers data */
895struct eth_rx_rate_limit {
896 __le16 mult;
897 __le16 cnst;
898 u8 add_sub_cnst;
899 u8 reserved0;
900 __le16 reserved1;
901};
902
903struct eth_ustorm_per_pf_stat {
904 struct regpair rcv_lb_ucast_bytes;
905 struct regpair rcv_lb_mcast_bytes;
906 struct regpair rcv_lb_bcast_bytes;
907 struct regpair rcv_lb_ucast_pkts;
908 struct regpair rcv_lb_mcast_pkts;
909 struct regpair rcv_lb_bcast_pkts;
910 struct regpair rcv_gre_bytes;
911 struct regpair rcv_vxlan_bytes;
912 struct regpair rcv_geneve_bytes;
913 struct regpair rcv_gre_pkts;
914 struct regpair rcv_vxlan_pkts;
915 struct regpair rcv_geneve_pkts;
Manish Chopra9df2ed02015-10-26 11:02:33 +0200916};
917
918struct eth_ustorm_per_queue_stat {
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300919 struct regpair rcv_ucast_bytes;
920 struct regpair rcv_mcast_bytes;
921 struct regpair rcv_bcast_bytes;
922 struct regpair rcv_ucast_pkts;
923 struct regpair rcv_mcast_pkts;
924 struct regpair rcv_bcast_pkts;
Manish Chopra9df2ed02015-10-26 11:02:33 +0200925};
926
Tomer Tayara2e76992017-12-27 19:30:05 +0200927/* Event Ring VF-PF Channel data */
928struct vf_pf_channel_eqe_data {
929 struct regpair msg_addr;
930};
931
932/* Event Ring malicious VF data */
933struct malicious_vf_eqe_data {
934 u8 vf_id;
935 u8 err_id;
936 __le16 reserved[3];
937};
938
939/* Event Ring initial cleanup data */
940struct initial_cleanup_eqe_data {
941 u8 vf_id;
942 u8 reserved[7];
943};
944
945/* Event Data Union */
946union event_ring_data {
947 u8 bytes[8];
948 struct vf_pf_channel_eqe_data vf_pf_channel;
949 struct iscsi_eqe_data iscsi_info;
950 union rdma_eqe_data rdma_data;
951 struct malicious_vf_eqe_data malicious_vf;
952 struct initial_cleanup_eqe_data vf_init_cleanup;
953};
954
955/* Event Ring Entry */
956struct event_ring_entry {
957 u8 protocol_id;
958 u8 opcode;
959 __le16 reserved0;
960 __le16 echo;
961 u8 fw_return_code;
962 u8 flags;
963#define EVENT_RING_ENTRY_ASYNC_MASK 0x1
964#define EVENT_RING_ENTRY_ASYNC_SHIFT 0
965#define EVENT_RING_ENTRY_RESERVED1_MASK 0x7F
966#define EVENT_RING_ENTRY_RESERVED1_SHIFT 1
967 union event_ring_data data;
968};
969
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200970/* Event Ring Next Page Address */
971struct event_ring_next_addr {
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300972 struct regpair addr;
973 __le32 reserved[2];
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200974};
975
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300976/* Event Ring Element */
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200977union event_ring_element {
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300978 struct event_ring_entry entry;
979 struct event_ring_next_addr next_addr;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200980};
981
Tomer Tayara2e76992017-12-27 19:30:05 +0200982/* Ports mode */
Mintz, Yuvalbe086e72017-03-11 18:39:18 +0200983enum fw_flow_ctrl_mode {
984 flow_ctrl_pause,
985 flow_ctrl_pfc,
986 MAX_FW_FLOW_CTRL_MODE
987};
988
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300989/* Major and Minor hsi Versions */
990struct hsi_fp_ver_struct {
991 u8 minor_ver_arr[2];
992 u8 major_ver_arr[2];
993};
994
Mintz, Yuval7b6859f2017-05-18 19:41:04 +0300995enum iwarp_ll2_tx_queues {
Tomer Tayara2e76992017-12-27 19:30:05 +0200996 IWARP_LL2_IN_ORDER_TX_QUEUE = 1,
Mintz, Yuval7b6859f2017-05-18 19:41:04 +0300997 IWARP_LL2_ALIGNED_TX_QUEUE,
998 IWARP_LL2_ALIGNED_RIGHT_TRIMMED_TX_QUEUE,
999 IWARP_LL2_ERROR,
1000 MAX_IWARP_LL2_TX_QUEUES
1001};
1002
Tomer Tayara2e76992017-12-27 19:30:05 +02001003/* Malicious VF error ID */
Yuval Mintz05fafbf2016-08-19 09:33:31 +03001004enum malicious_vf_error_id {
1005 MALICIOUS_VF_NO_ERROR,
1006 VF_PF_CHANNEL_NOT_READY,
1007 VF_ZONE_MSG_NOT_VALID,
1008 VF_ZONE_FUNC_NOT_ENABLED,
1009 ETH_PACKET_TOO_SMALL,
1010 ETH_ILLEGAL_VLAN_MODE,
1011 ETH_MTU_VIOLATION,
1012 ETH_ILLEGAL_INBAND_TAGS,
1013 ETH_VLAN_INSERT_AND_INBAND_VLAN,
1014 ETH_ILLEGAL_NBDS,
1015 ETH_FIRST_BD_WO_SOP,
1016 ETH_INSUFFICIENT_BDS,
1017 ETH_ILLEGAL_LSO_HDR_NBDS,
1018 ETH_ILLEGAL_LSO_MSS,
1019 ETH_ZERO_SIZE_BD,
1020 ETH_ILLEGAL_LSO_HDR_LEN,
1021 ETH_INSUFFICIENT_PAYLOAD,
1022 ETH_EDPM_OUT_OF_SYNC,
1023 ETH_TUNN_IPV6_EXT_NBD_ERR,
1024 ETH_CONTROL_PACKET_VIOLATION,
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02001025 ETH_ANTI_SPOOFING_ERR,
Yuval Mintz05fafbf2016-08-19 09:33:31 +03001026 MAX_MALICIOUS_VF_ERROR_ID
1027};
1028
Tomer Tayara2e76992017-12-27 19:30:05 +02001029/* Mstorm non-triggering VF zone */
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001030struct mstorm_non_trigger_vf_zone {
1031 struct eth_mstorm_per_queue_stat eth_queue_stat;
Yuval Mintz05fafbf2016-08-19 09:33:31 +03001032 struct eth_rx_prod_data eth_rx_queue_producers[ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD];
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001033};
1034
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001035/* Mstorm VF zone */
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001036struct mstorm_vf_zone {
1037 struct mstorm_non_trigger_vf_zone non_trigger;
1038};
1039
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001040/* personality per PF */
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001041enum personality_type {
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001042 BAD_PERSONALITY_TYP,
Yuval Mintzc5ac9312016-06-03 14:35:34 +03001043 PERSONALITY_ISCSI,
Arun Easi1e128c82017-02-15 06:28:22 -08001044 PERSONALITY_FCOE,
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001045 PERSONALITY_RDMA_AND_ETH,
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03001046 PERSONALITY_RDMA,
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001047 PERSONALITY_CORE,
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001048 PERSONALITY_ETH,
Tomer Tayara2e76992017-12-27 19:30:05 +02001049 PERSONALITY_RESERVED,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001050 MAX_PERSONALITY_TYPE
1051};
1052
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001053/* tunnel configuration */
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001054struct pf_start_tunnel_config {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001055 u8 set_vxlan_udp_port_flg;
1056 u8 set_geneve_udp_port_flg;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001057 u8 tunnel_clss_vxlan;
1058 u8 tunnel_clss_l2geneve;
1059 u8 tunnel_clss_ipgeneve;
1060 u8 tunnel_clss_l2gre;
1061 u8 tunnel_clss_ipgre;
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03001062 u8 reserved;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001063 __le16 vxlan_udp_port;
1064 __le16 geneve_udp_port;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001065};
1066
1067/* Ramrod data for PF start ramrod */
1068struct pf_start_ramrod_data {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001069 struct regpair event_ring_pbl_addr;
1070 struct regpair consolid_q_pbl_addr;
1071 struct pf_start_tunnel_config tunnel_config;
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03001072 __le32 reserved;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001073 __le16 event_ring_sb_id;
1074 u8 base_vf_id;
1075 u8 num_vfs;
1076 u8 event_ring_num_pages;
1077 u8 event_ring_sb_index;
1078 u8 path_id;
1079 u8 warning_as_error;
1080 u8 dont_log_ramrods;
1081 u8 personality;
1082 __le16 log_type_mask;
1083 u8 mf_mode;
1084 u8 integ_phase;
1085 u8 allow_npar_tx_switching;
1086 u8 inner_to_outer_pri_map[8];
1087 u8 pri_map_valid;
1088 __le32 outer_tag;
1089 struct hsi_fp_ver_struct hsi_fp_ver;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001090};
1091
Tomer Tayara2e76992017-12-27 19:30:05 +02001092/* Data for port update ramrod */
Sudarsana Reddy Kalluru39651ab2016-05-17 06:44:26 -04001093struct protocol_dcb_data {
1094 u8 dcb_enable_flag;
Yuval Mintz05fafbf2016-08-19 09:33:31 +03001095 u8 reserved_a;
Sudarsana Reddy Kalluru39651ab2016-05-17 06:44:26 -04001096 u8 dcb_priority;
1097 u8 dcb_tc;
Yuval Mintz05fafbf2016-08-19 09:33:31 +03001098 u8 reserved_b;
1099 u8 reserved0;
Sudarsana Reddy Kalluru39651ab2016-05-17 06:44:26 -04001100};
1101
Tomer Tayara2e76992017-12-27 19:30:05 +02001102/* Update tunnel configuration */
Manish Chopra464f6642016-04-14 01:38:29 -04001103struct pf_update_tunnel_config {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001104 u8 update_rx_pf_clss;
Yuval Mintz05fafbf2016-08-19 09:33:31 +03001105 u8 update_rx_def_ucast_clss;
1106 u8 update_rx_def_non_ucast_clss;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001107 u8 set_vxlan_udp_port_flg;
1108 u8 set_geneve_udp_port_flg;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001109 u8 tunnel_clss_vxlan;
1110 u8 tunnel_clss_l2geneve;
1111 u8 tunnel_clss_ipgeneve;
1112 u8 tunnel_clss_l2gre;
1113 u8 tunnel_clss_ipgre;
1114 __le16 vxlan_udp_port;
1115 __le16 geneve_udp_port;
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03001116 __le16 reserved;
Manish Chopra464f6642016-04-14 01:38:29 -04001117};
1118
Tomer Tayara2e76992017-12-27 19:30:05 +02001119/* Data for port update ramrod */
Manish Chopra464f6642016-04-14 01:38:29 -04001120struct pf_update_ramrod_data {
Sudarsana Reddy Kalluru39651ab2016-05-17 06:44:26 -04001121 u8 pf_id;
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03001122 u8 update_eth_dcb_data_mode;
1123 u8 update_fcoe_dcb_data_mode;
1124 u8 update_iscsi_dcb_data_mode;
1125 u8 update_roce_dcb_data_mode;
1126 u8 update_rroce_dcb_data_mode;
1127 u8 update_iwarp_dcb_data_mode;
Sudarsana Reddy Kalluru39651ab2016-05-17 06:44:26 -04001128 u8 update_mf_vlan_flag;
Sudarsana Reddy Kalluru39651ab2016-05-17 06:44:26 -04001129 struct protocol_dcb_data eth_dcb_data;
1130 struct protocol_dcb_data fcoe_dcb_data;
1131 struct protocol_dcb_data iscsi_dcb_data;
1132 struct protocol_dcb_data roce_dcb_data;
Yuval Mintz05fafbf2016-08-19 09:33:31 +03001133 struct protocol_dcb_data rroce_dcb_data;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001134 struct protocol_dcb_data iwarp_dcb_data;
1135 __le16 mf_vlan;
Yuval Mintz05fafbf2016-08-19 09:33:31 +03001136 __le16 reserved;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001137 struct pf_update_tunnel_config tunnel_config;
1138};
1139
1140/* Ports mode */
1141enum ports_mode {
1142 ENGX2_PORTX1,
1143 ENGX2_PORTX2,
1144 ENGX1_PORTX1,
1145 ENGX1_PORTX2,
1146 ENGX1_PORTX4,
1147 MAX_PORTS_MODE
1148};
1149
1150/* use to index in hsi_fp_[major|minor]_ver_arr per protocol */
1151enum protocol_version_array_key {
1152 ETH_VER_KEY = 0,
1153 ROCE_VER_KEY,
1154 MAX_PROTOCOL_VERSION_ARRAY_KEY
1155};
1156
Tomer Tayara2e76992017-12-27 19:30:05 +02001157/* RDMA TX Stats */
Yuval Mintz05fafbf2016-08-19 09:33:31 +03001158struct rdma_sent_stats {
1159 struct regpair sent_bytes;
1160 struct regpair sent_pkts;
1161};
1162
Tomer Tayara2e76992017-12-27 19:30:05 +02001163/* Pstorm non-triggering VF zone */
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001164struct pstorm_non_trigger_vf_zone {
1165 struct eth_pstorm_per_queue_stat eth_queue_stat;
Yuval Mintz05fafbf2016-08-19 09:33:31 +03001166 struct rdma_sent_stats rdma_stats;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001167};
1168
1169/* Pstorm VF zone */
1170struct pstorm_vf_zone {
1171 struct pstorm_non_trigger_vf_zone non_trigger;
1172 struct regpair reserved[7];
1173};
1174
1175/* Ramrod Header of SPQE */
1176struct ramrod_header {
1177 __le32 cid;
1178 u8 cmd_id;
1179 u8 protocol_id;
1180 __le16 echo;
1181};
1182
Tomer Tayara2e76992017-12-27 19:30:05 +02001183/* RDMA RX Stats */
Yuval Mintz05fafbf2016-08-19 09:33:31 +03001184struct rdma_rcv_stats {
1185 struct regpair rcv_bytes;
1186 struct regpair rcv_pkts;
1187};
1188
Tomer Tayara2e76992017-12-27 19:30:05 +02001189/* Slowpath Element (SPQE) */
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001190struct slow_path_element {
1191 struct ramrod_header hdr;
1192 struct regpair data_ptr;
1193};
1194
1195/* Tstorm non-triggering VF zone */
1196struct tstorm_non_trigger_vf_zone {
Yuval Mintz05fafbf2016-08-19 09:33:31 +03001197 struct rdma_rcv_stats rdma_stats;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001198};
1199
1200struct tstorm_per_port_stat {
1201 struct regpair trunc_error_discard;
1202 struct regpair mac_error_discard;
1203 struct regpair mftag_filter_discard;
1204 struct regpair eth_mac_filter_discard;
Yuval Mintz05fafbf2016-08-19 09:33:31 +03001205 struct regpair ll2_mac_filter_discard;
1206 struct regpair ll2_conn_disabled_discard;
1207 struct regpair iscsi_irregular_pkt;
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02001208 struct regpair fcoe_irregular_pkt;
Yuval Mintz05fafbf2016-08-19 09:33:31 +03001209 struct regpair roce_irregular_pkt;
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03001210 struct regpair iwarp_irregular_pkt;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001211 struct regpair eth_irregular_pkt;
Yuval Mintz05fafbf2016-08-19 09:33:31 +03001212 struct regpair reserved1;
1213 struct regpair preroce_irregular_pkt;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001214 struct regpair eth_gre_tunn_filter_discard;
1215 struct regpair eth_vxlan_tunn_filter_discard;
1216 struct regpair eth_geneve_tunn_filter_discard;
1217};
1218
1219/* Tstorm VF zone */
1220struct tstorm_vf_zone {
1221 struct tstorm_non_trigger_vf_zone non_trigger;
Manish Chopra464f6642016-04-14 01:38:29 -04001222};
1223
1224/* Tunnel classification scheme */
1225enum tunnel_clss {
1226 TUNNEL_CLSS_MAC_VLAN = 0,
1227 TUNNEL_CLSS_MAC_VNI,
1228 TUNNEL_CLSS_INNER_MAC_VLAN,
1229 TUNNEL_CLSS_INNER_MAC_VNI,
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001230 TUNNEL_CLSS_MAC_VLAN_DUAL_STAGE,
Manish Chopra464f6642016-04-14 01:38:29 -04001231 MAX_TUNNEL_CLSS
1232};
1233
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001234/* Ustorm non-triggering VF zone */
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001235struct ustorm_non_trigger_vf_zone {
1236 struct eth_ustorm_per_queue_stat eth_queue_stat;
1237 struct regpair vf_pf_msg_addr;
1238};
1239
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001240/* Ustorm triggering VF zone */
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001241struct ustorm_trigger_vf_zone {
1242 u8 vf_pf_msg_valid;
1243 u8 reserved[7];
1244};
1245
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001246/* Ustorm VF zone */
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001247struct ustorm_vf_zone {
1248 struct ustorm_non_trigger_vf_zone non_trigger;
1249 struct ustorm_trigger_vf_zone trigger;
1250};
1251
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001252/* VF-PF channel data */
1253struct vf_pf_channel_data {
1254 __le32 ready;
1255 u8 valid;
1256 u8 reserved0;
1257 __le16 reserved1;
1258};
1259
1260/* Ramrod data for VF start ramrod */
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001261struct vf_start_ramrod_data {
1262 u8 vf_id;
1263 u8 enable_flr_ack;
1264 __le16 opaque_fid;
1265 u8 personality;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001266 u8 reserved[7];
1267 struct hsi_fp_ver_struct hsi_fp_ver;
1268
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001269};
1270
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001271/* Ramrod data for VF start ramrod */
Yuval Mintz0b55e272016-05-11 16:36:15 +03001272struct vf_stop_ramrod_data {
1273 u8 vf_id;
1274 u8 reserved0;
1275 __le16 reserved1;
1276 __le32 reserved2;
1277};
1278
Tomer Tayara2e76992017-12-27 19:30:05 +02001279/* VF zone size mode */
Yuval Mintz05fafbf2016-08-19 09:33:31 +03001280enum vf_zone_size_mode {
1281 VF_ZONE_SIZE_MODE_DEFAULT,
1282 VF_ZONE_SIZE_MODE_DOUBLE,
1283 VF_ZONE_SIZE_MODE_QUAD,
1284 MAX_VF_ZONE_SIZE_MODE
1285};
1286
Tomer Tayara2e76992017-12-27 19:30:05 +02001287/* Attentions status block */
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001288struct atten_status_block {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001289 __le32 atten_bits;
1290 __le32 atten_ack;
1291 __le16 reserved0;
1292 __le16 sb_index;
1293 __le32 reserved1;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001294};
1295
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001296/* DMAE command */
1297struct dmae_cmd {
1298 __le32 opcode;
1299#define DMAE_CMD_SRC_MASK 0x1
1300#define DMAE_CMD_SRC_SHIFT 0
1301#define DMAE_CMD_DST_MASK 0x3
1302#define DMAE_CMD_DST_SHIFT 1
1303#define DMAE_CMD_C_DST_MASK 0x1
1304#define DMAE_CMD_C_DST_SHIFT 3
1305#define DMAE_CMD_CRC_RESET_MASK 0x1
1306#define DMAE_CMD_CRC_RESET_SHIFT 4
1307#define DMAE_CMD_SRC_ADDR_RESET_MASK 0x1
1308#define DMAE_CMD_SRC_ADDR_RESET_SHIFT 5
1309#define DMAE_CMD_DST_ADDR_RESET_MASK 0x1
1310#define DMAE_CMD_DST_ADDR_RESET_SHIFT 6
1311#define DMAE_CMD_COMP_FUNC_MASK 0x1
1312#define DMAE_CMD_COMP_FUNC_SHIFT 7
1313#define DMAE_CMD_COMP_WORD_EN_MASK 0x1
1314#define DMAE_CMD_COMP_WORD_EN_SHIFT 8
1315#define DMAE_CMD_COMP_CRC_EN_MASK 0x1
1316#define DMAE_CMD_COMP_CRC_EN_SHIFT 9
1317#define DMAE_CMD_COMP_CRC_OFFSET_MASK 0x7
1318#define DMAE_CMD_COMP_CRC_OFFSET_SHIFT 10
1319#define DMAE_CMD_RESERVED1_MASK 0x1
1320#define DMAE_CMD_RESERVED1_SHIFT 13
1321#define DMAE_CMD_ENDIANITY_MODE_MASK 0x3
1322#define DMAE_CMD_ENDIANITY_MODE_SHIFT 14
1323#define DMAE_CMD_ERR_HANDLING_MASK 0x3
1324#define DMAE_CMD_ERR_HANDLING_SHIFT 16
1325#define DMAE_CMD_PORT_ID_MASK 0x3
1326#define DMAE_CMD_PORT_ID_SHIFT 18
1327#define DMAE_CMD_SRC_PF_ID_MASK 0xF
1328#define DMAE_CMD_SRC_PF_ID_SHIFT 20
1329#define DMAE_CMD_DST_PF_ID_MASK 0xF
1330#define DMAE_CMD_DST_PF_ID_SHIFT 24
1331#define DMAE_CMD_SRC_VF_ID_VALID_MASK 0x1
1332#define DMAE_CMD_SRC_VF_ID_VALID_SHIFT 28
1333#define DMAE_CMD_DST_VF_ID_VALID_MASK 0x1
1334#define DMAE_CMD_DST_VF_ID_VALID_SHIFT 29
1335#define DMAE_CMD_RESERVED2_MASK 0x3
1336#define DMAE_CMD_RESERVED2_SHIFT 30
1337 __le32 src_addr_lo;
1338 __le32 src_addr_hi;
1339 __le32 dst_addr_lo;
1340 __le32 dst_addr_hi;
1341 __le16 length_dw;
1342 __le16 opcode_b;
1343#define DMAE_CMD_SRC_VF_ID_MASK 0xFF
1344#define DMAE_CMD_SRC_VF_ID_SHIFT 0
1345#define DMAE_CMD_DST_VF_ID_MASK 0xFF
1346#define DMAE_CMD_DST_VF_ID_SHIFT 8
1347 __le32 comp_addr_lo;
1348 __le32 comp_addr_hi;
1349 __le32 comp_val;
1350 __le32 crc32;
1351 __le32 crc_32_c;
1352 __le16 crc16;
1353 __le16 crc16_c;
1354 __le16 crc10;
1355 __le16 reserved;
1356 __le16 xsum16;
1357 __le16 xsum8;
1358};
1359
1360enum dmae_cmd_comp_crc_en_enum {
1361 dmae_cmd_comp_crc_disabled,
1362 dmae_cmd_comp_crc_enabled,
1363 MAX_DMAE_CMD_COMP_CRC_EN_ENUM
1364};
1365
1366enum dmae_cmd_comp_func_enum {
1367 dmae_cmd_comp_func_to_src,
1368 dmae_cmd_comp_func_to_dst,
1369 MAX_DMAE_CMD_COMP_FUNC_ENUM
1370};
1371
1372enum dmae_cmd_comp_word_en_enum {
1373 dmae_cmd_comp_word_disabled,
1374 dmae_cmd_comp_word_enabled,
1375 MAX_DMAE_CMD_COMP_WORD_EN_ENUM
1376};
1377
1378enum dmae_cmd_c_dst_enum {
1379 dmae_cmd_c_dst_pcie,
1380 dmae_cmd_c_dst_grc,
1381 MAX_DMAE_CMD_C_DST_ENUM
1382};
1383
1384enum dmae_cmd_dst_enum {
1385 dmae_cmd_dst_none_0,
1386 dmae_cmd_dst_pcie,
1387 dmae_cmd_dst_grc,
1388 dmae_cmd_dst_none_3,
1389 MAX_DMAE_CMD_DST_ENUM
1390};
1391
1392enum dmae_cmd_error_handling_enum {
1393 dmae_cmd_error_handling_send_regular_comp,
1394 dmae_cmd_error_handling_send_comp_with_err,
1395 dmae_cmd_error_handling_dont_send_comp,
1396 MAX_DMAE_CMD_ERROR_HANDLING_ENUM
1397};
1398
1399enum dmae_cmd_src_enum {
1400 dmae_cmd_src_pcie,
1401 dmae_cmd_src_grc,
1402 MAX_DMAE_CMD_SRC_ENUM
1403};
1404
Tomer Tayar21dd79e2017-12-27 19:30:06 +02001405struct e4_mstorm_core_conn_ag_ctx {
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03001406 u8 byte0;
1407 u8 byte1;
1408 u8 flags0;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02001409#define E4_MSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
1410#define E4_MSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
1411#define E4_MSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
1412#define E4_MSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
1413#define E4_MSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
1414#define E4_MSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
1415#define E4_MSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
1416#define E4_MSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
1417#define E4_MSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
1418#define E4_MSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03001419 u8 flags1;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02001420#define E4_MSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
1421#define E4_MSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
1422#define E4_MSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
1423#define E4_MSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
1424#define E4_MSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
1425#define E4_MSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
1426#define E4_MSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
1427#define E4_MSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3
1428#define E4_MSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
1429#define E4_MSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4
1430#define E4_MSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
1431#define E4_MSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5
1432#define E4_MSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
1433#define E4_MSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6
1434#define E4_MSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
1435#define E4_MSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03001436 __le16 word0;
1437 __le16 word1;
1438 __le32 reg0;
1439 __le32 reg1;
1440};
1441
Tomer Tayar21dd79e2017-12-27 19:30:06 +02001442struct e4_ystorm_core_conn_ag_ctx {
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03001443 u8 byte0;
1444 u8 byte1;
1445 u8 flags0;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02001446#define E4_YSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
1447#define E4_YSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
1448#define E4_YSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
1449#define E4_YSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
1450#define E4_YSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
1451#define E4_YSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
1452#define E4_YSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
1453#define E4_YSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
1454#define E4_YSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
1455#define E4_YSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03001456 u8 flags1;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02001457#define E4_YSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
1458#define E4_YSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
1459#define E4_YSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
1460#define E4_YSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
1461#define E4_YSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
1462#define E4_YSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
1463#define E4_YSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
1464#define E4_YSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3
1465#define E4_YSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
1466#define E4_YSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4
1467#define E4_YSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
1468#define E4_YSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5
1469#define E4_YSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
1470#define E4_YSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6
1471#define E4_YSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
1472#define E4_YSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03001473 u8 byte2;
1474 u8 byte3;
1475 __le16 word0;
1476 __le32 reg0;
1477 __le32 reg1;
1478 __le16 word1;
1479 __le16 word2;
1480 __le16 word3;
1481 __le16 word4;
1482 __le32 reg2;
1483 __le32 reg3;
1484};
1485
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001486/* IGU cleanup command */
1487struct igu_cleanup {
1488 __le32 sb_id_and_flags;
1489#define IGU_CLEANUP_RESERVED0_MASK 0x7FFFFFF
1490#define IGU_CLEANUP_RESERVED0_SHIFT 0
1491#define IGU_CLEANUP_CLEANUP_SET_MASK 0x1
1492#define IGU_CLEANUP_CLEANUP_SET_SHIFT 27
1493#define IGU_CLEANUP_CLEANUP_TYPE_MASK 0x7
1494#define IGU_CLEANUP_CLEANUP_TYPE_SHIFT 28
1495#define IGU_CLEANUP_COMMAND_TYPE_MASK 0x1
1496#define IGU_CLEANUP_COMMAND_TYPE_SHIFT 31
1497 __le32 reserved1;
1498};
1499
1500/* IGU firmware driver command */
1501union igu_command {
1502 struct igu_prod_cons_update prod_cons_update;
1503 struct igu_cleanup cleanup;
1504};
1505
1506/* IGU firmware driver command */
1507struct igu_command_reg_ctrl {
1508 __le16 opaque_fid;
1509 __le16 igu_command_reg_ctrl_fields;
1510#define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_MASK 0xFFF
1511#define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_SHIFT 0
1512#define IGU_COMMAND_REG_CTRL_RESERVED_MASK 0x7
1513#define IGU_COMMAND_REG_CTRL_RESERVED_SHIFT 12
1514#define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_MASK 0x1
1515#define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_SHIFT 15
1516};
1517
1518/* IGU mapping line structure */
1519struct igu_mapping_line {
1520 __le32 igu_mapping_line_fields;
1521#define IGU_MAPPING_LINE_VALID_MASK 0x1
1522#define IGU_MAPPING_LINE_VALID_SHIFT 0
1523#define IGU_MAPPING_LINE_VECTOR_NUMBER_MASK 0xFF
1524#define IGU_MAPPING_LINE_VECTOR_NUMBER_SHIFT 1
1525#define IGU_MAPPING_LINE_FUNCTION_NUMBER_MASK 0xFF
1526#define IGU_MAPPING_LINE_FUNCTION_NUMBER_SHIFT 9
1527#define IGU_MAPPING_LINE_PF_VALID_MASK 0x1
1528#define IGU_MAPPING_LINE_PF_VALID_SHIFT 17
1529#define IGU_MAPPING_LINE_IPS_GROUP_MASK 0x3F
1530#define IGU_MAPPING_LINE_IPS_GROUP_SHIFT 18
1531#define IGU_MAPPING_LINE_RESERVED_MASK 0xFF
1532#define IGU_MAPPING_LINE_RESERVED_SHIFT 24
1533};
1534
1535/* IGU MSIX line structure */
1536struct igu_msix_vector {
1537 struct regpair address;
1538 __le32 data;
1539 __le32 msix_vector_fields;
1540#define IGU_MSIX_VECTOR_MASK_BIT_MASK 0x1
1541#define IGU_MSIX_VECTOR_MASK_BIT_SHIFT 0
1542#define IGU_MSIX_VECTOR_RESERVED0_MASK 0x7FFF
1543#define IGU_MSIX_VECTOR_RESERVED0_SHIFT 1
1544#define IGU_MSIX_VECTOR_STEERING_TAG_MASK 0xFF
1545#define IGU_MSIX_VECTOR_STEERING_TAG_SHIFT 16
1546#define IGU_MSIX_VECTOR_RESERVED1_MASK 0xFF
1547#define IGU_MSIX_VECTOR_RESERVED1_SHIFT 24
1548};
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001549/* per encapsulation type enabling flags */
1550struct prs_reg_encapsulation_type_en {
1551 u8 flags;
1552#define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_MASK 0x1
1553#define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT 0
1554#define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_MASK 0x1
1555#define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT 1
1556#define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_MASK 0x1
1557#define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT 2
1558#define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_MASK 0x1
1559#define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_SHIFT 3
1560#define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_MASK 0x1
1561#define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_SHIFT 4
1562#define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_MASK 0x1
1563#define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT 5
1564#define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_MASK 0x3
1565#define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_SHIFT 6
1566};
1567
1568enum pxp_tph_st_hint {
1569 TPH_ST_HINT_BIDIR,
1570 TPH_ST_HINT_REQUESTER,
1571 TPH_ST_HINT_TARGET,
1572 TPH_ST_HINT_TARGET_PRIO,
1573 MAX_PXP_TPH_ST_HINT
1574};
1575
1576/* QM hardware structure of enable bypass credit mask */
1577struct qm_rf_bypass_mask {
1578 u8 flags;
1579#define QM_RF_BYPASS_MASK_LINEVOQ_MASK 0x1
1580#define QM_RF_BYPASS_MASK_LINEVOQ_SHIFT 0
1581#define QM_RF_BYPASS_MASK_RESERVED0_MASK 0x1
1582#define QM_RF_BYPASS_MASK_RESERVED0_SHIFT 1
1583#define QM_RF_BYPASS_MASK_PFWFQ_MASK 0x1
1584#define QM_RF_BYPASS_MASK_PFWFQ_SHIFT 2
1585#define QM_RF_BYPASS_MASK_VPWFQ_MASK 0x1
1586#define QM_RF_BYPASS_MASK_VPWFQ_SHIFT 3
1587#define QM_RF_BYPASS_MASK_PFRL_MASK 0x1
1588#define QM_RF_BYPASS_MASK_PFRL_SHIFT 4
1589#define QM_RF_BYPASS_MASK_VPQCNRL_MASK 0x1
1590#define QM_RF_BYPASS_MASK_VPQCNRL_SHIFT 5
1591#define QM_RF_BYPASS_MASK_FWPAUSE_MASK 0x1
1592#define QM_RF_BYPASS_MASK_FWPAUSE_SHIFT 6
1593#define QM_RF_BYPASS_MASK_RESERVED1_MASK 0x1
1594#define QM_RF_BYPASS_MASK_RESERVED1_SHIFT 7
1595};
1596
1597/* QM hardware structure of opportunistic credit mask */
1598struct qm_rf_opportunistic_mask {
1599 __le16 flags;
1600#define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_MASK 0x1
1601#define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_SHIFT 0
1602#define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_MASK 0x1
1603#define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_SHIFT 1
1604#define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_MASK 0x1
1605#define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_SHIFT 2
1606#define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_MASK 0x1
1607#define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_SHIFT 3
1608#define QM_RF_OPPORTUNISTIC_MASK_PFRL_MASK 0x1
1609#define QM_RF_OPPORTUNISTIC_MASK_PFRL_SHIFT 4
1610#define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_MASK 0x1
1611#define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_SHIFT 5
1612#define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_MASK 0x1
1613#define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_SHIFT 6
1614#define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_MASK 0x1
1615#define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_SHIFT 7
1616#define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_MASK 0x1
1617#define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_SHIFT 8
1618#define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_MASK 0x7F
1619#define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_SHIFT 9
1620};
1621
1622/* QM hardware structure of QM map memory */
Tomer Tayar21dd79e2017-12-27 19:30:06 +02001623struct qm_rf_pq_map_e4 {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001624 __le32 reg;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02001625#define QM_RF_PQ_MAP_E4_PQ_VALID_MASK 0x1
1626#define QM_RF_PQ_MAP_E4_PQ_VALID_SHIFT 0
1627#define QM_RF_PQ_MAP_E4_RL_ID_MASK 0xFF
1628#define QM_RF_PQ_MAP_E4_RL_ID_SHIFT 1
1629#define QM_RF_PQ_MAP_E4_VP_PQ_ID_MASK 0x1FF
1630#define QM_RF_PQ_MAP_E4_VP_PQ_ID_SHIFT 9
1631#define QM_RF_PQ_MAP_E4_VOQ_MASK 0x1F
1632#define QM_RF_PQ_MAP_E4_VOQ_SHIFT 18
1633#define QM_RF_PQ_MAP_E4_WRR_WEIGHT_GROUP_MASK 0x3
1634#define QM_RF_PQ_MAP_E4_WRR_WEIGHT_GROUP_SHIFT 23
1635#define QM_RF_PQ_MAP_E4_RL_VALID_MASK 0x1
1636#define QM_RF_PQ_MAP_E4_RL_VALID_SHIFT 25
1637#define QM_RF_PQ_MAP_E4_RESERVED_MASK 0x3F
1638#define QM_RF_PQ_MAP_E4_RESERVED_SHIFT 26
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001639};
1640
1641/* Completion params for aggregated interrupt completion */
1642struct sdm_agg_int_comp_params {
1643 __le16 params;
1644#define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_MASK 0x3F
1645#define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT 0
1646#define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_MASK 0x1
1647#define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT 6
1648#define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_MASK 0x1FF
1649#define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT 7
1650};
1651
1652/* SDM operation gen command (generate aggregative interrupt) */
1653struct sdm_op_gen {
1654 __le32 command;
1655#define SDM_OP_GEN_COMP_PARAM_MASK 0xFFFF
1656#define SDM_OP_GEN_COMP_PARAM_SHIFT 0
1657#define SDM_OP_GEN_COMP_TYPE_MASK 0xF
1658#define SDM_OP_GEN_COMP_TYPE_SHIFT 16
1659#define SDM_OP_GEN_RESERVED_MASK 0xFFF
1660#define SDM_OP_GEN_RESERVED_SHIFT 20
1661};
1662
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001663/****************************************/
1664/* Debug Tools HSI constants and macros */
1665/****************************************/
1666
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001667enum block_addr {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001668 GRCBASE_GRC = 0x50000,
1669 GRCBASE_MISCS = 0x9000,
1670 GRCBASE_MISC = 0x8000,
1671 GRCBASE_DBU = 0xa000,
1672 GRCBASE_PGLUE_B = 0x2a8000,
1673 GRCBASE_CNIG = 0x218000,
1674 GRCBASE_CPMU = 0x30000,
1675 GRCBASE_NCSI = 0x40000,
1676 GRCBASE_OPTE = 0x53000,
1677 GRCBASE_BMB = 0x540000,
1678 GRCBASE_PCIE = 0x54000,
1679 GRCBASE_MCP = 0xe00000,
1680 GRCBASE_MCP2 = 0x52000,
1681 GRCBASE_PSWHST = 0x2a0000,
1682 GRCBASE_PSWHST2 = 0x29e000,
1683 GRCBASE_PSWRD = 0x29c000,
1684 GRCBASE_PSWRD2 = 0x29d000,
1685 GRCBASE_PSWWR = 0x29a000,
1686 GRCBASE_PSWWR2 = 0x29b000,
1687 GRCBASE_PSWRQ = 0x280000,
1688 GRCBASE_PSWRQ2 = 0x240000,
1689 GRCBASE_PGLCS = 0x0,
1690 GRCBASE_DMAE = 0xc000,
1691 GRCBASE_PTU = 0x560000,
1692 GRCBASE_TCM = 0x1180000,
1693 GRCBASE_MCM = 0x1200000,
1694 GRCBASE_UCM = 0x1280000,
1695 GRCBASE_XCM = 0x1000000,
1696 GRCBASE_YCM = 0x1080000,
1697 GRCBASE_PCM = 0x1100000,
1698 GRCBASE_QM = 0x2f0000,
1699 GRCBASE_TM = 0x2c0000,
1700 GRCBASE_DORQ = 0x100000,
1701 GRCBASE_BRB = 0x340000,
1702 GRCBASE_SRC = 0x238000,
1703 GRCBASE_PRS = 0x1f0000,
1704 GRCBASE_TSDM = 0xfb0000,
1705 GRCBASE_MSDM = 0xfc0000,
1706 GRCBASE_USDM = 0xfd0000,
1707 GRCBASE_XSDM = 0xf80000,
1708 GRCBASE_YSDM = 0xf90000,
1709 GRCBASE_PSDM = 0xfa0000,
1710 GRCBASE_TSEM = 0x1700000,
1711 GRCBASE_MSEM = 0x1800000,
1712 GRCBASE_USEM = 0x1900000,
1713 GRCBASE_XSEM = 0x1400000,
1714 GRCBASE_YSEM = 0x1500000,
1715 GRCBASE_PSEM = 0x1600000,
1716 GRCBASE_RSS = 0x238800,
1717 GRCBASE_TMLD = 0x4d0000,
1718 GRCBASE_MULD = 0x4e0000,
1719 GRCBASE_YULD = 0x4c8000,
1720 GRCBASE_XYLD = 0x4c0000,
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03001721 GRCBASE_PTLD = 0x590000,
1722 GRCBASE_YPLD = 0x5b0000,
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001723 GRCBASE_PRM = 0x230000,
1724 GRCBASE_PBF_PB1 = 0xda0000,
1725 GRCBASE_PBF_PB2 = 0xda4000,
1726 GRCBASE_RPB = 0x23c000,
1727 GRCBASE_BTB = 0xdb0000,
1728 GRCBASE_PBF = 0xd80000,
1729 GRCBASE_RDIF = 0x300000,
1730 GRCBASE_TDIF = 0x310000,
1731 GRCBASE_CDU = 0x580000,
1732 GRCBASE_CCFC = 0x2e0000,
1733 GRCBASE_TCFC = 0x2d0000,
1734 GRCBASE_IGU = 0x180000,
1735 GRCBASE_CAU = 0x1c0000,
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03001736 GRCBASE_RGFS = 0xf00000,
1737 GRCBASE_RGSRC = 0x320000,
1738 GRCBASE_TGFS = 0xd00000,
1739 GRCBASE_TGSRC = 0x322000,
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001740 GRCBASE_UMAC = 0x51000,
1741 GRCBASE_XMAC = 0x210000,
1742 GRCBASE_DBG = 0x10000,
1743 GRCBASE_NIG = 0x500000,
1744 GRCBASE_WOL = 0x600000,
1745 GRCBASE_BMBN = 0x610000,
1746 GRCBASE_IPC = 0x20000,
1747 GRCBASE_NWM = 0x800000,
1748 GRCBASE_NWS = 0x700000,
1749 GRCBASE_MS = 0x6a0000,
1750 GRCBASE_PHY_PCIE = 0x620000,
1751 GRCBASE_LED = 0x6b8000,
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02001752 GRCBASE_AVS_WRAP = 0x6b0000,
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001753 GRCBASE_MISC_AEU = 0x8000,
1754 GRCBASE_BAR0_MAP = 0x1c00000,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001755 MAX_BLOCK_ADDR
1756};
1757
1758enum block_id {
1759 BLOCK_GRC,
1760 BLOCK_MISCS,
1761 BLOCK_MISC,
1762 BLOCK_DBU,
1763 BLOCK_PGLUE_B,
1764 BLOCK_CNIG,
1765 BLOCK_CPMU,
1766 BLOCK_NCSI,
1767 BLOCK_OPTE,
1768 BLOCK_BMB,
1769 BLOCK_PCIE,
1770 BLOCK_MCP,
1771 BLOCK_MCP2,
1772 BLOCK_PSWHST,
1773 BLOCK_PSWHST2,
1774 BLOCK_PSWRD,
1775 BLOCK_PSWRD2,
1776 BLOCK_PSWWR,
1777 BLOCK_PSWWR2,
1778 BLOCK_PSWRQ,
1779 BLOCK_PSWRQ2,
1780 BLOCK_PGLCS,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001781 BLOCK_DMAE,
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001782 BLOCK_PTU,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001783 BLOCK_TCM,
1784 BLOCK_MCM,
1785 BLOCK_UCM,
1786 BLOCK_XCM,
1787 BLOCK_YCM,
1788 BLOCK_PCM,
1789 BLOCK_QM,
1790 BLOCK_TM,
1791 BLOCK_DORQ,
1792 BLOCK_BRB,
1793 BLOCK_SRC,
1794 BLOCK_PRS,
1795 BLOCK_TSDM,
1796 BLOCK_MSDM,
1797 BLOCK_USDM,
1798 BLOCK_XSDM,
1799 BLOCK_YSDM,
1800 BLOCK_PSDM,
1801 BLOCK_TSEM,
1802 BLOCK_MSEM,
1803 BLOCK_USEM,
1804 BLOCK_XSEM,
1805 BLOCK_YSEM,
1806 BLOCK_PSEM,
1807 BLOCK_RSS,
1808 BLOCK_TMLD,
1809 BLOCK_MULD,
1810 BLOCK_YULD,
1811 BLOCK_XYLD,
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03001812 BLOCK_PTLD,
1813 BLOCK_YPLD,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001814 BLOCK_PRM,
1815 BLOCK_PBF_PB1,
1816 BLOCK_PBF_PB2,
1817 BLOCK_RPB,
1818 BLOCK_BTB,
1819 BLOCK_PBF,
1820 BLOCK_RDIF,
1821 BLOCK_TDIF,
1822 BLOCK_CDU,
1823 BLOCK_CCFC,
1824 BLOCK_TCFC,
1825 BLOCK_IGU,
1826 BLOCK_CAU,
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03001827 BLOCK_RGFS,
1828 BLOCK_RGSRC,
1829 BLOCK_TGFS,
1830 BLOCK_TGSRC,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001831 BLOCK_UMAC,
1832 BLOCK_XMAC,
1833 BLOCK_DBG,
1834 BLOCK_NIG,
1835 BLOCK_WOL,
1836 BLOCK_BMBN,
1837 BLOCK_IPC,
1838 BLOCK_NWM,
1839 BLOCK_NWS,
1840 BLOCK_MS,
1841 BLOCK_PHY_PCIE,
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001842 BLOCK_LED,
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02001843 BLOCK_AVS_WRAP,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001844 BLOCK_MISC_AEU,
1845 BLOCK_BAR0_MAP,
1846 MAX_BLOCK_ID
1847};
1848
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001849/* binary debug buffer types */
1850enum bin_dbg_buffer_type {
1851 BIN_BUF_DBG_MODE_TREE,
1852 BIN_BUF_DBG_DUMP_REG,
1853 BIN_BUF_DBG_DUMP_MEM,
1854 BIN_BUF_DBG_IDLE_CHK_REGS,
1855 BIN_BUF_DBG_IDLE_CHK_IMMS,
1856 BIN_BUF_DBG_IDLE_CHK_RULES,
1857 BIN_BUF_DBG_IDLE_CHK_PARSING_DATA,
1858 BIN_BUF_DBG_ATTN_BLOCKS,
1859 BIN_BUF_DBG_ATTN_REGS,
1860 BIN_BUF_DBG_ATTN_INDEXES,
1861 BIN_BUF_DBG_ATTN_NAME_OFFSETS,
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03001862 BIN_BUF_DBG_BUS_BLOCKS,
1863 BIN_BUF_DBG_BUS_LINES,
1864 BIN_BUF_DBG_BUS_BLOCKS_USER_DATA,
1865 BIN_BUF_DBG_BUS_LINE_NAME_OFFSETS,
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001866 BIN_BUF_DBG_PARSING_STRINGS,
1867 MAX_BIN_DBG_BUFFER_TYPE
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001868};
1869
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001870
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001871/* Attention bit mapping */
1872struct dbg_attn_bit_mapping {
1873 __le16 data;
1874#define DBG_ATTN_BIT_MAPPING_VAL_MASK 0x7FFF
1875#define DBG_ATTN_BIT_MAPPING_VAL_SHIFT 0
1876#define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_MASK 0x1
1877#define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_SHIFT 15
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001878};
1879
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001880/* Attention block per-type data */
1881struct dbg_attn_block_type_data {
1882 __le16 names_offset;
1883 __le16 reserved1;
1884 u8 num_regs;
1885 u8 reserved2;
1886 __le16 regs_offset;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001887};
1888
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001889/* Block attentions */
1890struct dbg_attn_block {
1891 struct dbg_attn_block_type_data per_type_data[2];
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001892};
1893
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001894/* Attention register result */
1895struct dbg_attn_reg_result {
1896 __le32 data;
1897#define DBG_ATTN_REG_RESULT_STS_ADDRESS_MASK 0xFFFFFF
1898#define DBG_ATTN_REG_RESULT_STS_ADDRESS_SHIFT 0
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02001899#define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_MASK 0xFF
1900#define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_SHIFT 24
1901 __le16 block_attn_offset;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001902 __le16 reserved;
1903 __le32 sts_val;
1904 __le32 mask_val;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001905};
1906
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001907/* Attention block result */
1908struct dbg_attn_block_result {
1909 u8 block_id;
1910 u8 data;
1911#define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_MASK 0x3
1912#define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_SHIFT 0
1913#define DBG_ATTN_BLOCK_RESULT_NUM_REGS_MASK 0x3F
1914#define DBG_ATTN_BLOCK_RESULT_NUM_REGS_SHIFT 2
1915 __le16 names_offset;
1916 struct dbg_attn_reg_result reg_results[15];
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001917};
1918
Tomer Tayara2e76992017-12-27 19:30:05 +02001919/* Mode header */
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001920struct dbg_mode_hdr {
1921 __le16 data;
1922#define DBG_MODE_HDR_EVAL_MODE_MASK 0x1
1923#define DBG_MODE_HDR_EVAL_MODE_SHIFT 0
1924#define DBG_MODE_HDR_MODES_BUF_OFFSET_MASK 0x7FFF
1925#define DBG_MODE_HDR_MODES_BUF_OFFSET_SHIFT 1
1926};
1927
1928/* Attention register */
1929struct dbg_attn_reg {
1930 struct dbg_mode_hdr mode;
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02001931 __le16 block_attn_offset;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001932 __le32 data;
1933#define DBG_ATTN_REG_STS_ADDRESS_MASK 0xFFFFFF
1934#define DBG_ATTN_REG_STS_ADDRESS_SHIFT 0
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02001935#define DBG_ATTN_REG_NUM_REG_ATTN_MASK 0xFF
1936#define DBG_ATTN_REG_NUM_REG_ATTN_SHIFT 24
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001937 __le32 sts_clr_address;
1938 __le32 mask_address;
1939};
1940
Tomer Tayara2e76992017-12-27 19:30:05 +02001941/* Attention types */
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001942enum dbg_attn_type {
1943 ATTN_TYPE_INTERRUPT,
1944 ATTN_TYPE_PARITY,
1945 MAX_DBG_ATTN_TYPE
1946};
1947
Tomer Tayara2e76992017-12-27 19:30:05 +02001948/* Debug Bus block data */
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03001949struct dbg_bus_block {
1950 u8 num_of_lines;
1951 u8 has_latency_events;
1952 __le16 lines_offset;
1953};
1954
Tomer Tayara2e76992017-12-27 19:30:05 +02001955/* Debug Bus block user data */
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03001956struct dbg_bus_block_user_data {
1957 u8 num_of_lines;
1958 u8 has_latency_events;
1959 __le16 names_offset;
1960};
1961
Tomer Tayara2e76992017-12-27 19:30:05 +02001962/* Block Debug line data */
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03001963struct dbg_bus_line {
1964 u8 data;
Tomer Tayara2e76992017-12-27 19:30:05 +02001965#define DBG_BUS_LINE_NUM_OF_GROUPS_MASK 0xF
1966#define DBG_BUS_LINE_NUM_OF_GROUPS_SHIFT 0
1967#define DBG_BUS_LINE_IS_256B_MASK 0x1
1968#define DBG_BUS_LINE_IS_256B_SHIFT 4
1969#define DBG_BUS_LINE_RESERVED_MASK 0x7
1970#define DBG_BUS_LINE_RESERVED_SHIFT 5
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03001971 u8 group_sizes;
1972};
1973
Tomer Tayara2e76992017-12-27 19:30:05 +02001974/* Condition header for registers dump */
Tomer Tayarc965db42016-09-07 16:36:24 +03001975struct dbg_dump_cond_hdr {
1976 struct dbg_mode_hdr mode; /* Mode header */
1977 u8 block_id; /* block ID */
1978 u8 data_size; /* size in dwords of the data following this header */
1979};
1980
Tomer Tayara2e76992017-12-27 19:30:05 +02001981/* Memory data for registers dump */
Tomer Tayarc965db42016-09-07 16:36:24 +03001982struct dbg_dump_mem {
1983 __le32 dword0;
Tomer Tayara2e76992017-12-27 19:30:05 +02001984#define DBG_DUMP_MEM_ADDRESS_MASK 0xFFFFFF
1985#define DBG_DUMP_MEM_ADDRESS_SHIFT 0
1986#define DBG_DUMP_MEM_MEM_GROUP_ID_MASK 0xFF
1987#define DBG_DUMP_MEM_MEM_GROUP_ID_SHIFT 24
Tomer Tayarc965db42016-09-07 16:36:24 +03001988 __le32 dword1;
Tomer Tayara2e76992017-12-27 19:30:05 +02001989#define DBG_DUMP_MEM_LENGTH_MASK 0xFFFFFF
1990#define DBG_DUMP_MEM_LENGTH_SHIFT 0
1991#define DBG_DUMP_MEM_WIDE_BUS_MASK 0x1
1992#define DBG_DUMP_MEM_WIDE_BUS_SHIFT 24
1993#define DBG_DUMP_MEM_RESERVED_MASK 0x7F
1994#define DBG_DUMP_MEM_RESERVED_SHIFT 25
Tomer Tayarc965db42016-09-07 16:36:24 +03001995};
1996
Tomer Tayara2e76992017-12-27 19:30:05 +02001997/* Register data for registers dump */
Tomer Tayarc965db42016-09-07 16:36:24 +03001998struct dbg_dump_reg {
1999 __le32 data;
Tomer Tayara2e76992017-12-27 19:30:05 +02002000#define DBG_DUMP_REG_ADDRESS_MASK 0x7FFFFF
2001#define DBG_DUMP_REG_ADDRESS_SHIFT 0
2002#define DBG_DUMP_REG_WIDE_BUS_MASK 0x1
2003#define DBG_DUMP_REG_WIDE_BUS_SHIFT 23
2004#define DBG_DUMP_REG_LENGTH_MASK 0xFF
2005#define DBG_DUMP_REG_LENGTH_SHIFT 24
Tomer Tayarc965db42016-09-07 16:36:24 +03002006};
2007
Tomer Tayara2e76992017-12-27 19:30:05 +02002008/* Split header for registers dump */
Tomer Tayarc965db42016-09-07 16:36:24 +03002009struct dbg_dump_split_hdr {
2010 __le32 hdr;
Tomer Tayara2e76992017-12-27 19:30:05 +02002011#define DBG_DUMP_SPLIT_HDR_DATA_SIZE_MASK 0xFFFFFF
2012#define DBG_DUMP_SPLIT_HDR_DATA_SIZE_SHIFT 0
2013#define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_MASK 0xFF
2014#define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_SHIFT 24
Tomer Tayarc965db42016-09-07 16:36:24 +03002015};
2016
Tomer Tayara2e76992017-12-27 19:30:05 +02002017/* Condition header for idle check */
Tomer Tayarc965db42016-09-07 16:36:24 +03002018struct dbg_idle_chk_cond_hdr {
2019 struct dbg_mode_hdr mode; /* Mode header */
2020 __le16 data_size; /* size in dwords of the data following this header */
2021};
2022
2023/* Idle Check condition register */
2024struct dbg_idle_chk_cond_reg {
2025 __le32 data;
Tomer Tayara2e76992017-12-27 19:30:05 +02002026#define DBG_IDLE_CHK_COND_REG_ADDRESS_MASK 0x7FFFFF
2027#define DBG_IDLE_CHK_COND_REG_ADDRESS_SHIFT 0
2028#define DBG_IDLE_CHK_COND_REG_WIDE_BUS_MASK 0x1
2029#define DBG_IDLE_CHK_COND_REG_WIDE_BUS_SHIFT 23
2030#define DBG_IDLE_CHK_COND_REG_BLOCK_ID_MASK 0xFF
2031#define DBG_IDLE_CHK_COND_REG_BLOCK_ID_SHIFT 24
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03002032 __le16 num_entries;
2033 u8 entry_size;
2034 u8 start_entry;
Tomer Tayarc965db42016-09-07 16:36:24 +03002035};
2036
2037/* Idle Check info register */
2038struct dbg_idle_chk_info_reg {
2039 __le32 data;
Tomer Tayara2e76992017-12-27 19:30:05 +02002040#define DBG_IDLE_CHK_INFO_REG_ADDRESS_MASK 0x7FFFFF
2041#define DBG_IDLE_CHK_INFO_REG_ADDRESS_SHIFT 0
2042#define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_MASK 0x1
2043#define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_SHIFT 23
2044#define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_MASK 0xFF
2045#define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_SHIFT 24
Tomer Tayarc965db42016-09-07 16:36:24 +03002046 __le16 size; /* register size in dwords */
2047 struct dbg_mode_hdr mode; /* Mode header */
2048};
2049
2050/* Idle Check register */
2051union dbg_idle_chk_reg {
2052 struct dbg_idle_chk_cond_reg cond_reg; /* condition register */
2053 struct dbg_idle_chk_info_reg info_reg; /* info register */
2054};
2055
2056/* Idle Check result header */
2057struct dbg_idle_chk_result_hdr {
2058 __le16 rule_id; /* Failing rule index */
2059 __le16 mem_entry_id; /* Failing memory entry index */
2060 u8 num_dumped_cond_regs; /* number of dumped condition registers */
2061 u8 num_dumped_info_regs; /* number of dumped condition registers */
2062 u8 severity; /* from dbg_idle_chk_severity_types enum */
2063 u8 reserved;
2064};
2065
2066/* Idle Check result register header */
2067struct dbg_idle_chk_result_reg_hdr {
2068 u8 data;
2069#define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_MASK 0x1
2070#define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_SHIFT 0
2071#define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_MASK 0x7F
2072#define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_SHIFT 1
2073 u8 start_entry; /* index of the first checked entry */
2074 __le16 size; /* register size in dwords */
2075};
2076
2077/* Idle Check rule */
2078struct dbg_idle_chk_rule {
2079 __le16 rule_id; /* Idle Check rule ID */
2080 u8 severity; /* value from dbg_idle_chk_severity_types enum */
2081 u8 cond_id; /* Condition ID */
2082 u8 num_cond_regs; /* number of condition registers */
2083 u8 num_info_regs; /* number of info registers */
2084 u8 num_imms; /* number of immediates in the condition */
2085 u8 reserved1;
2086 __le16 reg_offset; /* offset of this rules registers in the idle check
2087 * register array (in dbg_idle_chk_reg units).
2088 */
2089 __le16 imm_offset; /* offset of this rules immediate values in the
2090 * immediate values array (in dwords).
2091 */
2092};
2093
2094/* Idle Check rule parsing data */
2095struct dbg_idle_chk_rule_parsing_data {
2096 __le32 data;
Tomer Tayara2e76992017-12-27 19:30:05 +02002097#define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_MASK 0x1
2098#define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_SHIFT 0
2099#define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_MASK 0x7FFFFFFF
2100#define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_SHIFT 1
Tomer Tayarc965db42016-09-07 16:36:24 +03002101};
2102
Tomer Tayara2e76992017-12-27 19:30:05 +02002103/* Idle check severity types */
Tomer Tayarc965db42016-09-07 16:36:24 +03002104enum dbg_idle_chk_severity_types {
2105 /* idle check failure should cause an error */
2106 IDLE_CHK_SEVERITY_ERROR,
2107 /* idle check failure should cause an error only if theres no traffic */
2108 IDLE_CHK_SEVERITY_ERROR_NO_TRAFFIC,
2109 /* idle check failure should cause a warning */
2110 IDLE_CHK_SEVERITY_WARNING,
2111 MAX_DBG_IDLE_CHK_SEVERITY_TYPES
2112};
2113
2114/* Debug Bus block data */
2115struct dbg_bus_block_data {
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03002116 __le16 data;
Tomer Tayara2e76992017-12-27 19:30:05 +02002117#define DBG_BUS_BLOCK_DATA_ENABLE_MASK_MASK 0xF
2118#define DBG_BUS_BLOCK_DATA_ENABLE_MASK_SHIFT 0
2119#define DBG_BUS_BLOCK_DATA_RIGHT_SHIFT_MASK 0xF
2120#define DBG_BUS_BLOCK_DATA_RIGHT_SHIFT_SHIFT 4
2121#define DBG_BUS_BLOCK_DATA_FORCE_VALID_MASK_MASK 0xF
2122#define DBG_BUS_BLOCK_DATA_FORCE_VALID_MASK_SHIFT 8
2123#define DBG_BUS_BLOCK_DATA_FORCE_FRAME_MASK_MASK 0xF
2124#define DBG_BUS_BLOCK_DATA_FORCE_FRAME_MASK_SHIFT 12
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03002125 u8 line_num;
2126 u8 hw_id;
Tomer Tayarc965db42016-09-07 16:36:24 +03002127};
2128
2129/* Debug Bus Clients */
2130enum dbg_bus_clients {
2131 DBG_BUS_CLIENT_RBCN,
2132 DBG_BUS_CLIENT_RBCP,
2133 DBG_BUS_CLIENT_RBCR,
2134 DBG_BUS_CLIENT_RBCT,
2135 DBG_BUS_CLIENT_RBCU,
2136 DBG_BUS_CLIENT_RBCF,
2137 DBG_BUS_CLIENT_RBCX,
2138 DBG_BUS_CLIENT_RBCS,
2139 DBG_BUS_CLIENT_RBCH,
2140 DBG_BUS_CLIENT_RBCZ,
2141 DBG_BUS_CLIENT_OTHER_ENGINE,
2142 DBG_BUS_CLIENT_TIMESTAMP,
2143 DBG_BUS_CLIENT_CPU,
2144 DBG_BUS_CLIENT_RBCY,
2145 DBG_BUS_CLIENT_RBCQ,
2146 DBG_BUS_CLIENT_RBCM,
2147 DBG_BUS_CLIENT_RBCB,
2148 DBG_BUS_CLIENT_RBCW,
2149 DBG_BUS_CLIENT_RBCV,
2150 MAX_DBG_BUS_CLIENTS
2151};
2152
Tomer Tayara2e76992017-12-27 19:30:05 +02002153/* Debug Bus constraint operation types */
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02002154enum dbg_bus_constraint_ops {
2155 DBG_BUS_CONSTRAINT_OP_EQ,
2156 DBG_BUS_CONSTRAINT_OP_NE,
2157 DBG_BUS_CONSTRAINT_OP_LT,
2158 DBG_BUS_CONSTRAINT_OP_LTC,
2159 DBG_BUS_CONSTRAINT_OP_LE,
2160 DBG_BUS_CONSTRAINT_OP_LEC,
2161 DBG_BUS_CONSTRAINT_OP_GT,
2162 DBG_BUS_CONSTRAINT_OP_GTC,
2163 DBG_BUS_CONSTRAINT_OP_GE,
2164 DBG_BUS_CONSTRAINT_OP_GEC,
2165 MAX_DBG_BUS_CONSTRAINT_OPS
2166};
2167
Tomer Tayara2e76992017-12-27 19:30:05 +02002168/* Debug Bus trigger state data */
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03002169struct dbg_bus_trigger_state_data {
2170 u8 data;
Tomer Tayara2e76992017-12-27 19:30:05 +02002171#define DBG_BUS_TRIGGER_STATE_DATA_BLOCK_SHIFTED_ENABLE_MASK_MASK 0xF
2172#define DBG_BUS_TRIGGER_STATE_DATA_BLOCK_SHIFTED_ENABLE_MASK_SHIFT 0
2173#define DBG_BUS_TRIGGER_STATE_DATA_CONSTRAINT_DWORD_MASK_MASK 0xF
2174#define DBG_BUS_TRIGGER_STATE_DATA_CONSTRAINT_DWORD_MASK_SHIFT 4
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03002175};
2176
Tomer Tayarc965db42016-09-07 16:36:24 +03002177/* Debug Bus memory address */
2178struct dbg_bus_mem_addr {
2179 __le32 lo;
2180 __le32 hi;
2181};
2182
2183/* Debug Bus PCI buffer data */
2184struct dbg_bus_pci_buf_data {
2185 struct dbg_bus_mem_addr phys_addr; /* PCI buffer physical address */
2186 struct dbg_bus_mem_addr virt_addr; /* PCI buffer virtual address */
2187 __le32 size; /* PCI buffer size in bytes */
2188};
2189
2190/* Debug Bus Storm EID range filter params */
2191struct dbg_bus_storm_eid_range_params {
2192 u8 min; /* Minimal event ID to filter on */
2193 u8 max; /* Maximal event ID to filter on */
2194};
2195
2196/* Debug Bus Storm EID mask filter params */
2197struct dbg_bus_storm_eid_mask_params {
2198 u8 val; /* Event ID value */
2199 u8 mask; /* Event ID mask. 1s in the mask = dont care bits. */
2200};
2201
2202/* Debug Bus Storm EID filter params */
2203union dbg_bus_storm_eid_params {
2204 struct dbg_bus_storm_eid_range_params range;
2205 struct dbg_bus_storm_eid_mask_params mask;
2206};
2207
2208/* Debug Bus Storm data */
2209struct dbg_bus_storm_data {
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03002210 u8 enabled;
2211 u8 mode;
Tomer Tayarc965db42016-09-07 16:36:24 +03002212 u8 hw_id;
2213 u8 eid_filter_en;
2214 u8 eid_range_not_mask;
2215 u8 cid_filter_en;
2216 union dbg_bus_storm_eid_params eid_filter_params;
Tomer Tayarc965db42016-09-07 16:36:24 +03002217 __le32 cid;
2218};
2219
2220/* Debug Bus data */
2221struct dbg_bus_data {
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03002222 __le32 app_version;
2223 u8 state;
2224 u8 hw_dwords;
2225 __le16 hw_id_mask;
2226 u8 num_enabled_blocks;
2227 u8 num_enabled_storms;
2228 u8 target;
2229 u8 one_shot_en;
2230 u8 grc_input_en;
2231 u8 timestamp_input_en;
2232 u8 filter_en;
2233 u8 adding_filter;
2234 u8 filter_pre_trigger;
2235 u8 filter_post_trigger;
Tomer Tayarc965db42016-09-07 16:36:24 +03002236 __le16 reserved;
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03002237 u8 trigger_en;
2238 struct dbg_bus_trigger_state_data trigger_states[3];
2239 u8 next_trigger_state;
2240 u8 next_constraint_id;
2241 u8 unify_inputs;
2242 u8 rcv_from_other_engine;
2243 struct dbg_bus_pci_buf_data pci_buf;
2244 struct dbg_bus_block_data blocks[88];
2245 struct dbg_bus_storm_data storms[6];
Tomer Tayarc965db42016-09-07 16:36:24 +03002246};
2247
Tomer Tayara2e76992017-12-27 19:30:05 +02002248/* Debug bus filter types */
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02002249enum dbg_bus_filter_types {
2250 DBG_BUS_FILTER_TYPE_OFF,
2251 DBG_BUS_FILTER_TYPE_PRE,
2252 DBG_BUS_FILTER_TYPE_POST,
2253 DBG_BUS_FILTER_TYPE_ON,
2254 MAX_DBG_BUS_FILTER_TYPES
2255};
2256
Tomer Tayarc965db42016-09-07 16:36:24 +03002257/* Debug bus frame modes */
2258enum dbg_bus_frame_modes {
2259 DBG_BUS_FRAME_MODE_0HW_4ST = 0, /* 0 HW dwords, 4 Storm dwords */
2260 DBG_BUS_FRAME_MODE_4HW_0ST = 3, /* 4 HW dwords, 0 Storm dwords */
2261 DBG_BUS_FRAME_MODE_8HW_0ST = 4, /* 8 HW dwords, 0 Storm dwords */
2262 MAX_DBG_BUS_FRAME_MODES
2263};
2264
Tomer Tayara2e76992017-12-27 19:30:05 +02002265/* Debug bus other engine mode */
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02002266enum dbg_bus_other_engine_modes {
2267 DBG_BUS_OTHER_ENGINE_MODE_NONE,
2268 DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_TX,
2269 DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_RX,
2270 DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_TX,
2271 DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_RX,
2272 MAX_DBG_BUS_OTHER_ENGINE_MODES
2273};
2274
Tomer Tayara2e76992017-12-27 19:30:05 +02002275/* Debug bus post-trigger recording types */
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02002276enum dbg_bus_post_trigger_types {
2277 DBG_BUS_POST_TRIGGER_RECORD,
2278 DBG_BUS_POST_TRIGGER_DROP,
2279 MAX_DBG_BUS_POST_TRIGGER_TYPES
2280};
2281
Tomer Tayara2e76992017-12-27 19:30:05 +02002282/* Debug bus pre-trigger recording types */
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02002283enum dbg_bus_pre_trigger_types {
2284 DBG_BUS_PRE_TRIGGER_START_FROM_ZERO,
2285 DBG_BUS_PRE_TRIGGER_NUM_CHUNKS,
2286 DBG_BUS_PRE_TRIGGER_DROP,
2287 MAX_DBG_BUS_PRE_TRIGGER_TYPES
2288};
2289
Tomer Tayara2e76992017-12-27 19:30:05 +02002290/* Debug bus SEMI frame modes */
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02002291enum dbg_bus_semi_frame_modes {
Tomer Tayara2e76992017-12-27 19:30:05 +02002292 DBG_BUS_SEMI_FRAME_MODE_0SLOW_4FAST = 0,
2293 DBG_BUS_SEMI_FRAME_MODE_4SLOW_0FAST = 3,
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02002294 MAX_DBG_BUS_SEMI_FRAME_MODES
2295};
2296
Tomer Tayarc965db42016-09-07 16:36:24 +03002297/* Debug bus states */
2298enum dbg_bus_states {
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03002299 DBG_BUS_STATE_IDLE,
2300 DBG_BUS_STATE_READY,
2301 DBG_BUS_STATE_RECORDING,
2302 DBG_BUS_STATE_STOPPED,
Tomer Tayarc965db42016-09-07 16:36:24 +03002303 MAX_DBG_BUS_STATES
2304};
2305
Tomer Tayara2e76992017-12-27 19:30:05 +02002306/* Debug Bus Storm modes */
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02002307enum dbg_bus_storm_modes {
2308 DBG_BUS_STORM_MODE_PRINTF,
2309 DBG_BUS_STORM_MODE_PRAM_ADDR,
2310 DBG_BUS_STORM_MODE_DRA_RW,
2311 DBG_BUS_STORM_MODE_DRA_W,
2312 DBG_BUS_STORM_MODE_LD_ST_ADDR,
2313 DBG_BUS_STORM_MODE_DRA_FSM,
2314 DBG_BUS_STORM_MODE_RH,
2315 DBG_BUS_STORM_MODE_FOC,
2316 DBG_BUS_STORM_MODE_EXT_STORE,
2317 MAX_DBG_BUS_STORM_MODES
2318};
2319
Tomer Tayarc965db42016-09-07 16:36:24 +03002320/* Debug bus target IDs */
2321enum dbg_bus_targets {
Tomer Tayarc965db42016-09-07 16:36:24 +03002322 DBG_BUS_TARGET_ID_INT_BUF,
Tomer Tayarc965db42016-09-07 16:36:24 +03002323 DBG_BUS_TARGET_ID_NIG,
Tomer Tayarc965db42016-09-07 16:36:24 +03002324 DBG_BUS_TARGET_ID_PCI,
2325 MAX_DBG_BUS_TARGETS
2326};
2327
2328/* GRC Dump data */
2329struct dbg_grc_data {
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02002330 u8 params_initialized;
2331 u8 reserved1;
2332 __le16 reserved2;
2333 __le32 param_val[48];
Tomer Tayarc965db42016-09-07 16:36:24 +03002334};
2335
2336/* Debug GRC params */
2337enum dbg_grc_params {
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03002338 DBG_GRC_PARAM_DUMP_TSTORM,
2339 DBG_GRC_PARAM_DUMP_MSTORM,
2340 DBG_GRC_PARAM_DUMP_USTORM,
2341 DBG_GRC_PARAM_DUMP_XSTORM,
2342 DBG_GRC_PARAM_DUMP_YSTORM,
2343 DBG_GRC_PARAM_DUMP_PSTORM,
2344 DBG_GRC_PARAM_DUMP_REGS,
2345 DBG_GRC_PARAM_DUMP_RAM,
2346 DBG_GRC_PARAM_DUMP_PBUF,
2347 DBG_GRC_PARAM_DUMP_IOR,
2348 DBG_GRC_PARAM_DUMP_VFC,
2349 DBG_GRC_PARAM_DUMP_CM_CTX,
2350 DBG_GRC_PARAM_DUMP_PXP,
2351 DBG_GRC_PARAM_DUMP_RSS,
2352 DBG_GRC_PARAM_DUMP_CAU,
2353 DBG_GRC_PARAM_DUMP_QM,
2354 DBG_GRC_PARAM_DUMP_MCP,
2355 DBG_GRC_PARAM_RESERVED,
2356 DBG_GRC_PARAM_DUMP_CFC,
2357 DBG_GRC_PARAM_DUMP_IGU,
2358 DBG_GRC_PARAM_DUMP_BRB,
2359 DBG_GRC_PARAM_DUMP_BTB,
2360 DBG_GRC_PARAM_DUMP_BMB,
2361 DBG_GRC_PARAM_DUMP_NIG,
2362 DBG_GRC_PARAM_DUMP_MULD,
2363 DBG_GRC_PARAM_DUMP_PRS,
2364 DBG_GRC_PARAM_DUMP_DMAE,
2365 DBG_GRC_PARAM_DUMP_TM,
2366 DBG_GRC_PARAM_DUMP_SDM,
2367 DBG_GRC_PARAM_DUMP_DIF,
2368 DBG_GRC_PARAM_DUMP_STATIC,
2369 DBG_GRC_PARAM_UNSTALL,
2370 DBG_GRC_PARAM_NUM_LCIDS,
2371 DBG_GRC_PARAM_NUM_LTIDS,
Tomer Tayarc965db42016-09-07 16:36:24 +03002372 DBG_GRC_PARAM_EXCLUDE_ALL,
Tomer Tayarc965db42016-09-07 16:36:24 +03002373 DBG_GRC_PARAM_CRASH,
Tomer Tayarc965db42016-09-07 16:36:24 +03002374 DBG_GRC_PARAM_PARITY_SAFE,
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03002375 DBG_GRC_PARAM_DUMP_CM,
2376 DBG_GRC_PARAM_DUMP_PHY,
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02002377 DBG_GRC_PARAM_NO_MCP,
2378 DBG_GRC_PARAM_NO_FW_VER,
Tomer Tayarc965db42016-09-07 16:36:24 +03002379 MAX_DBG_GRC_PARAMS
2380};
2381
2382/* Debug reset registers */
2383enum dbg_reset_regs {
2384 DBG_RESET_REG_MISCS_PL_UA,
2385 DBG_RESET_REG_MISCS_PL_HV,
2386 DBG_RESET_REG_MISCS_PL_HV_2,
2387 DBG_RESET_REG_MISC_PL_UA,
2388 DBG_RESET_REG_MISC_PL_HV,
2389 DBG_RESET_REG_MISC_PL_PDA_VMAIN_1,
2390 DBG_RESET_REG_MISC_PL_PDA_VMAIN_2,
2391 DBG_RESET_REG_MISC_PL_PDA_VAUX,
2392 MAX_DBG_RESET_REGS
2393};
2394
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002395/* Debug status codes */
2396enum dbg_status {
2397 DBG_STATUS_OK,
2398 DBG_STATUS_APP_VERSION_NOT_SET,
2399 DBG_STATUS_UNSUPPORTED_APP_VERSION,
2400 DBG_STATUS_DBG_BLOCK_NOT_RESET,
2401 DBG_STATUS_INVALID_ARGS,
2402 DBG_STATUS_OUTPUT_ALREADY_SET,
2403 DBG_STATUS_INVALID_PCI_BUF_SIZE,
2404 DBG_STATUS_PCI_BUF_ALLOC_FAILED,
2405 DBG_STATUS_PCI_BUF_NOT_ALLOCATED,
2406 DBG_STATUS_TOO_MANY_INPUTS,
2407 DBG_STATUS_INPUT_OVERLAP,
2408 DBG_STATUS_HW_ONLY_RECORDING,
2409 DBG_STATUS_STORM_ALREADY_ENABLED,
2410 DBG_STATUS_STORM_NOT_ENABLED,
2411 DBG_STATUS_BLOCK_ALREADY_ENABLED,
2412 DBG_STATUS_BLOCK_NOT_ENABLED,
2413 DBG_STATUS_NO_INPUT_ENABLED,
2414 DBG_STATUS_NO_FILTER_TRIGGER_64B,
2415 DBG_STATUS_FILTER_ALREADY_ENABLED,
2416 DBG_STATUS_TRIGGER_ALREADY_ENABLED,
2417 DBG_STATUS_TRIGGER_NOT_ENABLED,
2418 DBG_STATUS_CANT_ADD_CONSTRAINT,
2419 DBG_STATUS_TOO_MANY_TRIGGER_STATES,
2420 DBG_STATUS_TOO_MANY_CONSTRAINTS,
2421 DBG_STATUS_RECORDING_NOT_STARTED,
2422 DBG_STATUS_DATA_DIDNT_TRIGGER,
2423 DBG_STATUS_NO_DATA_RECORDED,
2424 DBG_STATUS_DUMP_BUF_TOO_SMALL,
2425 DBG_STATUS_DUMP_NOT_CHUNK_ALIGNED,
2426 DBG_STATUS_UNKNOWN_CHIP,
2427 DBG_STATUS_VIRT_MEM_ALLOC_FAILED,
2428 DBG_STATUS_BLOCK_IN_RESET,
2429 DBG_STATUS_INVALID_TRACE_SIGNATURE,
2430 DBG_STATUS_INVALID_NVRAM_BUNDLE,
2431 DBG_STATUS_NVRAM_GET_IMAGE_FAILED,
2432 DBG_STATUS_NON_ALIGNED_NVRAM_IMAGE,
2433 DBG_STATUS_NVRAM_READ_FAILED,
2434 DBG_STATUS_IDLE_CHK_PARSE_FAILED,
2435 DBG_STATUS_MCP_TRACE_BAD_DATA,
2436 DBG_STATUS_MCP_TRACE_NO_META,
2437 DBG_STATUS_MCP_COULD_NOT_HALT,
2438 DBG_STATUS_MCP_COULD_NOT_RESUME,
2439 DBG_STATUS_DMAE_FAILED,
2440 DBG_STATUS_SEMI_FIFO_NOT_EMPTY,
2441 DBG_STATUS_IGU_FIFO_BAD_DATA,
2442 DBG_STATUS_MCP_COULD_NOT_MASK_PRTY,
2443 DBG_STATUS_FW_ASSERTS_PARSE_FAILED,
2444 DBG_STATUS_REG_FIFO_BAD_DATA,
2445 DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA,
2446 DBG_STATUS_DBG_ARRAY_NOT_SET,
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03002447 DBG_STATUS_FILTER_BUG,
2448 DBG_STATUS_NON_MATCHING_LINES,
2449 DBG_STATUS_INVALID_TRIGGER_DWORD_OFFSET,
2450 DBG_STATUS_DBG_BUS_IN_USE,
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002451 MAX_DBG_STATUS
2452};
2453
Tomer Tayarc965db42016-09-07 16:36:24 +03002454/* Debug Storms IDs */
2455enum dbg_storms {
2456 DBG_TSTORM_ID,
2457 DBG_MSTORM_ID,
2458 DBG_USTORM_ID,
2459 DBG_XSTORM_ID,
2460 DBG_YSTORM_ID,
2461 DBG_PSTORM_ID,
2462 MAX_DBG_STORMS
2463};
2464
2465/* Idle Check data */
2466struct idle_chk_data {
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03002467 __le32 buf_size;
2468 u8 buf_size_set;
Tomer Tayarc965db42016-09-07 16:36:24 +03002469 u8 reserved1;
2470 __le16 reserved2;
2471};
2472
2473/* Debug Tools data (per HW function) */
2474struct dbg_tools_data {
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03002475 struct dbg_grc_data grc;
2476 struct dbg_bus_data bus;
2477 struct idle_chk_data idle_chk;
2478 u8 mode_enable[40];
2479 u8 block_in_reset[88];
2480 u8 chip_id;
2481 u8 platform_id;
2482 u8 initialized;
Tomer Tayarc965db42016-09-07 16:36:24 +03002483 u8 reserved;
2484};
2485
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002486/********************************/
2487/* HSI Init Functions constants */
2488/********************************/
2489
2490/* Number of VLAN priorities */
2491#define NUM_OF_VLAN_PRIORITIES 8
2492
Tomer Tayara2e76992017-12-27 19:30:05 +02002493/* BRB RAM init requirements */
Yuval Mintz05fafbf2016-08-19 09:33:31 +03002494struct init_brb_ram_req {
2495 __le32 guranteed_per_tc;
2496 __le32 headroom_per_tc;
2497 __le32 min_pkt_size;
2498 __le32 max_ports_per_engine;
2499 u8 num_active_tcs[MAX_NUM_PORTS];
2500};
2501
Tomer Tayara2e76992017-12-27 19:30:05 +02002502/* ETS per-TC init requirements */
Yuval Mintz05fafbf2016-08-19 09:33:31 +03002503struct init_ets_tc_req {
2504 u8 use_sp;
2505 u8 use_wfq;
2506 __le16 weight;
2507};
2508
Tomer Tayara2e76992017-12-27 19:30:05 +02002509/* ETS init requirements */
Yuval Mintz05fafbf2016-08-19 09:33:31 +03002510struct init_ets_req {
2511 __le32 mtu;
2512 struct init_ets_tc_req tc_req[NUM_OF_TCS];
2513};
2514
Tomer Tayara2e76992017-12-27 19:30:05 +02002515/* NIG LB RL init requirements */
Yuval Mintz05fafbf2016-08-19 09:33:31 +03002516struct init_nig_lb_rl_req {
2517 __le16 lb_mac_rate;
2518 __le16 lb_rate;
2519 __le32 mtu;
2520 __le16 tc_rate[NUM_OF_PHYS_TCS];
2521};
2522
Tomer Tayara2e76992017-12-27 19:30:05 +02002523/* NIG TC mapping for each priority */
Yuval Mintz05fafbf2016-08-19 09:33:31 +03002524struct init_nig_pri_tc_map_entry {
2525 u8 tc_id;
2526 u8 valid;
2527};
2528
Tomer Tayara2e76992017-12-27 19:30:05 +02002529/* NIG priority to TC map init requirements */
Yuval Mintz05fafbf2016-08-19 09:33:31 +03002530struct init_nig_pri_tc_map_req {
2531 struct init_nig_pri_tc_map_entry pri[NUM_OF_VLAN_PRIORITIES];
2532};
2533
Tomer Tayara2e76992017-12-27 19:30:05 +02002534/* QM per-port init parameters */
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002535struct init_qm_port_params {
2536 u8 active;
2537 u8 active_phys_tcs;
2538 __le16 num_pbf_cmd_lines;
2539 __le16 num_btb_blocks;
2540 __le16 reserved;
2541};
2542
2543/* QM per-PQ init parameters */
2544struct init_qm_pq_params {
2545 u8 vport_id;
2546 u8 tc_id;
2547 u8 wrr_group;
2548 u8 rl_valid;
2549};
2550
2551/* QM per-vport init parameters */
2552struct init_qm_vport_params {
2553 __le32 vport_rl;
2554 __le16 vport_wfq;
2555 __le16 first_tx_pq_id[NUM_OF_TCS];
2556};
2557
2558/**************************************/
2559/* Init Tool HSI constants and macros */
2560/**************************************/
2561
2562/* Width of GRC address in bits (addresses are specified in dwords) */
2563#define GRC_ADDR_BITS 23
Yuval Mintz05fafbf2016-08-19 09:33:31 +03002564#define MAX_GRC_ADDR (BIT(GRC_ADDR_BITS) - 1)
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002565
2566/* indicates an init that should be applied to any phase ID */
2567#define ANY_PHASE_ID 0xffff
2568
2569/* Max size in dwords of a zipped array */
2570#define MAX_ZIPPED_SIZE 8192
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03002571enum chip_ids {
2572 CHIP_BB,
2573 CHIP_K2,
2574 CHIP_RESERVED,
2575 MAX_CHIP_IDS
2576};
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002577
Tomer Tayarc965db42016-09-07 16:36:24 +03002578struct fw_asserts_ram_section {
2579 __le16 section_ram_line_offset;
2580 __le16 section_ram_line_size;
2581 u8 list_dword_offset;
2582 u8 list_element_dword_size;
2583 u8 list_num_elements;
2584 u8 list_next_index_dword_offset;
2585};
2586
2587struct fw_ver_num {
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03002588 u8 major;
2589 u8 minor;
2590 u8 rev;
2591 u8 eng;
Tomer Tayarc965db42016-09-07 16:36:24 +03002592};
2593
2594struct fw_ver_info {
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03002595 __le16 tools_ver;
2596 u8 image_id;
Tomer Tayarc965db42016-09-07 16:36:24 +03002597 u8 reserved1;
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03002598 struct fw_ver_num num;
2599 __le32 timestamp;
Tomer Tayarc965db42016-09-07 16:36:24 +03002600 __le32 reserved2;
2601};
2602
2603struct fw_info {
2604 struct fw_ver_info ver;
2605 struct fw_asserts_ram_section fw_asserts_section;
2606};
2607
2608struct fw_info_location {
2609 __le32 grc_addr;
2610 __le32 size;
2611};
2612
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002613enum init_modes {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002614 MODE_RESERVED,
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02002615 MODE_BB,
Tomer Tayarc965db42016-09-07 16:36:24 +03002616 MODE_K2,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002617 MODE_ASIC,
Tomer Tayarc965db42016-09-07 16:36:24 +03002618 MODE_RESERVED2,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002619 MODE_RESERVED3,
2620 MODE_RESERVED4,
2621 MODE_RESERVED5,
2622 MODE_SF,
2623 MODE_MF_SD,
2624 MODE_MF_SI,
2625 MODE_PORTS_PER_ENG_1,
2626 MODE_PORTS_PER_ENG_2,
2627 MODE_PORTS_PER_ENG_4,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002628 MODE_100G,
Tomer Tayarc965db42016-09-07 16:36:24 +03002629 MODE_RESERVED6,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002630 MAX_INIT_MODES
2631};
2632
2633enum init_phases {
2634 PHASE_ENGINE,
2635 PHASE_PORT,
2636 PHASE_PF,
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03002637 PHASE_VF,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002638 PHASE_QM_PF,
2639 MAX_INIT_PHASES
2640};
2641
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002642enum init_split_types {
2643 SPLIT_TYPE_NONE,
2644 SPLIT_TYPE_PORT,
2645 SPLIT_TYPE_PF,
2646 SPLIT_TYPE_PORT_PF,
2647 SPLIT_TYPE_VF,
2648 MAX_INIT_SPLIT_TYPES
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002649};
2650
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002651/* Binary buffer header */
2652struct bin_buffer_hdr {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002653 __le32 offset;
2654 __le32 length;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002655};
2656
Tomer Tayara2e76992017-12-27 19:30:05 +02002657/* Binary init buffer types */
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002658enum bin_init_buffer_type {
Yuval Mintz05fafbf2016-08-19 09:33:31 +03002659 BIN_BUF_INIT_FW_VER_INFO,
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002660 BIN_BUF_INIT_CMD,
2661 BIN_BUF_INIT_VAL,
2662 BIN_BUF_INIT_MODE_TREE,
Yuval Mintz05fafbf2016-08-19 09:33:31 +03002663 BIN_BUF_INIT_IRO,
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002664 MAX_BIN_INIT_BUFFER_TYPE
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002665};
2666
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002667/* init array header: raw */
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002668struct init_array_raw_hdr {
2669 __le32 data;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002670#define INIT_ARRAY_RAW_HDR_TYPE_MASK 0xF
2671#define INIT_ARRAY_RAW_HDR_TYPE_SHIFT 0
2672#define INIT_ARRAY_RAW_HDR_PARAMS_MASK 0xFFFFFFF
2673#define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT 4
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002674};
2675
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002676/* init array header: standard */
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002677struct init_array_standard_hdr {
2678 __le32 data;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002679#define INIT_ARRAY_STANDARD_HDR_TYPE_MASK 0xF
2680#define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0
2681#define INIT_ARRAY_STANDARD_HDR_SIZE_MASK 0xFFFFFFF
2682#define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT 4
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002683};
2684
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002685/* init array header: zipped */
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002686struct init_array_zipped_hdr {
2687 __le32 data;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002688#define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK 0xF
2689#define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT 0
2690#define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK 0xFFFFFFF
2691#define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT 4
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002692};
2693
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002694/* init array header: pattern */
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002695struct init_array_pattern_hdr {
2696 __le32 data;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002697#define INIT_ARRAY_PATTERN_HDR_TYPE_MASK 0xF
2698#define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT 0
2699#define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK 0xF
2700#define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT 4
2701#define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK 0xFFFFFF
2702#define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT 8
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002703};
2704
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002705/* init array header union */
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002706union init_array_hdr {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002707 struct init_array_raw_hdr raw;
2708 struct init_array_standard_hdr standard;
2709 struct init_array_zipped_hdr zipped;
2710 struct init_array_pattern_hdr pattern;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002711};
2712
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002713/* init array types */
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002714enum init_array_types {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002715 INIT_ARR_STANDARD,
2716 INIT_ARR_ZIPPED,
2717 INIT_ARR_PATTERN,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002718 MAX_INIT_ARRAY_TYPES
2719};
2720
2721/* init operation: callback */
2722struct init_callback_op {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002723 __le32 op_data;
2724#define INIT_CALLBACK_OP_OP_MASK 0xF
2725#define INIT_CALLBACK_OP_OP_SHIFT 0
2726#define INIT_CALLBACK_OP_RESERVED_MASK 0xFFFFFFF
2727#define INIT_CALLBACK_OP_RESERVED_SHIFT 4
2728 __le16 callback_id;
2729 __le16 block_id;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002730};
2731
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002732/* init operation: delay */
2733struct init_delay_op {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002734 __le32 op_data;
2735#define INIT_DELAY_OP_OP_MASK 0xF
2736#define INIT_DELAY_OP_OP_SHIFT 0
2737#define INIT_DELAY_OP_RESERVED_MASK 0xFFFFFFF
2738#define INIT_DELAY_OP_RESERVED_SHIFT 4
2739 __le32 delay;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002740};
2741
2742/* init operation: if_mode */
2743struct init_if_mode_op {
2744 __le32 op_data;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002745#define INIT_IF_MODE_OP_OP_MASK 0xF
2746#define INIT_IF_MODE_OP_OP_SHIFT 0
2747#define INIT_IF_MODE_OP_RESERVED1_MASK 0xFFF
2748#define INIT_IF_MODE_OP_RESERVED1_SHIFT 4
2749#define INIT_IF_MODE_OP_CMD_OFFSET_MASK 0xFFFF
2750#define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT 16
2751 __le16 reserved2;
2752 __le16 modes_buf_offset;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002753};
2754
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002755/* init operation: if_phase */
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002756struct init_if_phase_op {
2757 __le32 op_data;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002758#define INIT_IF_PHASE_OP_OP_MASK 0xF
2759#define INIT_IF_PHASE_OP_OP_SHIFT 0
2760#define INIT_IF_PHASE_OP_DMAE_ENABLE_MASK 0x1
2761#define INIT_IF_PHASE_OP_DMAE_ENABLE_SHIFT 4
2762#define INIT_IF_PHASE_OP_RESERVED1_MASK 0x7FF
2763#define INIT_IF_PHASE_OP_RESERVED1_SHIFT 5
2764#define INIT_IF_PHASE_OP_CMD_OFFSET_MASK 0xFFFF
2765#define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT 16
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002766 __le32 phase_data;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002767#define INIT_IF_PHASE_OP_PHASE_MASK 0xFF
2768#define INIT_IF_PHASE_OP_PHASE_SHIFT 0
2769#define INIT_IF_PHASE_OP_RESERVED2_MASK 0xFF
2770#define INIT_IF_PHASE_OP_RESERVED2_SHIFT 8
2771#define INIT_IF_PHASE_OP_PHASE_ID_MASK 0xFFFF
2772#define INIT_IF_PHASE_OP_PHASE_ID_SHIFT 16
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002773};
2774
2775/* init mode operators */
2776enum init_mode_ops {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002777 INIT_MODE_OP_NOT,
2778 INIT_MODE_OP_OR,
2779 INIT_MODE_OP_AND,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002780 MAX_INIT_MODE_OPS
2781};
2782
2783/* init operation: raw */
2784struct init_raw_op {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002785 __le32 op_data;
2786#define INIT_RAW_OP_OP_MASK 0xF
2787#define INIT_RAW_OP_OP_SHIFT 0
2788#define INIT_RAW_OP_PARAM1_MASK 0xFFFFFFF
2789#define INIT_RAW_OP_PARAM1_SHIFT 4
2790 __le32 param2;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002791};
2792
2793/* init array params */
2794struct init_op_array_params {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002795 __le16 size;
2796 __le16 offset;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002797};
2798
2799/* Write init operation arguments */
2800union init_write_args {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002801 __le32 inline_val;
2802 __le32 zeros_count;
2803 __le32 array_offset;
2804 struct init_op_array_params runtime;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002805};
2806
2807/* init operation: write */
2808struct init_write_op {
2809 __le32 data;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002810#define INIT_WRITE_OP_OP_MASK 0xF
2811#define INIT_WRITE_OP_OP_SHIFT 0
2812#define INIT_WRITE_OP_SOURCE_MASK 0x7
2813#define INIT_WRITE_OP_SOURCE_SHIFT 4
2814#define INIT_WRITE_OP_RESERVED_MASK 0x1
2815#define INIT_WRITE_OP_RESERVED_SHIFT 7
2816#define INIT_WRITE_OP_WIDE_BUS_MASK 0x1
2817#define INIT_WRITE_OP_WIDE_BUS_SHIFT 8
2818#define INIT_WRITE_OP_ADDRESS_MASK 0x7FFFFF
2819#define INIT_WRITE_OP_ADDRESS_SHIFT 9
2820 union init_write_args args;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002821};
2822
2823/* init operation: read */
2824struct init_read_op {
2825 __le32 op_data;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002826#define INIT_READ_OP_OP_MASK 0xF
2827#define INIT_READ_OP_OP_SHIFT 0
2828#define INIT_READ_OP_POLL_TYPE_MASK 0xF
2829#define INIT_READ_OP_POLL_TYPE_SHIFT 4
2830#define INIT_READ_OP_RESERVED_MASK 0x1
2831#define INIT_READ_OP_RESERVED_SHIFT 8
2832#define INIT_READ_OP_ADDRESS_MASK 0x7FFFFF
2833#define INIT_READ_OP_ADDRESS_SHIFT 9
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002834 __le32 expected_val;
2835};
2836
2837/* Init operations union */
2838union init_op {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002839 struct init_raw_op raw;
2840 struct init_write_op write;
2841 struct init_read_op read;
2842 struct init_if_mode_op if_mode;
2843 struct init_if_phase_op if_phase;
2844 struct init_callback_op callback;
2845 struct init_delay_op delay;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002846};
2847
2848/* Init command operation types */
2849enum init_op_types {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002850 INIT_OP_READ,
2851 INIT_OP_WRITE,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002852 INIT_OP_IF_MODE,
2853 INIT_OP_IF_PHASE,
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002854 INIT_OP_DELAY,
2855 INIT_OP_CALLBACK,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002856 MAX_INIT_OP_TYPES
2857};
2858
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002859/* init polling types */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002860enum init_poll_types {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002861 INIT_POLL_NONE,
2862 INIT_POLL_EQ,
2863 INIT_POLL_OR,
2864 INIT_POLL_AND,
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002865 MAX_INIT_POLL_TYPES
2866};
2867
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002868/* init source types */
2869enum init_source_types {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002870 INIT_SRC_INLINE,
2871 INIT_SRC_ZEROS,
2872 INIT_SRC_ARRAY,
2873 INIT_SRC_RUNTIME,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002874 MAX_INIT_SOURCE_TYPES
2875};
2876
2877/* Internal RAM Offsets macro data */
2878struct iro {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002879 __le32 base;
2880 __le16 m1;
2881 __le16 m2;
2882 __le16 m3;
2883 __le16 size;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002884};
2885
Tomer Tayarc965db42016-09-07 16:36:24 +03002886/***************************** Public Functions *******************************/
Tomer Tayara2e76992017-12-27 19:30:05 +02002887
Yuval Mintz351a4ded2016-06-02 10:23:29 +03002888/**
Tomer Tayarc965db42016-09-07 16:36:24 +03002889 * @brief qed_dbg_set_bin_ptr - Sets a pointer to the binary data with debug
2890 * arrays.
2891 *
2892 * @param bin_ptr - a pointer to the binary data with debug arrays.
2893 */
2894enum dbg_status qed_dbg_set_bin_ptr(const u8 * const bin_ptr);
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03002895
Tomer Tayarc965db42016-09-07 16:36:24 +03002896/**
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02002897 * @brief qed_dbg_grc_set_params_default - Reverts all GRC parameters to their
2898 * default value.
2899 *
2900 * @param p_hwfn - HW device data
2901 */
2902void qed_dbg_grc_set_params_default(struct qed_hwfn *p_hwfn);
2903/**
Tomer Tayarc965db42016-09-07 16:36:24 +03002904 * @brief qed_dbg_grc_get_dump_buf_size - Returns the required buffer size for
2905 * GRC Dump.
2906 *
2907 * @param p_hwfn - HW device data
2908 * @param p_ptt - Ptt window used for writing the registers.
2909 * @param buf_size - OUT: required buffer size (in dwords) for the GRC Dump
2910 * data.
2911 *
2912 * @return error if one of the following holds:
2913 * - the version wasn't set
2914 * Otherwise, returns ok.
2915 */
2916enum dbg_status qed_dbg_grc_get_dump_buf_size(struct qed_hwfn *p_hwfn,
2917 struct qed_ptt *p_ptt,
2918 u32 *buf_size);
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03002919
Tomer Tayarc965db42016-09-07 16:36:24 +03002920/**
2921 * @brief qed_dbg_grc_dump - Dumps GRC data into the specified buffer.
2922 *
2923 * @param p_hwfn - HW device data
2924 * @param p_ptt - Ptt window used for writing the registers.
2925 * @param dump_buf - Pointer to write the collected GRC data into.
2926 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
2927 * @param num_dumped_dwords - OUT: number of dumped dwords.
2928 *
2929 * @return error if one of the following holds:
2930 * - the version wasn't set
2931 * - the specified dump buffer is too small
2932 * Otherwise, returns ok.
2933 */
2934enum dbg_status qed_dbg_grc_dump(struct qed_hwfn *p_hwfn,
2935 struct qed_ptt *p_ptt,
2936 u32 *dump_buf,
2937 u32 buf_size_in_dwords,
2938 u32 *num_dumped_dwords);
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03002939
Tomer Tayarc965db42016-09-07 16:36:24 +03002940/**
2941 * @brief qed_dbg_idle_chk_get_dump_buf_size - Returns the required buffer size
2942 * for idle check results.
2943 *
2944 * @param p_hwfn - HW device data
2945 * @param p_ptt - Ptt window used for writing the registers.
2946 * @param buf_size - OUT: required buffer size (in dwords) for the idle check
2947 * data.
2948 *
2949 * @return error if one of the following holds:
2950 * - the version wasn't set
2951 * Otherwise, returns ok.
2952 */
2953enum dbg_status qed_dbg_idle_chk_get_dump_buf_size(struct qed_hwfn *p_hwfn,
2954 struct qed_ptt *p_ptt,
2955 u32 *buf_size);
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03002956
Tomer Tayarc965db42016-09-07 16:36:24 +03002957/**
2958 * @brief qed_dbg_idle_chk_dump - Performs idle check and writes the results
2959 * into the specified buffer.
2960 *
2961 * @param p_hwfn - HW device data
2962 * @param p_ptt - Ptt window used for writing the registers.
2963 * @param dump_buf - Pointer to write the idle check data into.
2964 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
2965 * @param num_dumped_dwords - OUT: number of dumped dwords.
2966 *
2967 * @return error if one of the following holds:
2968 * - the version wasn't set
2969 * - the specified buffer is too small
2970 * Otherwise, returns ok.
2971 */
2972enum dbg_status qed_dbg_idle_chk_dump(struct qed_hwfn *p_hwfn,
2973 struct qed_ptt *p_ptt,
2974 u32 *dump_buf,
2975 u32 buf_size_in_dwords,
2976 u32 *num_dumped_dwords);
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03002977
Tomer Tayarc965db42016-09-07 16:36:24 +03002978/**
2979 * @brief qed_dbg_mcp_trace_get_dump_buf_size - Returns the required buffer size
2980 * for mcp trace results.
2981 *
2982 * @param p_hwfn - HW device data
2983 * @param p_ptt - Ptt window used for writing the registers.
2984 * @param buf_size - OUT: required buffer size (in dwords) for mcp trace data.
2985 *
2986 * @return error if one of the following holds:
2987 * - the version wasn't set
2988 * - the trace data in MCP scratchpad contain an invalid signature
2989 * - the bundle ID in NVRAM is invalid
2990 * - the trace meta data cannot be found (in NVRAM or image file)
2991 * Otherwise, returns ok.
2992 */
2993enum dbg_status qed_dbg_mcp_trace_get_dump_buf_size(struct qed_hwfn *p_hwfn,
2994 struct qed_ptt *p_ptt,
2995 u32 *buf_size);
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03002996
Tomer Tayarc965db42016-09-07 16:36:24 +03002997/**
2998 * @brief qed_dbg_mcp_trace_dump - Performs mcp trace and writes the results
2999 * into the specified buffer.
3000 *
3001 * @param p_hwfn - HW device data
3002 * @param p_ptt - Ptt window used for writing the registers.
3003 * @param dump_buf - Pointer to write the mcp trace data into.
3004 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3005 * @param num_dumped_dwords - OUT: number of dumped dwords.
3006 *
3007 * @return error if one of the following holds:
3008 * - the version wasn't set
3009 * - the specified buffer is too small
3010 * - the trace data in MCP scratchpad contain an invalid signature
3011 * - the bundle ID in NVRAM is invalid
3012 * - the trace meta data cannot be found (in NVRAM or image file)
3013 * - the trace meta data cannot be read (from NVRAM or image file)
3014 * Otherwise, returns ok.
3015 */
3016enum dbg_status qed_dbg_mcp_trace_dump(struct qed_hwfn *p_hwfn,
3017 struct qed_ptt *p_ptt,
3018 u32 *dump_buf,
3019 u32 buf_size_in_dwords,
3020 u32 *num_dumped_dwords);
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03003021
Tomer Tayarc965db42016-09-07 16:36:24 +03003022/**
3023 * @brief qed_dbg_reg_fifo_get_dump_buf_size - Returns the required buffer size
3024 * for grc trace fifo results.
3025 *
3026 * @param p_hwfn - HW device data
3027 * @param p_ptt - Ptt window used for writing the registers.
3028 * @param buf_size - OUT: required buffer size (in dwords) for reg fifo data.
3029 *
3030 * @return error if one of the following holds:
3031 * - the version wasn't set
3032 * Otherwise, returns ok.
3033 */
3034enum dbg_status qed_dbg_reg_fifo_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3035 struct qed_ptt *p_ptt,
3036 u32 *buf_size);
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03003037
Tomer Tayarc965db42016-09-07 16:36:24 +03003038/**
3039 * @brief qed_dbg_reg_fifo_dump - Reads the reg fifo and writes the results into
3040 * the specified buffer.
3041 *
3042 * @param p_hwfn - HW device data
3043 * @param p_ptt - Ptt window used for writing the registers.
3044 * @param dump_buf - Pointer to write the reg fifo data into.
3045 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3046 * @param num_dumped_dwords - OUT: number of dumped dwords.
3047 *
3048 * @return error if one of the following holds:
3049 * - the version wasn't set
3050 * - the specified buffer is too small
3051 * - DMAE transaction failed
3052 * Otherwise, returns ok.
3053 */
3054enum dbg_status qed_dbg_reg_fifo_dump(struct qed_hwfn *p_hwfn,
3055 struct qed_ptt *p_ptt,
3056 u32 *dump_buf,
3057 u32 buf_size_in_dwords,
3058 u32 *num_dumped_dwords);
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03003059
Tomer Tayarc965db42016-09-07 16:36:24 +03003060/**
3061 * @brief qed_dbg_igu_fifo_get_dump_buf_size - Returns the required buffer size
3062 * for the IGU fifo results.
3063 *
3064 * @param p_hwfn - HW device data
3065 * @param p_ptt - Ptt window used for writing the registers.
3066 * @param buf_size - OUT: required buffer size (in dwords) for the IGU fifo
3067 * data.
3068 *
3069 * @return error if one of the following holds:
3070 * - the version wasn't set
3071 * Otherwise, returns ok.
3072 */
3073enum dbg_status qed_dbg_igu_fifo_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3074 struct qed_ptt *p_ptt,
3075 u32 *buf_size);
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03003076
Tomer Tayarc965db42016-09-07 16:36:24 +03003077/**
3078 * @brief qed_dbg_igu_fifo_dump - Reads the IGU fifo and writes the results into
3079 * the specified buffer.
3080 *
3081 * @param p_hwfn - HW device data
3082 * @param p_ptt - Ptt window used for writing the registers.
3083 * @param dump_buf - Pointer to write the IGU fifo data into.
3084 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3085 * @param num_dumped_dwords - OUT: number of dumped dwords.
3086 *
3087 * @return error if one of the following holds:
3088 * - the version wasn't set
3089 * - the specified buffer is too small
3090 * - DMAE transaction failed
3091 * Otherwise, returns ok.
3092 */
3093enum dbg_status qed_dbg_igu_fifo_dump(struct qed_hwfn *p_hwfn,
3094 struct qed_ptt *p_ptt,
3095 u32 *dump_buf,
3096 u32 buf_size_in_dwords,
3097 u32 *num_dumped_dwords);
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03003098
Tomer Tayarc965db42016-09-07 16:36:24 +03003099/**
3100 * @brief qed_dbg_protection_override_get_dump_buf_size - Returns the required
3101 * buffer size for protection override window results.
3102 *
3103 * @param p_hwfn - HW device data
3104 * @param p_ptt - Ptt window used for writing the registers.
3105 * @param buf_size - OUT: required buffer size (in dwords) for protection
3106 * override data.
3107 *
3108 * @return error if one of the following holds:
3109 * - the version wasn't set
3110 * Otherwise, returns ok.
3111 */
3112enum dbg_status
3113qed_dbg_protection_override_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3114 struct qed_ptt *p_ptt,
3115 u32 *buf_size);
3116/**
3117 * @brief qed_dbg_protection_override_dump - Reads protection override window
3118 * entries and writes the results into the specified buffer.
3119 *
3120 * @param p_hwfn - HW device data
3121 * @param p_ptt - Ptt window used for writing the registers.
3122 * @param dump_buf - Pointer to write the protection override data into.
3123 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3124 * @param num_dumped_dwords - OUT: number of dumped dwords.
3125 *
3126 * @return error if one of the following holds:
3127 * - the version wasn't set
3128 * - the specified buffer is too small
3129 * - DMAE transaction failed
3130 * Otherwise, returns ok.
3131 */
3132enum dbg_status qed_dbg_protection_override_dump(struct qed_hwfn *p_hwfn,
3133 struct qed_ptt *p_ptt,
3134 u32 *dump_buf,
3135 u32 buf_size_in_dwords,
3136 u32 *num_dumped_dwords);
3137/**
3138 * @brief qed_dbg_fw_asserts_get_dump_buf_size - Returns the required buffer
3139 * size for FW Asserts results.
3140 *
3141 * @param p_hwfn - HW device data
3142 * @param p_ptt - Ptt window used for writing the registers.
3143 * @param buf_size - OUT: required buffer size (in dwords) for FW Asserts data.
3144 *
3145 * @return error if one of the following holds:
3146 * - the version wasn't set
3147 * Otherwise, returns ok.
3148 */
3149enum dbg_status qed_dbg_fw_asserts_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3150 struct qed_ptt *p_ptt,
3151 u32 *buf_size);
3152/**
3153 * @brief qed_dbg_fw_asserts_dump - Reads the FW Asserts and writes the results
3154 * into the specified buffer.
3155 *
3156 * @param p_hwfn - HW device data
3157 * @param p_ptt - Ptt window used for writing the registers.
3158 * @param dump_buf - Pointer to write the FW Asserts data into.
3159 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3160 * @param num_dumped_dwords - OUT: number of dumped dwords.
3161 *
3162 * @return error if one of the following holds:
3163 * - the version wasn't set
3164 * - the specified buffer is too small
3165 * Otherwise, returns ok.
3166 */
3167enum dbg_status qed_dbg_fw_asserts_dump(struct qed_hwfn *p_hwfn,
3168 struct qed_ptt *p_ptt,
3169 u32 *dump_buf,
3170 u32 buf_size_in_dwords,
3171 u32 *num_dumped_dwords);
Mintz, Yuval0ebbd1c2017-05-29 09:53:10 +03003172
3173/**
3174 * @brief qed_dbg_read_attn - Reads the attention registers of the specified
3175 * block and type, and writes the results into the specified buffer.
3176 *
3177 * @param p_hwfn - HW device data
3178 * @param p_ptt - Ptt window used for writing the registers.
3179 * @param block - Block ID.
3180 * @param attn_type - Attention type.
3181 * @param clear_status - Indicates if the attention status should be cleared.
3182 * @param results - OUT: Pointer to write the read results into
3183 *
3184 * @return error if one of the following holds:
3185 * - the version wasn't set
3186 * Otherwise, returns ok.
3187 */
3188enum dbg_status qed_dbg_read_attn(struct qed_hwfn *p_hwfn,
3189 struct qed_ptt *p_ptt,
3190 enum block_id block,
3191 enum dbg_attn_type attn_type,
3192 bool clear_status,
3193 struct dbg_attn_block_result *results);
3194
Tomer Tayarc965db42016-09-07 16:36:24 +03003195/**
3196 * @brief qed_dbg_print_attn - Prints attention registers values in the
3197 * specified results struct.
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003198 *
3199 * @param p_hwfn
3200 * @param results - Pointer to the attention read results
3201 *
3202 * @return error if one of the following holds:
3203 * - the version wasn't set
3204 * Otherwise, returns ok.
3205 */
3206enum dbg_status qed_dbg_print_attn(struct qed_hwfn *p_hwfn,
3207 struct dbg_attn_block_result *results);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003208
Tomer Tayarc965db42016-09-07 16:36:24 +03003209/******************************** Constants **********************************/
3210
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003211#define MAX_NAME_LEN 16
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003212
Tomer Tayarc965db42016-09-07 16:36:24 +03003213/***************************** Public Functions *******************************/
Tomer Tayara2e76992017-12-27 19:30:05 +02003214
Tomer Tayarc965db42016-09-07 16:36:24 +03003215/**
3216 * @brief qed_dbg_user_set_bin_ptr - Sets a pointer to the binary data with
3217 * debug arrays.
3218 *
3219 * @param bin_ptr - a pointer to the binary data with debug arrays.
3220 */
3221enum dbg_status qed_dbg_user_set_bin_ptr(const u8 * const bin_ptr);
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03003222
Tomer Tayarc965db42016-09-07 16:36:24 +03003223/**
3224 * @brief qed_dbg_get_status_str - Returns a string for the specified status.
3225 *
3226 * @param status - a debug status code.
3227 *
3228 * @return a string for the specified status
3229 */
3230const char *qed_dbg_get_status_str(enum dbg_status status);
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03003231
Tomer Tayarc965db42016-09-07 16:36:24 +03003232/**
3233 * @brief qed_get_idle_chk_results_buf_size - Returns the required buffer size
3234 * for idle check results (in bytes).
3235 *
3236 * @param p_hwfn - HW device data
3237 * @param dump_buf - idle check dump buffer.
3238 * @param num_dumped_dwords - number of dwords that were dumped.
3239 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3240 * results.
3241 *
3242 * @return error if the parsing fails, ok otherwise.
3243 */
3244enum dbg_status qed_get_idle_chk_results_buf_size(struct qed_hwfn *p_hwfn,
3245 u32 *dump_buf,
3246 u32 num_dumped_dwords,
3247 u32 *results_buf_size);
3248/**
3249 * @brief qed_print_idle_chk_results - Prints idle check results
3250 *
3251 * @param p_hwfn - HW device data
3252 * @param dump_buf - idle check dump buffer.
3253 * @param num_dumped_dwords - number of dwords that were dumped.
3254 * @param results_buf - buffer for printing the idle check results.
3255 * @param num_errors - OUT: number of errors found in idle check.
3256 * @param num_warnings - OUT: number of warnings found in idle check.
3257 *
3258 * @return error if the parsing fails, ok otherwise.
3259 */
3260enum dbg_status qed_print_idle_chk_results(struct qed_hwfn *p_hwfn,
3261 u32 *dump_buf,
3262 u32 num_dumped_dwords,
3263 char *results_buf,
3264 u32 *num_errors,
3265 u32 *num_warnings);
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03003266
Tomer Tayarc965db42016-09-07 16:36:24 +03003267/**
3268 * @brief qed_get_mcp_trace_results_buf_size - Returns the required buffer size
3269 * for MCP Trace results (in bytes).
3270 *
3271 * @param p_hwfn - HW device data
3272 * @param dump_buf - MCP Trace dump buffer.
3273 * @param num_dumped_dwords - number of dwords that were dumped.
3274 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3275 * results.
3276 *
3277 * @return error if the parsing fails, ok otherwise.
3278 */
3279enum dbg_status qed_get_mcp_trace_results_buf_size(struct qed_hwfn *p_hwfn,
3280 u32 *dump_buf,
3281 u32 num_dumped_dwords,
3282 u32 *results_buf_size);
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03003283
Tomer Tayarc965db42016-09-07 16:36:24 +03003284/**
3285 * @brief qed_print_mcp_trace_results - Prints MCP Trace results
3286 *
3287 * @param p_hwfn - HW device data
3288 * @param dump_buf - mcp trace dump buffer, starting from the header.
3289 * @param num_dumped_dwords - number of dwords that were dumped.
3290 * @param results_buf - buffer for printing the mcp trace results.
3291 *
3292 * @return error if the parsing fails, ok otherwise.
3293 */
3294enum dbg_status qed_print_mcp_trace_results(struct qed_hwfn *p_hwfn,
3295 u32 *dump_buf,
3296 u32 num_dumped_dwords,
3297 char *results_buf);
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03003298
Tomer Tayarc965db42016-09-07 16:36:24 +03003299/**
3300 * @brief qed_get_reg_fifo_results_buf_size - Returns the required buffer size
3301 * for reg_fifo results (in bytes).
3302 *
3303 * @param p_hwfn - HW device data
3304 * @param dump_buf - reg fifo dump buffer.
3305 * @param num_dumped_dwords - number of dwords that were dumped.
3306 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3307 * results.
3308 *
3309 * @return error if the parsing fails, ok otherwise.
3310 */
3311enum dbg_status qed_get_reg_fifo_results_buf_size(struct qed_hwfn *p_hwfn,
3312 u32 *dump_buf,
3313 u32 num_dumped_dwords,
3314 u32 *results_buf_size);
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03003315
Tomer Tayarc965db42016-09-07 16:36:24 +03003316/**
3317 * @brief qed_print_reg_fifo_results - Prints reg fifo results
3318 *
3319 * @param p_hwfn - HW device data
3320 * @param dump_buf - reg fifo dump buffer, starting from the header.
3321 * @param num_dumped_dwords - number of dwords that were dumped.
3322 * @param results_buf - buffer for printing the reg fifo results.
3323 *
3324 * @return error if the parsing fails, ok otherwise.
3325 */
3326enum dbg_status qed_print_reg_fifo_results(struct qed_hwfn *p_hwfn,
3327 u32 *dump_buf,
3328 u32 num_dumped_dwords,
3329 char *results_buf);
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03003330
Tomer Tayarc965db42016-09-07 16:36:24 +03003331/**
3332 * @brief qed_get_igu_fifo_results_buf_size - Returns the required buffer size
3333 * for igu_fifo results (in bytes).
3334 *
3335 * @param p_hwfn - HW device data
3336 * @param dump_buf - IGU fifo dump buffer.
3337 * @param num_dumped_dwords - number of dwords that were dumped.
3338 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3339 * results.
3340 *
3341 * @return error if the parsing fails, ok otherwise.
3342 */
3343enum dbg_status qed_get_igu_fifo_results_buf_size(struct qed_hwfn *p_hwfn,
3344 u32 *dump_buf,
3345 u32 num_dumped_dwords,
3346 u32 *results_buf_size);
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03003347
Tomer Tayarc965db42016-09-07 16:36:24 +03003348/**
3349 * @brief qed_print_igu_fifo_results - Prints IGU fifo results
3350 *
3351 * @param p_hwfn - HW device data
3352 * @param dump_buf - IGU fifo dump buffer, starting from the header.
3353 * @param num_dumped_dwords - number of dwords that were dumped.
3354 * @param results_buf - buffer for printing the IGU fifo results.
3355 *
3356 * @return error if the parsing fails, ok otherwise.
3357 */
3358enum dbg_status qed_print_igu_fifo_results(struct qed_hwfn *p_hwfn,
3359 u32 *dump_buf,
3360 u32 num_dumped_dwords,
3361 char *results_buf);
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03003362
Tomer Tayarc965db42016-09-07 16:36:24 +03003363/**
3364 * @brief qed_get_protection_override_results_buf_size - Returns the required
3365 * buffer size for protection override results (in bytes).
3366 *
3367 * @param p_hwfn - HW device data
3368 * @param dump_buf - protection override dump buffer.
3369 * @param num_dumped_dwords - number of dwords that were dumped.
3370 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3371 * results.
3372 *
3373 * @return error if the parsing fails, ok otherwise.
3374 */
3375enum dbg_status
3376qed_get_protection_override_results_buf_size(struct qed_hwfn *p_hwfn,
3377 u32 *dump_buf,
3378 u32 num_dumped_dwords,
3379 u32 *results_buf_size);
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03003380
Tomer Tayarc965db42016-09-07 16:36:24 +03003381/**
3382 * @brief qed_print_protection_override_results - Prints protection override
3383 * results.
3384 *
3385 * @param p_hwfn - HW device data
3386 * @param dump_buf - protection override dump buffer, starting from the header.
3387 * @param num_dumped_dwords - number of dwords that were dumped.
3388 * @param results_buf - buffer for printing the reg fifo results.
3389 *
3390 * @return error if the parsing fails, ok otherwise.
3391 */
3392enum dbg_status qed_print_protection_override_results(struct qed_hwfn *p_hwfn,
3393 u32 *dump_buf,
3394 u32 num_dumped_dwords,
3395 char *results_buf);
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03003396
Tomer Tayarc965db42016-09-07 16:36:24 +03003397/**
3398 * @brief qed_get_fw_asserts_results_buf_size - Returns the required buffer size
3399 * for FW Asserts results (in bytes).
3400 *
3401 * @param p_hwfn - HW device data
3402 * @param dump_buf - FW Asserts dump buffer.
3403 * @param num_dumped_dwords - number of dwords that were dumped.
3404 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3405 * results.
3406 *
3407 * @return error if the parsing fails, ok otherwise.
3408 */
3409enum dbg_status qed_get_fw_asserts_results_buf_size(struct qed_hwfn *p_hwfn,
3410 u32 *dump_buf,
3411 u32 num_dumped_dwords,
3412 u32 *results_buf_size);
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03003413
Tomer Tayarc965db42016-09-07 16:36:24 +03003414/**
3415 * @brief qed_print_fw_asserts_results - Prints FW Asserts results
3416 *
3417 * @param p_hwfn - HW device data
3418 * @param dump_buf - FW Asserts dump buffer, starting from the header.
3419 * @param num_dumped_dwords - number of dwords that were dumped.
3420 * @param results_buf - buffer for printing the FW Asserts results.
3421 *
3422 * @return error if the parsing fails, ok otherwise.
3423 */
3424enum dbg_status qed_print_fw_asserts_results(struct qed_hwfn *p_hwfn,
3425 u32 *dump_buf,
3426 u32 num_dumped_dwords,
3427 char *results_buf);
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03003428
Mintz, Yuval0ebbd1c2017-05-29 09:53:10 +03003429/**
3430 * @brief qed_dbg_parse_attn - Parses and prints attention registers values in
3431 * the specified results struct.
3432 *
3433 * @param p_hwfn - HW device data
3434 * @param results - Pointer to the attention read results
3435 *
3436 * @return error if one of the following holds:
3437 * - the version wasn't set
3438 * Otherwise, returns ok.
3439 */
3440enum dbg_status qed_dbg_parse_attn(struct qed_hwfn *p_hwfn,
3441 struct dbg_attn_block_result *results);
3442
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03003443/* Debug Bus blocks */
3444static const u32 dbg_bus_blocks[] = {
3445 0x0000000f, /* grc, bb, 15 lines */
3446 0x0000000f, /* grc, k2, 15 lines */
3447 0x00000000,
3448 0x00000000, /* miscs, bb, 0 lines */
3449 0x00000000, /* miscs, k2, 0 lines */
3450 0x00000000,
3451 0x00000000, /* misc, bb, 0 lines */
3452 0x00000000, /* misc, k2, 0 lines */
3453 0x00000000,
3454 0x00000000, /* dbu, bb, 0 lines */
3455 0x00000000, /* dbu, k2, 0 lines */
3456 0x00000000,
3457 0x000f0127, /* pglue_b, bb, 39 lines */
3458 0x0036012a, /* pglue_b, k2, 42 lines */
3459 0x00000000,
3460 0x00000000, /* cnig, bb, 0 lines */
3461 0x00120102, /* cnig, k2, 2 lines */
3462 0x00000000,
3463 0x00000000, /* cpmu, bb, 0 lines */
3464 0x00000000, /* cpmu, k2, 0 lines */
3465 0x00000000,
3466 0x00000001, /* ncsi, bb, 1 lines */
3467 0x00000001, /* ncsi, k2, 1 lines */
3468 0x00000000,
3469 0x00000000, /* opte, bb, 0 lines */
3470 0x00000000, /* opte, k2, 0 lines */
3471 0x00000000,
3472 0x00600085, /* bmb, bb, 133 lines */
3473 0x00600085, /* bmb, k2, 133 lines */
3474 0x00000000,
3475 0x00000000, /* pcie, bb, 0 lines */
3476 0x00e50033, /* pcie, k2, 51 lines */
3477 0x00000000,
3478 0x00000000, /* mcp, bb, 0 lines */
3479 0x00000000, /* mcp, k2, 0 lines */
3480 0x00000000,
3481 0x01180009, /* mcp2, bb, 9 lines */
3482 0x01180009, /* mcp2, k2, 9 lines */
3483 0x00000000,
3484 0x01210104, /* pswhst, bb, 4 lines */
3485 0x01210104, /* pswhst, k2, 4 lines */
3486 0x00000000,
3487 0x01250103, /* pswhst2, bb, 3 lines */
3488 0x01250103, /* pswhst2, k2, 3 lines */
3489 0x00000000,
3490 0x00340101, /* pswrd, bb, 1 lines */
3491 0x00340101, /* pswrd, k2, 1 lines */
3492 0x00000000,
3493 0x01280119, /* pswrd2, bb, 25 lines */
3494 0x01280119, /* pswrd2, k2, 25 lines */
3495 0x00000000,
3496 0x01410109, /* pswwr, bb, 9 lines */
3497 0x01410109, /* pswwr, k2, 9 lines */
3498 0x00000000,
3499 0x00000000, /* pswwr2, bb, 0 lines */
3500 0x00000000, /* pswwr2, k2, 0 lines */
3501 0x00000000,
3502 0x001c0001, /* pswrq, bb, 1 lines */
3503 0x001c0001, /* pswrq, k2, 1 lines */
3504 0x00000000,
3505 0x014a0015, /* pswrq2, bb, 21 lines */
3506 0x014a0015, /* pswrq2, k2, 21 lines */
3507 0x00000000,
3508 0x00000000, /* pglcs, bb, 0 lines */
3509 0x00120006, /* pglcs, k2, 6 lines */
3510 0x00000000,
3511 0x00100001, /* dmae, bb, 1 lines */
3512 0x00100001, /* dmae, k2, 1 lines */
3513 0x00000000,
3514 0x015f0105, /* ptu, bb, 5 lines */
3515 0x015f0105, /* ptu, k2, 5 lines */
3516 0x00000000,
3517 0x01640120, /* tcm, bb, 32 lines */
3518 0x01640120, /* tcm, k2, 32 lines */
3519 0x00000000,
3520 0x01640120, /* mcm, bb, 32 lines */
3521 0x01640120, /* mcm, k2, 32 lines */
3522 0x00000000,
3523 0x01640120, /* ucm, bb, 32 lines */
3524 0x01640120, /* ucm, k2, 32 lines */
3525 0x00000000,
3526 0x01640120, /* xcm, bb, 32 lines */
3527 0x01640120, /* xcm, k2, 32 lines */
3528 0x00000000,
3529 0x01640120, /* ycm, bb, 32 lines */
3530 0x01640120, /* ycm, k2, 32 lines */
3531 0x00000000,
3532 0x01640120, /* pcm, bb, 32 lines */
3533 0x01640120, /* pcm, k2, 32 lines */
3534 0x00000000,
3535 0x01840062, /* qm, bb, 98 lines */
3536 0x01840062, /* qm, k2, 98 lines */
3537 0x00000000,
3538 0x01e60021, /* tm, bb, 33 lines */
3539 0x01e60021, /* tm, k2, 33 lines */
3540 0x00000000,
3541 0x02070107, /* dorq, bb, 7 lines */
3542 0x02070107, /* dorq, k2, 7 lines */
3543 0x00000000,
3544 0x00600185, /* brb, bb, 133 lines */
3545 0x00600185, /* brb, k2, 133 lines */
3546 0x00000000,
3547 0x020e0019, /* src, bb, 25 lines */
3548 0x020c001a, /* src, k2, 26 lines */
3549 0x00000000,
3550 0x02270104, /* prs, bb, 4 lines */
3551 0x02270104, /* prs, k2, 4 lines */
3552 0x00000000,
3553 0x022b0133, /* tsdm, bb, 51 lines */
3554 0x022b0133, /* tsdm, k2, 51 lines */
3555 0x00000000,
3556 0x022b0133, /* msdm, bb, 51 lines */
3557 0x022b0133, /* msdm, k2, 51 lines */
3558 0x00000000,
3559 0x022b0133, /* usdm, bb, 51 lines */
3560 0x022b0133, /* usdm, k2, 51 lines */
3561 0x00000000,
3562 0x022b0133, /* xsdm, bb, 51 lines */
3563 0x022b0133, /* xsdm, k2, 51 lines */
3564 0x00000000,
3565 0x022b0133, /* ysdm, bb, 51 lines */
3566 0x022b0133, /* ysdm, k2, 51 lines */
3567 0x00000000,
3568 0x022b0133, /* psdm, bb, 51 lines */
3569 0x022b0133, /* psdm, k2, 51 lines */
3570 0x00000000,
3571 0x025e010c, /* tsem, bb, 12 lines */
3572 0x025e010c, /* tsem, k2, 12 lines */
3573 0x00000000,
3574 0x025e010c, /* msem, bb, 12 lines */
3575 0x025e010c, /* msem, k2, 12 lines */
3576 0x00000000,
3577 0x025e010c, /* usem, bb, 12 lines */
3578 0x025e010c, /* usem, k2, 12 lines */
3579 0x00000000,
3580 0x025e010c, /* xsem, bb, 12 lines */
3581 0x025e010c, /* xsem, k2, 12 lines */
3582 0x00000000,
3583 0x025e010c, /* ysem, bb, 12 lines */
3584 0x025e010c, /* ysem, k2, 12 lines */
3585 0x00000000,
3586 0x025e010c, /* psem, bb, 12 lines */
3587 0x025e010c, /* psem, k2, 12 lines */
3588 0x00000000,
3589 0x026a000d, /* rss, bb, 13 lines */
3590 0x026a000d, /* rss, k2, 13 lines */
3591 0x00000000,
3592 0x02770106, /* tmld, bb, 6 lines */
3593 0x02770106, /* tmld, k2, 6 lines */
3594 0x00000000,
3595 0x027d0106, /* muld, bb, 6 lines */
3596 0x027d0106, /* muld, k2, 6 lines */
3597 0x00000000,
3598 0x02770005, /* yuld, bb, 5 lines */
3599 0x02770005, /* yuld, k2, 5 lines */
3600 0x00000000,
3601 0x02830107, /* xyld, bb, 7 lines */
3602 0x027d0107, /* xyld, k2, 7 lines */
3603 0x00000000,
3604 0x00000000, /* ptld, bb, 0 lines */
3605 0x00000000, /* ptld, k2, 0 lines */
3606 0x00000000,
3607 0x00000000, /* ypld, bb, 0 lines */
3608 0x00000000, /* ypld, k2, 0 lines */
3609 0x00000000,
3610 0x028a010e, /* prm, bb, 14 lines */
3611 0x02980110, /* prm, k2, 16 lines */
3612 0x00000000,
3613 0x02a8000d, /* pbf_pb1, bb, 13 lines */
3614 0x02a8000d, /* pbf_pb1, k2, 13 lines */
3615 0x00000000,
3616 0x02a8000d, /* pbf_pb2, bb, 13 lines */
3617 0x02a8000d, /* pbf_pb2, k2, 13 lines */
3618 0x00000000,
3619 0x02a8000d, /* rpb, bb, 13 lines */
3620 0x02a8000d, /* rpb, k2, 13 lines */
3621 0x00000000,
3622 0x00600185, /* btb, bb, 133 lines */
3623 0x00600185, /* btb, k2, 133 lines */
3624 0x00000000,
3625 0x02b50117, /* pbf, bb, 23 lines */
3626 0x02b50117, /* pbf, k2, 23 lines */
3627 0x00000000,
3628 0x02cc0006, /* rdif, bb, 6 lines */
3629 0x02cc0006, /* rdif, k2, 6 lines */
3630 0x00000000,
3631 0x02d20006, /* tdif, bb, 6 lines */
3632 0x02d20006, /* tdif, k2, 6 lines */
3633 0x00000000,
3634 0x02d80003, /* cdu, bb, 3 lines */
3635 0x02db000e, /* cdu, k2, 14 lines */
3636 0x00000000,
3637 0x02e9010d, /* ccfc, bb, 13 lines */
3638 0x02f60117, /* ccfc, k2, 23 lines */
3639 0x00000000,
3640 0x02e9010d, /* tcfc, bb, 13 lines */
3641 0x02f60117, /* tcfc, k2, 23 lines */
3642 0x00000000,
3643 0x030d0133, /* igu, bb, 51 lines */
3644 0x030d0133, /* igu, k2, 51 lines */
3645 0x00000000,
3646 0x03400106, /* cau, bb, 6 lines */
3647 0x03400106, /* cau, k2, 6 lines */
3648 0x00000000,
3649 0x00000000, /* rgfs, bb, 0 lines */
3650 0x00000000, /* rgfs, k2, 0 lines */
3651 0x00000000,
3652 0x00000000, /* rgsrc, bb, 0 lines */
3653 0x00000000, /* rgsrc, k2, 0 lines */
3654 0x00000000,
3655 0x00000000, /* tgfs, bb, 0 lines */
3656 0x00000000, /* tgfs, k2, 0 lines */
3657 0x00000000,
3658 0x00000000, /* tgsrc, bb, 0 lines */
3659 0x00000000, /* tgsrc, k2, 0 lines */
3660 0x00000000,
3661 0x00000000, /* umac, bb, 0 lines */
3662 0x00120006, /* umac, k2, 6 lines */
3663 0x00000000,
3664 0x00000000, /* xmac, bb, 0 lines */
3665 0x00000000, /* xmac, k2, 0 lines */
3666 0x00000000,
3667 0x00000000, /* dbg, bb, 0 lines */
3668 0x00000000, /* dbg, k2, 0 lines */
3669 0x00000000,
3670 0x0346012b, /* nig, bb, 43 lines */
3671 0x0346011d, /* nig, k2, 29 lines */
3672 0x00000000,
3673 0x00000000, /* wol, bb, 0 lines */
3674 0x001c0002, /* wol, k2, 2 lines */
3675 0x00000000,
3676 0x00000000, /* bmbn, bb, 0 lines */
3677 0x00210008, /* bmbn, k2, 8 lines */
3678 0x00000000,
3679 0x00000000, /* ipc, bb, 0 lines */
3680 0x00000000, /* ipc, k2, 0 lines */
3681 0x00000000,
3682 0x00000000, /* nwm, bb, 0 lines */
3683 0x0371000b, /* nwm, k2, 11 lines */
3684 0x00000000,
3685 0x00000000, /* nws, bb, 0 lines */
3686 0x037c0009, /* nws, k2, 9 lines */
3687 0x00000000,
3688 0x00000000, /* ms, bb, 0 lines */
3689 0x00120004, /* ms, k2, 4 lines */
3690 0x00000000,
3691 0x00000000, /* phy_pcie, bb, 0 lines */
3692 0x00e5001a, /* phy_pcie, k2, 26 lines */
3693 0x00000000,
3694 0x00000000, /* led, bb, 0 lines */
3695 0x00000000, /* led, k2, 0 lines */
3696 0x00000000,
3697 0x00000000, /* avs_wrap, bb, 0 lines */
3698 0x00000000, /* avs_wrap, k2, 0 lines */
3699 0x00000000,
3700 0x00000000, /* bar0_map, bb, 0 lines */
3701 0x00000000, /* bar0_map, k2, 0 lines */
3702 0x00000000,
3703};
3704
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003705/* Win 2 */
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003706#define GTT_BAR0_MAP_REG_IGU_CMD 0x00f000UL
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003707
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003708/* Win 3 */
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003709#define GTT_BAR0_MAP_REG_TSDM_RAM 0x010000UL
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003710
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003711/* Win 4 */
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003712#define GTT_BAR0_MAP_REG_MSDM_RAM 0x011000UL
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003713
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003714/* Win 5 */
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003715#define GTT_BAR0_MAP_REG_MSDM_RAM_1024 0x012000UL
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003716
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003717/* Win 6 */
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003718#define GTT_BAR0_MAP_REG_USDM_RAM 0x013000UL
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003719
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003720/* Win 7 */
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003721#define GTT_BAR0_MAP_REG_USDM_RAM_1024 0x014000UL
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003722
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003723/* Win 8 */
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003724#define GTT_BAR0_MAP_REG_USDM_RAM_2048 0x015000UL
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003725
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003726/* Win 9 */
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003727#define GTT_BAR0_MAP_REG_XSDM_RAM 0x016000UL
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003728
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003729/* Win 10 */
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003730#define GTT_BAR0_MAP_REG_YSDM_RAM 0x017000UL
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003731
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003732/* Win 11 */
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003733#define GTT_BAR0_MAP_REG_PSDM_RAM 0x018000UL
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003734
3735/**
3736 * @brief qed_qm_pf_mem_size - prepare QM ILT sizes
3737 *
3738 * Returns the required host memory size in 4KB units.
3739 * Must be called before all QM init HSI functions.
3740 *
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003741 * @param pf_id - physical function ID
3742 * @param num_pf_cids - number of connections used by this PF
3743 * @param num_vf_cids - number of connections used by VFs of this PF
3744 * @param num_tids - number of tasks used by this PF
3745 * @param num_pf_pqs - number of PQs used by this PF
3746 * @param num_vf_pqs - number of PQs used by VFs of this PF
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003747 *
3748 * @return The required host memory size in 4KB units.
3749 */
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003750u32 qed_qm_pf_mem_size(u8 pf_id,
3751 u32 num_pf_cids,
3752 u32 num_vf_cids,
3753 u32 num_tids, u16 num_pf_pqs, u16 num_vf_pqs);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003754
3755struct qed_qm_common_rt_init_params {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003756 u8 max_ports_per_engine;
3757 u8 max_phys_tcs_per_port;
3758 bool pf_rl_en;
3759 bool pf_wfq_en;
3760 bool vport_rl_en;
3761 bool vport_wfq_en;
3762 struct init_qm_port_params *port_params;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003763};
3764
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003765int qed_qm_common_rt_init(struct qed_hwfn *p_hwfn,
3766 struct qed_qm_common_rt_init_params *p_params);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003767
3768struct qed_qm_pf_rt_init_params {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003769 u8 port_id;
3770 u8 pf_id;
3771 u8 max_phys_tcs_per_port;
3772 bool is_first_pf;
3773 u32 num_pf_cids;
3774 u32 num_vf_cids;
3775 u32 num_tids;
3776 u16 start_pq;
3777 u16 num_pf_pqs;
3778 u16 num_vf_pqs;
3779 u8 start_vport;
3780 u8 num_vports;
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003781 u16 pf_wfq;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003782 u32 pf_rl;
3783 struct init_qm_pq_params *pq_params;
3784 struct init_qm_vport_params *vport_params;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003785};
3786
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003787int qed_qm_pf_rt_init(struct qed_hwfn *p_hwfn,
3788 struct qed_ptt *p_ptt,
3789 struct qed_qm_pf_rt_init_params *p_params);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003790
3791/**
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003792 * @brief qed_init_pf_wfq - Initializes the WFQ weight of the specified PF
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003793 *
3794 * @param p_hwfn
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003795 * @param p_ptt - ptt window used for writing the registers
3796 * @param pf_id - PF ID
3797 * @param pf_wfq - WFQ weight. Must be non-zero.
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003798 *
3799 * @return 0 on success, -1 on error.
3800 */
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003801int qed_init_pf_wfq(struct qed_hwfn *p_hwfn,
3802 struct qed_ptt *p_ptt, u8 pf_id, u16 pf_wfq);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003803
3804/**
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003805 * @brief qed_init_pf_rl - Initializes the rate limit of the specified PF
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003806 *
3807 * @param p_hwfn
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003808 * @param p_ptt - ptt window used for writing the registers
3809 * @param pf_id - PF ID
3810 * @param pf_rl - rate limit in Mb/sec units
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003811 *
3812 * @return 0 on success, -1 on error.
3813 */
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003814int qed_init_pf_rl(struct qed_hwfn *p_hwfn,
3815 struct qed_ptt *p_ptt, u8 pf_id, u32 pf_rl);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003816
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003817/**
3818 * @brief qed_init_vport_wfq Initializes the WFQ weight of the specified VPORT
3819 *
3820 * @param p_hwfn
3821 * @param p_ptt - ptt window used for writing the registers
3822 * @param first_tx_pq_id- An array containing the first Tx PQ ID associated
3823 * with the VPORT for each TC. This array is filled by
3824 * qed_qm_pf_rt_init
3825 * @param vport_wfq - WFQ weight. Must be non-zero.
3826 *
3827 * @return 0 on success, -1 on error.
3828 */
3829int qed_init_vport_wfq(struct qed_hwfn *p_hwfn,
3830 struct qed_ptt *p_ptt,
3831 u16 first_tx_pq_id[NUM_OF_TCS], u16 vport_wfq);
3832
3833/**
3834 * @brief qed_init_vport_rl - Initializes the rate limit of the specified VPORT
3835 *
3836 * @param p_hwfn
3837 * @param p_ptt - ptt window used for writing the registers
3838 * @param vport_id - VPORT ID
3839 * @param vport_rl - rate limit in Mb/sec units
3840 *
3841 * @return 0 on success, -1 on error.
3842 */
3843int qed_init_vport_rl(struct qed_hwfn *p_hwfn,
3844 struct qed_ptt *p_ptt, u8 vport_id, u32 vport_rl);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003845/**
3846 * @brief qed_send_qm_stop_cmd Sends a stop command to the QM
3847 *
3848 * @param p_hwfn
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003849 * @param p_ptt
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003850 * @param is_release_cmd - true for release, false for stop.
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003851 * @param is_tx_pq - true for Tx PQs, false for Other PQs.
3852 * @param start_pq - first PQ ID to stop
3853 * @param num_pqs - Number of PQs to stop, starting from start_pq.
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003854 *
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003855 * @return bool, true if successful, false if timeout occured while waiting for QM command done.
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003856 */
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003857bool qed_send_qm_stop_cmd(struct qed_hwfn *p_hwfn,
3858 struct qed_ptt *p_ptt,
3859 bool is_release_cmd,
3860 bool is_tx_pq, u16 start_pq, u16 num_pqs);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003861
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003862/**
3863 * @brief qed_set_vxlan_dest_port - initializes vxlan tunnel destination udp port
3864 *
3865 * @param p_ptt - ptt window used for writing the registers.
3866 * @param dest_port - vxlan destination udp port.
3867 */
Manish Chopra464f6642016-04-14 01:38:29 -04003868void qed_set_vxlan_dest_port(struct qed_hwfn *p_hwfn,
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003869 struct qed_ptt *p_ptt, u16 dest_port);
3870
3871/**
3872 * @brief qed_set_vxlan_enable - enable or disable VXLAN tunnel in HW
3873 *
3874 * @param p_ptt - ptt window used for writing the registers.
3875 * @param vxlan_enable - vxlan enable flag.
3876 */
Manish Chopra464f6642016-04-14 01:38:29 -04003877void qed_set_vxlan_enable(struct qed_hwfn *p_hwfn,
3878 struct qed_ptt *p_ptt, bool vxlan_enable);
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003879
3880/**
3881 * @brief qed_set_gre_enable - enable or disable GRE tunnel in HW
3882 *
3883 * @param p_ptt - ptt window used for writing the registers.
3884 * @param eth_gre_enable - eth GRE enable enable flag.
3885 * @param ip_gre_enable - IP GRE enable enable flag.
3886 */
Manish Chopra464f6642016-04-14 01:38:29 -04003887void qed_set_gre_enable(struct qed_hwfn *p_hwfn,
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003888 struct qed_ptt *p_ptt,
3889 bool eth_gre_enable, bool ip_gre_enable);
3890
3891/**
3892 * @brief qed_set_geneve_dest_port - initializes geneve tunnel destination udp port
3893 *
3894 * @param p_ptt - ptt window used for writing the registers.
3895 * @param dest_port - geneve destination udp port.
3896 */
Manish Chopra464f6642016-04-14 01:38:29 -04003897void qed_set_geneve_dest_port(struct qed_hwfn *p_hwfn,
3898 struct qed_ptt *p_ptt, u16 dest_port);
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003899
3900/**
3901 * @brief qed_set_gre_enable - enable or disable GRE tunnel in HW
3902 *
3903 * @param p_ptt - ptt window used for writing the registers.
3904 * @param eth_geneve_enable - eth GENEVE enable enable flag.
3905 * @param ip_geneve_enable - IP GENEVE enable enable flag.
3906 */
Manish Chopra464f6642016-04-14 01:38:29 -04003907void qed_set_geneve_enable(struct qed_hwfn *p_hwfn,
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003908 struct qed_ptt *p_ptt,
3909 bool eth_geneve_enable, bool ip_geneve_enable);
Chopra, Manishd51e4af2017-04-13 04:54:44 -07003910void qed_set_rfs_mode_disable(struct qed_hwfn *p_hwfn,
3911 struct qed_ptt *p_ptt, u16 pf_id);
3912void qed_set_rfs_mode_enable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
3913 u16 pf_id, bool tcp, bool udp,
3914 bool ipv4, bool ipv6);
Manish Chopra464f6642016-04-14 01:38:29 -04003915
Tomer Tayara2e76992017-12-27 19:30:05 +02003916/* Ystorm flow control mode. Use enum fw_flow_ctrl_mode */
3917#define YSTORM_FLOW_CONTROL_MODE_OFFSET (IRO[0].base)
3918#define YSTORM_FLOW_CONTROL_MODE_SIZE (IRO[0].size)
3919
3920/* Tstorm port statistics */
3921#define TSTORM_PORT_STAT_OFFSET(port_id) \
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003922 (IRO[1].base + ((port_id) * IRO[1].m1))
Tomer Tayara2e76992017-12-27 19:30:05 +02003923#define TSTORM_PORT_STAT_SIZE (IRO[1].size)
3924
3925/* Tstorm ll2 port statistics */
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003926#define TSTORM_LL2_PORT_STAT_OFFSET(port_id) \
3927 (IRO[2].base + ((port_id) * IRO[2].m1))
3928#define TSTORM_LL2_PORT_STAT_SIZE (IRO[2].size)
Tomer Tayara2e76992017-12-27 19:30:05 +02003929
3930/* Ustorm VF-PF Channel ready flag */
3931#define USTORM_VF_PF_CHANNEL_READY_OFFSET(vf_id) \
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003932 (IRO[3].base + ((vf_id) * IRO[3].m1))
Tomer Tayara2e76992017-12-27 19:30:05 +02003933#define USTORM_VF_PF_CHANNEL_READY_SIZE (IRO[3].size)
3934
3935/* Ustorm Final flr cleanup ack */
3936#define USTORM_FLR_FINAL_ACK_OFFSET(pf_id) \
3937 (IRO[4].base + ((pf_id) * IRO[4].m1))
3938#define USTORM_FLR_FINAL_ACK_SIZE (IRO[4].size)
3939
3940/* Ustorm Event ring consumer */
3941#define USTORM_EQE_CONS_OFFSET(pf_id) \
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003942 (IRO[5].base + ((pf_id) * IRO[5].m1))
Tomer Tayara2e76992017-12-27 19:30:05 +02003943#define USTORM_EQE_CONS_SIZE (IRO[5].size)
3944
3945/* Ustorm eth queue zone */
3946#define USTORM_ETH_QUEUE_ZONE_OFFSET(queue_zone_id) \
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003947 (IRO[6].base + ((queue_zone_id) * IRO[6].m1))
Tomer Tayara2e76992017-12-27 19:30:05 +02003948#define USTORM_ETH_QUEUE_ZONE_SIZE (IRO[6].size)
3949
3950/* Ustorm Common Queue ring consumer */
3951#define USTORM_COMMON_QUEUE_CONS_OFFSET(queue_zone_id) \
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003952 (IRO[7].base + ((queue_zone_id) * IRO[7].m1))
Tomer Tayara2e76992017-12-27 19:30:05 +02003953#define USTORM_COMMON_QUEUE_CONS_SIZE (IRO[7].size)
3954
3955/* Tstorm producers */
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003956#define TSTORM_LL2_RX_PRODS_OFFSET(core_rx_queue_id) \
Tomer Tayara2e76992017-12-27 19:30:05 +02003957 (IRO[14].base + ((core_rx_queue_id) * IRO[14].m1))
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003958#define TSTORM_LL2_RX_PRODS_SIZE (IRO[14].size)
Tomer Tayara2e76992017-12-27 19:30:05 +02003959
3960/* Tstorm LightL2 queue statistics */
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003961#define CORE_LL2_TSTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
3962 (IRO[15].base + ((core_rx_queue_id) * IRO[15].m1))
3963#define CORE_LL2_TSTORM_PER_QUEUE_STAT_SIZE (IRO[15].size)
Tomer Tayara2e76992017-12-27 19:30:05 +02003964
3965/* Ustorm LiteL2 queue statistics */
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003966#define CORE_LL2_USTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
Tomer Tayara2e76992017-12-27 19:30:05 +02003967 (IRO[16].base + ((core_rx_queue_id) * IRO[16].m1))
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003968#define CORE_LL2_USTORM_PER_QUEUE_STAT_SIZE (IRO[16].size)
Tomer Tayara2e76992017-12-27 19:30:05 +02003969
3970/* Pstorm LiteL2 queue statistics */
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003971#define CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(core_tx_stats_id) \
Tomer Tayara2e76992017-12-27 19:30:05 +02003972 (IRO[17].base + ((core_tx_stats_id) * IRO[17].m1))
3973#define CORE_LL2_PSTORM_PER_QUEUE_STAT_SIZE (IRO[17].size)
3974
3975/* Mstorm queue statistics */
3976#define MSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003977 (IRO[18].base + ((stat_counter_id) * IRO[18].m1))
Tomer Tayara2e76992017-12-27 19:30:05 +02003978#define MSTORM_QUEUE_STAT_SIZE (IRO[18].size)
3979
3980/* Mstorm ETH PF queues producers */
3981#define MSTORM_ETH_PF_PRODS_OFFSET(queue_id) \
Yuval Mintz351a4ded2016-06-02 10:23:29 +03003982 (IRO[19].base + ((queue_id) * IRO[19].m1))
Tomer Tayara2e76992017-12-27 19:30:05 +02003983#define MSTORM_ETH_PF_PRODS_SIZE (IRO[19].size)
3984
3985/* Mstorm ETH VF queues producers offset in RAM. Used in default VF zone size
3986 * mode.
3987 */
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003988#define MSTORM_ETH_VF_PRODS_OFFSET(vf_id, vf_queue_id) \
Tomer Tayara2e76992017-12-27 19:30:05 +02003989 (IRO[20].base + ((vf_id) * IRO[20].m1) + ((vf_queue_id) * IRO[20].m2))
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003990#define MSTORM_ETH_VF_PRODS_SIZE (IRO[20].size)
Tomer Tayara2e76992017-12-27 19:30:05 +02003991
3992/* TPA agregation timeout in us resolution (on ASIC) */
3993#define MSTORM_TPA_TIMEOUT_US_OFFSET (IRO[21].base)
3994#define MSTORM_TPA_TIMEOUT_US_SIZE (IRO[21].size)
3995
3996/* Mstorm pf statistics */
3997#define MSTORM_ETH_PF_STAT_OFFSET(pf_id) \
Yuval Mintz05fafbf2016-08-19 09:33:31 +03003998 (IRO[22].base + ((pf_id) * IRO[22].m1))
Tomer Tayara2e76992017-12-27 19:30:05 +02003999#define MSTORM_ETH_PF_STAT_SIZE (IRO[22].size)
4000
4001/* Ustorm queue statistics */
4002#define USTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004003 (IRO[23].base + ((stat_counter_id) * IRO[23].m1))
Tomer Tayara2e76992017-12-27 19:30:05 +02004004#define USTORM_QUEUE_STAT_SIZE (IRO[23].size)
4005
4006/* Ustorm pf statistics */
4007#define USTORM_ETH_PF_STAT_OFFSET(pf_id)\
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004008 (IRO[24].base + ((pf_id) * IRO[24].m1))
Tomer Tayara2e76992017-12-27 19:30:05 +02004009#define USTORM_ETH_PF_STAT_SIZE (IRO[24].size)
4010
4011/* Pstorm queue statistics */
4012#define PSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004013 (IRO[25].base + ((stat_counter_id) * IRO[25].m1))
Tomer Tayara2e76992017-12-27 19:30:05 +02004014#define PSTORM_QUEUE_STAT_SIZE (IRO[25].size)
4015
4016/* Pstorm pf statistics */
4017#define PSTORM_ETH_PF_STAT_OFFSET(pf_id) \
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004018 (IRO[26].base + ((pf_id) * IRO[26].m1))
Tomer Tayara2e76992017-12-27 19:30:05 +02004019#define PSTORM_ETH_PF_STAT_SIZE (IRO[26].size)
4020
4021/* Control frame's EthType configuration for TX control frame security */
4022#define PSTORM_CTL_FRAME_ETHTYPE_OFFSET(eth_type_id) \
4023 (IRO[27].base + ((eth_type_id) * IRO[27].m1))
4024#define PSTORM_CTL_FRAME_ETHTYPE_SIZE (IRO[27].size)
4025
4026/* Tstorm last parser message */
4027#define TSTORM_ETH_PRS_INPUT_OFFSET (IRO[28].base)
4028#define TSTORM_ETH_PRS_INPUT_SIZE (IRO[28].size)
4029
4030/* Tstorm Eth limit Rx rate */
4031#define ETH_RX_RATE_LIMIT_OFFSET(pf_id) \
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004032 (IRO[29].base + ((pf_id) * IRO[29].m1))
Tomer Tayara2e76992017-12-27 19:30:05 +02004033#define ETH_RX_RATE_LIMIT_SIZE (IRO[29].size)
4034
4035/* Xstorm queue zone */
4036#define XSTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) \
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004037 (IRO[30].base + ((queue_id) * IRO[30].m1))
Tomer Tayara2e76992017-12-27 19:30:05 +02004038#define XSTORM_ETH_QUEUE_ZONE_SIZE (IRO[30].size)
4039
4040/* Tstorm cmdq-cons of given command queue-id */
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004041#define TSTORM_SCSI_CMDQ_CONS_OFFSET(cmdq_queue_id) \
Tomer Tayara2e76992017-12-27 19:30:05 +02004042 (IRO[34].base + ((cmdq_queue_id) * IRO[34].m1))
4043#define TSTORM_SCSI_CMDQ_CONS_SIZE (IRO[34].size)
4044
4045/* Tstorm (reflects M-Storm) bdq-external-producer of given function ID,
4046 * BDqueue-id.
4047 */
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004048#define TSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) \
Tomer Tayara2e76992017-12-27 19:30:05 +02004049 (IRO[35].base + ((func_id) * IRO[35].m1) + ((bdq_id) * IRO[35].m2))
4050#define TSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[35].size)
4051
4052/* Mstorm bdq-external-producer of given BDQ resource ID, BDqueue-id */
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004053#define MSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) \
Tomer Tayara2e76992017-12-27 19:30:05 +02004054 (IRO[36].base + ((func_id) * IRO[36].m1) + ((bdq_id) * IRO[36].m2))
4055#define MSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[36].size)
4056
4057/* Tstorm iSCSI RX stats */
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004058#define TSTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
Tomer Tayara2e76992017-12-27 19:30:05 +02004059 (IRO[37].base + ((pf_id) * IRO[37].m1))
4060#define TSTORM_ISCSI_RX_STATS_SIZE (IRO[37].size)
4061
4062/* Mstorm iSCSI RX stats */
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004063#define MSTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
Tomer Tayara2e76992017-12-27 19:30:05 +02004064 (IRO[38].base + ((pf_id) * IRO[38].m1))
4065#define MSTORM_ISCSI_RX_STATS_SIZE (IRO[38].size)
4066
4067/* Ustorm iSCSI RX stats */
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004068#define USTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
Tomer Tayara2e76992017-12-27 19:30:05 +02004069 (IRO[39].base + ((pf_id) * IRO[39].m1))
4070#define USTORM_ISCSI_RX_STATS_SIZE (IRO[39].size)
4071
4072/* Xstorm iSCSI TX stats */
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004073#define XSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
Tomer Tayara2e76992017-12-27 19:30:05 +02004074 (IRO[40].base + ((pf_id) * IRO[40].m1))
4075#define XSTORM_ISCSI_TX_STATS_SIZE (IRO[40].size)
4076
4077/* Ystorm iSCSI TX stats */
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004078#define YSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
Tomer Tayara2e76992017-12-27 19:30:05 +02004079 (IRO[41].base + ((pf_id) * IRO[41].m1))
4080#define YSTORM_ISCSI_TX_STATS_SIZE (IRO[41].size)
4081
4082/* Pstorm iSCSI TX stats */
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004083#define PSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
Tomer Tayara2e76992017-12-27 19:30:05 +02004084 (IRO[42].base + ((pf_id) * IRO[42].m1))
4085#define PSTORM_ISCSI_TX_STATS_SIZE (IRO[42].size)
4086
4087/* Tstorm FCoE RX stats */
Arun Easi1e128c82017-02-15 06:28:22 -08004088#define TSTORM_FCOE_RX_STATS_OFFSET(pf_id) \
Tomer Tayara2e76992017-12-27 19:30:05 +02004089 (IRO[43].base + ((pf_id) * IRO[43].m1))
4090
4091/* Pstorm FCoE TX stats */
Arun Easi1e128c82017-02-15 06:28:22 -08004092#define PSTORM_FCOE_TX_STATS_OFFSET(pf_id) \
4093 (IRO[44].base + ((pf_id) * IRO[44].m1))
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004094
Tomer Tayara2e76992017-12-27 19:30:05 +02004095/* Pstorm RDMA queue statistics */
4096#define PSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \
4097 (IRO[45].base + ((rdma_stat_counter_id) * IRO[45].m1))
4098#define PSTORM_RDMA_QUEUE_STAT_SIZE (IRO[45].size)
4099
4100/* Tstorm RDMA queue statistics */
4101#define TSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \
4102 (IRO[46].base + ((rdma_stat_counter_id) * IRO[46].m1))
4103#define TSTORM_RDMA_QUEUE_STAT_SIZE (IRO[46].size)
4104
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03004105static const struct iro iro_arr[49] = {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004106 {0x0, 0x0, 0x0, 0x0, 0x8},
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02004107 {0x4cb0, 0x80, 0x0, 0x0, 0x80},
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03004108 {0x6518, 0x20, 0x0, 0x0, 0x20},
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004109 {0xb00, 0x8, 0x0, 0x0, 0x4},
4110 {0xa80, 0x8, 0x0, 0x0, 0x4},
4111 {0x0, 0x8, 0x0, 0x0, 0x2},
4112 {0x80, 0x8, 0x0, 0x0, 0x4},
4113 {0x84, 0x8, 0x0, 0x0, 0x2},
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03004114 {0x4c40, 0x0, 0x0, 0x0, 0x78},
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004115 {0x3df0, 0x0, 0x0, 0x0, 0x78},
4116 {0x29b0, 0x0, 0x0, 0x0, 0x78},
4117 {0x4c38, 0x0, 0x0, 0x0, 0x78},
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004118 {0x4990, 0x0, 0x0, 0x0, 0x78},
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03004119 {0x7f48, 0x0, 0x0, 0x0, 0x78},
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004120 {0xa28, 0x8, 0x0, 0x0, 0x8},
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03004121 {0x61f8, 0x10, 0x0, 0x0, 0x10},
4122 {0xbd20, 0x30, 0x0, 0x0, 0x30},
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004123 {0x95b8, 0x30, 0x0, 0x0, 0x30},
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004124 {0x4b60, 0x80, 0x0, 0x0, 0x40},
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004125 {0x1f8, 0x4, 0x0, 0x0, 0x4},
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004126 {0x53a0, 0x80, 0x4, 0x0, 0x4},
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03004127 {0xc7c8, 0x0, 0x0, 0x0, 0x4},
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004128 {0x4ba0, 0x80, 0x0, 0x0, 0x20},
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03004129 {0x8150, 0x40, 0x0, 0x0, 0x30},
4130 {0xec70, 0x60, 0x0, 0x0, 0x60},
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004131 {0x2b48, 0x80, 0x0, 0x0, 0x38},
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03004132 {0xf1b0, 0x78, 0x0, 0x0, 0x78},
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004133 {0x1f8, 0x4, 0x0, 0x0, 0x4},
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03004134 {0xaef8, 0x0, 0x0, 0x0, 0xf0},
4135 {0xafe8, 0x8, 0x0, 0x0, 0x8},
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004136 {0x1f8, 0x8, 0x0, 0x0, 0x8},
4137 {0xac0, 0x8, 0x0, 0x0, 0x8},
4138 {0x2578, 0x8, 0x0, 0x0, 0x8},
4139 {0x24f8, 0x8, 0x0, 0x0, 0x8},
4140 {0x0, 0x8, 0x0, 0x0, 0x8},
4141 {0x200, 0x10, 0x8, 0x0, 0x8},
4142 {0xb78, 0x10, 0x8, 0x0, 0x2},
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03004143 {0xd9a8, 0x38, 0x0, 0x0, 0x24},
4144 {0x12988, 0x10, 0x0, 0x0, 0x8},
4145 {0x11fa0, 0x38, 0x0, 0x0, 0x18},
4146 {0xa580, 0x38, 0x0, 0x0, 0x10},
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02004147 {0x86f8, 0x30, 0x0, 0x0, 0x18},
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004148 {0x101f8, 0x10, 0x0, 0x0, 0x10},
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03004149 {0xde28, 0x48, 0x0, 0x0, 0x38},
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004150 {0x10660, 0x20, 0x0, 0x0, 0x20},
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004151 {0x2b80, 0x80, 0x0, 0x0, 0x10},
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02004152 {0x5020, 0x10, 0x0, 0x0, 0x10},
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03004153 {0xc9b0, 0x30, 0x0, 0x0, 0x10},
4154 {0xeec0, 0x10, 0x0, 0x0, 0x10},
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004155};
4156
4157/* Runtime array offsets */
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004158#define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET 0
4159#define DORQ_REG_PF_MAX_ICID_1_RT_OFFSET 1
4160#define DORQ_REG_PF_MAX_ICID_2_RT_OFFSET 2
4161#define DORQ_REG_PF_MAX_ICID_3_RT_OFFSET 3
4162#define DORQ_REG_PF_MAX_ICID_4_RT_OFFSET 4
4163#define DORQ_REG_PF_MAX_ICID_5_RT_OFFSET 5
4164#define DORQ_REG_PF_MAX_ICID_6_RT_OFFSET 6
4165#define DORQ_REG_PF_MAX_ICID_7_RT_OFFSET 7
4166#define DORQ_REG_VF_MAX_ICID_0_RT_OFFSET 8
4167#define DORQ_REG_VF_MAX_ICID_1_RT_OFFSET 9
4168#define DORQ_REG_VF_MAX_ICID_2_RT_OFFSET 10
4169#define DORQ_REG_VF_MAX_ICID_3_RT_OFFSET 11
4170#define DORQ_REG_VF_MAX_ICID_4_RT_OFFSET 12
4171#define DORQ_REG_VF_MAX_ICID_5_RT_OFFSET 13
4172#define DORQ_REG_VF_MAX_ICID_6_RT_OFFSET 14
4173#define DORQ_REG_VF_MAX_ICID_7_RT_OFFSET 15
4174#define DORQ_REG_PF_WAKE_ALL_RT_OFFSET 16
4175#define DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET 17
4176#define IGU_REG_PF_CONFIGURATION_RT_OFFSET 18
4177#define IGU_REG_VF_CONFIGURATION_RT_OFFSET 19
4178#define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET 20
4179#define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET 21
4180#define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET 22
4181#define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET 23
4182#define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET 24
4183#define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 761
4184#define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736
4185#define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 761
4186#define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736
4187#define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET 1497
4188#define CAU_REG_SB_ADDR_MEMORY_RT_SIZE 736
4189#define CAU_REG_PI_MEMORY_RT_OFFSET 2233
4190#define CAU_REG_PI_MEMORY_RT_SIZE 4416
4191#define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET 6649
4192#define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET 6650
4193#define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET 6651
4194#define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET 6652
4195#define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET 6653
4196#define PRS_REG_SEARCH_TCP_RT_OFFSET 6654
4197#define PRS_REG_SEARCH_FCOE_RT_OFFSET 6655
4198#define PRS_REG_SEARCH_ROCE_RT_OFFSET 6656
4199#define PRS_REG_ROCE_DEST_QP_MAX_VF_RT_OFFSET 6657
4200#define PRS_REG_ROCE_DEST_QP_MAX_PF_RT_OFFSET 6658
4201#define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET 6659
4202#define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET 6660
4203#define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET 6661
4204#define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET 6662
4205#define PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET 6663
4206#define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET 6664
4207#define SRC_REG_FIRSTFREE_RT_OFFSET 6665
4208#define SRC_REG_FIRSTFREE_RT_SIZE 2
4209#define SRC_REG_LASTFREE_RT_OFFSET 6667
4210#define SRC_REG_LASTFREE_RT_SIZE 2
4211#define SRC_REG_COUNTFREE_RT_OFFSET 6669
4212#define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET 6670
4213#define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET 6671
4214#define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET 6672
4215#define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET 6673
4216#define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET 6674
4217#define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET 6675
4218#define PSWRQ2_REG_TSDM_P_SIZE_RT_OFFSET 6676
4219#define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET 6677
4220#define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET 6678
4221#define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET 6679
4222#define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET 6680
4223#define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET 6681
4224#define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET 6682
4225#define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET 6683
4226#define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET 6684
4227#define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET 6685
4228#define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET 6686
4229#define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET 6687
4230#define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET 6688
4231#define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6689
4232#define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6690
4233#define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6691
4234#define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET 6692
4235#define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET 6693
4236#define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET 6694
4237#define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET 6695
4238#define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET 6696
4239#define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET 6697
4240#define PSWRQ2_REG_VF_BASE_RT_OFFSET 6698
4241#define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET 6699
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03004242#define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET 6700
4243#define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET 6701
4244#define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET 6702
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004245#define PSWRQ2_REG_ILT_MEMORY_RT_SIZE 22000
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03004246#define PGLUE_REG_B_VF_BASE_RT_OFFSET 28702
4247#define PGLUE_REG_B_MSDM_OFFSET_MASK_B_RT_OFFSET 28703
4248#define PGLUE_REG_B_MSDM_VF_SHIFT_B_RT_OFFSET 28704
4249#define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET 28705
4250#define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET 28706
4251#define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET 28707
4252#define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET 28708
4253#define TM_REG_VF_ENABLE_CONN_RT_OFFSET 28709
4254#define TM_REG_PF_ENABLE_CONN_RT_OFFSET 28710
4255#define TM_REG_PF_ENABLE_TASK_RT_OFFSET 28711
4256#define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET 28712
4257#define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET 28713
4258#define TM_REG_CONFIG_CONN_MEM_RT_OFFSET 28714
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004259#define TM_REG_CONFIG_CONN_MEM_RT_SIZE 416
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03004260#define TM_REG_CONFIG_TASK_MEM_RT_OFFSET 29130
4261#define TM_REG_CONFIG_TASK_MEM_RT_SIZE 608
4262#define QM_REG_MAXPQSIZE_0_RT_OFFSET 29738
4263#define QM_REG_MAXPQSIZE_1_RT_OFFSET 29739
4264#define QM_REG_MAXPQSIZE_2_RT_OFFSET 29740
4265#define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET 29741
4266#define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET 29742
4267#define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET 29743
4268#define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET 29744
4269#define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET 29745
4270#define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET 29746
4271#define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET 29747
4272#define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET 29748
4273#define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET 29749
4274#define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET 29750
4275#define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET 29751
4276#define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET 29752
4277#define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET 29753
4278#define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET 29754
4279#define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET 29755
4280#define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET 29756
4281#define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET 29757
4282#define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET 29758
4283#define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET 29759
4284#define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET 29760
4285#define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET 29761
4286#define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET 29762
4287#define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET 29763
4288#define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET 29764
4289#define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET 29765
4290#define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET 29766
4291#define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET 29767
4292#define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET 29768
4293#define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET 29769
4294#define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET 29770
4295#define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET 29771
4296#define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET 29772
4297#define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET 29773
4298#define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET 29774
4299#define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET 29775
4300#define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET 29776
4301#define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET 29777
4302#define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET 29778
4303#define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET 29779
4304#define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET 29780
4305#define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET 29781
4306#define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET 29782
4307#define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET 29783
4308#define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET 29784
4309#define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET 29785
4310#define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET 29786
4311#define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET 29787
4312#define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET 29788
4313#define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET 29789
4314#define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET 29790
4315#define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET 29791
4316#define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET 29792
4317#define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET 29793
4318#define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET 29794
4319#define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET 29795
4320#define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET 29796
4321#define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET 29797
4322#define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET 29798
4323#define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET 29799
4324#define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET 29800
4325#define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET 29801
4326#define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET 29802
4327#define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET 29803
4328#define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET 29804
4329#define QM_REG_BASEADDROTHERPQ_RT_OFFSET 29805
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004330#define QM_REG_BASEADDROTHERPQ_RT_SIZE 128
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03004331#define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET 29933
4332#define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET 29934
4333#define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET 29935
4334#define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET 29936
4335#define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET 29937
4336#define QM_REG_WRROTHERPQGRP_0_RT_OFFSET 29938
4337#define QM_REG_WRROTHERPQGRP_1_RT_OFFSET 29939
4338#define QM_REG_WRROTHERPQGRP_2_RT_OFFSET 29940
4339#define QM_REG_WRROTHERPQGRP_3_RT_OFFSET 29941
4340#define QM_REG_WRROTHERPQGRP_4_RT_OFFSET 29942
4341#define QM_REG_WRROTHERPQGRP_5_RT_OFFSET 29943
4342#define QM_REG_WRROTHERPQGRP_6_RT_OFFSET 29944
4343#define QM_REG_WRROTHERPQGRP_7_RT_OFFSET 29945
4344#define QM_REG_WRROTHERPQGRP_8_RT_OFFSET 29946
4345#define QM_REG_WRROTHERPQGRP_9_RT_OFFSET 29947
4346#define QM_REG_WRROTHERPQGRP_10_RT_OFFSET 29948
4347#define QM_REG_WRROTHERPQGRP_11_RT_OFFSET 29949
4348#define QM_REG_WRROTHERPQGRP_12_RT_OFFSET 29950
4349#define QM_REG_WRROTHERPQGRP_13_RT_OFFSET 29951
4350#define QM_REG_WRROTHERPQGRP_14_RT_OFFSET 29952
4351#define QM_REG_WRROTHERPQGRP_15_RT_OFFSET 29953
4352#define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET 29954
4353#define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET 29955
4354#define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET 29956
4355#define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET 29957
4356#define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET 29958
4357#define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET 29959
4358#define QM_REG_PQTX2PF_0_RT_OFFSET 29960
4359#define QM_REG_PQTX2PF_1_RT_OFFSET 29961
4360#define QM_REG_PQTX2PF_2_RT_OFFSET 29962
4361#define QM_REG_PQTX2PF_3_RT_OFFSET 29963
4362#define QM_REG_PQTX2PF_4_RT_OFFSET 29964
4363#define QM_REG_PQTX2PF_5_RT_OFFSET 29965
4364#define QM_REG_PQTX2PF_6_RT_OFFSET 29966
4365#define QM_REG_PQTX2PF_7_RT_OFFSET 29967
4366#define QM_REG_PQTX2PF_8_RT_OFFSET 29968
4367#define QM_REG_PQTX2PF_9_RT_OFFSET 29969
4368#define QM_REG_PQTX2PF_10_RT_OFFSET 29970
4369#define QM_REG_PQTX2PF_11_RT_OFFSET 29971
4370#define QM_REG_PQTX2PF_12_RT_OFFSET 29972
4371#define QM_REG_PQTX2PF_13_RT_OFFSET 29973
4372#define QM_REG_PQTX2PF_14_RT_OFFSET 29974
4373#define QM_REG_PQTX2PF_15_RT_OFFSET 29975
4374#define QM_REG_PQTX2PF_16_RT_OFFSET 29976
4375#define QM_REG_PQTX2PF_17_RT_OFFSET 29977
4376#define QM_REG_PQTX2PF_18_RT_OFFSET 29978
4377#define QM_REG_PQTX2PF_19_RT_OFFSET 29979
4378#define QM_REG_PQTX2PF_20_RT_OFFSET 29980
4379#define QM_REG_PQTX2PF_21_RT_OFFSET 29981
4380#define QM_REG_PQTX2PF_22_RT_OFFSET 29982
4381#define QM_REG_PQTX2PF_23_RT_OFFSET 29983
4382#define QM_REG_PQTX2PF_24_RT_OFFSET 29984
4383#define QM_REG_PQTX2PF_25_RT_OFFSET 29985
4384#define QM_REG_PQTX2PF_26_RT_OFFSET 29986
4385#define QM_REG_PQTX2PF_27_RT_OFFSET 29987
4386#define QM_REG_PQTX2PF_28_RT_OFFSET 29988
4387#define QM_REG_PQTX2PF_29_RT_OFFSET 29989
4388#define QM_REG_PQTX2PF_30_RT_OFFSET 29990
4389#define QM_REG_PQTX2PF_31_RT_OFFSET 29991
4390#define QM_REG_PQTX2PF_32_RT_OFFSET 29992
4391#define QM_REG_PQTX2PF_33_RT_OFFSET 29993
4392#define QM_REG_PQTX2PF_34_RT_OFFSET 29994
4393#define QM_REG_PQTX2PF_35_RT_OFFSET 29995
4394#define QM_REG_PQTX2PF_36_RT_OFFSET 29996
4395#define QM_REG_PQTX2PF_37_RT_OFFSET 29997
4396#define QM_REG_PQTX2PF_38_RT_OFFSET 29998
4397#define QM_REG_PQTX2PF_39_RT_OFFSET 29999
4398#define QM_REG_PQTX2PF_40_RT_OFFSET 30000
4399#define QM_REG_PQTX2PF_41_RT_OFFSET 30001
4400#define QM_REG_PQTX2PF_42_RT_OFFSET 30002
4401#define QM_REG_PQTX2PF_43_RT_OFFSET 30003
4402#define QM_REG_PQTX2PF_44_RT_OFFSET 30004
4403#define QM_REG_PQTX2PF_45_RT_OFFSET 30005
4404#define QM_REG_PQTX2PF_46_RT_OFFSET 30006
4405#define QM_REG_PQTX2PF_47_RT_OFFSET 30007
4406#define QM_REG_PQTX2PF_48_RT_OFFSET 30008
4407#define QM_REG_PQTX2PF_49_RT_OFFSET 30009
4408#define QM_REG_PQTX2PF_50_RT_OFFSET 30010
4409#define QM_REG_PQTX2PF_51_RT_OFFSET 30011
4410#define QM_REG_PQTX2PF_52_RT_OFFSET 30012
4411#define QM_REG_PQTX2PF_53_RT_OFFSET 30013
4412#define QM_REG_PQTX2PF_54_RT_OFFSET 30014
4413#define QM_REG_PQTX2PF_55_RT_OFFSET 30015
4414#define QM_REG_PQTX2PF_56_RT_OFFSET 30016
4415#define QM_REG_PQTX2PF_57_RT_OFFSET 30017
4416#define QM_REG_PQTX2PF_58_RT_OFFSET 30018
4417#define QM_REG_PQTX2PF_59_RT_OFFSET 30019
4418#define QM_REG_PQTX2PF_60_RT_OFFSET 30020
4419#define QM_REG_PQTX2PF_61_RT_OFFSET 30021
4420#define QM_REG_PQTX2PF_62_RT_OFFSET 30022
4421#define QM_REG_PQTX2PF_63_RT_OFFSET 30023
4422#define QM_REG_PQOTHER2PF_0_RT_OFFSET 30024
4423#define QM_REG_PQOTHER2PF_1_RT_OFFSET 30025
4424#define QM_REG_PQOTHER2PF_2_RT_OFFSET 30026
4425#define QM_REG_PQOTHER2PF_3_RT_OFFSET 30027
4426#define QM_REG_PQOTHER2PF_4_RT_OFFSET 30028
4427#define QM_REG_PQOTHER2PF_5_RT_OFFSET 30029
4428#define QM_REG_PQOTHER2PF_6_RT_OFFSET 30030
4429#define QM_REG_PQOTHER2PF_7_RT_OFFSET 30031
4430#define QM_REG_PQOTHER2PF_8_RT_OFFSET 30032
4431#define QM_REG_PQOTHER2PF_9_RT_OFFSET 30033
4432#define QM_REG_PQOTHER2PF_10_RT_OFFSET 30034
4433#define QM_REG_PQOTHER2PF_11_RT_OFFSET 30035
4434#define QM_REG_PQOTHER2PF_12_RT_OFFSET 30036
4435#define QM_REG_PQOTHER2PF_13_RT_OFFSET 30037
4436#define QM_REG_PQOTHER2PF_14_RT_OFFSET 30038
4437#define QM_REG_PQOTHER2PF_15_RT_OFFSET 30039
4438#define QM_REG_RLGLBLPERIOD_0_RT_OFFSET 30040
4439#define QM_REG_RLGLBLPERIOD_1_RT_OFFSET 30041
4440#define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET 30042
4441#define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET 30043
4442#define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET 30044
4443#define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET 30045
4444#define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET 30046
4445#define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET 30047
4446#define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET 30048
4447#define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET 30049
4448#define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET 30050
4449#define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET 30051
4450#define QM_REG_RLGLBLINCVAL_RT_OFFSET 30052
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004451#define QM_REG_RLGLBLINCVAL_RT_SIZE 256
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03004452#define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET 30308
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004453#define QM_REG_RLGLBLUPPERBOUND_RT_SIZE 256
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03004454#define QM_REG_RLGLBLCRD_RT_OFFSET 30564
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004455#define QM_REG_RLGLBLCRD_RT_SIZE 256
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03004456#define QM_REG_RLGLBLENABLE_RT_OFFSET 30820
4457#define QM_REG_RLPFPERIOD_RT_OFFSET 30821
4458#define QM_REG_RLPFPERIODTIMER_RT_OFFSET 30822
4459#define QM_REG_RLPFINCVAL_RT_OFFSET 30823
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004460#define QM_REG_RLPFINCVAL_RT_SIZE 16
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03004461#define QM_REG_RLPFUPPERBOUND_RT_OFFSET 30839
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004462#define QM_REG_RLPFUPPERBOUND_RT_SIZE 16
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03004463#define QM_REG_RLPFCRD_RT_OFFSET 30855
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004464#define QM_REG_RLPFCRD_RT_SIZE 16
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03004465#define QM_REG_RLPFENABLE_RT_OFFSET 30871
4466#define QM_REG_RLPFVOQENABLE_RT_OFFSET 30872
4467#define QM_REG_WFQPFWEIGHT_RT_OFFSET 30873
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004468#define QM_REG_WFQPFWEIGHT_RT_SIZE 16
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03004469#define QM_REG_WFQPFUPPERBOUND_RT_OFFSET 30889
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004470#define QM_REG_WFQPFUPPERBOUND_RT_SIZE 16
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03004471#define QM_REG_WFQPFCRD_RT_OFFSET 30905
4472#define QM_REG_WFQPFCRD_RT_SIZE 256
4473#define QM_REG_WFQPFENABLE_RT_OFFSET 31161
4474#define QM_REG_WFQVPENABLE_RT_OFFSET 31162
4475#define QM_REG_BASEADDRTXPQ_RT_OFFSET 31163
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004476#define QM_REG_BASEADDRTXPQ_RT_SIZE 512
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03004477#define QM_REG_TXPQMAP_RT_OFFSET 31675
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004478#define QM_REG_TXPQMAP_RT_SIZE 512
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03004479#define QM_REG_WFQVPWEIGHT_RT_OFFSET 32187
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004480#define QM_REG_WFQVPWEIGHT_RT_SIZE 512
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03004481#define QM_REG_WFQVPCRD_RT_OFFSET 32699
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004482#define QM_REG_WFQVPCRD_RT_SIZE 512
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03004483#define QM_REG_WFQVPMAP_RT_OFFSET 33211
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004484#define QM_REG_WFQVPMAP_RT_SIZE 512
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03004485#define QM_REG_WFQPFCRD_MSB_RT_OFFSET 33723
4486#define QM_REG_WFQPFCRD_MSB_RT_SIZE 320
4487#define QM_REG_VOQCRDLINE_RT_OFFSET 34043
4488#define QM_REG_VOQCRDLINE_RT_SIZE 36
4489#define QM_REG_VOQINITCRDLINE_RT_OFFSET 34079
4490#define QM_REG_VOQINITCRDLINE_RT_SIZE 36
4491#define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET 34115
4492#define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET 34116
4493#define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET 34117
4494#define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET 34118
4495#define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET 34119
4496#define NIG_REG_OUTER_TAG_VALUE_MASK_RT_OFFSET 34120
4497#define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET 34121
4498#define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET 34122
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004499#define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE 4
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03004500#define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_OFFSET 34126
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004501#define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_SIZE 4
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03004502#define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET 34130
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004503#define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE 4
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03004504#define NIG_REG_LLH_FUNC_NO_TAG_RT_OFFSET 34134
4505#define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET 34135
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004506#define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE 32
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03004507#define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET 34167
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004508#define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE 16
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03004509#define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET 34183
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004510#define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE 16
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03004511#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 34199
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004512#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 16
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03004513#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET 34215
Yuval Mintz05fafbf2016-08-19 09:33:31 +03004514#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE 16
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03004515#define NIG_REG_TX_EDPM_CTRL_RT_OFFSET 34231
4516#define NIG_REG_ROCE_DUPLICATE_TO_HOST_RT_OFFSET 34232
4517#define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET 34233
4518#define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET 34234
4519#define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET 34235
4520#define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET 34236
4521#define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET 34237
4522#define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET 34238
4523#define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 34239
4524#define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET 34240
4525#define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET 34241
4526#define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET 34242
4527#define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 34243
4528#define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET 34244
4529#define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET 34245
4530#define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET 34246
4531#define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET 34247
4532#define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET 34248
4533#define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET 34249
4534#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET 34250
4535#define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET 34251
4536#define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET 34252
4537#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET 34253
4538#define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET 34254
4539#define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET 34255
4540#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET 34256
4541#define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET 34257
4542#define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET 34258
4543#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET 34259
4544#define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET 34260
4545#define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET 34261
4546#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET 34262
4547#define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET 34263
4548#define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET 34264
4549#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET 34265
4550#define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET 34266
4551#define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET 34267
4552#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET 34268
4553#define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET 34269
4554#define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET 34270
4555#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET 34271
4556#define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET 34272
4557#define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET 34273
4558#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET 34274
4559#define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET 34275
4560#define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET 34276
4561#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET 34277
4562#define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET 34278
4563#define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET 34279
4564#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET 34280
4565#define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET 34281
4566#define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET 34282
4567#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET 34283
4568#define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET 34284
4569#define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET 34285
4570#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET 34286
4571#define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET 34287
4572#define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET 34288
4573#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET 34289
4574#define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET 34290
4575#define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET 34291
4576#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET 34292
4577#define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET 34293
4578#define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET 34294
4579#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET 34295
4580#define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET 34296
4581#define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET 34297
4582#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET 34298
4583#define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET 34299
4584#define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET 34300
4585#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET 34301
4586#define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET 34302
4587#define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET 34303
4588#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET 34304
4589#define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET 34305
4590#define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET 34306
4591#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET 34307
4592#define XCM_REG_CON_PHY_Q3_RT_OFFSET 34308
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004593
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03004594#define RUNTIME_ARRAY_SIZE 34309
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004595
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05004596/* The eth storm context for the Tstorm */
4597struct tstorm_eth_conn_st_ctx {
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004598 __le32 reserved[4];
4599};
4600
4601/* The eth storm context for the Pstorm */
4602struct pstorm_eth_conn_st_ctx {
4603 __le32 reserved[8];
4604};
4605
4606/* The eth storm context for the Xstorm */
4607struct xstorm_eth_conn_st_ctx {
4608 __le32 reserved[60];
4609};
4610
Tomer Tayar21dd79e2017-12-27 19:30:06 +02004611struct e4_xstorm_eth_conn_ag_ctx {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004612 u8 reserved0;
4613 u8 eth_state;
4614 u8 flags0;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02004615#define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
4616#define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
4617#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK 0x1
4618#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT 1
4619#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK 0x1
4620#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT 2
4621#define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
4622#define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
4623#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK 0x1
4624#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT 4
4625#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK 0x1
4626#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT 5
4627#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK 0x1
4628#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT 6
4629#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK 0x1
4630#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT 7
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004631 u8 flags1;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02004632#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK 0x1
4633#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT 0
4634#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK 0x1
4635#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT 1
4636#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK 0x1
4637#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT 2
4638#define E4_XSTORM_ETH_CONN_AG_CTX_BIT11_MASK 0x1
4639#define E4_XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT 3
4640#define E4_XSTORM_ETH_CONN_AG_CTX_BIT12_MASK 0x1
4641#define E4_XSTORM_ETH_CONN_AG_CTX_BIT12_SHIFT 4
4642#define E4_XSTORM_ETH_CONN_AG_CTX_BIT13_MASK 0x1
4643#define E4_XSTORM_ETH_CONN_AG_CTX_BIT13_SHIFT 5
4644#define E4_XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
4645#define E4_XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
4646#define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
4647#define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004648 u8 flags2;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02004649#define E4_XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
4650#define E4_XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 0
4651#define E4_XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
4652#define E4_XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 2
4653#define E4_XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
4654#define E4_XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 4
4655#define E4_XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
4656#define E4_XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 6
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004657 u8 flags3;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02004658#define E4_XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3
4659#define E4_XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 0
4660#define E4_XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3
4661#define E4_XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 2
4662#define E4_XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3
4663#define E4_XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 4
4664#define E4_XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3
4665#define E4_XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 6
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004666 u8 flags4;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02004667#define E4_XSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3
4668#define E4_XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 0
4669#define E4_XSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3
4670#define E4_XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 2
4671#define E4_XSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3
4672#define E4_XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 4
4673#define E4_XSTORM_ETH_CONN_AG_CTX_CF11_MASK 0x3
4674#define E4_XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT 6
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004675 u8 flags5;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02004676#define E4_XSTORM_ETH_CONN_AG_CTX_CF12_MASK 0x3
4677#define E4_XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT 0
4678#define E4_XSTORM_ETH_CONN_AG_CTX_CF13_MASK 0x3
4679#define E4_XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT 2
4680#define E4_XSTORM_ETH_CONN_AG_CTX_CF14_MASK 0x3
4681#define E4_XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT 4
4682#define E4_XSTORM_ETH_CONN_AG_CTX_CF15_MASK 0x3
4683#define E4_XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT 6
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004684 u8 flags6;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02004685#define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3
4686#define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0
4687#define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
4688#define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2
4689#define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK 0x3
4690#define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT 4
4691#define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
4692#define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004693 u8 flags7;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02004694#define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
4695#define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
4696#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK 0x3
4697#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT 2
4698#define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK 0x3
4699#define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT 4
4700#define E4_XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
4701#define E4_XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 6
4702#define E4_XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
4703#define E4_XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 7
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004704 u8 flags8;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02004705#define E4_XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
4706#define E4_XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 0
4707#define E4_XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
4708#define E4_XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 1
4709#define E4_XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1
4710#define E4_XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 2
4711#define E4_XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1
4712#define E4_XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 3
4713#define E4_XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1
4714#define E4_XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 4
4715#define E4_XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1
4716#define E4_XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 5
4717#define E4_XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1
4718#define E4_XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 6
4719#define E4_XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1
4720#define E4_XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 7
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004721 u8 flags9;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02004722#define E4_XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1
4723#define E4_XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 0
4724#define E4_XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK 0x1
4725#define E4_XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT 1
4726#define E4_XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK 0x1
4727#define E4_XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT 2
4728#define E4_XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK 0x1
4729#define E4_XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT 3
4730#define E4_XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK 0x1
4731#define E4_XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT 4
4732#define E4_XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK 0x1
4733#define E4_XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT 5
4734#define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1
4735#define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6
4736#define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
4737#define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004738 u8 flags10;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02004739#define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
4740#define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
4741#define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
4742#define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
4743#define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
4744#define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
4745#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK 0x1
4746#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT 3
4747#define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
4748#define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
4749#define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1
4750#define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
4751#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK 0x1
4752#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT 6
4753#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK 0x1
4754#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT 7
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004755 u8 flags11;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02004756#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK 0x1
4757#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT 0
4758#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK 0x1
4759#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT 1
4760#define E4_XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
4761#define E4_XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
4762#define E4_XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
4763#define E4_XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 3
4764#define E4_XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1
4765#define E4_XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 4
4766#define E4_XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
4767#define E4_XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 5
4768#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
4769#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
4770#define E4_XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK 0x1
4771#define E4_XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT 7
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004772 u8 flags12;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02004773#define E4_XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK 0x1
4774#define E4_XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT 0
4775#define E4_XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK 0x1
4776#define E4_XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT 1
4777#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
4778#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
4779#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
4780#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
4781#define E4_XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK 0x1
4782#define E4_XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT 4
4783#define E4_XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK 0x1
4784#define E4_XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT 5
4785#define E4_XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK 0x1
4786#define E4_XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT 6
4787#define E4_XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK 0x1
4788#define E4_XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT 7
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004789 u8 flags13;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02004790#define E4_XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK 0x1
4791#define E4_XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT 0
4792#define E4_XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK 0x1
4793#define E4_XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT 1
4794#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
4795#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
4796#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
4797#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
4798#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
4799#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
4800#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
4801#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
4802#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
4803#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
4804#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
4805#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004806 u8 flags14;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02004807#define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1
4808#define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0
4809#define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1
4810#define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1
4811#define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1
4812#define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2
4813#define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1
4814#define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3
4815#define E4_XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1
4816#define E4_XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4
4817#define E4_XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
4818#define E4_XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
4819#define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK 0x3
4820#define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT 6
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004821 u8 edpm_event_id;
4822 __le16 physical_q0;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02004823 __le16 e5_reserved1;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004824 __le16 edpm_num_bds;
4825 __le16 tx_bd_cons;
4826 __le16 tx_bd_prod;
4827 __le16 tx_class;
4828 __le16 conn_dpi;
4829 u8 byte3;
4830 u8 byte4;
4831 u8 byte5;
4832 u8 byte6;
4833 __le32 reg0;
4834 __le32 reg1;
4835 __le32 reg2;
4836 __le32 reg3;
4837 __le32 reg4;
4838 __le32 reg5;
4839 __le32 reg6;
4840 __le16 word7;
4841 __le16 word8;
4842 __le16 word9;
4843 __le16 word10;
4844 __le32 reg7;
4845 __le32 reg8;
4846 __le32 reg9;
4847 u8 byte7;
4848 u8 byte8;
4849 u8 byte9;
4850 u8 byte10;
4851 u8 byte11;
4852 u8 byte12;
4853 u8 byte13;
4854 u8 byte14;
4855 u8 byte15;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02004856 u8 e5_reserved;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004857 __le16 word11;
4858 __le32 reg10;
4859 __le32 reg11;
4860 __le32 reg12;
4861 __le32 reg13;
4862 __le32 reg14;
4863 __le32 reg15;
4864 __le32 reg16;
4865 __le32 reg17;
4866 __le32 reg18;
4867 __le32 reg19;
4868 __le16 word12;
4869 __le16 word13;
4870 __le16 word14;
4871 __le16 word15;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004872};
4873
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05004874/* The eth storm context for the Ystorm */
4875struct ystorm_eth_conn_st_ctx {
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004876 __le32 reserved[8];
4877};
4878
Tomer Tayar21dd79e2017-12-27 19:30:06 +02004879struct e4_ystorm_eth_conn_ag_ctx {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004880 u8 byte0;
4881 u8 state;
4882 u8 flags0;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02004883#define E4_YSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
4884#define E4_YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
4885#define E4_YSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
4886#define E4_YSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
4887#define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3
4888#define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 2
4889#define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK 0x3
4890#define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_SHIFT 4
4891#define E4_YSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
4892#define E4_YSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004893 u8 flags1;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02004894#define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1
4895#define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 0
4896#define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK 0x1
4897#define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_SHIFT 1
4898#define E4_YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
4899#define E4_YSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
4900#define E4_YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
4901#define E4_YSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3
4902#define E4_YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
4903#define E4_YSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4
4904#define E4_YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
4905#define E4_YSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5
4906#define E4_YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
4907#define E4_YSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6
4908#define E4_YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
4909#define E4_YSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004910 u8 tx_q0_int_coallecing_timeset;
4911 u8 byte3;
4912 __le16 word0;
4913 __le32 terminate_spqe;
4914 __le32 reg1;
4915 __le16 tx_bd_cons_upd;
4916 __le16 word2;
4917 __le16 word3;
4918 __le16 word4;
4919 __le32 reg2;
4920 __le32 reg3;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004921};
4922
Tomer Tayar21dd79e2017-12-27 19:30:06 +02004923struct e4_tstorm_eth_conn_ag_ctx {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03004924 u8 byte0;
4925 u8 byte1;
4926 u8 flags0;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02004927#define E4_TSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
4928#define E4_TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
4929#define E4_TSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
4930#define E4_TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
4931#define E4_TSTORM_ETH_CONN_AG_CTX_BIT2_MASK 0x1
4932#define E4_TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT 2
4933#define E4_TSTORM_ETH_CONN_AG_CTX_BIT3_MASK 0x1
4934#define E4_TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT 3
4935#define E4_TSTORM_ETH_CONN_AG_CTX_BIT4_MASK 0x1
4936#define E4_TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT 4
4937#define E4_TSTORM_ETH_CONN_AG_CTX_BIT5_MASK 0x1
4938#define E4_TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT 5
4939#define E4_TSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
4940#define E4_TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 6
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004941 u8 flags1;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02004942#define E4_TSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
4943#define E4_TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 0
4944#define E4_TSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
4945#define E4_TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 2
4946#define E4_TSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
4947#define E4_TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 4
4948#define E4_TSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3
4949#define E4_TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 6
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004950 u8 flags2;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02004951#define E4_TSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3
4952#define E4_TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 0
4953#define E4_TSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3
4954#define E4_TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 2
4955#define E4_TSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3
4956#define E4_TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 4
4957#define E4_TSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3
4958#define E4_TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 6
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004959 u8 flags3;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02004960#define E4_TSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3
4961#define E4_TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 0
4962#define E4_TSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3
4963#define E4_TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 2
4964#define E4_TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
4965#define E4_TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 4
4966#define E4_TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
4967#define E4_TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 5
4968#define E4_TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
4969#define E4_TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 6
4970#define E4_TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
4971#define E4_TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 7
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004972 u8 flags4;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02004973#define E4_TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1
4974#define E4_TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 0
4975#define E4_TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1
4976#define E4_TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 1
4977#define E4_TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1
4978#define E4_TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 2
4979#define E4_TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1
4980#define E4_TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 3
4981#define E4_TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1
4982#define E4_TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 4
4983#define E4_TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1
4984#define E4_TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 5
4985#define E4_TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1
4986#define E4_TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 6
4987#define E4_TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
4988#define E4_TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02004989 u8 flags5;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02004990#define E4_TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
4991#define E4_TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
4992#define E4_TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
4993#define E4_TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1
4994#define E4_TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
4995#define E4_TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2
4996#define E4_TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
4997#define E4_TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3
4998#define E4_TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
4999#define E4_TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4
5000#define E4_TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK 0x1
5001#define E4_TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT 5
5002#define E4_TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
5003#define E4_TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6
5004#define E4_TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1
5005#define E4_TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005006 __le32 reg0;
5007 __le32 reg1;
5008 __le32 reg2;
5009 __le32 reg3;
5010 __le32 reg4;
5011 __le32 reg5;
5012 __le32 reg6;
5013 __le32 reg7;
5014 __le32 reg8;
5015 u8 byte2;
5016 u8 byte3;
5017 __le16 rx_bd_cons;
5018 u8 byte4;
5019 u8 byte5;
5020 __le16 rx_bd_prod;
5021 __le16 word2;
5022 __le16 word3;
5023 __le32 reg9;
5024 __le32 reg10;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02005025};
5026
Tomer Tayar21dd79e2017-12-27 19:30:06 +02005027struct e4_ustorm_eth_conn_ag_ctx {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005028 u8 byte0;
5029 u8 byte1;
5030 u8 flags0;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02005031#define E4_USTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
5032#define E4_USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
5033#define E4_USTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
5034#define E4_USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
5035#define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK 0x3
5036#define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_SHIFT 2
5037#define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK 0x3
5038#define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_SHIFT 4
5039#define E4_USTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
5040#define E4_USTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02005041 u8 flags1;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02005042#define E4_USTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
5043#define E4_USTORM_ETH_CONN_AG_CTX_CF3_SHIFT 0
5044#define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK 0x3
5045#define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT 2
5046#define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK 0x3
5047#define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT 4
5048#define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3
5049#define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 6
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02005050 u8 flags2;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02005051#define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK 0x1
5052#define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT 0
5053#define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK 0x1
5054#define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_SHIFT 1
5055#define E4_USTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
5056#define E4_USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
5057#define E4_USTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
5058#define E4_USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 3
5059#define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK 0x1
5060#define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT 4
5061#define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK 0x1
5062#define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT 5
5063#define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1
5064#define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 6
5065#define E4_USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
5066#define E4_USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02005067 u8 flags3;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02005068#define E4_USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
5069#define E4_USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
5070#define E4_USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
5071#define E4_USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1
5072#define E4_USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
5073#define E4_USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2
5074#define E4_USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
5075#define E4_USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3
5076#define E4_USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
5077#define E4_USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4
5078#define E4_USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1
5079#define E4_USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 5
5080#define E4_USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
5081#define E4_USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6
5082#define E4_USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1
5083#define E4_USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005084 u8 byte2;
5085 u8 byte3;
5086 __le16 word0;
5087 __le16 tx_bd_cons;
5088 __le32 reg0;
5089 __le32 reg1;
5090 __le32 reg2;
5091 __le32 tx_int_coallecing_timeset;
5092 __le16 tx_drv_bd_cons;
5093 __le16 rx_drv_cqe_cons;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02005094};
5095
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005096/* The eth storm context for the Ustorm */
5097struct ustorm_eth_conn_st_ctx {
5098 __le32 reserved[40];
5099};
5100
5101/* The eth storm context for the Mstorm */
5102struct mstorm_eth_conn_st_ctx {
5103 __le32 reserved[8];
5104};
5105
5106/* eth connection context */
Tomer Tayar21dd79e2017-12-27 19:30:06 +02005107struct e4_eth_conn_context {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005108 struct tstorm_eth_conn_st_ctx tstorm_st_context;
5109 struct regpair tstorm_st_padding[2];
5110 struct pstorm_eth_conn_st_ctx pstorm_st_context;
5111 struct xstorm_eth_conn_st_ctx xstorm_st_context;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02005112 struct e4_xstorm_eth_conn_ag_ctx xstorm_ag_context;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005113 struct ystorm_eth_conn_st_ctx ystorm_st_context;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02005114 struct e4_ystorm_eth_conn_ag_ctx ystorm_ag_context;
5115 struct e4_tstorm_eth_conn_ag_ctx tstorm_ag_context;
5116 struct e4_ustorm_eth_conn_ag_ctx ustorm_ag_context;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005117 struct ustorm_eth_conn_st_ctx ustorm_st_context;
5118 struct mstorm_eth_conn_st_ctx mstorm_st_context;
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005119};
5120
Tomer Tayara2e76992017-12-27 19:30:05 +02005121/* Ethernet filter types: mac/vlan/pair */
Yuval Mintz05fafbf2016-08-19 09:33:31 +03005122enum eth_error_code {
5123 ETH_OK = 0x00,
5124 ETH_FILTERS_MAC_ADD_FAIL_FULL,
5125 ETH_FILTERS_MAC_ADD_FAIL_FULL_MTT2,
5126 ETH_FILTERS_MAC_ADD_FAIL_DUP_MTT2,
5127 ETH_FILTERS_MAC_ADD_FAIL_DUP_STT2,
5128 ETH_FILTERS_MAC_DEL_FAIL_NOF,
5129 ETH_FILTERS_MAC_DEL_FAIL_NOF_MTT2,
5130 ETH_FILTERS_MAC_DEL_FAIL_NOF_STT2,
5131 ETH_FILTERS_MAC_ADD_FAIL_ZERO_MAC,
5132 ETH_FILTERS_VLAN_ADD_FAIL_FULL,
5133 ETH_FILTERS_VLAN_ADD_FAIL_DUP,
5134 ETH_FILTERS_VLAN_DEL_FAIL_NOF,
5135 ETH_FILTERS_VLAN_DEL_FAIL_NOF_TT1,
5136 ETH_FILTERS_PAIR_ADD_FAIL_DUP,
5137 ETH_FILTERS_PAIR_ADD_FAIL_FULL,
5138 ETH_FILTERS_PAIR_ADD_FAIL_FULL_MAC,
5139 ETH_FILTERS_PAIR_DEL_FAIL_NOF,
5140 ETH_FILTERS_PAIR_DEL_FAIL_NOF_TT1,
5141 ETH_FILTERS_PAIR_ADD_FAIL_ZERO_MAC,
5142 ETH_FILTERS_VNI_ADD_FAIL_FULL,
5143 ETH_FILTERS_VNI_ADD_FAIL_DUP,
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03005144 ETH_FILTERS_GFT_UPDATE_FAIL,
Yuval Mintz05fafbf2016-08-19 09:33:31 +03005145 MAX_ETH_ERROR_CODE
5146};
5147
Tomer Tayara2e76992017-12-27 19:30:05 +02005148/* Opcodes for the event ring */
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005149enum eth_event_opcode {
5150 ETH_EVENT_UNUSED,
5151 ETH_EVENT_VPORT_START,
5152 ETH_EVENT_VPORT_UPDATE,
5153 ETH_EVENT_VPORT_STOP,
5154 ETH_EVENT_TX_QUEUE_START,
5155 ETH_EVENT_TX_QUEUE_STOP,
5156 ETH_EVENT_RX_QUEUE_START,
5157 ETH_EVENT_RX_QUEUE_UPDATE,
5158 ETH_EVENT_RX_QUEUE_STOP,
5159 ETH_EVENT_FILTERS_UPDATE,
5160 ETH_EVENT_RESERVED,
5161 ETH_EVENT_RESERVED2,
5162 ETH_EVENT_RESERVED3,
5163 ETH_EVENT_RX_ADD_UDP_FILTER,
5164 ETH_EVENT_RX_DELETE_UDP_FILTER,
5165 ETH_EVENT_RESERVED4,
5166 ETH_EVENT_RESERVED5,
5167 MAX_ETH_EVENT_OPCODE
5168};
5169
5170/* Classify rule types in E2/E3 */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005171enum eth_filter_action {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005172 ETH_FILTER_ACTION_UNUSED,
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005173 ETH_FILTER_ACTION_REMOVE,
5174 ETH_FILTER_ACTION_ADD,
5175 ETH_FILTER_ACTION_REMOVE_ALL,
5176 MAX_ETH_FILTER_ACTION
5177};
5178
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005179/* Command for adding/removing a classification rule $$KEEP_ENDIANNESS$$ */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005180struct eth_filter_cmd {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005181 u8 type;
5182 u8 vport_id;
5183 u8 action;
5184 u8 reserved0;
5185 __le32 vni;
5186 __le16 mac_lsb;
5187 __le16 mac_mid;
5188 __le16 mac_msb;
5189 __le16 vlan_id;
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005190};
5191
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005192/* $$KEEP_ENDIANNESS$$ */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005193struct eth_filter_cmd_header {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005194 u8 rx;
5195 u8 tx;
5196 u8 cmd_cnt;
5197 u8 assert_on_error;
5198 u8 reserved1[4];
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005199};
5200
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005201/* Ethernet filter types: mac/vlan/pair */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005202enum eth_filter_type {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005203 ETH_FILTER_TYPE_UNUSED,
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005204 ETH_FILTER_TYPE_MAC,
5205 ETH_FILTER_TYPE_VLAN,
5206 ETH_FILTER_TYPE_PAIR,
5207 ETH_FILTER_TYPE_INNER_MAC,
5208 ETH_FILTER_TYPE_INNER_VLAN,
5209 ETH_FILTER_TYPE_INNER_PAIR,
5210 ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR,
5211 ETH_FILTER_TYPE_MAC_VNI_PAIR,
5212 ETH_FILTER_TYPE_VNI,
5213 MAX_ETH_FILTER_TYPE
5214};
5215
Tomer Tayara2e76992017-12-27 19:30:05 +02005216/* Eth IPv4 Fragment Type */
Yuval Mintz05fafbf2016-08-19 09:33:31 +03005217enum eth_ipv4_frag_type {
5218 ETH_IPV4_NOT_FRAG,
5219 ETH_IPV4_FIRST_FRAG,
5220 ETH_IPV4_NON_FIRST_FRAG,
5221 MAX_ETH_IPV4_FRAG_TYPE
5222};
5223
Tomer Tayara2e76992017-12-27 19:30:05 +02005224/* eth IPv4 Fragment Type */
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02005225enum eth_ip_type {
5226 ETH_IPV4,
5227 ETH_IPV6,
5228 MAX_ETH_IP_TYPE
5229};
5230
Tomer Tayara2e76992017-12-27 19:30:05 +02005231/* Ethernet Ramrod Command IDs */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005232enum eth_ramrod_cmd_id {
5233 ETH_RAMROD_UNUSED,
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005234 ETH_RAMROD_VPORT_START,
5235 ETH_RAMROD_VPORT_UPDATE,
5236 ETH_RAMROD_VPORT_STOP,
5237 ETH_RAMROD_RX_QUEUE_START,
5238 ETH_RAMROD_RX_QUEUE_STOP,
5239 ETH_RAMROD_TX_QUEUE_START,
5240 ETH_RAMROD_TX_QUEUE_STOP,
5241 ETH_RAMROD_FILTERS_UPDATE,
5242 ETH_RAMROD_RX_QUEUE_UPDATE,
5243 ETH_RAMROD_RX_CREATE_OPENFLOW_ACTION,
5244 ETH_RAMROD_RX_ADD_OPENFLOW_FILTER,
5245 ETH_RAMROD_RX_DELETE_OPENFLOW_FILTER,
5246 ETH_RAMROD_RX_ADD_UDP_FILTER,
5247 ETH_RAMROD_RX_DELETE_UDP_FILTER,
5248 ETH_RAMROD_RX_CREATE_GFT_ACTION,
5249 ETH_RAMROD_GFT_UPDATE_FILTER,
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005250 MAX_ETH_RAMROD_CMD_ID
5251};
5252
Tomer Tayara2e76992017-12-27 19:30:05 +02005253/* Return code from eth sp ramrods */
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005254struct eth_return_code {
5255 u8 value;
5256#define ETH_RETURN_CODE_ERR_CODE_MASK 0x1F
5257#define ETH_RETURN_CODE_ERR_CODE_SHIFT 0
5258#define ETH_RETURN_CODE_RESERVED_MASK 0x3
5259#define ETH_RETURN_CODE_RESERVED_SHIFT 5
5260#define ETH_RETURN_CODE_RX_TX_MASK 0x1
5261#define ETH_RETURN_CODE_RX_TX_SHIFT 7
5262};
5263
5264/* What to do in case an error occurs */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005265enum eth_tx_err {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005266 ETH_TX_ERR_DROP,
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005267 ETH_TX_ERR_ASSERT_MALICIOUS,
5268 MAX_ETH_TX_ERR
5269};
5270
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005271/* Array of the different error type behaviors */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005272struct eth_tx_err_vals {
5273 __le16 values;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005274#define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_MASK 0x1
5275#define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_SHIFT 0
5276#define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_MASK 0x1
5277#define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_SHIFT 1
5278#define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_MASK 0x1
5279#define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_SHIFT 2
5280#define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_MASK 0x1
5281#define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_SHIFT 3
5282#define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_MASK 0x1
5283#define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_SHIFT 4
5284#define ETH_TX_ERR_VALS_MTU_VIOLATION_MASK 0x1
5285#define ETH_TX_ERR_VALS_MTU_VIOLATION_SHIFT 5
5286#define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_MASK 0x1
5287#define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_SHIFT 6
5288#define ETH_TX_ERR_VALS_RESERVED_MASK 0x1FF
5289#define ETH_TX_ERR_VALS_RESERVED_SHIFT 7
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005290};
5291
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005292/* vport rss configuration data */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005293struct eth_vport_rss_config {
5294 __le16 capabilities;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005295#define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_MASK 0x1
5296#define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_SHIFT 0
5297#define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_MASK 0x1
5298#define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_SHIFT 1
5299#define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_MASK 0x1
5300#define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_SHIFT 2
5301#define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_MASK 0x1
5302#define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_SHIFT 3
5303#define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_MASK 0x1
5304#define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_SHIFT 4
5305#define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_MASK 0x1
5306#define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_SHIFT 5
5307#define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_MASK 0x1
5308#define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_SHIFT 6
5309#define ETH_VPORT_RSS_CONFIG_RESERVED0_MASK 0x1FF
5310#define ETH_VPORT_RSS_CONFIG_RESERVED0_SHIFT 7
5311 u8 rss_id;
5312 u8 rss_mode;
5313 u8 update_rss_key;
5314 u8 update_rss_ind_table;
5315 u8 update_rss_capabilities;
5316 u8 tbl_size;
5317 __le32 reserved2[2];
5318 __le16 indirection_table[ETH_RSS_IND_TABLE_ENTRIES_NUM];
5319
5320 __le32 rss_key[ETH_RSS_KEY_SIZE_REGS];
5321 __le32 reserved3[2];
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005322};
5323
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005324/* eth vport RSS mode */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005325enum eth_vport_rss_mode {
5326 ETH_VPORT_RSS_MODE_DISABLED,
5327 ETH_VPORT_RSS_MODE_REGULAR,
5328 MAX_ETH_VPORT_RSS_MODE
5329};
5330
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005331/* Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005332struct eth_vport_rx_mode {
5333 __le16 state;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005334#define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_MASK 0x1
5335#define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_SHIFT 0
5336#define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_MASK 0x1
5337#define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_SHIFT 1
5338#define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_MASK 0x1
5339#define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_SHIFT 2
5340#define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_MASK 0x1
5341#define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_SHIFT 3
5342#define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_MASK 0x1
5343#define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_SHIFT 4
5344#define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_MASK 0x1
5345#define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_SHIFT 5
5346#define ETH_VPORT_RX_MODE_RESERVED1_MASK 0x3FF
5347#define ETH_VPORT_RX_MODE_RESERVED1_SHIFT 6
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005348 __le16 reserved2[3];
5349};
5350
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005351/* Command for setting tpa parameters */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005352struct eth_vport_tpa_param {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005353 u8 tpa_ipv4_en_flg;
5354 u8 tpa_ipv6_en_flg;
5355 u8 tpa_ipv4_tunn_en_flg;
5356 u8 tpa_ipv6_tunn_en_flg;
5357 u8 tpa_pkt_split_flg;
5358 u8 tpa_hdr_data_split_flg;
5359 u8 tpa_gro_consistent_flg;
5360
5361 u8 tpa_max_aggs_num;
5362
5363 __le16 tpa_max_size;
5364 __le16 tpa_min_size_to_start;
5365
5366 __le16 tpa_min_size_to_cont;
5367 u8 max_buff_num;
5368 u8 reserved;
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005369};
5370
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005371/* Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005372struct eth_vport_tx_mode {
5373 __le16 state;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005374#define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_MASK 0x1
5375#define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_SHIFT 0
5376#define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_MASK 0x1
5377#define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_SHIFT 1
5378#define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_MASK 0x1
5379#define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_SHIFT 2
5380#define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_MASK 0x1
5381#define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_SHIFT 3
5382#define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_MASK 0x1
5383#define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_SHIFT 4
5384#define ETH_VPORT_TX_MODE_RESERVED1_MASK 0x7FF
5385#define ETH_VPORT_TX_MODE_RESERVED1_SHIFT 5
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005386 __le16 reserved2[3];
5387};
5388
Tomer Tayara2e76992017-12-27 19:30:05 +02005389/* GFT filter update action type */
Chopra, Manishd51e4af2017-04-13 04:54:44 -07005390enum gft_filter_update_action {
5391 GFT_ADD_FILTER,
5392 GFT_DELETE_FILTER,
5393 MAX_GFT_FILTER_UPDATE_ACTION
5394};
5395
5396enum gft_logic_filter_type {
5397 GFT_FILTER_TYPE,
5398 RFS_FILTER_TYPE,
5399 MAX_GFT_LOGIC_FILTER_TYPE
5400};
5401
Tomer Tayara2e76992017-12-27 19:30:05 +02005402/* Ramrod data for rx add openflow filter */
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03005403struct rx_add_openflow_filter_data {
5404 __le16 action_icid;
5405 u8 priority;
5406 u8 reserved0;
5407 __le32 tenant_id;
5408 __le16 dst_mac_hi;
5409 __le16 dst_mac_mid;
5410 __le16 dst_mac_lo;
5411 __le16 src_mac_hi;
5412 __le16 src_mac_mid;
5413 __le16 src_mac_lo;
5414 __le16 vlan_id;
5415 __le16 l2_eth_type;
5416 u8 ipv4_dscp;
5417 u8 ipv4_frag_type;
5418 u8 ipv4_over_ip;
5419 u8 tenant_id_exists;
5420 __le32 ipv4_dst_addr;
5421 __le32 ipv4_src_addr;
5422 __le16 l4_dst_port;
5423 __le16 l4_src_port;
5424};
5425
Tomer Tayara2e76992017-12-27 19:30:05 +02005426/* Ramrod data for rx create gft action */
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03005427struct rx_create_gft_action_data {
5428 u8 vport_id;
5429 u8 reserved[7];
5430};
5431
Tomer Tayara2e76992017-12-27 19:30:05 +02005432/* Ramrod data for rx create openflow action */
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03005433struct rx_create_openflow_action_data {
5434 u8 vport_id;
5435 u8 reserved[7];
5436};
5437
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005438/* Ramrod data for rx queue start ramrod */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005439struct rx_queue_start_ramrod_data {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005440 __le16 rx_queue_id;
5441 __le16 num_of_pbl_pages;
5442 __le16 bd_max_bytes;
5443 __le16 sb_id;
5444 u8 sb_index;
5445 u8 vport_id;
5446 u8 default_rss_queue_flg;
5447 u8 complete_cqe_flg;
5448 u8 complete_event_flg;
5449 u8 stats_counter_id;
5450 u8 pin_context;
5451 u8 pxp_tph_valid_bd;
5452 u8 pxp_tph_valid_pkt;
5453 u8 pxp_st_hint;
5454
5455 __le16 pxp_st_index;
5456 u8 pmd_mode;
5457
5458 u8 notify_en;
5459 u8 toggle_val;
5460
5461 u8 vf_rx_prod_index;
Yuval Mintz05fafbf2016-08-19 09:33:31 +03005462 u8 vf_rx_prod_use_zone_a;
5463 u8 reserved[5];
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005464 __le16 reserved1;
5465 struct regpair cqe_pbl_addr;
5466 struct regpair bd_base;
5467 struct regpair reserved2;
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005468};
5469
Tomer Tayara2e76992017-12-27 19:30:05 +02005470/* Ramrod data for rx queue stop ramrod */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005471struct rx_queue_stop_ramrod_data {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005472 __le16 rx_queue_id;
5473 u8 complete_cqe_flg;
5474 u8 complete_event_flg;
5475 u8 vport_id;
5476 u8 reserved[3];
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005477};
5478
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005479/* Ramrod data for rx queue update ramrod */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005480struct rx_queue_update_ramrod_data {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005481 __le16 rx_queue_id;
5482 u8 complete_cqe_flg;
5483 u8 complete_event_flg;
5484 u8 vport_id;
5485 u8 reserved[4];
5486 u8 reserved1;
5487 u8 reserved2;
5488 u8 reserved3;
5489 __le16 reserved4;
5490 __le16 reserved5;
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005491 struct regpair reserved6;
5492};
5493
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005494/* Ramrod data for rx Add UDP Filter */
5495struct rx_udp_filter_data {
5496 __le16 action_icid;
5497 __le16 vlan_id;
5498 u8 ip_type;
5499 u8 tenant_id_exists;
5500 __le16 reserved1;
5501 __le32 ip_dst_addr[4];
5502 __le32 ip_src_addr[4];
5503 __le16 udp_dst_port;
5504 __le16 udp_src_port;
5505 __le32 tenant_id;
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005506};
5507
Tomer Tayara2e76992017-12-27 19:30:05 +02005508/* Add or delete GFT filter - filter is packet header of type of packet wished
5509 * to pass certain FW flow.
5510 */
Chopra, Manishd51e4af2017-04-13 04:54:44 -07005511struct rx_update_gft_filter_data {
5512 struct regpair pkt_hdr_addr;
5513 __le16 pkt_hdr_length;
5514 __le16 rx_qid_or_action_icid;
5515 u8 vport_id;
5516 u8 filter_type;
5517 u8 filter_action;
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03005518 u8 assert_on_error;
Chopra, Manishd51e4af2017-04-13 04:54:44 -07005519};
5520
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005521/* Ramrod data for rx queue start ramrod */
5522struct tx_queue_start_ramrod_data {
5523 __le16 sb_id;
5524 u8 sb_index;
5525 u8 vport_id;
5526 u8 reserved0;
5527 u8 stats_counter_id;
5528 __le16 qm_pq_id;
5529 u8 flags;
5530#define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_MASK 0x1
5531#define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_SHIFT 0
5532#define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_MASK 0x1
5533#define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_SHIFT 1
5534#define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_MASK 0x1
5535#define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_SHIFT 2
5536#define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_MASK 0x1
5537#define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_SHIFT 3
5538#define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_MASK 0x1
5539#define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_SHIFT 4
5540#define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_MASK 0x1
5541#define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_SHIFT 5
5542#define TX_QUEUE_START_RAMROD_DATA_RESERVED1_MASK 0x3
5543#define TX_QUEUE_START_RAMROD_DATA_RESERVED1_SHIFT 6
5544 u8 pxp_st_hint;
5545 u8 pxp_tph_valid_bd;
5546 u8 pxp_tph_valid_pkt;
5547 __le16 pxp_st_index;
5548 __le16 comp_agg_size;
5549 __le16 queue_zone_id;
Yuval Mintz05fafbf2016-08-19 09:33:31 +03005550 __le16 reserved2;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005551 __le16 pbl_size;
5552 __le16 tx_queue_id;
Yuval Mintz05fafbf2016-08-19 09:33:31 +03005553 __le16 same_as_last_id;
5554 __le16 reserved[3];
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005555 struct regpair pbl_base_addr;
5556 struct regpair bd_cons_address;
5557};
5558
5559/* Ramrod data for tx queue stop ramrod */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005560struct tx_queue_stop_ramrod_data {
5561 __le16 reserved[4];
5562};
5563
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005564/* Ramrod data for vport update ramrod */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005565struct vport_filter_update_ramrod_data {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005566 struct eth_filter_cmd_header filter_cmd_hdr;
5567 struct eth_filter_cmd filter_cmds[ETH_FILTER_RULES_COUNT];
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005568};
5569
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005570/* Ramrod data for vport start ramrod */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005571struct vport_start_ramrod_data {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005572 u8 vport_id;
5573 u8 sw_fid;
5574 __le16 mtu;
5575 u8 drop_ttl0_en;
5576 u8 inner_vlan_removal_en;
5577 struct eth_vport_rx_mode rx_mode;
5578 struct eth_vport_tx_mode tx_mode;
5579 struct eth_vport_tpa_param tpa_param;
5580 __le16 default_vlan;
5581 u8 tx_switching_en;
5582 u8 anti_spoofing_en;
5583
5584 u8 default_vlan_en;
5585
5586 u8 handle_ptp_pkts;
5587 u8 silent_vlan_removal_en;
5588 u8 untagged;
5589 struct eth_tx_err_vals tx_err_behav;
5590
5591 u8 zero_placement_offset;
5592 u8 ctl_frame_mac_check_en;
5593 u8 ctl_frame_ethtype_check_en;
5594 u8 reserved[5];
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005595};
5596
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005597/* Ramrod data for vport stop ramrod */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005598struct vport_stop_ramrod_data {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005599 u8 vport_id;
5600 u8 reserved[7];
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005601};
5602
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005603/* Ramrod data for vport update ramrod */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005604struct vport_update_ramrod_data_cmn {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005605 u8 vport_id;
5606 u8 update_rx_active_flg;
5607 u8 rx_active_flg;
5608 u8 update_tx_active_flg;
5609 u8 tx_active_flg;
5610 u8 update_rx_mode_flg;
5611 u8 update_tx_mode_flg;
5612 u8 update_approx_mcast_flg;
5613
5614 u8 update_rss_flg;
5615 u8 update_inner_vlan_removal_en_flg;
5616
5617 u8 inner_vlan_removal_en;
5618 u8 update_tpa_param_flg;
5619 u8 update_tpa_en_flg;
5620 u8 update_tx_switching_en_flg;
5621
5622 u8 tx_switching_en;
5623 u8 update_anti_spoofing_en_flg;
5624
5625 u8 anti_spoofing_en;
5626 u8 update_handle_ptp_pkts;
5627
5628 u8 handle_ptp_pkts;
5629 u8 update_default_vlan_en_flg;
5630
5631 u8 default_vlan_en;
5632
5633 u8 update_default_vlan_flg;
5634
5635 __le16 default_vlan;
5636 u8 update_accept_any_vlan_flg;
5637
5638 u8 accept_any_vlan;
5639 u8 silent_vlan_removal_en;
5640 u8 update_mtu_flg;
5641
5642 __le16 mtu;
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02005643 u8 update_ctl_frame_checks_en_flg;
5644 u8 ctl_frame_mac_check_en;
5645 u8 ctl_frame_ethtype_check_en;
5646 u8 reserved[15];
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005647};
5648
5649struct vport_update_ramrod_mcast {
5650 __le32 bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
5651};
5652
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005653/* Ramrod data for vport update ramrod */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05005654struct vport_update_ramrod_data {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03005655 struct vport_update_ramrod_data_cmn common;
5656
5657 struct eth_vport_rx_mode rx_mode;
5658 struct eth_vport_tx_mode tx_mode;
5659 struct eth_vport_tpa_param tpa_param;
5660 struct vport_update_ramrod_mcast approx_mcast;
5661 struct eth_vport_rss_config rss_config;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02005662};
5663
Tomer Tayar21dd79e2017-12-27 19:30:06 +02005664struct e4_xstorm_eth_conn_ag_ctx_dq_ext_ldpart {
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02005665 u8 reserved0;
5666 u8 eth_state;
5667 u8 flags0;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02005668#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1
5669#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0
5670#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_MASK 0x1
5671#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_SHIFT 1
5672#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_MASK 0x1
5673#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_SHIFT 2
5674#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1
5675#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3
5676#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_MASK 0x1
5677#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_SHIFT 4
5678#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_MASK 0x1
5679#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_SHIFT 5
5680#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_MASK 0x1
5681#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_SHIFT 6
5682#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_MASK 0x1
5683#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_SHIFT 7
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02005684 u8 flags1;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02005685#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_MASK 0x1
5686#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_SHIFT 0
5687#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_MASK 0x1
5688#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_SHIFT 1
5689#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_MASK 0x1
5690#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_SHIFT 2
5691#define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_MASK 0x1
5692#define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_SHIFT 3
5693#define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT12_MASK 0x1
5694#define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT12_SHIFT 4
5695#define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT13_MASK 0x1
5696#define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT13_SHIFT 5
5697#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_MASK 0x1
5698#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_SHIFT 6
5699#define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_MASK 0x1
5700#define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_SHIFT 7
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02005701 u8 flags2;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02005702#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_MASK 0x3
5703#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_SHIFT 0
5704#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_MASK 0x3
5705#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_SHIFT 2
5706#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_MASK 0x3
5707#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_SHIFT 4
5708#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_MASK 0x3
5709#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_SHIFT 6
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02005710 u8 flags3;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02005711#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_MASK 0x3
5712#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_SHIFT 0
5713#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_MASK 0x3
5714#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_SHIFT 2
5715#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_MASK 0x3
5716#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_SHIFT 4
5717#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_MASK 0x3
5718#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_SHIFT 6
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02005719 u8 flags4;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02005720#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_MASK 0x3
5721#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_SHIFT 0
5722#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_MASK 0x3
5723#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_SHIFT 2
5724#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_MASK 0x3
5725#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_SHIFT 4
5726#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_MASK 0x3
5727#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_SHIFT 6
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02005728 u8 flags5;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02005729#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_MASK 0x3
5730#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_SHIFT 0
5731#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_MASK 0x3
5732#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_SHIFT 2
5733#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_MASK 0x3
5734#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_SHIFT 4
5735#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_MASK 0x3
5736#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_SHIFT 6
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02005737 u8 flags6;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02005738#define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_MASK 0x3
5739#define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_SHIFT 0
5740#define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_MASK 0x3
5741#define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_SHIFT 2
5742#define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_MASK 0x3
5743#define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_SHIFT 4
5744#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_MASK 0x3
5745#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_SHIFT 6
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02005746 u8 flags7;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02005747#define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_MASK 0x3
5748#define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_SHIFT 0
5749#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_MASK 0x3
5750#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_SHIFT 2
5751#define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3
5752#define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4
5753#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1
5754#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6
5755#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1
5756#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02005757 u8 flags8;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02005758#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1
5759#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0
5760#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1
5761#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1
5762#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1
5763#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2
5764#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1
5765#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3
5766#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1
5767#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4
5768#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_MASK 0x1
5769#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_SHIFT 5
5770#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1
5771#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6
5772#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1
5773#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02005774 u8 flags9;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02005775#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1
5776#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0
5777#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1
5778#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1
5779#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1
5780#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2
5781#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1
5782#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3
5783#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1
5784#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4
5785#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1
5786#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5
5787#define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_MASK 0x1
5788#define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_SHIFT 6
5789#define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_MASK 0x1
5790#define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_SHIFT 7
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02005791 u8 flags10;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02005792#define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_MASK 0x1
5793#define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_SHIFT 0
5794#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_MASK 0x1
5795#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_SHIFT 1
5796#define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_MASK 0x1
5797#define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_SHIFT 2
5798#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_MASK 0x1
5799#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_SHIFT 3
5800#define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1
5801#define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4
5802#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_MASK 0x1
5803#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_SHIFT 5
5804#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_MASK 0x1
5805#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_SHIFT 6
5806#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_MASK 0x1
5807#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_SHIFT 7
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02005808 u8 flags11;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02005809#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_MASK 0x1
5810#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_SHIFT 0
5811#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_MASK 0x1
5812#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_SHIFT 1
5813#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_MASK 0x1
5814#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_SHIFT 2
5815#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1
5816#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3
5817#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1
5818#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4
5819#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1
5820#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5
5821#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1
5822#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6
5823#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1
5824#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02005825 u8 flags12;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02005826#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1
5827#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0
5828#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1
5829#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1
5830#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1
5831#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2
5832#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1
5833#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3
5834#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1
5835#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4
5836#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1
5837#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5
5838#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1
5839#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6
5840#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1
5841#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02005842 u8 flags13;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02005843#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1
5844#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0
5845#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1
5846#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1
5847#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1
5848#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2
5849#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1
5850#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3
5851#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1
5852#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4
5853#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1
5854#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5
5855#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1
5856#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6
5857#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1
5858#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02005859 u8 flags14;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02005860#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_MASK 0x1
5861#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_SHIFT 0
5862#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_MASK 0x1
5863#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_SHIFT 1
5864#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_MASK 0x1
5865#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_SHIFT 2
5866#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_MASK 0x1
5867#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_SHIFT 3
5868#define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_MASK 0x1
5869#define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_SHIFT 4
5870#define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1
5871#define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5
5872#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_MASK 0x3
5873#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_SHIFT 6
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02005874 u8 edpm_event_id;
5875 __le16 physical_q0;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02005876 __le16 e5_reserved1;
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02005877 __le16 edpm_num_bds;
5878 __le16 tx_bd_cons;
5879 __le16 tx_bd_prod;
5880 __le16 tx_class;
5881 __le16 conn_dpi;
5882 u8 byte3;
5883 u8 byte4;
5884 u8 byte5;
5885 u8 byte6;
5886 __le32 reg0;
5887 __le32 reg1;
5888 __le32 reg2;
5889 __le32 reg3;
5890 __le32 reg4;
5891};
5892
Tomer Tayar21dd79e2017-12-27 19:30:06 +02005893struct e4_mstorm_eth_conn_ag_ctx {
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03005894 u8 byte0;
5895 u8 byte1;
5896 u8 flags0;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02005897#define E4_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
5898#define E4_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
5899#define E4_MSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
5900#define E4_MSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
5901#define E4_MSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
5902#define E4_MSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 2
5903#define E4_MSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
5904#define E4_MSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 4
5905#define E4_MSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
5906#define E4_MSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03005907 u8 flags1;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02005908#define E4_MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
5909#define E4_MSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 0
5910#define E4_MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
5911#define E4_MSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 1
5912#define E4_MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
5913#define E4_MSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
5914#define E4_MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
5915#define E4_MSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3
5916#define E4_MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
5917#define E4_MSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4
5918#define E4_MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
5919#define E4_MSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5
5920#define E4_MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
5921#define E4_MSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6
5922#define E4_MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
5923#define E4_MSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03005924 __le16 word0;
5925 __le16 word1;
5926 __le32 reg0;
5927 __le32 reg1;
5928};
5929
Tomer Tayar21dd79e2017-12-27 19:30:06 +02005930struct e4_xstorm_eth_hw_conn_ag_ctx {
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02005931 u8 reserved0;
5932 u8 eth_state;
5933 u8 flags0;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02005934#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
5935#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
5936#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK 0x1
5937#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_SHIFT 1
5938#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK 0x1
5939#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_SHIFT 2
5940#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
5941#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
5942#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK 0x1
5943#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_SHIFT 4
5944#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK 0x1
5945#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_SHIFT 5
5946#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK 0x1
5947#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_SHIFT 6
5948#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK 0x1
5949#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_SHIFT 7
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02005950 u8 flags1;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02005951#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK 0x1
5952#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_SHIFT 0
5953#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK 0x1
5954#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_SHIFT 1
5955#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK 0x1
5956#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_SHIFT 2
5957#define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK 0x1
5958#define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT11_SHIFT 3
5959#define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT12_MASK 0x1
5960#define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT12_SHIFT 4
5961#define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT13_MASK 0x1
5962#define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT13_SHIFT 5
5963#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
5964#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
5965#define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
5966#define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02005967 u8 flags2;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02005968#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK 0x3
5969#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0_SHIFT 0
5970#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK 0x3
5971#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1_SHIFT 2
5972#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK 0x3
5973#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2_SHIFT 4
5974#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK 0x3
5975#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3_SHIFT 6
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02005976 u8 flags3;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02005977#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK 0x3
5978#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4_SHIFT 0
5979#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK 0x3
5980#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5_SHIFT 2
5981#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK 0x3
5982#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6_SHIFT 4
5983#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK 0x3
5984#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7_SHIFT 6
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02005985 u8 flags4;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02005986#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK 0x3
5987#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8_SHIFT 0
5988#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK 0x3
5989#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9_SHIFT 2
5990#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK 0x3
5991#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10_SHIFT 4
5992#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK 0x3
5993#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11_SHIFT 6
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02005994 u8 flags5;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02005995#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK 0x3
5996#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12_SHIFT 0
5997#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK 0x3
5998#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13_SHIFT 2
5999#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK 0x3
6000#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14_SHIFT 4
6001#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK 0x3
6002#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15_SHIFT 6
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02006003 u8 flags6;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02006004#define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3
6005#define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0
6006#define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
6007#define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2
6008#define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK 0x3
6009#define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_SHIFT 4
6010#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
6011#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02006012 u8 flags7;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02006013#define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
6014#define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
6015#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK 0x3
6016#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_SHIFT 2
6017#define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK 0x3
6018#define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_SHIFT 4
6019#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK 0x1
6020#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_SHIFT 6
6021#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK 0x1
6022#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_SHIFT 7
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02006023 u8 flags8;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02006024#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK 0x1
6025#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_SHIFT 0
6026#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK 0x1
6027#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_SHIFT 1
6028#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK 0x1
6029#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_SHIFT 2
6030#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK 0x1
6031#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_SHIFT 3
6032#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK 0x1
6033#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_SHIFT 4
6034#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK 0x1
6035#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_SHIFT 5
6036#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK 0x1
6037#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_SHIFT 6
6038#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK 0x1
6039#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_SHIFT 7
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02006040 u8 flags9;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02006041#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK 0x1
6042#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_SHIFT 0
6043#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK 0x1
6044#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_SHIFT 1
6045#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK 0x1
6046#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_SHIFT 2
6047#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK 0x1
6048#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_SHIFT 3
6049#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK 0x1
6050#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_SHIFT 4
6051#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK 0x1
6052#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_SHIFT 5
6053#define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1
6054#define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6
6055#define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
6056#define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02006057 u8 flags10;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02006058#define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
6059#define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
6060#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
6061#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
6062#define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
6063#define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
6064#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK 0x1
6065#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_SHIFT 3
6066#define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
6067#define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
6068#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1
6069#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
6070#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK 0x1
6071#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_SHIFT 6
6072#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK 0x1
6073#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_SHIFT 7
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02006074 u8 flags11;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02006075#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK 0x1
6076#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_SHIFT 0
6077#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK 0x1
6078#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_SHIFT 1
6079#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
6080#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
6081#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK 0x1
6082#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_SHIFT 3
6083#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK 0x1
6084#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_SHIFT 4
6085#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK 0x1
6086#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_SHIFT 5
6087#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
6088#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
6089#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK 0x1
6090#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_SHIFT 7
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02006091 u8 flags12;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02006092#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK 0x1
6093#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_SHIFT 0
6094#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK 0x1
6095#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_SHIFT 1
6096#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
6097#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
6098#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
6099#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
6100#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK 0x1
6101#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_SHIFT 4
6102#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK 0x1
6103#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_SHIFT 5
6104#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK 0x1
6105#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_SHIFT 6
6106#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK 0x1
6107#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_SHIFT 7
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02006108 u8 flags13;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02006109#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK 0x1
6110#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_SHIFT 0
6111#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK 0x1
6112#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_SHIFT 1
6113#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
6114#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
6115#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
6116#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
6117#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
6118#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
6119#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
6120#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
6121#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
6122#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
6123#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
6124#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02006125 u8 flags14;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02006126#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1
6127#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0
6128#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1
6129#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1
6130#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1
6131#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2
6132#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1
6133#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3
6134#define E4_XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1
6135#define E4_XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4
6136#define E4_XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
6137#define E4_XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
6138#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK 0x3
6139#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_SHIFT 6
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02006140 u8 edpm_event_id;
6141 __le16 physical_q0;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02006142 __le16 e5_reserved1;
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02006143 __le16 edpm_num_bds;
6144 __le16 tx_bd_cons;
6145 __le16 tx_bd_prod;
6146 __le16 tx_class;
6147 __le16 conn_dpi;
6148};
6149
Tomer Tayara2e76992017-12-27 19:30:05 +02006150/* GFT CAM line struct */
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03006151struct gft_cam_line {
6152 __le32 camline;
6153#define GFT_CAM_LINE_VALID_MASK 0x1
6154#define GFT_CAM_LINE_VALID_SHIFT 0
6155#define GFT_CAM_LINE_DATA_MASK 0x3FFF
6156#define GFT_CAM_LINE_DATA_SHIFT 1
6157#define GFT_CAM_LINE_MASK_BITS_MASK 0x3FFF
6158#define GFT_CAM_LINE_MASK_BITS_SHIFT 15
6159#define GFT_CAM_LINE_RESERVED1_MASK 0x7
6160#define GFT_CAM_LINE_RESERVED1_SHIFT 29
6161};
6162
Tomer Tayara2e76992017-12-27 19:30:05 +02006163/* GFT CAM line struct with fields breakout */
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03006164struct gft_cam_line_mapped {
6165 __le32 camline;
6166#define GFT_CAM_LINE_MAPPED_VALID_MASK 0x1
6167#define GFT_CAM_LINE_MAPPED_VALID_SHIFT 0
6168#define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK 0x1
6169#define GFT_CAM_LINE_MAPPED_IP_VERSION_SHIFT 1
6170#define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK 0x1
6171#define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_SHIFT 2
6172#define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK 0xF
6173#define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_SHIFT 3
6174#define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK 0xF
6175#define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_SHIFT 7
6176#define GFT_CAM_LINE_MAPPED_PF_ID_MASK 0xF
6177#define GFT_CAM_LINE_MAPPED_PF_ID_SHIFT 11
6178#define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_MASK 0x1
6179#define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_SHIFT 15
6180#define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_MASK 0x1
6181#define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_SHIFT 16
6182#define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_MASK 0xF
6183#define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_SHIFT 17
6184#define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_MASK 0xF
6185#define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_SHIFT 21
6186#define GFT_CAM_LINE_MAPPED_PF_ID_MASK_MASK 0xF
6187#define GFT_CAM_LINE_MAPPED_PF_ID_MASK_SHIFT 25
6188#define GFT_CAM_LINE_MAPPED_RESERVED1_MASK 0x7
6189#define GFT_CAM_LINE_MAPPED_RESERVED1_SHIFT 29
6190};
6191
6192union gft_cam_line_union {
6193 struct gft_cam_line cam_line;
6194 struct gft_cam_line_mapped cam_line_mapped;
6195};
6196
Tomer Tayara2e76992017-12-27 19:30:05 +02006197/* Used in gft_profile_key: Indication for ip version */
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03006198enum gft_profile_ip_version {
6199 GFT_PROFILE_IPV4 = 0,
6200 GFT_PROFILE_IPV6 = 1,
6201 MAX_GFT_PROFILE_IP_VERSION
6202};
6203
Tomer Tayara2e76992017-12-27 19:30:05 +02006204/* Profile key stucr fot GFT logic in Prs */
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03006205struct gft_profile_key {
6206 __le16 profile_key;
Tomer Tayara2e76992017-12-27 19:30:05 +02006207#define GFT_PROFILE_KEY_IP_VERSION_MASK 0x1
6208#define GFT_PROFILE_KEY_IP_VERSION_SHIFT 0
6209#define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_MASK 0x1
6210#define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_SHIFT 1
6211#define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_MASK 0xF
6212#define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_SHIFT 2
6213#define GFT_PROFILE_KEY_TUNNEL_TYPE_MASK 0xF
6214#define GFT_PROFILE_KEY_TUNNEL_TYPE_SHIFT 6
6215#define GFT_PROFILE_KEY_PF_ID_MASK 0xF
6216#define GFT_PROFILE_KEY_PF_ID_SHIFT 10
6217#define GFT_PROFILE_KEY_RESERVED0_MASK 0x3
6218#define GFT_PROFILE_KEY_RESERVED0_SHIFT 14
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03006219};
6220
Tomer Tayara2e76992017-12-27 19:30:05 +02006221/* Used in gft_profile_key: Indication for tunnel type */
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03006222enum gft_profile_tunnel_type {
6223 GFT_PROFILE_NO_TUNNEL = 0,
6224 GFT_PROFILE_VXLAN_TUNNEL = 1,
6225 GFT_PROFILE_GRE_MAC_OR_NVGRE_TUNNEL = 2,
6226 GFT_PROFILE_GRE_IP_TUNNEL = 3,
6227 GFT_PROFILE_GENEVE_MAC_TUNNEL = 4,
6228 GFT_PROFILE_GENEVE_IP_TUNNEL = 5,
6229 MAX_GFT_PROFILE_TUNNEL_TYPE
6230};
6231
Tomer Tayara2e76992017-12-27 19:30:05 +02006232/* Used in gft_profile_key: Indication for protocol type */
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03006233enum gft_profile_upper_protocol_type {
6234 GFT_PROFILE_ROCE_PROTOCOL = 0,
6235 GFT_PROFILE_RROCE_PROTOCOL = 1,
6236 GFT_PROFILE_FCOE_PROTOCOL = 2,
6237 GFT_PROFILE_ICMP_PROTOCOL = 3,
6238 GFT_PROFILE_ARP_PROTOCOL = 4,
6239 GFT_PROFILE_USER_TCP_SRC_PORT_1_INNER = 5,
6240 GFT_PROFILE_USER_TCP_DST_PORT_1_INNER = 6,
6241 GFT_PROFILE_TCP_PROTOCOL = 7,
6242 GFT_PROFILE_USER_UDP_DST_PORT_1_INNER = 8,
6243 GFT_PROFILE_USER_UDP_DST_PORT_2_OUTER = 9,
6244 GFT_PROFILE_UDP_PROTOCOL = 10,
6245 GFT_PROFILE_USER_IP_1_INNER = 11,
6246 GFT_PROFILE_USER_IP_2_OUTER = 12,
6247 GFT_PROFILE_USER_ETH_1_INNER = 13,
6248 GFT_PROFILE_USER_ETH_2_OUTER = 14,
6249 GFT_PROFILE_RAW = 15,
6250 MAX_GFT_PROFILE_UPPER_PROTOCOL_TYPE
6251};
6252
Tomer Tayara2e76992017-12-27 19:30:05 +02006253/* GFT RAM line struct */
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03006254struct gft_ram_line {
6255 __le32 lo;
6256#define GFT_RAM_LINE_VLAN_SELECT_MASK 0x3
6257#define GFT_RAM_LINE_VLAN_SELECT_SHIFT 0
6258#define GFT_RAM_LINE_TUNNEL_ENTROPHY_MASK 0x1
6259#define GFT_RAM_LINE_TUNNEL_ENTROPHY_SHIFT 2
6260#define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_MASK 0x1
6261#define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_SHIFT 3
6262#define GFT_RAM_LINE_TUNNEL_TTL_MASK 0x1
6263#define GFT_RAM_LINE_TUNNEL_TTL_SHIFT 4
6264#define GFT_RAM_LINE_TUNNEL_ETHERTYPE_MASK 0x1
6265#define GFT_RAM_LINE_TUNNEL_ETHERTYPE_SHIFT 5
6266#define GFT_RAM_LINE_TUNNEL_DST_PORT_MASK 0x1
6267#define GFT_RAM_LINE_TUNNEL_DST_PORT_SHIFT 6
6268#define GFT_RAM_LINE_TUNNEL_SRC_PORT_MASK 0x1
6269#define GFT_RAM_LINE_TUNNEL_SRC_PORT_SHIFT 7
6270#define GFT_RAM_LINE_TUNNEL_DSCP_MASK 0x1
6271#define GFT_RAM_LINE_TUNNEL_DSCP_SHIFT 8
6272#define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_MASK 0x1
6273#define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_SHIFT 9
6274#define GFT_RAM_LINE_TUNNEL_DST_IP_MASK 0x1
6275#define GFT_RAM_LINE_TUNNEL_DST_IP_SHIFT 10
6276#define GFT_RAM_LINE_TUNNEL_SRC_IP_MASK 0x1
6277#define GFT_RAM_LINE_TUNNEL_SRC_IP_SHIFT 11
6278#define GFT_RAM_LINE_TUNNEL_PRIORITY_MASK 0x1
6279#define GFT_RAM_LINE_TUNNEL_PRIORITY_SHIFT 12
6280#define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_MASK 0x1
6281#define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_SHIFT 13
6282#define GFT_RAM_LINE_TUNNEL_VLAN_MASK 0x1
6283#define GFT_RAM_LINE_TUNNEL_VLAN_SHIFT 14
6284#define GFT_RAM_LINE_TUNNEL_DST_MAC_MASK 0x1
6285#define GFT_RAM_LINE_TUNNEL_DST_MAC_SHIFT 15
6286#define GFT_RAM_LINE_TUNNEL_SRC_MAC_MASK 0x1
6287#define GFT_RAM_LINE_TUNNEL_SRC_MAC_SHIFT 16
6288#define GFT_RAM_LINE_TTL_EQUAL_ONE_MASK 0x1
6289#define GFT_RAM_LINE_TTL_EQUAL_ONE_SHIFT 17
6290#define GFT_RAM_LINE_TTL_MASK 0x1
6291#define GFT_RAM_LINE_TTL_SHIFT 18
6292#define GFT_RAM_LINE_ETHERTYPE_MASK 0x1
6293#define GFT_RAM_LINE_ETHERTYPE_SHIFT 19
6294#define GFT_RAM_LINE_RESERVED0_MASK 0x1
6295#define GFT_RAM_LINE_RESERVED0_SHIFT 20
6296#define GFT_RAM_LINE_TCP_FLAG_FIN_MASK 0x1
6297#define GFT_RAM_LINE_TCP_FLAG_FIN_SHIFT 21
6298#define GFT_RAM_LINE_TCP_FLAG_SYN_MASK 0x1
6299#define GFT_RAM_LINE_TCP_FLAG_SYN_SHIFT 22
6300#define GFT_RAM_LINE_TCP_FLAG_RST_MASK 0x1
6301#define GFT_RAM_LINE_TCP_FLAG_RST_SHIFT 23
6302#define GFT_RAM_LINE_TCP_FLAG_PSH_MASK 0x1
6303#define GFT_RAM_LINE_TCP_FLAG_PSH_SHIFT 24
6304#define GFT_RAM_LINE_TCP_FLAG_ACK_MASK 0x1
6305#define GFT_RAM_LINE_TCP_FLAG_ACK_SHIFT 25
6306#define GFT_RAM_LINE_TCP_FLAG_URG_MASK 0x1
6307#define GFT_RAM_LINE_TCP_FLAG_URG_SHIFT 26
6308#define GFT_RAM_LINE_TCP_FLAG_ECE_MASK 0x1
6309#define GFT_RAM_LINE_TCP_FLAG_ECE_SHIFT 27
6310#define GFT_RAM_LINE_TCP_FLAG_CWR_MASK 0x1
6311#define GFT_RAM_LINE_TCP_FLAG_CWR_SHIFT 28
6312#define GFT_RAM_LINE_TCP_FLAG_NS_MASK 0x1
6313#define GFT_RAM_LINE_TCP_FLAG_NS_SHIFT 29
6314#define GFT_RAM_LINE_DST_PORT_MASK 0x1
6315#define GFT_RAM_LINE_DST_PORT_SHIFT 30
6316#define GFT_RAM_LINE_SRC_PORT_MASK 0x1
6317#define GFT_RAM_LINE_SRC_PORT_SHIFT 31
6318 __le32 hi;
6319#define GFT_RAM_LINE_DSCP_MASK 0x1
6320#define GFT_RAM_LINE_DSCP_SHIFT 0
6321#define GFT_RAM_LINE_OVER_IP_PROTOCOL_MASK 0x1
6322#define GFT_RAM_LINE_OVER_IP_PROTOCOL_SHIFT 1
6323#define GFT_RAM_LINE_DST_IP_MASK 0x1
6324#define GFT_RAM_LINE_DST_IP_SHIFT 2
6325#define GFT_RAM_LINE_SRC_IP_MASK 0x1
6326#define GFT_RAM_LINE_SRC_IP_SHIFT 3
6327#define GFT_RAM_LINE_PRIORITY_MASK 0x1
6328#define GFT_RAM_LINE_PRIORITY_SHIFT 4
6329#define GFT_RAM_LINE_PROVIDER_VLAN_MASK 0x1
6330#define GFT_RAM_LINE_PROVIDER_VLAN_SHIFT 5
6331#define GFT_RAM_LINE_VLAN_MASK 0x1
6332#define GFT_RAM_LINE_VLAN_SHIFT 6
6333#define GFT_RAM_LINE_DST_MAC_MASK 0x1
6334#define GFT_RAM_LINE_DST_MAC_SHIFT 7
6335#define GFT_RAM_LINE_SRC_MAC_MASK 0x1
6336#define GFT_RAM_LINE_SRC_MAC_SHIFT 8
6337#define GFT_RAM_LINE_TENANT_ID_MASK 0x1
6338#define GFT_RAM_LINE_TENANT_ID_SHIFT 9
6339#define GFT_RAM_LINE_RESERVED1_MASK 0x3FFFFF
6340#define GFT_RAM_LINE_RESERVED1_SHIFT 10
6341};
6342
Tomer Tayara2e76992017-12-27 19:30:05 +02006343/* Used in the first 2 bits for gft_ram_line: Indication for vlan mask */
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03006344enum gft_vlan_select {
6345 INNER_PROVIDER_VLAN = 0,
6346 INNER_VLAN = 1,
6347 OUTER_PROVIDER_VLAN = 2,
6348 OUTER_VLAN = 3,
6349 MAX_GFT_VLAN_SELECT
6350};
6351
Tomer Tayara2e76992017-12-27 19:30:05 +02006352/* The rdma task context of Mstorm */
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03006353struct ystorm_rdma_task_st_ctx {
6354 struct regpair temp[4];
6355};
6356
Tomer Tayar21dd79e2017-12-27 19:30:06 +02006357struct e4_ystorm_rdma_task_ag_ctx {
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03006358 u8 reserved;
6359 u8 byte1;
6360 __le16 msem_ctx_upd_seq;
6361 u8 flags0;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02006362#define E4_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
6363#define E4_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
6364#define E4_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
6365#define E4_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
6366#define E4_YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
6367#define E4_YSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
6368#define E4_YSTORM_RDMA_TASK_AG_CTX_VALID_MASK 0x1
6369#define E4_YSTORM_RDMA_TASK_AG_CTX_VALID_SHIFT 6
6370#define E4_YSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1
6371#define E4_YSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03006372 u8 flags1;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02006373#define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
6374#define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0
6375#define E4_YSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
6376#define E4_YSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2
6377#define E4_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK 0x3
6378#define E4_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_SHIFT 4
6379#define E4_YSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
6380#define E4_YSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6
6381#define E4_YSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
6382#define E4_YSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03006383 u8 flags2;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02006384#define E4_YSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1
6385#define E4_YSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0
6386#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
6387#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1
6388#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
6389#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2
6390#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
6391#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3
6392#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
6393#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4
6394#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
6395#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5
6396#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
6397#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6
6398#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
6399#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03006400 u8 key;
6401 __le32 mw_cnt;
6402 u8 ref_cnt_seq;
6403 u8 ctx_upd_seq;
6404 __le16 dif_flags;
6405 __le16 tx_ref_count;
6406 __le16 last_used_ltid;
6407 __le16 parent_mr_lo;
6408 __le16 parent_mr_hi;
6409 __le32 fbo_lo;
6410 __le32 fbo_hi;
6411};
6412
Tomer Tayar21dd79e2017-12-27 19:30:06 +02006413struct e4_mstorm_rdma_task_ag_ctx {
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03006414 u8 reserved;
6415 u8 byte1;
6416 __le16 icid;
6417 u8 flags0;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02006418#define E4_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
6419#define E4_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
6420#define E4_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
6421#define E4_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
6422#define E4_MSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
6423#define E4_MSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
6424#define E4_MSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1
6425#define E4_MSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6
6426#define E4_MSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1
6427#define E4_MSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03006428 u8 flags1;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02006429#define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
6430#define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0
6431#define E4_MSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
6432#define E4_MSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2
6433#define E4_MSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3
6434#define E4_MSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 4
6435#define E4_MSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
6436#define E4_MSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6
6437#define E4_MSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
6438#define E4_MSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03006439 u8 flags2;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02006440#define E4_MSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1
6441#define E4_MSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 0
6442#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
6443#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1
6444#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
6445#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2
6446#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
6447#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3
6448#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
6449#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4
6450#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
6451#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5
6452#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
6453#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6
6454#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
6455#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03006456 u8 key;
6457 __le32 mw_cnt;
6458 u8 ref_cnt_seq;
6459 u8 ctx_upd_seq;
6460 __le16 dif_flags;
6461 __le16 tx_ref_count;
6462 __le16 last_used_ltid;
6463 __le16 parent_mr_lo;
6464 __le16 parent_mr_hi;
6465 __le32 fbo_lo;
6466 __le32 fbo_hi;
6467};
6468
Tomer Tayara2e76992017-12-27 19:30:05 +02006469/* The roce task context of Mstorm */
6470struct mstorm_rdma_task_st_ctx {
6471 struct regpair temp[4];
6472};
6473
6474/* The roce task context of Ustorm */
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03006475struct ustorm_rdma_task_st_ctx {
6476 struct regpair temp[2];
6477};
6478
Tomer Tayar21dd79e2017-12-27 19:30:06 +02006479struct e4_ustorm_rdma_task_ag_ctx {
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03006480 u8 reserved;
6481 u8 byte1;
6482 __le16 icid;
6483 u8 flags0;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02006484#define E4_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
6485#define E4_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
6486#define E4_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
6487#define E4_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
6488#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_MASK 0x1
6489#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_SHIFT 5
6490#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK 0x3
6491#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03006492 u8 flags1;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02006493#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK 0x3
6494#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_SHIFT 0
6495#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK 0x3
6496#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_SHIFT 2
6497#define E4_USTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3
6498#define E4_USTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 4
6499#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3
6500#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03006501 u8 flags2;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02006502#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_MASK 0x1
6503#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_SHIFT 0
6504#define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED2_MASK 0x1
6505#define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED2_SHIFT 1
6506#define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED3_MASK 0x1
6507#define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED3_SHIFT 2
6508#define E4_USTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1
6509#define E4_USTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 3
6510#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
6511#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
6512#define E4_USTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
6513#define E4_USTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 5
6514#define E4_USTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
6515#define E4_USTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 6
6516#define E4_USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
6517#define E4_USTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03006518 u8 flags3;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02006519#define E4_USTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
6520#define E4_USTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 0
6521#define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
6522#define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 1
6523#define E4_USTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
6524#define E4_USTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 2
6525#define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
6526#define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 3
6527#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
6528#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03006529 __le32 dif_err_intervals;
6530 __le32 dif_error_1st_interval;
6531 __le32 reg2;
6532 __le32 dif_runt_value;
6533 __le32 reg4;
6534 __le32 reg5;
6535};
6536
Tomer Tayara2e76992017-12-27 19:30:05 +02006537/* RDMA task context */
Tomer Tayar21dd79e2017-12-27 19:30:06 +02006538struct e4_rdma_task_context {
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03006539 struct ystorm_rdma_task_st_ctx ystorm_st_context;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02006540 struct e4_ystorm_rdma_task_ag_ctx ystorm_ag_context;
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03006541 struct tdif_task_context tdif_context;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02006542 struct e4_mstorm_rdma_task_ag_ctx mstorm_ag_context;
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03006543 struct mstorm_rdma_task_st_ctx mstorm_st_context;
6544 struct rdif_task_context rdif_context;
6545 struct ustorm_rdma_task_st_ctx ustorm_st_context;
6546 struct regpair ustorm_st_padding[2];
Tomer Tayar21dd79e2017-12-27 19:30:06 +02006547 struct e4_ustorm_rdma_task_ag_ctx ustorm_ag_context;
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03006548};
6549
Tomer Tayara2e76992017-12-27 19:30:05 +02006550/* rdma function init ramrod data */
6551struct rdma_close_func_ramrod_data {
6552 u8 cnq_start_offset;
6553 u8 num_cnqs;
6554 u8 vf_id;
6555 u8 vf_valid;
6556 u8 reserved[4];
6557};
6558
6559/* rdma function init CNQ parameters */
6560struct rdma_cnq_params {
6561 __le16 sb_num;
6562 u8 sb_index;
6563 u8 num_pbl_pages;
6564 __le32 reserved;
6565 struct regpair pbl_base_addr;
6566 __le16 queue_zone_num;
6567 u8 reserved1[6];
6568};
6569
6570/* rdma create cq ramrod data */
6571struct rdma_create_cq_ramrod_data {
6572 struct regpair cq_handle;
6573 struct regpair pbl_addr;
6574 __le32 max_cqes;
6575 __le16 pbl_num_pages;
6576 __le16 dpi;
6577 u8 is_two_level_pbl;
6578 u8 cnq_id;
6579 u8 pbl_log_page_size;
6580 u8 toggle_bit;
6581 __le16 int_timeout;
6582 __le16 reserved1;
6583};
6584
6585/* rdma deregister tid ramrod data */
6586struct rdma_deregister_tid_ramrod_data {
6587 __le32 itid;
6588 __le32 reserved;
6589};
6590
6591/* rdma destroy cq output params */
6592struct rdma_destroy_cq_output_params {
6593 __le16 cnq_num;
6594 __le16 reserved0;
6595 __le32 reserved1;
6596};
6597
6598/* rdma destroy cq ramrod data */
6599struct rdma_destroy_cq_ramrod_data {
6600 struct regpair output_params_addr;
6601};
6602
6603/* RDMA slow path EQ cmd IDs */
6604enum rdma_event_opcode {
6605 RDMA_EVENT_UNUSED,
6606 RDMA_EVENT_FUNC_INIT,
6607 RDMA_EVENT_FUNC_CLOSE,
6608 RDMA_EVENT_REGISTER_MR,
6609 RDMA_EVENT_DEREGISTER_MR,
6610 RDMA_EVENT_CREATE_CQ,
6611 RDMA_EVENT_RESIZE_CQ,
6612 RDMA_EVENT_DESTROY_CQ,
6613 RDMA_EVENT_CREATE_SRQ,
6614 RDMA_EVENT_MODIFY_SRQ,
6615 RDMA_EVENT_DESTROY_SRQ,
6616 MAX_RDMA_EVENT_OPCODE
6617};
6618
6619/* RDMA FW return code for slow path ramrods */
6620enum rdma_fw_return_code {
6621 RDMA_RETURN_OK = 0,
6622 RDMA_RETURN_REGISTER_MR_BAD_STATE_ERR,
6623 RDMA_RETURN_DEREGISTER_MR_BAD_STATE_ERR,
6624 RDMA_RETURN_RESIZE_CQ_ERR,
6625 RDMA_RETURN_NIG_DRAIN_REQ,
6626 MAX_RDMA_FW_RETURN_CODE
6627};
6628
6629/* rdma function init header */
6630struct rdma_init_func_hdr {
6631 u8 cnq_start_offset;
6632 u8 num_cnqs;
6633 u8 cq_ring_mode;
6634 u8 vf_id;
6635 u8 vf_valid;
6636 u8 reserved[3];
6637};
6638
6639/* rdma function init ramrod data */
6640struct rdma_init_func_ramrod_data {
6641 struct rdma_init_func_hdr params_header;
6642 struct rdma_cnq_params cnq_params[NUM_OF_GLOBAL_QUEUES];
6643};
6644
6645/* RDMA ramrod command IDs */
6646enum rdma_ramrod_cmd_id {
6647 RDMA_RAMROD_UNUSED,
6648 RDMA_RAMROD_FUNC_INIT,
6649 RDMA_RAMROD_FUNC_CLOSE,
6650 RDMA_RAMROD_REGISTER_MR,
6651 RDMA_RAMROD_DEREGISTER_MR,
6652 RDMA_RAMROD_CREATE_CQ,
6653 RDMA_RAMROD_RESIZE_CQ,
6654 RDMA_RAMROD_DESTROY_CQ,
6655 RDMA_RAMROD_CREATE_SRQ,
6656 RDMA_RAMROD_MODIFY_SRQ,
6657 RDMA_RAMROD_DESTROY_SRQ,
6658 MAX_RDMA_RAMROD_CMD_ID
6659};
6660
6661/* rdma register tid ramrod data */
6662struct rdma_register_tid_ramrod_data {
6663 __le16 flags;
6664#define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_MASK 0x1F
6665#define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_SHIFT 0
6666#define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_MASK 0x1
6667#define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_SHIFT 5
6668#define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_MASK 0x1
6669#define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_SHIFT 6
6670#define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_MASK 0x1
6671#define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_SHIFT 7
6672#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_MASK 0x1
6673#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_SHIFT 8
6674#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_MASK 0x1
6675#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_SHIFT 9
6676#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_MASK 0x1
6677#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_SHIFT 10
6678#define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_MASK 0x1
6679#define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_SHIFT 11
6680#define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_MASK 0x1
6681#define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_SHIFT 12
6682#define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_MASK 0x1
6683#define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_SHIFT 13
6684#define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_MASK 0x3
6685#define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_SHIFT 14
6686 u8 flags1;
6687#define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_MASK 0x1F
6688#define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_SHIFT 0
6689#define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_MASK 0x7
6690#define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_SHIFT 5
6691 u8 flags2;
6692#define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_MASK 0x1
6693#define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_SHIFT 0
6694#define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_MASK 0x1
6695#define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_SHIFT 1
6696#define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_MASK 0x3F
6697#define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_SHIFT 2
6698 u8 key;
6699 u8 length_hi;
6700 u8 vf_id;
6701 u8 vf_valid;
6702 __le16 pd;
6703 __le16 reserved2;
6704 __le32 length_lo;
6705 __le32 itid;
6706 __le32 reserved3;
6707 struct regpair va;
6708 struct regpair pbl_base;
6709 struct regpair dif_error_addr;
6710 struct regpair dif_runt_addr;
6711 __le32 reserved4[2];
6712};
6713
6714/* rdma resize cq output params */
6715struct rdma_resize_cq_output_params {
6716 __le32 old_cq_cons;
6717 __le32 old_cq_prod;
6718};
6719
6720/* rdma resize cq ramrod data */
6721struct rdma_resize_cq_ramrod_data {
6722 u8 flags;
6723#define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_MASK 0x1
6724#define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_SHIFT 0
6725#define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_MASK 0x1
6726#define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_SHIFT 1
6727#define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_MASK 0x3F
6728#define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_SHIFT 2
6729 u8 pbl_log_page_size;
6730 __le16 pbl_num_pages;
6731 __le32 max_cqes;
6732 struct regpair pbl_addr;
6733 struct regpair output_params_addr;
6734};
6735
6736/* The rdma storm context of Mstorm */
6737struct rdma_srq_context {
6738 struct regpair temp[8];
6739};
6740
6741/* rdma create qp requester ramrod data */
6742struct rdma_srq_create_ramrod_data {
6743 struct regpair pbl_base_addr;
6744 __le16 pages_in_srq_pbl;
6745 __le16 pd_id;
6746 struct rdma_srq_id srq_id;
6747 __le16 page_size;
6748 __le16 reserved1;
6749 __le32 reserved2;
6750 struct regpair producers_addr;
6751};
6752
6753/* rdma create qp requester ramrod data */
6754struct rdma_srq_destroy_ramrod_data {
6755 struct rdma_srq_id srq_id;
6756 __le32 reserved;
6757};
6758
6759/* rdma create qp requester ramrod data */
6760struct rdma_srq_modify_ramrod_data {
6761 struct rdma_srq_id srq_id;
6762 __le32 wqe_limit;
6763};
6764
6765/* RDMA Tid type enumeration (for register_tid ramrod) */
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03006766enum rdma_tid_type {
6767 RDMA_TID_REGISTERED_MR,
6768 RDMA_TID_FMR,
6769 RDMA_TID_MW_TYPE1,
6770 RDMA_TID_MW_TYPE2A,
6771 MAX_RDMA_TID_TYPE
6772};
6773
Tomer Tayar21dd79e2017-12-27 19:30:06 +02006774struct e4_xstorm_roce_conn_ag_ctx_dq_ext_ld_part {
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03006775 u8 reserved0;
6776 u8 state;
6777 u8 flags0;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02006778#define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1
6779#define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0
6780#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_MASK 0x1
6781#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_SHIFT 1
6782#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_MASK 0x1
6783#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_SHIFT 2
6784#define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1
6785#define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3
6786#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_MASK 0x1
6787#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_SHIFT 4
6788#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_MASK 0x1
6789#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_SHIFT 5
6790#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_MASK 0x1
6791#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_SHIFT 6
6792#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_MASK 0x1
6793#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_SHIFT 7
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03006794 u8 flags1;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02006795#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_MASK 0x1
6796#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_SHIFT 0
6797#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_MASK 0x1
6798#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_SHIFT 1
6799#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_MASK 0x1
6800#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_SHIFT 2
6801#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK 0x1
6802#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_SHIFT 3
6803#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_MASK 0x1
6804#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_SHIFT 4
6805#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSTORM_FLUSH_MASK 0x1
6806#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSTORM_FLUSH_SHIFT 5
6807#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_MASK 0x1
6808#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_SHIFT 6
6809#define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK 0x1
6810#define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_SHIFT 7
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03006811 u8 flags2;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02006812#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_MASK 0x3
6813#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_SHIFT 0
6814#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_MASK 0x3
6815#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_SHIFT 2
6816#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_MASK 0x3
6817#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_SHIFT 4
6818#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_MASK 0x3
6819#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_SHIFT 6
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03006820 u8 flags3;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02006821#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_MASK 0x3
6822#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_SHIFT 0
6823#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_MASK 0x3
6824#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_SHIFT 2
6825#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_MASK 0x3
6826#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_SHIFT 4
6827#define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_MASK 0x3
6828#define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_SHIFT 6
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03006829 u8 flags4;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02006830#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_MASK 0x3
6831#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_SHIFT 0
6832#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_MASK 0x3
6833#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_SHIFT 2
6834#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_MASK 0x3
6835#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_SHIFT 4
6836#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_MASK 0x3
6837#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_SHIFT 6
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03006838 u8 flags5;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02006839#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_MASK 0x3
6840#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_SHIFT 0
6841#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_MASK 0x3
6842#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_SHIFT 2
6843#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_MASK 0x3
6844#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_SHIFT 4
6845#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_MASK 0x3
6846#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_SHIFT 6
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03006847 u8 flags6;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02006848#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_MASK 0x3
6849#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_SHIFT 0
6850#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_MASK 0x3
6851#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_SHIFT 2
6852#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_MASK 0x3
6853#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_SHIFT 4
6854#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_MASK 0x3
6855#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_SHIFT 6
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03006856 u8 flags7;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02006857#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_MASK 0x3
6858#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_SHIFT 0
6859#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_MASK 0x3
6860#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_SHIFT 2
6861#define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3
6862#define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4
6863#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1
6864#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6
6865#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1
6866#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03006867 u8 flags8;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02006868#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1
6869#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0
6870#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1
6871#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1
6872#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1
6873#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2
6874#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1
6875#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3
6876#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1
6877#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4
6878#define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_MASK 0x1
6879#define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_SHIFT 5
6880#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1
6881#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6
6882#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1
6883#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03006884 u8 flags9;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02006885#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1
6886#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0
6887#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1
6888#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1
6889#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1
6890#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2
6891#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1
6892#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3
6893#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1
6894#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4
6895#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1
6896#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5
6897#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_MASK 0x1
6898#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_SHIFT 6
6899#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_MASK 0x1
6900#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_SHIFT 7
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03006901 u8 flags10;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02006902#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_MASK 0x1
6903#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_SHIFT 0
6904#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_MASK 0x1
6905#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_SHIFT 1
6906#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_MASK 0x1
6907#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_SHIFT 2
6908#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_MASK 0x1
6909#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_SHIFT 3
6910#define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1
6911#define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4
6912#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_MASK 0x1
6913#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_SHIFT 5
6914#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_MASK 0x1
6915#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_SHIFT 6
6916#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_MASK 0x1
6917#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_SHIFT 7
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03006918 u8 flags11;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02006919#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_MASK 0x1
6920#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_SHIFT 0
6921#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_MASK 0x1
6922#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_SHIFT 1
6923#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_MASK 0x1
6924#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_SHIFT 2
6925#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1
6926#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3
6927#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1
6928#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4
6929#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1
6930#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5
6931#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1
6932#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6
6933#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1
6934#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03006935 u8 flags12;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02006936#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1
6937#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0
6938#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1
6939#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1
6940#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1
6941#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2
6942#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1
6943#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3
6944#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1
6945#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4
6946#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1
6947#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5
6948#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1
6949#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6
6950#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1
6951#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03006952 u8 flags13;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02006953#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1
6954#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0
6955#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1
6956#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1
6957#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1
6958#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2
6959#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1
6960#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3
6961#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1
6962#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4
6963#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1
6964#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5
6965#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1
6966#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6
6967#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1
6968#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03006969 u8 flags14;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02006970#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_MASK 0x1
6971#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_SHIFT 0
6972#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_MASK 0x1
6973#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_SHIFT 1
6974#define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_MASK 0x3
6975#define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_SHIFT 2
6976#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_MASK 0x1
6977#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_SHIFT 4
6978#define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1
6979#define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5
6980#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_MASK 0x3
6981#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_SHIFT 6
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03006982 u8 byte2;
6983 __le16 physical_q0;
6984 __le16 word1;
6985 __le16 word2;
6986 __le16 word3;
6987 __le16 word4;
6988 __le16 word5;
6989 __le16 conn_dpi;
6990 u8 byte3;
6991 u8 byte4;
6992 u8 byte5;
6993 u8 byte6;
6994 __le32 reg0;
6995 __le32 reg1;
6996 __le32 reg2;
6997 __le32 snd_nxt_psn;
6998 __le32 reg4;
6999};
7000
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007001struct e4_mstorm_rdma_conn_ag_ctx {
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007002 u8 byte0;
7003 u8 byte1;
7004 u8 flags0;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007005#define E4_MSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1
7006#define E4_MSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0
7007#define E4_MSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1
7008#define E4_MSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
7009#define E4_MSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3
7010#define E4_MSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2
7011#define E4_MSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
7012#define E4_MSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4
7013#define E4_MSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
7014#define E4_MSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007015 u8 flags1;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007016#define E4_MSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1
7017#define E4_MSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0
7018#define E4_MSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
7019#define E4_MSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1
7020#define E4_MSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
7021#define E4_MSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2
7022#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1
7023#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3
7024#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1
7025#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4
7026#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
7027#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5
7028#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
7029#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6
7030#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
7031#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007032 __le16 word0;
7033 __le16 word1;
7034 __le32 reg0;
7035 __le32 reg1;
7036};
7037
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007038struct e4_tstorm_rdma_conn_ag_ctx {
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007039 u8 reserved0;
7040 u8 byte1;
7041 u8 flags0;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007042#define E4_TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
7043#define E4_TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
7044#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1
7045#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
7046#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1
7047#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2
7048#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT3_MASK 0x1
7049#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT3_SHIFT 3
7050#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1
7051#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4
7052#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1
7053#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5
7054#define E4_TSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3
7055#define E4_TSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007056 u8 flags1;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007057#define E4_TSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
7058#define E4_TSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 0
7059#define E4_TSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
7060#define E4_TSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 2
7061#define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
7062#define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4
7063#define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
7064#define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007065 u8 flags2;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007066#define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
7067#define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
7068#define E4_TSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3
7069#define E4_TSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 2
7070#define E4_TSTORM_RDMA_CONN_AG_CTX_CF7_MASK 0x3
7071#define E4_TSTORM_RDMA_CONN_AG_CTX_CF7_SHIFT 4
7072#define E4_TSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3
7073#define E4_TSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007074 u8 flags3;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007075#define E4_TSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3
7076#define E4_TSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 0
7077#define E4_TSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3
7078#define E4_TSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 2
7079#define E4_TSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1
7080#define E4_TSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 4
7081#define E4_TSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
7082#define E4_TSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 5
7083#define E4_TSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
7084#define E4_TSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 6
7085#define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
7086#define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007087 u8 flags4;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007088#define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
7089#define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
7090#define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
7091#define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1
7092#define E4_TSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1
7093#define E4_TSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 2
7094#define E4_TSTORM_RDMA_CONN_AG_CTX_CF7EN_MASK 0x1
7095#define E4_TSTORM_RDMA_CONN_AG_CTX_CF7EN_SHIFT 3
7096#define E4_TSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1
7097#define E4_TSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 4
7098#define E4_TSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1
7099#define E4_TSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 5
7100#define E4_TSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1
7101#define E4_TSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 6
7102#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1
7103#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007104 u8 flags5;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007105#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1
7106#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 0
7107#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
7108#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1
7109#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
7110#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2
7111#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
7112#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3
7113#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1
7114#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4
7115#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1
7116#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5
7117#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1
7118#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6
7119#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1
7120#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007121 __le32 reg0;
7122 __le32 reg1;
7123 __le32 reg2;
7124 __le32 reg3;
7125 __le32 reg4;
7126 __le32 reg5;
7127 __le32 reg6;
7128 __le32 reg7;
7129 __le32 reg8;
7130 u8 byte2;
7131 u8 byte3;
7132 __le16 word0;
7133 u8 byte4;
7134 u8 byte5;
7135 __le16 word1;
7136 __le16 word2;
7137 __le16 word3;
7138 __le32 reg9;
7139 __le32 reg10;
7140};
7141
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007142struct e4_tstorm_rdma_task_ag_ctx {
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007143 u8 byte0;
7144 u8 byte1;
7145 __le16 word0;
7146 u8 flags0;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007147#define E4_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_MASK 0xF
7148#define E4_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_SHIFT 0
7149#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT0_MASK 0x1
7150#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT0_SHIFT 4
7151#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
7152#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
7153#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1
7154#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6
7155#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1
7156#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007157 u8 flags1;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007158#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1
7159#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0
7160#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT5_MASK 0x1
7161#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT5_SHIFT 1
7162#define E4_TSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
7163#define E4_TSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 2
7164#define E4_TSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
7165#define E4_TSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 4
7166#define E4_TSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3
7167#define E4_TSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007168 u8 flags2;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007169#define E4_TSTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3
7170#define E4_TSTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 0
7171#define E4_TSTORM_RDMA_TASK_AG_CTX_CF4_MASK 0x3
7172#define E4_TSTORM_RDMA_TASK_AG_CTX_CF4_SHIFT 2
7173#define E4_TSTORM_RDMA_TASK_AG_CTX_CF5_MASK 0x3
7174#define E4_TSTORM_RDMA_TASK_AG_CTX_CF5_SHIFT 4
7175#define E4_TSTORM_RDMA_TASK_AG_CTX_CF6_MASK 0x3
7176#define E4_TSTORM_RDMA_TASK_AG_CTX_CF6_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007177 u8 flags3;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007178#define E4_TSTORM_RDMA_TASK_AG_CTX_CF7_MASK 0x3
7179#define E4_TSTORM_RDMA_TASK_AG_CTX_CF7_SHIFT 0
7180#define E4_TSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
7181#define E4_TSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 2
7182#define E4_TSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
7183#define E4_TSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 3
7184#define E4_TSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1
7185#define E4_TSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 4
7186#define E4_TSTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1
7187#define E4_TSTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 5
7188#define E4_TSTORM_RDMA_TASK_AG_CTX_CF4EN_MASK 0x1
7189#define E4_TSTORM_RDMA_TASK_AG_CTX_CF4EN_SHIFT 6
7190#define E4_TSTORM_RDMA_TASK_AG_CTX_CF5EN_MASK 0x1
7191#define E4_TSTORM_RDMA_TASK_AG_CTX_CF5EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007192 u8 flags4;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007193#define E4_TSTORM_RDMA_TASK_AG_CTX_CF6EN_MASK 0x1
7194#define E4_TSTORM_RDMA_TASK_AG_CTX_CF6EN_SHIFT 0
7195#define E4_TSTORM_RDMA_TASK_AG_CTX_CF7EN_MASK 0x1
7196#define E4_TSTORM_RDMA_TASK_AG_CTX_CF7EN_SHIFT 1
7197#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
7198#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 2
7199#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
7200#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 3
7201#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
7202#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 4
7203#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
7204#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 5
7205#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
7206#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 6
7207#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
7208#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007209 u8 byte2;
7210 __le16 word1;
7211 __le32 reg0;
7212 u8 byte3;
7213 u8 byte4;
7214 __le16 word2;
7215 __le16 word3;
7216 __le16 word4;
7217 __le32 reg1;
7218 __le32 reg2;
7219};
7220
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007221struct e4_ustorm_rdma_conn_ag_ctx {
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007222 u8 reserved;
7223 u8 byte1;
7224 u8 flags0;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007225#define E4_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
7226#define E4_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
7227#define E4_USTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1
7228#define E4_USTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
7229#define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
7230#define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 2
7231#define E4_USTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
7232#define E4_USTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4
7233#define E4_USTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
7234#define E4_USTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007235 u8 flags1;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007236#define E4_USTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3
7237#define E4_USTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 0
7238#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3
7239#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2
7240#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3
7241#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4
7242#define E4_USTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3
7243#define E4_USTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007244 u8 flags2;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007245#define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
7246#define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
7247#define E4_USTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
7248#define E4_USTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1
7249#define E4_USTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
7250#define E4_USTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2
7251#define E4_USTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1
7252#define E4_USTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 3
7253#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1
7254#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4
7255#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1
7256#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5
7257#define E4_USTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1
7258#define E4_USTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 6
7259#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_MASK 0x1
7260#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007261 u8 flags3;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007262#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_EN_MASK 0x1
7263#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_EN_SHIFT 0
7264#define E4_USTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
7265#define E4_USTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1
7266#define E4_USTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
7267#define E4_USTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2
7268#define E4_USTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
7269#define E4_USTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3
7270#define E4_USTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1
7271#define E4_USTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4
7272#define E4_USTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1
7273#define E4_USTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5
7274#define E4_USTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1
7275#define E4_USTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6
7276#define E4_USTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1
7277#define E4_USTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007278 u8 byte2;
7279 u8 byte3;
7280 __le16 conn_dpi;
7281 __le16 word1;
7282 __le32 cq_cons;
7283 __le32 cq_se_prod;
7284 __le32 cq_prod;
7285 __le32 reg3;
7286 __le16 int_timeout;
7287 __le16 word3;
7288};
7289
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007290struct e4_xstorm_rdma_conn_ag_ctx {
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007291 u8 reserved0;
7292 u8 state;
7293 u8 flags0;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007294#define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
7295#define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
7296#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1
7297#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
7298#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1
7299#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2
7300#define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
7301#define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
7302#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1
7303#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4
7304#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1
7305#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5
7306#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT6_MASK 0x1
7307#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT6_SHIFT 6
7308#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT7_MASK 0x1
7309#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT7_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007310 u8 flags1;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007311#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT8_MASK 0x1
7312#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT8_SHIFT 0
7313#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT9_MASK 0x1
7314#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT9_SHIFT 1
7315#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT10_MASK 0x1
7316#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT10_SHIFT 2
7317#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT11_MASK 0x1
7318#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT11_SHIFT 3
7319#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT12_MASK 0x1
7320#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT12_SHIFT 4
7321#define E4_XSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1
7322#define E4_XSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 5
7323#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT14_MASK 0x1
7324#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT14_SHIFT 6
7325#define E4_XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
7326#define E4_XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007327 u8 flags2;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007328#define E4_XSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3
7329#define E4_XSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 0
7330#define E4_XSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
7331#define E4_XSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 2
7332#define E4_XSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
7333#define E4_XSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 4
7334#define E4_XSTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3
7335#define E4_XSTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007336 u8 flags3;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007337#define E4_XSTORM_RDMA_CONN_AG_CTX_CF4_MASK 0x3
7338#define E4_XSTORM_RDMA_CONN_AG_CTX_CF4_SHIFT 0
7339#define E4_XSTORM_RDMA_CONN_AG_CTX_CF5_MASK 0x3
7340#define E4_XSTORM_RDMA_CONN_AG_CTX_CF5_SHIFT 2
7341#define E4_XSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3
7342#define E4_XSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 4
7343#define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
7344#define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007345 u8 flags4;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007346#define E4_XSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3
7347#define E4_XSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 0
7348#define E4_XSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3
7349#define E4_XSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 2
7350#define E4_XSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3
7351#define E4_XSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 4
7352#define E4_XSTORM_RDMA_CONN_AG_CTX_CF11_MASK 0x3
7353#define E4_XSTORM_RDMA_CONN_AG_CTX_CF11_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007354 u8 flags5;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007355#define E4_XSTORM_RDMA_CONN_AG_CTX_CF12_MASK 0x3
7356#define E4_XSTORM_RDMA_CONN_AG_CTX_CF12_SHIFT 0
7357#define E4_XSTORM_RDMA_CONN_AG_CTX_CF13_MASK 0x3
7358#define E4_XSTORM_RDMA_CONN_AG_CTX_CF13_SHIFT 2
7359#define E4_XSTORM_RDMA_CONN_AG_CTX_CF14_MASK 0x3
7360#define E4_XSTORM_RDMA_CONN_AG_CTX_CF14_SHIFT 4
7361#define E4_XSTORM_RDMA_CONN_AG_CTX_CF15_MASK 0x3
7362#define E4_XSTORM_RDMA_CONN_AG_CTX_CF15_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007363 u8 flags6;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007364#define E4_XSTORM_RDMA_CONN_AG_CTX_CF16_MASK 0x3
7365#define E4_XSTORM_RDMA_CONN_AG_CTX_CF16_SHIFT 0
7366#define E4_XSTORM_RDMA_CONN_AG_CTX_CF17_MASK 0x3
7367#define E4_XSTORM_RDMA_CONN_AG_CTX_CF17_SHIFT 2
7368#define E4_XSTORM_RDMA_CONN_AG_CTX_CF18_MASK 0x3
7369#define E4_XSTORM_RDMA_CONN_AG_CTX_CF18_SHIFT 4
7370#define E4_XSTORM_RDMA_CONN_AG_CTX_CF19_MASK 0x3
7371#define E4_XSTORM_RDMA_CONN_AG_CTX_CF19_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007372 u8 flags7;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007373#define E4_XSTORM_RDMA_CONN_AG_CTX_CF20_MASK 0x3
7374#define E4_XSTORM_RDMA_CONN_AG_CTX_CF20_SHIFT 0
7375#define E4_XSTORM_RDMA_CONN_AG_CTX_CF21_MASK 0x3
7376#define E4_XSTORM_RDMA_CONN_AG_CTX_CF21_SHIFT 2
7377#define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_MASK 0x3
7378#define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_SHIFT 4
7379#define E4_XSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1
7380#define E4_XSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 6
7381#define E4_XSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
7382#define E4_XSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007383 u8 flags8;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007384#define E4_XSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
7385#define E4_XSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 0
7386#define E4_XSTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1
7387#define E4_XSTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 1
7388#define E4_XSTORM_RDMA_CONN_AG_CTX_CF4EN_MASK 0x1
7389#define E4_XSTORM_RDMA_CONN_AG_CTX_CF4EN_SHIFT 2
7390#define E4_XSTORM_RDMA_CONN_AG_CTX_CF5EN_MASK 0x1
7391#define E4_XSTORM_RDMA_CONN_AG_CTX_CF5EN_SHIFT 3
7392#define E4_XSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1
7393#define E4_XSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 4
7394#define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
7395#define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
7396#define E4_XSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1
7397#define E4_XSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 6
7398#define E4_XSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1
7399#define E4_XSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007400 u8 flags9;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007401#define E4_XSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1
7402#define E4_XSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 0
7403#define E4_XSTORM_RDMA_CONN_AG_CTX_CF11EN_MASK 0x1
7404#define E4_XSTORM_RDMA_CONN_AG_CTX_CF11EN_SHIFT 1
7405#define E4_XSTORM_RDMA_CONN_AG_CTX_CF12EN_MASK 0x1
7406#define E4_XSTORM_RDMA_CONN_AG_CTX_CF12EN_SHIFT 2
7407#define E4_XSTORM_RDMA_CONN_AG_CTX_CF13EN_MASK 0x1
7408#define E4_XSTORM_RDMA_CONN_AG_CTX_CF13EN_SHIFT 3
7409#define E4_XSTORM_RDMA_CONN_AG_CTX_CF14EN_MASK 0x1
7410#define E4_XSTORM_RDMA_CONN_AG_CTX_CF14EN_SHIFT 4
7411#define E4_XSTORM_RDMA_CONN_AG_CTX_CF15EN_MASK 0x1
7412#define E4_XSTORM_RDMA_CONN_AG_CTX_CF15EN_SHIFT 5
7413#define E4_XSTORM_RDMA_CONN_AG_CTX_CF16EN_MASK 0x1
7414#define E4_XSTORM_RDMA_CONN_AG_CTX_CF16EN_SHIFT 6
7415#define E4_XSTORM_RDMA_CONN_AG_CTX_CF17EN_MASK 0x1
7416#define E4_XSTORM_RDMA_CONN_AG_CTX_CF17EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007417 u8 flags10;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007418#define E4_XSTORM_RDMA_CONN_AG_CTX_CF18EN_MASK 0x1
7419#define E4_XSTORM_RDMA_CONN_AG_CTX_CF18EN_SHIFT 0
7420#define E4_XSTORM_RDMA_CONN_AG_CTX_CF19EN_MASK 0x1
7421#define E4_XSTORM_RDMA_CONN_AG_CTX_CF19EN_SHIFT 1
7422#define E4_XSTORM_RDMA_CONN_AG_CTX_CF20EN_MASK 0x1
7423#define E4_XSTORM_RDMA_CONN_AG_CTX_CF20EN_SHIFT 2
7424#define E4_XSTORM_RDMA_CONN_AG_CTX_CF21EN_MASK 0x1
7425#define E4_XSTORM_RDMA_CONN_AG_CTX_CF21EN_SHIFT 3
7426#define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
7427#define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
7428#define E4_XSTORM_RDMA_CONN_AG_CTX_CF23EN_MASK 0x1
7429#define E4_XSTORM_RDMA_CONN_AG_CTX_CF23EN_SHIFT 5
7430#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1
7431#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 6
7432#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1
7433#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007434 u8 flags11;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007435#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
7436#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 0
7437#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
7438#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 1
7439#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
7440#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 2
7441#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1
7442#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 3
7443#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1
7444#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 4
7445#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1
7446#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 5
7447#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
7448#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
7449#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE9EN_MASK 0x1
7450#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE9EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007451 u8 flags12;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007452#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE10EN_MASK 0x1
7453#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE10EN_SHIFT 0
7454#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE11EN_MASK 0x1
7455#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE11EN_SHIFT 1
7456#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
7457#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
7458#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
7459#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
7460#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE14EN_MASK 0x1
7461#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE14EN_SHIFT 4
7462#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE15EN_MASK 0x1
7463#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE15EN_SHIFT 5
7464#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE16EN_MASK 0x1
7465#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE16EN_SHIFT 6
7466#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE17EN_MASK 0x1
7467#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE17EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007468 u8 flags13;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007469#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE18EN_MASK 0x1
7470#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE18EN_SHIFT 0
7471#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE19EN_MASK 0x1
7472#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE19EN_SHIFT 1
7473#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
7474#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
7475#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
7476#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
7477#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
7478#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
7479#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
7480#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
7481#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
7482#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
7483#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
7484#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007485 u8 flags14;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007486#define E4_XSTORM_RDMA_CONN_AG_CTX_MIGRATION_MASK 0x1
7487#define E4_XSTORM_RDMA_CONN_AG_CTX_MIGRATION_SHIFT 0
7488#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT17_MASK 0x1
7489#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT17_SHIFT 1
7490#define E4_XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3
7491#define E4_XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2
7492#define E4_XSTORM_RDMA_CONN_AG_CTX_RESERVED_MASK 0x1
7493#define E4_XSTORM_RDMA_CONN_AG_CTX_RESERVED_SHIFT 4
7494#define E4_XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
7495#define E4_XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
7496#define E4_XSTORM_RDMA_CONN_AG_CTX_CF23_MASK 0x3
7497#define E4_XSTORM_RDMA_CONN_AG_CTX_CF23_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007498 u8 byte2;
7499 __le16 physical_q0;
7500 __le16 word1;
7501 __le16 word2;
7502 __le16 word3;
7503 __le16 word4;
7504 __le16 word5;
7505 __le16 conn_dpi;
7506 u8 byte3;
7507 u8 byte4;
7508 u8 byte5;
7509 u8 byte6;
7510 __le32 reg0;
7511 __le32 reg1;
7512 __le32 reg2;
7513 __le32 snd_nxt_psn;
7514 __le32 reg4;
7515 __le32 reg5;
7516 __le32 reg6;
7517};
7518
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007519struct e4_ystorm_rdma_conn_ag_ctx {
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007520 u8 byte0;
7521 u8 byte1;
7522 u8 flags0;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007523#define E4_YSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1
7524#define E4_YSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0
7525#define E4_YSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1
7526#define E4_YSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
7527#define E4_YSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3
7528#define E4_YSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2
7529#define E4_YSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
7530#define E4_YSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4
7531#define E4_YSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
7532#define E4_YSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007533 u8 flags1;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007534#define E4_YSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1
7535#define E4_YSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0
7536#define E4_YSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
7537#define E4_YSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1
7538#define E4_YSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
7539#define E4_YSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2
7540#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1
7541#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3
7542#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1
7543#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4
7544#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
7545#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5
7546#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
7547#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6
7548#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
7549#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007550 u8 byte2;
7551 u8 byte3;
7552 __le16 word0;
7553 __le32 reg0;
7554 __le32 reg1;
7555 __le16 word1;
7556 __le16 word2;
7557 __le16 word3;
7558 __le16 word4;
7559 __le32 reg2;
7560 __le32 reg3;
7561};
7562
Tomer Tayara2e76992017-12-27 19:30:05 +02007563/* The roce storm context of Ystorm */
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007564struct ystorm_roce_conn_st_ctx {
7565 struct regpair temp[2];
7566};
7567
Tomer Tayara2e76992017-12-27 19:30:05 +02007568/* The roce storm context of Mstorm */
7569struct pstorm_roce_conn_st_ctx {
7570 struct regpair temp[16];
7571};
7572
7573/* The roce storm context of Xstorm */
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007574struct xstorm_roce_conn_st_ctx {
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02007575 struct regpair temp[24];
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007576};
7577
Tomer Tayara2e76992017-12-27 19:30:05 +02007578/* The roce storm context of Tstorm */
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007579struct tstorm_roce_conn_st_ctx {
7580 struct regpair temp[30];
7581};
7582
Tomer Tayara2e76992017-12-27 19:30:05 +02007583/* The roce storm context of Mstorm */
7584struct mstorm_roce_conn_st_ctx {
7585 struct regpair temp[6];
7586};
7587
7588/* The roce storm context of Ystorm */
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007589struct ustorm_roce_conn_st_ctx {
7590 struct regpair temp[12];
7591};
7592
Tomer Tayara2e76992017-12-27 19:30:05 +02007593/* roce connection context */
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007594struct e4_roce_conn_context {
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007595 struct ystorm_roce_conn_st_ctx ystorm_st_context;
7596 struct regpair ystorm_st_padding[2];
7597 struct pstorm_roce_conn_st_ctx pstorm_st_context;
7598 struct xstorm_roce_conn_st_ctx xstorm_st_context;
7599 struct regpair xstorm_st_padding[2];
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007600 struct e4_xstorm_rdma_conn_ag_ctx xstorm_ag_context;
7601 struct e4_tstorm_rdma_conn_ag_ctx tstorm_ag_context;
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007602 struct timers_context timer_context;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007603 struct e4_ustorm_rdma_conn_ag_ctx ustorm_ag_context;
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007604 struct tstorm_roce_conn_st_ctx tstorm_st_context;
7605 struct mstorm_roce_conn_st_ctx mstorm_st_context;
7606 struct ustorm_roce_conn_st_ctx ustorm_st_context;
7607 struct regpair ustorm_st_padding[2];
7608};
7609
Tomer Tayara2e76992017-12-27 19:30:05 +02007610/* roce create qp requester ramrod data */
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007611struct roce_create_qp_req_ramrod_data {
7612 __le16 flags;
Tomer Tayara2e76992017-12-27 19:30:05 +02007613#define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3
7614#define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0
7615#define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1
7616#define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT 2
7617#define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_MASK 0x1
7618#define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_SHIFT 3
7619#define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_MASK 0x7
7620#define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_SHIFT 4
7621#define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_MASK 0x1
7622#define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_SHIFT 7
7623#define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF
7624#define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT 8
7625#define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF
7626#define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT 12
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007627 u8 max_ord;
7628 u8 traffic_class;
7629 u8 hop_limit;
7630 u8 orq_num_pages;
7631 __le16 p_key;
7632 __le32 flow_label;
7633 __le32 dst_qp_id;
7634 __le32 ack_timeout_val;
7635 __le32 initial_psn;
7636 __le16 mtu;
7637 __le16 pd;
7638 __le16 sq_num_pages;
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02007639 __le16 low_latency_phy_queue;
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007640 struct regpair sq_pbl_addr;
7641 struct regpair orq_pbl_addr;
7642 __le16 local_mac_addr[3];
7643 __le16 remote_mac_addr[3];
7644 __le16 vlan_id;
7645 __le16 udp_src_port;
7646 __le32 src_gid[4];
7647 __le32 dst_gid[4];
7648 struct regpair qp_handle_for_cqe;
7649 struct regpair qp_handle_for_async;
7650 u8 stats_counter_id;
7651 u8 reserved3[7];
7652 __le32 cq_cid;
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02007653 __le16 regular_latency_phy_queue;
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007654 __le16 dpi;
7655};
7656
Tomer Tayara2e76992017-12-27 19:30:05 +02007657/* roce create qp responder ramrod data */
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007658struct roce_create_qp_resp_ramrod_data {
7659 __le16 flags;
Tomer Tayara2e76992017-12-27 19:30:05 +02007660#define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3
7661#define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0
7662#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
7663#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT 2
7664#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
7665#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT 3
7666#define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
7667#define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT 4
7668#define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_MASK 0x1
7669#define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_SHIFT 5
7670#define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_MASK 0x1
7671#define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_SHIFT 6
7672#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_MASK 0x1
7673#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_SHIFT 7
7674#define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_MASK 0x7
7675#define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_SHIFT 8
7676#define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F
7677#define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 11
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007678 u8 max_ird;
7679 u8 traffic_class;
7680 u8 hop_limit;
7681 u8 irq_num_pages;
7682 __le16 p_key;
7683 __le32 flow_label;
7684 __le32 dst_qp_id;
7685 u8 stats_counter_id;
7686 u8 reserved1;
7687 __le16 mtu;
7688 __le32 initial_psn;
7689 __le16 pd;
7690 __le16 rq_num_pages;
7691 struct rdma_srq_id srq_id;
7692 struct regpair rq_pbl_addr;
7693 struct regpair irq_pbl_addr;
7694 __le16 local_mac_addr[3];
7695 __le16 remote_mac_addr[3];
7696 __le16 vlan_id;
7697 __le16 udp_src_port;
7698 __le32 src_gid[4];
7699 __le32 dst_gid[4];
7700 struct regpair qp_handle_for_cqe;
7701 struct regpair qp_handle_for_async;
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02007702 __le16 low_latency_phy_queue;
7703 u8 reserved2[6];
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007704 __le32 cq_cid;
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02007705 __le16 regular_latency_phy_queue;
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007706 __le16 dpi;
7707};
7708
Tomer Tayara2e76992017-12-27 19:30:05 +02007709/* RoCE destroy qp requester output params */
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007710struct roce_destroy_qp_req_output_params {
7711 __le32 num_bound_mw;
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02007712 __le32 cq_prod;
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007713};
7714
Tomer Tayara2e76992017-12-27 19:30:05 +02007715/* RoCE destroy qp requester ramrod data */
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007716struct roce_destroy_qp_req_ramrod_data {
7717 struct regpair output_params_addr;
7718};
7719
Tomer Tayara2e76992017-12-27 19:30:05 +02007720/* RoCE destroy qp responder output params */
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007721struct roce_destroy_qp_resp_output_params {
7722 __le32 num_invalidated_mw;
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02007723 __le32 cq_prod;
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007724};
7725
Tomer Tayara2e76992017-12-27 19:30:05 +02007726/* RoCE destroy qp responder ramrod data */
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007727struct roce_destroy_qp_resp_ramrod_data {
7728 struct regpair output_params_addr;
7729};
7730
Tomer Tayara2e76992017-12-27 19:30:05 +02007731/* roce special events statistics */
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03007732struct roce_events_stats {
7733 __le16 silent_drops;
7734 __le16 rnr_naks_sent;
7735 __le32 retransmit_count;
7736 __le32 icrc_error_count;
7737 __le32 reserved;
7738};
7739
Tomer Tayara2e76992017-12-27 19:30:05 +02007740/* ROCE slow path EQ cmd IDs */
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007741enum roce_event_opcode {
7742 ROCE_EVENT_CREATE_QP = 11,
7743 ROCE_EVENT_MODIFY_QP,
7744 ROCE_EVENT_QUERY_QP,
7745 ROCE_EVENT_DESTROY_QP,
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03007746 ROCE_EVENT_CREATE_UD_QP,
7747 ROCE_EVENT_DESTROY_UD_QP,
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007748 MAX_ROCE_EVENT_OPCODE
7749};
7750
Tomer Tayara2e76992017-12-27 19:30:05 +02007751/* roce func init ramrod data */
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03007752struct roce_init_func_params {
7753 u8 ll2_queue_id;
7754 u8 cnp_vlan_priority;
7755 u8 cnp_dscp;
7756 u8 reserved;
7757 __le32 cnp_send_timeout;
7758};
7759
Tomer Tayara2e76992017-12-27 19:30:05 +02007760/* roce func init ramrod data */
Yuval Mintz05fafbf2016-08-19 09:33:31 +03007761struct roce_init_func_ramrod_data {
7762 struct rdma_init_func_ramrod_data rdma;
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03007763 struct roce_init_func_params roce;
Yuval Mintz05fafbf2016-08-19 09:33:31 +03007764};
7765
Tomer Tayara2e76992017-12-27 19:30:05 +02007766/* roce modify qp requester ramrod data */
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007767struct roce_modify_qp_req_ramrod_data {
7768 __le16 flags;
Tomer Tayara2e76992017-12-27 19:30:05 +02007769#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1
7770#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0
7771#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_MASK 0x1
7772#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_SHIFT 1
7773#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_MASK 0x1
7774#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_SHIFT 2
7775#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_MASK 0x1
7776#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_SHIFT 3
7777#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1
7778#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT 4
7779#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_MASK 0x1
7780#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_SHIFT 5
7781#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_MASK 0x1
7782#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_SHIFT 6
7783#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_MASK 0x1
7784#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_SHIFT 7
7785#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_MASK 0x1
7786#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_SHIFT 8
7787#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_MASK 0x1
7788#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_SHIFT 9
7789#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_MASK 0x7
7790#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_SHIFT 10
7791#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_MASK 0x7
7792#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_SHIFT 13
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007793 u8 fields;
Tomer Tayara2e76992017-12-27 19:30:05 +02007794#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF
7795#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT 0
7796#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF
7797#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT 4
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007798 u8 max_ord;
7799 u8 traffic_class;
7800 u8 hop_limit;
7801 __le16 p_key;
7802 __le32 flow_label;
7803 __le32 ack_timeout_val;
7804 __le16 mtu;
7805 __le16 reserved2;
7806 __le32 reserved3[3];
7807 __le32 src_gid[4];
7808 __le32 dst_gid[4];
7809};
7810
Tomer Tayara2e76992017-12-27 19:30:05 +02007811/* roce modify qp responder ramrod data */
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007812struct roce_modify_qp_resp_ramrod_data {
7813 __le16 flags;
Tomer Tayara2e76992017-12-27 19:30:05 +02007814#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1
7815#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0
7816#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
7817#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT 1
7818#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
7819#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT 2
7820#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
7821#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT 3
7822#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_MASK 0x1
7823#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_SHIFT 4
7824#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1
7825#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT 5
7826#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_MASK 0x1
7827#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_SHIFT 6
7828#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_MASK 0x1
7829#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_SHIFT 7
7830#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_MASK 0x1
7831#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_SHIFT 8
7832#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1
7833#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT 9
7834#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_MASK 0x3F
7835#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_SHIFT 10
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007836 u8 fields;
Tomer Tayara2e76992017-12-27 19:30:05 +02007837#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_MASK 0x7
7838#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_SHIFT 0
7839#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F
7840#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 3
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007841 u8 max_ird;
7842 u8 traffic_class;
7843 u8 hop_limit;
7844 __le16 p_key;
7845 __le32 flow_label;
7846 __le16 mtu;
7847 __le16 reserved2;
7848 __le32 src_gid[4];
7849 __le32 dst_gid[4];
7850};
7851
Tomer Tayara2e76992017-12-27 19:30:05 +02007852/* RoCE query qp requester output params */
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007853struct roce_query_qp_req_output_params {
7854 __le32 psn;
7855 __le32 flags;
Tomer Tayara2e76992017-12-27 19:30:05 +02007856#define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_MASK 0x1
7857#define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_SHIFT 0
7858#define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_MASK 0x1
7859#define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_SHIFT 1
7860#define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_MASK 0x3FFFFFFF
7861#define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_SHIFT 2
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007862};
7863
Tomer Tayara2e76992017-12-27 19:30:05 +02007864/* RoCE query qp requester ramrod data */
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007865struct roce_query_qp_req_ramrod_data {
7866 struct regpair output_params_addr;
7867};
7868
Tomer Tayara2e76992017-12-27 19:30:05 +02007869/* RoCE query qp responder output params */
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007870struct roce_query_qp_resp_output_params {
7871 __le32 psn;
7872 __le32 err_flag;
7873#define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_MASK 0x1
7874#define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0
7875#define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_MASK 0x7FFFFFFF
7876#define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_SHIFT 1
7877};
7878
Tomer Tayara2e76992017-12-27 19:30:05 +02007879/* RoCE query qp responder ramrod data */
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007880struct roce_query_qp_resp_ramrod_data {
7881 struct regpair output_params_addr;
7882};
7883
Tomer Tayara2e76992017-12-27 19:30:05 +02007884/* ROCE ramrod command IDs */
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007885enum roce_ramrod_cmd_id {
7886 ROCE_RAMROD_CREATE_QP = 11,
7887 ROCE_RAMROD_MODIFY_QP,
7888 ROCE_RAMROD_QUERY_QP,
7889 ROCE_RAMROD_DESTROY_QP,
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03007890 ROCE_RAMROD_CREATE_UD_QP,
7891 ROCE_RAMROD_DESTROY_UD_QP,
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007892 MAX_ROCE_RAMROD_CMD_ID
7893};
7894
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007895struct e4_mstorm_roce_req_conn_ag_ctx {
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007896 u8 byte0;
7897 u8 byte1;
7898 u8 flags0;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007899#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
7900#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
7901#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
7902#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1
7903#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
7904#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2
7905#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
7906#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4
7907#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
7908#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007909 u8 flags1;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007910#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
7911#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
7912#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
7913#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1
7914#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
7915#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2
7916#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
7917#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3
7918#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
7919#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4
7920#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
7921#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5
7922#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
7923#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6
7924#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
7925#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007926 __le16 word0;
7927 __le16 word1;
7928 __le32 reg0;
7929 __le32 reg1;
7930};
7931
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007932struct e4_mstorm_roce_resp_conn_ag_ctx {
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007933 u8 byte0;
7934 u8 byte1;
7935 u8 flags0;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007936#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
7937#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
7938#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
7939#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1
7940#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
7941#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2
7942#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
7943#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4
7944#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
7945#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007946 u8 flags1;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007947#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
7948#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
7949#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
7950#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1
7951#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
7952#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2
7953#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
7954#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3
7955#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
7956#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4
7957#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
7958#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5
7959#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
7960#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6
7961#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
7962#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007963 __le16 word0;
7964 __le16 word1;
7965 __le32 reg0;
7966 __le32 reg1;
7967};
7968
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007969struct e4_tstorm_roce_req_conn_ag_ctx {
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007970 u8 reserved0;
7971 u8 state;
7972 u8 flags0;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007973#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
7974#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
7975#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURRED_MASK 0x1
7976#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURRED_SHIFT 1
7977#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURRED_MASK 0x1
7978#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURRED_SHIFT 2
7979#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_MASK 0x1
7980#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_SHIFT 3
7981#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1
7982#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4
7983#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_MASK 0x1
7984#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_SHIFT 5
7985#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_MASK 0x3
7986#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007987 u8 flags1;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007988#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
7989#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 0
7990#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_MASK 0x3
7991#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_SHIFT 2
7992#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
7993#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4
7994#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
7995#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03007996 u8 flags2;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02007997#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
7998#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
7999#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_MASK 0x3
8000#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_SHIFT 2
8001#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_MASK 0x3
8002#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_SHIFT 4
8003#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_MASK 0x3
8004#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008005 u8 flags3;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008006#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_MASK 0x3
8007#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_SHIFT 0
8008#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_MASK 0x3
8009#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_SHIFT 2
8010#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_MASK 0x1
8011#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_SHIFT 4
8012#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
8013#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 5
8014#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_MASK 0x1
8015#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_SHIFT 6
8016#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
8017#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008018 u8 flags4;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008019#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
8020#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
8021#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
8022#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1
8023#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_MASK 0x1
8024#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_SHIFT 2
8025#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_MASK 0x1
8026#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_SHIFT 3
8027#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_MASK 0x1
8028#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_SHIFT 4
8029#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_MASK 0x1
8030#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_SHIFT 5
8031#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_MASK 0x1
8032#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_SHIFT 6
8033#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
8034#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008035 u8 flags5;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008036#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
8037#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0
8038#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
8039#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1
8040#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
8041#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2
8042#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
8043#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3
8044#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
8045#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4
8046#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_MASK 0x1
8047#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_SHIFT 5
8048#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1
8049#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6
8050#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1
8051#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008052 __le32 reg0;
8053 __le32 snd_nxt_psn;
8054 __le32 snd_max_psn;
8055 __le32 orq_prod;
8056 __le32 reg4;
8057 __le32 reg5;
8058 __le32 reg6;
8059 __le32 reg7;
8060 __le32 reg8;
8061 u8 tx_cqe_error_type;
8062 u8 orq_cache_idx;
8063 __le16 snd_sq_cons_th;
8064 u8 byte4;
8065 u8 byte5;
8066 __le16 snd_sq_cons;
8067 __le16 word2;
8068 __le16 word3;
8069 __le32 reg9;
8070 __le32 reg10;
8071};
8072
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008073struct e4_tstorm_roce_resp_conn_ag_ctx {
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008074 u8 byte0;
8075 u8 state;
8076 u8 flags0;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008077#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
8078#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
8079#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_MASK 0x1
8080#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_SHIFT 1
8081#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_MASK 0x1
8082#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_SHIFT 2
8083#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_MASK 0x1
8084#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_SHIFT 3
8085#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1
8086#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4
8087#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_MASK 0x1
8088#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_SHIFT 5
8089#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
8090#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008091 u8 flags1;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008092#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
8093#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 0
8094#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_MASK 0x3
8095#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_SHIFT 2
8096#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
8097#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 4
8098#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
8099#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008100 u8 flags2;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008101#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
8102#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
8103#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3
8104#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 2
8105#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_MASK 0x3
8106#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_SHIFT 4
8107#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3
8108#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008109 u8 flags3;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008110#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3
8111#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 0
8112#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3
8113#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 2
8114#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
8115#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 4
8116#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
8117#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 5
8118#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_MASK 0x1
8119#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_SHIFT 6
8120#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
8121#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008122 u8 flags4;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008123#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
8124#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
8125#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
8126#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1
8127#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1
8128#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 2
8129#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_MASK 0x1
8130#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_SHIFT 3
8131#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1
8132#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 4
8133#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1
8134#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 5
8135#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1
8136#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 6
8137#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
8138#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008139 u8 flags5;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008140#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
8141#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0
8142#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
8143#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1
8144#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
8145#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2
8146#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
8147#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3
8148#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
8149#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4
8150#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_MASK 0x1
8151#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_SHIFT 5
8152#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
8153#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6
8154#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1
8155#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008156 __le32 psn_and_rxmit_id_echo;
8157 __le32 reg1;
8158 __le32 reg2;
8159 __le32 reg3;
8160 __le32 reg4;
8161 __le32 reg5;
8162 __le32 reg6;
8163 __le32 reg7;
8164 __le32 reg8;
8165 u8 tx_async_error_type;
8166 u8 byte3;
8167 __le16 rq_cons;
8168 u8 byte4;
8169 u8 byte5;
8170 __le16 rq_prod;
8171 __le16 conn_dpi;
8172 __le16 irq_cons;
8173 __le32 num_invlidated_mw;
8174 __le32 reg10;
8175};
8176
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008177struct e4_ustorm_roce_req_conn_ag_ctx {
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008178 u8 byte0;
8179 u8 byte1;
8180 u8 flags0;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008181#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
8182#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
8183#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
8184#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1
8185#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
8186#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2
8187#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
8188#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4
8189#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
8190#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008191 u8 flags1;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008192#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3
8193#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 0
8194#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4_MASK 0x3
8195#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4_SHIFT 2
8196#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5_MASK 0x3
8197#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5_SHIFT 4
8198#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6_MASK 0x3
8199#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008200 u8 flags2;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008201#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
8202#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
8203#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
8204#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1
8205#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
8206#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2
8207#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1
8208#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 3
8209#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_MASK 0x1
8210#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_SHIFT 4
8211#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_MASK 0x1
8212#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_SHIFT 5
8213#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_MASK 0x1
8214#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_SHIFT 6
8215#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
8216#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008217 u8 flags3;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008218#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
8219#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0
8220#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
8221#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1
8222#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
8223#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2
8224#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
8225#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3
8226#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
8227#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4
8228#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1
8229#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 5
8230#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1
8231#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6
8232#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1
8233#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008234 u8 byte2;
8235 u8 byte3;
8236 __le16 word0;
8237 __le16 word1;
8238 __le32 reg0;
8239 __le32 reg1;
8240 __le32 reg2;
8241 __le32 reg3;
8242 __le16 word2;
8243 __le16 word3;
8244};
8245
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008246struct e4_ustorm_roce_resp_conn_ag_ctx {
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008247 u8 byte0;
8248 u8 byte1;
8249 u8 flags0;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008250#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
8251#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
8252#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
8253#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1
8254#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
8255#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2
8256#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
8257#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4
8258#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
8259#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008260 u8 flags1;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008261#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
8262#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 0
8263#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4_MASK 0x3
8264#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4_SHIFT 2
8265#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5_MASK 0x3
8266#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5_SHIFT 4
8267#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3
8268#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008269 u8 flags2;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008270#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
8271#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
8272#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
8273#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1
8274#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
8275#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2
8276#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
8277#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 3
8278#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_MASK 0x1
8279#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_SHIFT 4
8280#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_MASK 0x1
8281#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_SHIFT 5
8282#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1
8283#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 6
8284#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
8285#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008286 u8 flags3;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008287#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
8288#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0
8289#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
8290#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1
8291#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
8292#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2
8293#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
8294#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3
8295#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
8296#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4
8297#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1
8298#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 5
8299#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
8300#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6
8301#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1
8302#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008303 u8 byte2;
8304 u8 byte3;
8305 __le16 word0;
8306 __le16 word1;
8307 __le32 reg0;
8308 __le32 reg1;
8309 __le32 reg2;
8310 __le32 reg3;
8311 __le16 word2;
8312 __le16 word3;
8313};
8314
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008315struct e4_xstorm_roce_req_conn_ag_ctx {
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008316 u8 reserved0;
8317 u8 state;
8318 u8 flags0;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008319#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
8320#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
8321#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_MASK 0x1
8322#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_SHIFT 1
8323#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_MASK 0x1
8324#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_SHIFT 2
8325#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
8326#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
8327#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_MASK 0x1
8328#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_SHIFT 4
8329#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_MASK 0x1
8330#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_SHIFT 5
8331#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_MASK 0x1
8332#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_SHIFT 6
8333#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_MASK 0x1
8334#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008335 u8 flags1;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008336#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_MASK 0x1
8337#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_SHIFT 0
8338#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_MASK 0x1
8339#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_SHIFT 1
8340#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_MASK 0x1
8341#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_SHIFT 2
8342#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_MASK 0x1
8343#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_SHIFT 3
8344#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_MASK 0x1
8345#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_SHIFT 4
8346#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_MASK 0x1
8347#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_SHIFT 5
8348#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_MASK 0x1
8349#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_SHIFT 6
8350#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
8351#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008352 u8 flags2;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008353#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
8354#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 0
8355#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
8356#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 2
8357#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
8358#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 4
8359#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3
8360#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008361 u8 flags3;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008362#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3
8363#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 0
8364#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
8365#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2
8366#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_MASK 0x3
8367#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_SHIFT 4
8368#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
8369#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008370 u8 flags4;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008371#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_MASK 0x3
8372#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_SHIFT 0
8373#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_MASK 0x3
8374#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_SHIFT 2
8375#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_MASK 0x3
8376#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_SHIFT 4
8377#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_MASK 0x3
8378#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008379 u8 flags5;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008380#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_MASK 0x3
8381#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_SHIFT 0
8382#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_MASK 0x3
8383#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_SHIFT 2
8384#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_MASK 0x3
8385#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_SHIFT 4
8386#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_MASK 0x3
8387#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008388 u8 flags6;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008389#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_MASK 0x3
8390#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_SHIFT 0
8391#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_MASK 0x3
8392#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_SHIFT 2
8393#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_MASK 0x3
8394#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_SHIFT 4
8395#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_MASK 0x3
8396#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008397 u8 flags7;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008398#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_MASK 0x3
8399#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_SHIFT 0
8400#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_MASK 0x3
8401#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_SHIFT 2
8402#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_MASK 0x3
8403#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_SHIFT 4
8404#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
8405#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 6
8406#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
8407#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008408 u8 flags8;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008409#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
8410#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 0
8411#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1
8412#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 1
8413#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1
8414#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 2
8415#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
8416#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3
8417#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_MASK 0x1
8418#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_SHIFT 4
8419#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
8420#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
8421#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_MASK 0x1
8422#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_SHIFT 6
8423#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_MASK 0x1
8424#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008425 u8 flags9;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008426#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_MASK 0x1
8427#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_SHIFT 0
8428#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_MASK 0x1
8429#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_SHIFT 1
8430#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_MASK 0x1
8431#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_SHIFT 2
8432#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_MASK 0x1
8433#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_SHIFT 3
8434#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_MASK 0x1
8435#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_SHIFT 4
8436#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_MASK 0x1
8437#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_SHIFT 5
8438#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_MASK 0x1
8439#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_SHIFT 6
8440#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_MASK 0x1
8441#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008442 u8 flags10;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008443#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_MASK 0x1
8444#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_SHIFT 0
8445#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_MASK 0x1
8446#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_SHIFT 1
8447#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_MASK 0x1
8448#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_SHIFT 2
8449#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_MASK 0x1
8450#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_SHIFT 3
8451#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
8452#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
8453#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_MASK 0x1
8454#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_SHIFT 5
8455#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
8456#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 6
8457#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
8458#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008459 u8 flags11;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008460#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
8461#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 0
8462#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
8463#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 1
8464#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
8465#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 2
8466#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
8467#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 3
8468#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1
8469#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 4
8470#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_MASK 0x1
8471#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_SHIFT 5
8472#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
8473#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
8474#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_MASK 0x1
8475#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008476 u8 flags12;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008477#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_MASK 0x1
8478#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_SHIFT 0
8479#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_MASK 0x1
8480#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_SHIFT 1
8481#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
8482#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
8483#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
8484#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
8485#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_MASK 0x1
8486#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_SHIFT 4
8487#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_MASK 0x1
8488#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_SHIFT 5
8489#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_MASK 0x1
8490#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_SHIFT 6
8491#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_MASK 0x1
8492#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008493 u8 flags13;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008494#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_MASK 0x1
8495#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_SHIFT 0
8496#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_MASK 0x1
8497#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_SHIFT 1
8498#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
8499#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
8500#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
8501#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
8502#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
8503#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
8504#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
8505#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
8506#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
8507#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
8508#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
8509#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008510 u8 flags14;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008511#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_MASK 0x1
8512#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_SHIFT 0
8513#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_MASK 0x1
8514#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_SHIFT 1
8515#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3
8516#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2
8517#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_MASK 0x1
8518#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_SHIFT 4
8519#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
8520#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
8521#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_MASK 0x3
8522#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008523 u8 byte2;
8524 __le16 physical_q0;
8525 __le16 word1;
8526 __le16 sq_cmp_cons;
8527 __le16 sq_cons;
8528 __le16 sq_prod;
8529 __le16 word5;
8530 __le16 conn_dpi;
8531 u8 byte3;
8532 u8 byte4;
8533 u8 byte5;
8534 u8 byte6;
8535 __le32 lsn;
8536 __le32 ssn;
8537 __le32 snd_una_psn;
8538 __le32 snd_nxt_psn;
8539 __le32 reg4;
8540 __le32 orq_cons_th;
8541 __le32 orq_cons;
8542};
8543
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008544struct e4_xstorm_roce_resp_conn_ag_ctx {
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008545 u8 reserved0;
8546 u8 state;
8547 u8 flags0;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008548#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
8549#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
8550#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_MASK 0x1
8551#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_SHIFT 1
8552#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_MASK 0x1
8553#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_SHIFT 2
8554#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
8555#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
8556#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_MASK 0x1
8557#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_SHIFT 4
8558#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_MASK 0x1
8559#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_SHIFT 5
8560#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_MASK 0x1
8561#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_SHIFT 6
8562#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_MASK 0x1
8563#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008564 u8 flags1;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008565#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_MASK 0x1
8566#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_SHIFT 0
8567#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_MASK 0x1
8568#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_SHIFT 1
8569#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_MASK 0x1
8570#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_SHIFT 2
8571#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_MASK 0x1
8572#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_SHIFT 3
8573#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_MASK 0x1
8574#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_SHIFT 4
8575#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_MASK 0x1
8576#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_SHIFT 5
8577#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_MASK 0x1
8578#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_SHIFT 6
8579#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
8580#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008581 u8 flags2;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008582#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
8583#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 0
8584#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
8585#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 2
8586#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
8587#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 4
8588#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
8589#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008590 u8 flags3;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008591#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_MASK 0x3
8592#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_SHIFT 0
8593#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
8594#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2
8595#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_MASK 0x3
8596#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_SHIFT 4
8597#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
8598#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008599 u8 flags4;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008600#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3
8601#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 0
8602#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3
8603#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 2
8604#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3
8605#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 4
8606#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_MASK 0x3
8607#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008608 u8 flags5;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008609#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_MASK 0x3
8610#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_SHIFT 0
8611#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_MASK 0x3
8612#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_SHIFT 2
8613#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_MASK 0x3
8614#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_SHIFT 4
8615#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_MASK 0x3
8616#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008617 u8 flags6;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008618#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_MASK 0x3
8619#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_SHIFT 0
8620#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_MASK 0x3
8621#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_SHIFT 2
8622#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_MASK 0x3
8623#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_SHIFT 4
8624#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_MASK 0x3
8625#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008626 u8 flags7;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008627#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_MASK 0x3
8628#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_SHIFT 0
8629#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_MASK 0x3
8630#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_SHIFT 2
8631#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_MASK 0x3
8632#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_SHIFT 4
8633#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
8634#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 6
8635#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
8636#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008637 u8 flags8;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008638#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
8639#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 0
8640#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
8641#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 1
8642#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_MASK 0x1
8643#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_SHIFT 2
8644#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
8645#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3
8646#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_MASK 0x1
8647#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_SHIFT 4
8648#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
8649#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
8650#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1
8651#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 6
8652#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1
8653#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008654 u8 flags9;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008655#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1
8656#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 0
8657#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_MASK 0x1
8658#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_SHIFT 1
8659#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_MASK 0x1
8660#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_SHIFT 2
8661#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_MASK 0x1
8662#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_SHIFT 3
8663#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_MASK 0x1
8664#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_SHIFT 4
8665#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_MASK 0x1
8666#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_SHIFT 5
8667#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_MASK 0x1
8668#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_SHIFT 6
8669#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_MASK 0x1
8670#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008671 u8 flags10;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008672#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_MASK 0x1
8673#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_SHIFT 0
8674#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_MASK 0x1
8675#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_SHIFT 1
8676#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_MASK 0x1
8677#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_SHIFT 2
8678#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_MASK 0x1
8679#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_SHIFT 3
8680#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
8681#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
8682#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_MASK 0x1
8683#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_SHIFT 5
8684#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
8685#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 6
8686#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
8687#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008688 u8 flags11;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008689#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
8690#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 0
8691#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
8692#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 1
8693#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
8694#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 2
8695#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
8696#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 3
8697#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1
8698#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 4
8699#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
8700#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 5
8701#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
8702#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
8703#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_MASK 0x1
8704#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008705 u8 flags12;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008706#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_MASK 0x1
8707#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_SHIFT 0
8708#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE11EN_MASK 0x1
8709#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE11EN_SHIFT 1
8710#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
8711#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
8712#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
8713#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
8714#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_MASK 0x1
8715#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_SHIFT 4
8716#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_MASK 0x1
8717#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_SHIFT 5
8718#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_MASK 0x1
8719#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_SHIFT 6
8720#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_MASK 0x1
8721#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008722 u8 flags13;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008723#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_MASK 0x1
8724#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_SHIFT 0
8725#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_MASK 0x1
8726#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_SHIFT 1
8727#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
8728#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
8729#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
8730#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
8731#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
8732#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
8733#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
8734#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
8735#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
8736#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
8737#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
8738#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008739 u8 flags14;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008740#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_MASK 0x1
8741#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_SHIFT 0
8742#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_MASK 0x1
8743#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_SHIFT 1
8744#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_MASK 0x1
8745#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_SHIFT 2
8746#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_MASK 0x1
8747#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_SHIFT 3
8748#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_MASK 0x1
8749#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_SHIFT 4
8750#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_MASK 0x1
8751#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_SHIFT 5
8752#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_MASK 0x3
8753#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008754 u8 byte2;
8755 __le16 physical_q0;
8756 __le16 word1;
8757 __le16 irq_prod;
8758 __le16 word3;
8759 __le16 word4;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008760 __le16 e5_reserved1;
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008761 __le16 irq_cons;
8762 u8 rxmit_opcode;
8763 u8 byte4;
8764 u8 byte5;
8765 u8 byte6;
8766 __le32 rxmit_psn_and_id;
8767 __le32 rxmit_bytes_length;
8768 __le32 psn;
8769 __le32 reg3;
8770 __le32 reg4;
8771 __le32 reg5;
8772 __le32 msn_and_syndrome;
8773};
8774
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008775struct e4_ystorm_roce_req_conn_ag_ctx {
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008776 u8 byte0;
8777 u8 byte1;
8778 u8 flags0;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008779#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
8780#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
8781#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
8782#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1
8783#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
8784#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2
8785#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
8786#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4
8787#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
8788#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008789 u8 flags1;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008790#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
8791#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
8792#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
8793#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1
8794#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
8795#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2
8796#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
8797#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3
8798#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
8799#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4
8800#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
8801#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5
8802#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
8803#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6
8804#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
8805#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008806 u8 byte2;
8807 u8 byte3;
8808 __le16 word0;
8809 __le32 reg0;
8810 __le32 reg1;
8811 __le16 word1;
8812 __le16 word2;
8813 __le16 word3;
8814 __le16 word4;
8815 __le32 reg2;
8816 __le32 reg3;
8817};
8818
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008819struct e4_ystorm_roce_resp_conn_ag_ctx {
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008820 u8 byte0;
8821 u8 byte1;
8822 u8 flags0;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008823#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
8824#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
8825#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
8826#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1
8827#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
8828#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2
8829#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
8830#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4
8831#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
8832#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008833 u8 flags1;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008834#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
8835#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
8836#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
8837#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1
8838#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
8839#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2
8840#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
8841#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3
8842#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
8843#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4
8844#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
8845#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5
8846#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
8847#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6
8848#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
8849#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +03008850 u8 byte2;
8851 u8 byte3;
8852 __le16 word0;
8853 __le32 reg0;
8854 __le32 reg1;
8855 __le16 word1;
8856 __le16 word2;
8857 __le16 word3;
8858 __le16 word4;
8859 __le32 reg2;
8860 __le32 reg3;
8861};
8862
Tomer Tayara2e76992017-12-27 19:30:05 +02008863/* Roce doorbell data */
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03008864enum roce_flavor {
8865 PLAIN_ROCE,
8866 RROCE_IPV4,
8867 RROCE_IPV6,
8868 MAX_ROCE_FLAVOR
8869};
8870
Tomer Tayara2e76992017-12-27 19:30:05 +02008871/* The iwarp storm context of Ystorm */
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03008872struct ystorm_iwarp_conn_st_ctx {
8873 __le32 reserved[4];
8874};
8875
Tomer Tayara2e76992017-12-27 19:30:05 +02008876/* The iwarp storm context of Pstorm */
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03008877struct pstorm_iwarp_conn_st_ctx {
8878 __le32 reserved[36];
8879};
8880
Tomer Tayara2e76992017-12-27 19:30:05 +02008881/* The iwarp storm context of Xstorm */
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03008882struct xstorm_iwarp_conn_st_ctx {
8883 __le32 reserved[44];
8884};
8885
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008886struct e4_xstorm_iwarp_conn_ag_ctx {
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03008887 u8 reserved0;
8888 u8 state;
8889 u8 flags0;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008890#define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
8891#define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
8892#define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1
8893#define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_SHIFT 1
8894#define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_MASK 0x1
8895#define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_SHIFT 2
8896#define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
8897#define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
8898#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1
8899#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT 4
8900#define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED2_MASK 0x1
8901#define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED2_SHIFT 5
8902#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT6_MASK 0x1
8903#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT6_SHIFT 6
8904#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT7_MASK 0x1
8905#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT7_SHIFT 7
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03008906 u8 flags1;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008907#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT8_MASK 0x1
8908#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT8_SHIFT 0
8909#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT9_MASK 0x1
8910#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT9_SHIFT 1
8911#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT10_MASK 0x1
8912#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT10_SHIFT 2
8913#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT11_MASK 0x1
8914#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT11_SHIFT 3
8915#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT12_MASK 0x1
8916#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT12_SHIFT 4
8917#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT13_MASK 0x1
8918#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT13_SHIFT 5
8919#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT14_MASK 0x1
8920#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT14_SHIFT 6
8921#define E4_XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_MASK 0x1
8922#define E4_XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_SHIFT 7
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03008923 u8 flags2;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008924#define E4_XSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
8925#define E4_XSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 0
8926#define E4_XSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
8927#define E4_XSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 2
8928#define E4_XSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
8929#define E4_XSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 4
8930#define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
8931#define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 6
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03008932 u8 flags3;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008933#define E4_XSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3
8934#define E4_XSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT 0
8935#define E4_XSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3
8936#define E4_XSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT 2
8937#define E4_XSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3
8938#define E4_XSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 4
8939#define E4_XSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3
8940#define E4_XSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT 6
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03008941 u8 flags4;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008942#define E4_XSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3
8943#define E4_XSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT 0
8944#define E4_XSTORM_IWARP_CONN_AG_CTX_CF9_MASK 0x3
8945#define E4_XSTORM_IWARP_CONN_AG_CTX_CF9_SHIFT 2
8946#define E4_XSTORM_IWARP_CONN_AG_CTX_CF10_MASK 0x3
8947#define E4_XSTORM_IWARP_CONN_AG_CTX_CF10_SHIFT 4
8948#define E4_XSTORM_IWARP_CONN_AG_CTX_CF11_MASK 0x3
8949#define E4_XSTORM_IWARP_CONN_AG_CTX_CF11_SHIFT 6
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03008950 u8 flags5;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008951#define E4_XSTORM_IWARP_CONN_AG_CTX_CF12_MASK 0x3
8952#define E4_XSTORM_IWARP_CONN_AG_CTX_CF12_SHIFT 0
8953#define E4_XSTORM_IWARP_CONN_AG_CTX_CF13_MASK 0x3
8954#define E4_XSTORM_IWARP_CONN_AG_CTX_CF13_SHIFT 2
8955#define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3
8956#define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 4
8957#define E4_XSTORM_IWARP_CONN_AG_CTX_CF15_MASK 0x3
8958#define E4_XSTORM_IWARP_CONN_AG_CTX_CF15_SHIFT 6
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03008959 u8 flags6;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008960#define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_MASK 0x3
8961#define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_SHIFT 0
8962#define E4_XSTORM_IWARP_CONN_AG_CTX_CF17_MASK 0x3
8963#define E4_XSTORM_IWARP_CONN_AG_CTX_CF17_SHIFT 2
8964#define E4_XSTORM_IWARP_CONN_AG_CTX_CF18_MASK 0x3
8965#define E4_XSTORM_IWARP_CONN_AG_CTX_CF18_SHIFT 4
8966#define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_MASK 0x3
8967#define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_SHIFT 6
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03008968 u8 flags7;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008969#define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
8970#define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
8971#define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_MASK 0x3
8972#define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_SHIFT 2
8973#define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_MASK 0x3
8974#define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_SHIFT 4
8975#define E4_XSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
8976#define E4_XSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 6
8977#define E4_XSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
8978#define E4_XSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 7
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03008979 u8 flags8;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008980#define E4_XSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
8981#define E4_XSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 0
8982#define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
8983#define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 1
8984#define E4_XSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1
8985#define E4_XSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 2
8986#define E4_XSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1
8987#define E4_XSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT 3
8988#define E4_XSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1
8989#define E4_XSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 4
8990#define E4_XSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1
8991#define E4_XSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT 5
8992#define E4_XSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1
8993#define E4_XSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT 6
8994#define E4_XSTORM_IWARP_CONN_AG_CTX_CF9EN_MASK 0x1
8995#define E4_XSTORM_IWARP_CONN_AG_CTX_CF9EN_SHIFT 7
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03008996 u8 flags9;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02008997#define E4_XSTORM_IWARP_CONN_AG_CTX_CF10EN_MASK 0x1
8998#define E4_XSTORM_IWARP_CONN_AG_CTX_CF10EN_SHIFT 0
8999#define E4_XSTORM_IWARP_CONN_AG_CTX_CF11EN_MASK 0x1
9000#define E4_XSTORM_IWARP_CONN_AG_CTX_CF11EN_SHIFT 1
9001#define E4_XSTORM_IWARP_CONN_AG_CTX_CF12EN_MASK 0x1
9002#define E4_XSTORM_IWARP_CONN_AG_CTX_CF12EN_SHIFT 2
9003#define E4_XSTORM_IWARP_CONN_AG_CTX_CF13EN_MASK 0x1
9004#define E4_XSTORM_IWARP_CONN_AG_CTX_CF13EN_SHIFT 3
9005#define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1
9006#define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 4
9007#define E4_XSTORM_IWARP_CONN_AG_CTX_CF15EN_MASK 0x1
9008#define E4_XSTORM_IWARP_CONN_AG_CTX_CF15EN_SHIFT 5
9009#define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_MASK 0x1
9010#define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_SHIFT 6
9011#define E4_XSTORM_IWARP_CONN_AG_CTX_CF17EN_MASK 0x1
9012#define E4_XSTORM_IWARP_CONN_AG_CTX_CF17EN_SHIFT 7
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009013 u8 flags10;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02009014#define E4_XSTORM_IWARP_CONN_AG_CTX_CF18EN_MASK 0x1
9015#define E4_XSTORM_IWARP_CONN_AG_CTX_CF18EN_SHIFT 0
9016#define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1
9017#define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT 1
9018#define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
9019#define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
9020#define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_MASK 0x1
9021#define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_SHIFT 3
9022#define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
9023#define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
9024#define E4_XSTORM_IWARP_CONN_AG_CTX_CF23EN_MASK 0x1
9025#define E4_XSTORM_IWARP_CONN_AG_CTX_CF23EN_SHIFT 5
9026#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
9027#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 6
9028#define E4_XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_MASK 0x1
9029#define E4_XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_SHIFT 7
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009030 u8 flags11;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02009031#define E4_XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1
9032#define E4_XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0
9033#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
9034#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 1
9035#define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED3_MASK 0x1
9036#define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED3_SHIFT 2
9037#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1
9038#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 3
9039#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1
9040#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT 4
9041#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1
9042#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 5
9043#define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
9044#define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
9045#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE9EN_MASK 0x1
9046#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE9EN_SHIFT 7
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009047 u8 flags12;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02009048#define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_MASK 0x1
9049#define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_SHIFT 0
9050#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE11EN_MASK 0x1
9051#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE11EN_SHIFT 1
9052#define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
9053#define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
9054#define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
9055#define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
9056#define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_MASK 0x1
9057#define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_SHIFT 4
9058#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE15EN_MASK 0x1
9059#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE15EN_SHIFT 5
9060#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE16EN_MASK 0x1
9061#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE16EN_SHIFT 6
9062#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE17EN_MASK 0x1
9063#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE17EN_SHIFT 7
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009064 u8 flags13;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02009065#define E4_XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_MASK 0x1
9066#define E4_XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_SHIFT 0
9067#define E4_XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_MASK 0x1
9068#define E4_XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_SHIFT 1
9069#define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_MASK 0x1
9070#define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_SHIFT 2
9071#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE21EN_MASK 0x1
9072#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE21EN_SHIFT 3
9073#define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
9074#define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
9075#define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_MASK 0x1
9076#define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_SHIFT 5
9077#define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
9078#define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
9079#define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
9080#define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009081 u8 flags14;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02009082#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT16_MASK 0x1
9083#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT16_SHIFT 0
9084#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT17_MASK 0x1
9085#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT17_SHIFT 1
9086#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT18_MASK 0x1
9087#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT18_SHIFT 2
9088#define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_MASK 0x1
9089#define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_SHIFT 3
9090#define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_MASK 0x1
9091#define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_SHIFT 4
9092#define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_MASK 0x1
9093#define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_SHIFT 5
9094#define E4_XSTORM_IWARP_CONN_AG_CTX_CF23_MASK 0x3
9095#define E4_XSTORM_IWARP_CONN_AG_CTX_CF23_SHIFT 6
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009096 u8 byte2;
9097 __le16 physical_q0;
9098 __le16 physical_q1;
9099 __le16 sq_comp_cons;
9100 __le16 sq_tx_cons;
9101 __le16 sq_prod;
9102 __le16 word5;
9103 __le16 conn_dpi;
9104 u8 byte3;
9105 u8 byte4;
9106 u8 byte5;
9107 u8 byte6;
9108 __le32 reg0;
9109 __le32 reg1;
9110 __le32 reg2;
9111 __le32 more_to_send_seq;
9112 __le32 reg4;
9113 __le32 rewinded_snd_max;
9114 __le32 rd_msn;
9115 __le16 irq_prod_via_msdm;
9116 __le16 irq_cons;
9117 __le16 hq_cons_th_or_mpa_data;
9118 __le16 hq_cons;
9119 __le32 atom_msn;
9120 __le32 orq_cons;
9121 __le32 orq_cons_th;
9122 u8 byte7;
9123 u8 max_ord;
9124 u8 wqe_data_pad_bytes;
9125 u8 former_hq_prod;
9126 u8 irq_prod_via_msem;
9127 u8 byte12;
9128 u8 max_pkt_pdu_size_lo;
9129 u8 max_pkt_pdu_size_hi;
9130 u8 byte15;
9131 u8 e5_reserved;
9132 __le16 e5_reserved4;
9133 __le32 reg10;
9134 __le32 reg11;
9135 __le32 shared_queue_page_addr_lo;
9136 __le32 shared_queue_page_addr_hi;
9137 __le32 reg14;
9138 __le32 reg15;
9139 __le32 reg16;
9140 __le32 reg17;
9141};
9142
Tomer Tayar21dd79e2017-12-27 19:30:06 +02009143struct e4_tstorm_iwarp_conn_ag_ctx {
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009144 u8 reserved0;
9145 u8 state;
9146 u8 flags0;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02009147#define E4_TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
9148#define E4_TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
9149#define E4_TSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
9150#define E4_TSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1
9151#define E4_TSTORM_IWARP_CONN_AG_CTX_BIT2_MASK 0x1
9152#define E4_TSTORM_IWARP_CONN_AG_CTX_BIT2_SHIFT 2
9153#define E4_TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1
9154#define E4_TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 3
9155#define E4_TSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1
9156#define E4_TSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT 4
9157#define E4_TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_MASK 0x1
9158#define E4_TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_SHIFT 5
9159#define E4_TSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
9160#define E4_TSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 6
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009161 u8 flags1;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02009162#define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_MASK 0x3
9163#define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_SHIFT 0
9164#define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_MASK 0x3
9165#define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_SHIFT 2
9166#define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
9167#define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 4
9168#define E4_TSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3
9169#define E4_TSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT 6
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009170 u8 flags2;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02009171#define E4_TSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3
9172#define E4_TSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT 0
9173#define E4_TSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3
9174#define E4_TSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 2
9175#define E4_TSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3
9176#define E4_TSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT 4
9177#define E4_TSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3
9178#define E4_TSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT 6
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009179 u8 flags3;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02009180#define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
9181#define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
9182#define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_MASK 0x3
9183#define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_SHIFT 2
9184#define E4_TSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
9185#define E4_TSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 4
9186#define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_MASK 0x1
9187#define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_SHIFT 5
9188#define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_MASK 0x1
9189#define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_SHIFT 6
9190#define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
9191#define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009192 u8 flags4;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02009193#define E4_TSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1
9194#define E4_TSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 0
9195#define E4_TSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1
9196#define E4_TSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT 1
9197#define E4_TSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1
9198#define E4_TSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 2
9199#define E4_TSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1
9200#define E4_TSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT 3
9201#define E4_TSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1
9202#define E4_TSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT 4
9203#define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
9204#define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 5
9205#define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_MASK 0x1
9206#define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_SHIFT 6
9207#define E4_TSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
9208#define E4_TSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 7
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009209 u8 flags5;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02009210#define E4_TSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1
9211#define E4_TSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 0
9212#define E4_TSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
9213#define E4_TSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 1
9214#define E4_TSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
9215#define E4_TSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 2
9216#define E4_TSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
9217#define E4_TSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 3
9218#define E4_TSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1
9219#define E4_TSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 4
9220#define E4_TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_MASK 0x1
9221#define E4_TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_SHIFT 5
9222#define E4_TSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1
9223#define E4_TSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 6
9224#define E4_TSTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1
9225#define E4_TSTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT 7
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009226 __le32 reg0;
9227 __le32 reg1;
9228 __le32 unaligned_nxt_seq;
9229 __le32 reg3;
9230 __le32 reg4;
9231 __le32 reg5;
9232 __le32 reg6;
9233 __le32 reg7;
9234 __le32 reg8;
9235 u8 orq_cache_idx;
9236 u8 hq_prod;
9237 __le16 sq_tx_cons_th;
9238 u8 orq_prod;
9239 u8 irq_cons;
9240 __le16 sq_tx_cons;
9241 __le16 conn_dpi;
9242 __le16 rq_prod;
9243 __le32 snd_seq;
9244 __le32 last_hq_sequence;
9245};
9246
Tomer Tayara2e76992017-12-27 19:30:05 +02009247/* The iwarp storm context of Tstorm */
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009248struct tstorm_iwarp_conn_st_ctx {
9249 __le32 reserved[60];
9250};
9251
Tomer Tayara2e76992017-12-27 19:30:05 +02009252/* The iwarp storm context of Mstorm */
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009253struct mstorm_iwarp_conn_st_ctx {
9254 __le32 reserved[32];
9255};
9256
Tomer Tayara2e76992017-12-27 19:30:05 +02009257/* The iwarp storm context of Ustorm */
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009258struct ustorm_iwarp_conn_st_ctx {
9259 __le32 reserved[24];
9260};
9261
Tomer Tayara2e76992017-12-27 19:30:05 +02009262/* iwarp connection context */
Tomer Tayar21dd79e2017-12-27 19:30:06 +02009263struct e4_iwarp_conn_context {
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009264 struct ystorm_iwarp_conn_st_ctx ystorm_st_context;
9265 struct regpair ystorm_st_padding[2];
9266 struct pstorm_iwarp_conn_st_ctx pstorm_st_context;
9267 struct regpair pstorm_st_padding[2];
9268 struct xstorm_iwarp_conn_st_ctx xstorm_st_context;
9269 struct regpair xstorm_st_padding[2];
Tomer Tayar21dd79e2017-12-27 19:30:06 +02009270 struct e4_xstorm_iwarp_conn_ag_ctx xstorm_ag_context;
9271 struct e4_tstorm_iwarp_conn_ag_ctx tstorm_ag_context;
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009272 struct timers_context timer_context;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02009273 struct e4_ustorm_rdma_conn_ag_ctx ustorm_ag_context;
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009274 struct tstorm_iwarp_conn_st_ctx tstorm_st_context;
9275 struct regpair tstorm_st_padding[2];
9276 struct mstorm_iwarp_conn_st_ctx mstorm_st_context;
9277 struct ustorm_iwarp_conn_st_ctx ustorm_st_context;
9278};
9279
Tomer Tayara2e76992017-12-27 19:30:05 +02009280/* iWARP create QP params passed by driver to FW in CreateQP Request Ramrod */
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009281struct iwarp_create_qp_ramrod_data {
9282 u8 flags;
9283#define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1
Tomer Tayara2e76992017-12-27 19:30:05 +02009284#define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT 0
9285#define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_MASK 0x1
9286#define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_SHIFT 1
9287#define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
9288#define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT 2
9289#define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
9290#define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_SHIFT 3
9291#define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
9292#define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_SHIFT 4
9293#define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_MASK 0x1
9294#define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_SHIFT 5
9295#define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_MASK 0x3
9296#define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_SHIFT 6
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009297 u8 reserved1;
9298 __le16 pd;
9299 __le16 sq_num_pages;
9300 __le16 rq_num_pages;
9301 __le32 reserved3[2];
9302 struct regpair qp_handle_for_cqe;
9303 struct rdma_srq_id srq_id;
9304 __le32 cq_cid_for_sq;
9305 __le32 cq_cid_for_rq;
9306 __le16 dpi;
9307 __le16 physical_q0;
9308 __le16 physical_q1;
9309 u8 reserved2[6];
9310};
9311
Tomer Tayara2e76992017-12-27 19:30:05 +02009312/* iWARP completion queue types */
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009313enum iwarp_eqe_async_opcode {
9314 IWARP_EVENT_TYPE_ASYNC_CONNECT_COMPLETE,
9315 IWARP_EVENT_TYPE_ASYNC_ENHANCED_MPA_REPLY_ARRIVED,
9316 IWARP_EVENT_TYPE_ASYNC_MPA_HANDSHAKE_COMPLETE,
9317 IWARP_EVENT_TYPE_ASYNC_CID_CLEANED,
9318 IWARP_EVENT_TYPE_ASYNC_EXCEPTION_DETECTED,
9319 IWARP_EVENT_TYPE_ASYNC_QP_IN_ERROR_STATE,
9320 IWARP_EVENT_TYPE_ASYNC_CQ_OVERFLOW,
9321 MAX_IWARP_EQE_ASYNC_OPCODE
9322};
9323
9324struct iwarp_eqe_data_mpa_async_completion {
9325 __le16 ulp_data_len;
9326 u8 reserved[6];
9327};
9328
9329struct iwarp_eqe_data_tcp_async_completion {
9330 __le16 ulp_data_len;
9331 u8 mpa_handshake_mode;
9332 u8 reserved[5];
9333};
9334
Tomer Tayara2e76992017-12-27 19:30:05 +02009335/* iWARP completion queue types */
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009336enum iwarp_eqe_sync_opcode {
9337 IWARP_EVENT_TYPE_TCP_OFFLOAD =
9338 11,
9339 IWARP_EVENT_TYPE_MPA_OFFLOAD,
9340 IWARP_EVENT_TYPE_MPA_OFFLOAD_SEND_RTR,
9341 IWARP_EVENT_TYPE_CREATE_QP,
9342 IWARP_EVENT_TYPE_QUERY_QP,
9343 IWARP_EVENT_TYPE_MODIFY_QP,
9344 IWARP_EVENT_TYPE_DESTROY_QP,
9345 MAX_IWARP_EQE_SYNC_OPCODE
9346};
9347
Tomer Tayara2e76992017-12-27 19:30:05 +02009348/* iWARP EQE completion status */
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009349enum iwarp_fw_return_code {
9350 IWARP_CONN_ERROR_TCP_CONNECT_INVALID_PACKET = 5,
9351 IWARP_CONN_ERROR_TCP_CONNECTION_RST,
9352 IWARP_CONN_ERROR_TCP_CONNECT_TIMEOUT,
9353 IWARP_CONN_ERROR_MPA_ERROR_REJECT,
9354 IWARP_CONN_ERROR_MPA_NOT_SUPPORTED_VER,
9355 IWARP_CONN_ERROR_MPA_RST,
9356 IWARP_CONN_ERROR_MPA_FIN,
9357 IWARP_CONN_ERROR_MPA_RTR_MISMATCH,
9358 IWARP_CONN_ERROR_MPA_INSUF_IRD,
9359 IWARP_CONN_ERROR_MPA_INVALID_PACKET,
9360 IWARP_CONN_ERROR_MPA_LOCAL_ERROR,
9361 IWARP_CONN_ERROR_MPA_TIMEOUT,
9362 IWARP_CONN_ERROR_MPA_TERMINATE,
9363 IWARP_QP_IN_ERROR_GOOD_CLOSE,
9364 IWARP_QP_IN_ERROR_BAD_CLOSE,
9365 IWARP_EXCEPTION_DETECTED_LLP_CLOSED,
9366 IWARP_EXCEPTION_DETECTED_LLP_RESET,
9367 IWARP_EXCEPTION_DETECTED_IRQ_FULL,
9368 IWARP_EXCEPTION_DETECTED_RQ_EMPTY,
9369 IWARP_EXCEPTION_DETECTED_LLP_TIMEOUT,
9370 IWARP_EXCEPTION_DETECTED_REMOTE_PROTECTION_ERROR,
9371 IWARP_EXCEPTION_DETECTED_CQ_OVERFLOW,
9372 IWARP_EXCEPTION_DETECTED_LOCAL_CATASTROPHIC,
9373 IWARP_EXCEPTION_DETECTED_LOCAL_ACCESS_ERROR,
9374 IWARP_EXCEPTION_DETECTED_REMOTE_OPERATION_ERROR,
9375 IWARP_EXCEPTION_DETECTED_TERMINATE_RECEIVED,
9376 MAX_IWARP_FW_RETURN_CODE
9377};
9378
Tomer Tayara2e76992017-12-27 19:30:05 +02009379/* unaligned opaque data received from LL2 */
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009380struct iwarp_init_func_params {
9381 u8 ll2_ooo_q_index;
9382 u8 reserved1[7];
9383};
9384
Tomer Tayara2e76992017-12-27 19:30:05 +02009385/* iwarp func init ramrod data */
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009386struct iwarp_init_func_ramrod_data {
9387 struct rdma_init_func_ramrod_data rdma;
9388 struct tcp_init_params tcp;
9389 struct iwarp_init_func_params iwarp;
9390};
9391
Tomer Tayara2e76992017-12-27 19:30:05 +02009392/* iWARP QP - possible states to transition to */
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009393enum iwarp_modify_qp_new_state_type {
9394 IWARP_MODIFY_QP_STATE_CLOSING = 1,
Tomer Tayara2e76992017-12-27 19:30:05 +02009395 IWARP_MODIFY_QP_STATE_ERROR = 2,
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009396 MAX_IWARP_MODIFY_QP_NEW_STATE_TYPE
9397};
9398
Tomer Tayara2e76992017-12-27 19:30:05 +02009399/* iwarp modify qp responder ramrod data */
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009400struct iwarp_modify_qp_ramrod_data {
9401 __le16 transition_to_state;
9402 __le16 flags;
Tomer Tayara2e76992017-12-27 19:30:05 +02009403#define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
9404#define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT 0
9405#define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
9406#define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_SHIFT 1
9407#define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
9408#define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_SHIFT 2
9409#define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_MASK 0x1
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009410#define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_SHIFT 3
9411#define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1
Tomer Tayara2e76992017-12-27 19:30:05 +02009412#define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT 4
9413#define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_MASK 0x7FF
9414#define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_SHIFT 5
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009415 __le32 reserved3[3];
9416 __le32 reserved4[8];
9417};
9418
Tomer Tayara2e76992017-12-27 19:30:05 +02009419/* MPA params for Enhanced mode */
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009420struct mpa_rq_params {
9421 __le32 ird;
9422 __le32 ord;
9423};
9424
Tomer Tayara2e76992017-12-27 19:30:05 +02009425/* MPA host Address-Len for private data */
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009426struct mpa_ulp_buffer {
9427 struct regpair addr;
9428 __le16 len;
9429 __le16 reserved[3];
9430};
9431
Tomer Tayara2e76992017-12-27 19:30:05 +02009432/* iWARP MPA offload params common to Basic and Enhanced modes */
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009433struct mpa_outgoing_params {
9434 u8 crc_needed;
9435 u8 reject;
9436 u8 reserved[6];
9437 struct mpa_rq_params out_rq;
9438 struct mpa_ulp_buffer outgoing_ulp_buffer;
9439};
9440
Tomer Tayara2e76992017-12-27 19:30:05 +02009441/* iWARP MPA offload params passed by driver to FW in MPA Offload Request
9442 * Ramrod.
9443 */
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009444struct iwarp_mpa_offload_ramrod_data {
9445 struct mpa_outgoing_params common;
9446 __le32 tcp_cid;
9447 u8 mode;
9448 u8 tcp_connect_side;
9449 u8 rtr_pref;
9450#define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_MASK 0x7
Tomer Tayara2e76992017-12-27 19:30:05 +02009451#define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_SHIFT 0
9452#define IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_MASK 0x1F
9453#define IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_SHIFT 3
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009454 u8 reserved2;
9455 struct mpa_ulp_buffer incoming_ulp_buffer;
9456 struct regpair async_eqe_output_buf;
9457 struct regpair handle_for_async;
9458 struct regpair shared_queue_addr;
9459 u8 stats_counter_id;
9460 u8 reserved3[15];
9461};
9462
Tomer Tayara2e76992017-12-27 19:30:05 +02009463/* iWARP TCP connection offload params passed by driver to FW */
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009464struct iwarp_offload_params {
9465 struct mpa_ulp_buffer incoming_ulp_buffer;
9466 struct regpair async_eqe_output_buf;
9467 struct regpair handle_for_async;
9468 __le16 physical_q0;
9469 __le16 physical_q1;
9470 u8 stats_counter_id;
9471 u8 mpa_mode;
9472 u8 reserved[10];
9473};
9474
Tomer Tayara2e76992017-12-27 19:30:05 +02009475/* iWARP query QP output params */
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009476struct iwarp_query_qp_output_params {
9477 __le32 flags;
9478#define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_MASK 0x1
Tomer Tayara2e76992017-12-27 19:30:05 +02009479#define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009480#define IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_MASK 0x7FFFFFFF
Tomer Tayara2e76992017-12-27 19:30:05 +02009481#define IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_SHIFT 1
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009482 u8 reserved1[4];
9483};
9484
Tomer Tayara2e76992017-12-27 19:30:05 +02009485/* iWARP query QP ramrod data */
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009486struct iwarp_query_qp_ramrod_data {
9487 struct regpair output_params_addr;
9488};
9489
Tomer Tayara2e76992017-12-27 19:30:05 +02009490/* iWARP Ramrod Command IDs */
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009491enum iwarp_ramrod_cmd_id {
Tomer Tayara2e76992017-12-27 19:30:05 +02009492 IWARP_RAMROD_CMD_ID_TCP_OFFLOAD = 11,
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009493 IWARP_RAMROD_CMD_ID_MPA_OFFLOAD,
9494 IWARP_RAMROD_CMD_ID_MPA_OFFLOAD_SEND_RTR,
9495 IWARP_RAMROD_CMD_ID_CREATE_QP,
9496 IWARP_RAMROD_CMD_ID_QUERY_QP,
9497 IWARP_RAMROD_CMD_ID_MODIFY_QP,
9498 IWARP_RAMROD_CMD_ID_DESTROY_QP,
9499 MAX_IWARP_RAMROD_CMD_ID
9500};
9501
Tomer Tayara2e76992017-12-27 19:30:05 +02009502/* Per PF iWARP retransmit path statistics */
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009503struct iwarp_rxmit_stats_drv {
9504 struct regpair tx_go_to_slow_start_event_cnt;
9505 struct regpair tx_fast_retransmit_event_cnt;
9506};
9507
Tomer Tayara2e76992017-12-27 19:30:05 +02009508/* iWARP and TCP connection offload params passed by driver to FW in iWARP
9509 * offload ramrod.
9510 */
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009511struct iwarp_tcp_offload_ramrod_data {
9512 struct iwarp_offload_params iwarp;
9513 struct tcp_offload_params_opt2 tcp;
9514};
9515
Tomer Tayara2e76992017-12-27 19:30:05 +02009516/* iWARP MPA negotiation types */
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009517enum mpa_negotiation_mode {
9518 MPA_NEGOTIATION_TYPE_BASIC = 1,
9519 MPA_NEGOTIATION_TYPE_ENHANCED = 2,
9520 MAX_MPA_NEGOTIATION_MODE
9521};
9522
Tomer Tayara2e76992017-12-27 19:30:05 +02009523/* iWARP MPA Enhanced mode RTR types */
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009524enum mpa_rtr_type {
9525 MPA_RTR_TYPE_NONE = 0,
9526 MPA_RTR_TYPE_ZERO_SEND = 1,
9527 MPA_RTR_TYPE_ZERO_WRITE = 2,
9528 MPA_RTR_TYPE_ZERO_SEND_AND_WRITE = 3,
9529 MPA_RTR_TYPE_ZERO_READ = 4,
9530 MPA_RTR_TYPE_ZERO_SEND_AND_READ = 5,
9531 MPA_RTR_TYPE_ZERO_WRITE_AND_READ = 6,
9532 MPA_RTR_TYPE_ZERO_SEND_AND_WRITE_AND_READ = 7,
9533 MAX_MPA_RTR_TYPE
9534};
9535
Tomer Tayara2e76992017-12-27 19:30:05 +02009536/* unaligned opaque data received from LL2 */
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009537struct unaligned_opaque_data {
9538 __le16 first_mpa_offset;
9539 u8 tcp_payload_offset;
9540 u8 flags;
9541#define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_MASK 0x1
Tomer Tayara2e76992017-12-27 19:30:05 +02009542#define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_SHIFT 0
9543#define UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_MASK 0x1
9544#define UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_SHIFT 1
9545#define UNALIGNED_OPAQUE_DATA_RESERVED_MASK 0x3F
9546#define UNALIGNED_OPAQUE_DATA_RESERVED_SHIFT 2
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009547 __le32 cid;
9548};
9549
Tomer Tayar21dd79e2017-12-27 19:30:06 +02009550struct e4_mstorm_iwarp_conn_ag_ctx {
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009551 u8 reserved;
9552 u8 state;
9553 u8 flags0;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02009554#define E4_MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
9555#define E4_MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
9556#define E4_MSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
9557#define E4_MSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1
9558#define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_MASK 0x3
9559#define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_SHIFT 2
9560#define E4_MSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
9561#define E4_MSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4
9562#define E4_MSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
9563#define E4_MSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009564 u8 flags1;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02009565#define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_MASK 0x1
9566#define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_SHIFT 0
9567#define E4_MSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
9568#define E4_MSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1
9569#define E4_MSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
9570#define E4_MSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2
9571#define E4_MSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
9572#define E4_MSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 3
9573#define E4_MSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1
9574#define E4_MSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 4
9575#define E4_MSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
9576#define E4_MSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 5
9577#define E4_MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_MASK 0x1
9578#define E4_MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_SHIFT 6
9579#define E4_MSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
9580#define E4_MSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 7
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009581 __le16 rcq_cons;
9582 __le16 rcq_cons_th;
9583 __le32 reg0;
9584 __le32 reg1;
9585};
9586
Tomer Tayar21dd79e2017-12-27 19:30:06 +02009587struct e4_ustorm_iwarp_conn_ag_ctx {
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009588 u8 reserved;
9589 u8 byte1;
9590 u8 flags0;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02009591#define E4_USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
9592#define E4_USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
9593#define E4_USTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
9594#define E4_USTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1
9595#define E4_USTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
9596#define E4_USTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 2
9597#define E4_USTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
9598#define E4_USTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4
9599#define E4_USTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
9600#define E4_USTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009601 u8 flags1;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02009602#define E4_USTORM_IWARP_CONN_AG_CTX_CF3_MASK 0x3
9603#define E4_USTORM_IWARP_CONN_AG_CTX_CF3_SHIFT 0
9604#define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3
9605#define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2
9606#define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3
9607#define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4
9608#define E4_USTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3
9609#define E4_USTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 6
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009610 u8 flags2;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02009611#define E4_USTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
9612#define E4_USTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0
9613#define E4_USTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
9614#define E4_USTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1
9615#define E4_USTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
9616#define E4_USTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2
9617#define E4_USTORM_IWARP_CONN_AG_CTX_CF3EN_MASK 0x1
9618#define E4_USTORM_IWARP_CONN_AG_CTX_CF3EN_SHIFT 3
9619#define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1
9620#define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4
9621#define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1
9622#define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5
9623#define E4_USTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1
9624#define E4_USTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 6
9625#define E4_USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_MASK 0x1
9626#define E4_USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_SHIFT 7
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009627 u8 flags3;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02009628#define E4_USTORM_IWARP_CONN_AG_CTX_CQ_EN_MASK 0x1
9629#define E4_USTORM_IWARP_CONN_AG_CTX_CQ_EN_SHIFT 0
9630#define E4_USTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
9631#define E4_USTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 1
9632#define E4_USTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
9633#define E4_USTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 2
9634#define E4_USTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
9635#define E4_USTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 3
9636#define E4_USTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1
9637#define E4_USTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 4
9638#define E4_USTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1
9639#define E4_USTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT 5
9640#define E4_USTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1
9641#define E4_USTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 6
9642#define E4_USTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1
9643#define E4_USTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT 7
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009644 u8 byte2;
9645 u8 byte3;
9646 __le16 word0;
9647 __le16 word1;
9648 __le32 cq_cons;
9649 __le32 cq_se_prod;
9650 __le32 cq_prod;
9651 __le32 reg3;
9652 __le16 word2;
9653 __le16 word3;
9654};
9655
Tomer Tayar21dd79e2017-12-27 19:30:06 +02009656struct e4_ystorm_iwarp_conn_ag_ctx {
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009657 u8 byte0;
9658 u8 byte1;
9659 u8 flags0;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02009660#define E4_YSTORM_IWARP_CONN_AG_CTX_BIT0_MASK 0x1
9661#define E4_YSTORM_IWARP_CONN_AG_CTX_BIT0_SHIFT 0
9662#define E4_YSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
9663#define E4_YSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1
9664#define E4_YSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
9665#define E4_YSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 2
9666#define E4_YSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
9667#define E4_YSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4
9668#define E4_YSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
9669#define E4_YSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009670 u8 flags1;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02009671#define E4_YSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
9672#define E4_YSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0
9673#define E4_YSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
9674#define E4_YSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1
9675#define E4_YSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
9676#define E4_YSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2
9677#define E4_YSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
9678#define E4_YSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 3
9679#define E4_YSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1
9680#define E4_YSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 4
9681#define E4_YSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
9682#define E4_YSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 5
9683#define E4_YSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
9684#define E4_YSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 6
9685#define E4_YSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
9686#define E4_YSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 7
Mintz, Yuval7b6859f2017-05-18 19:41:04 +03009687 u8 byte2;
9688 u8 byte3;
9689 __le16 word0;
9690 __le32 reg0;
9691 __le32 reg1;
9692 __le16 word1;
9693 __le16 word2;
9694 __le16 word3;
9695 __le16 word4;
9696 __le32 reg2;
9697 __le32 reg3;
9698};
9699
Tomer Tayara2e76992017-12-27 19:30:05 +02009700/* The fcoe storm context of Ystorm */
Arun Easi1e128c82017-02-15 06:28:22 -08009701struct ystorm_fcoe_conn_st_ctx {
9702 u8 func_mode;
9703 u8 cos;
9704 u8 conf_version;
9705 u8 eth_hdr_size;
9706 __le16 stat_ram_addr;
9707 __le16 mtu;
9708 __le16 max_fc_payload_len;
9709 __le16 tx_max_fc_pay_len;
9710 u8 fcp_cmd_size;
9711 u8 fcp_rsp_size;
9712 __le16 mss;
9713 struct regpair reserved;
Mintz, Yuvalbe086e72017-03-11 18:39:18 +02009714 __le16 min_frame_size;
Arun Easi1e128c82017-02-15 06:28:22 -08009715 u8 protection_info_flags;
Tomer Tayara2e76992017-12-27 19:30:05 +02009716#define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1
9717#define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT 0
9718#define YSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1
9719#define YSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT 1
9720#define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_MASK 0x3F
9721#define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_SHIFT 2
Arun Easi1e128c82017-02-15 06:28:22 -08009722 u8 dst_protection_per_mss;
9723 u8 src_protection_per_mss;
9724 u8 ptu_log_page_size;
9725 u8 flags;
Tomer Tayara2e76992017-12-27 19:30:05 +02009726#define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1
9727#define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 0
9728#define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1
9729#define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT 1
9730#define YSTORM_FCOE_CONN_ST_CTX_RSRV_MASK 0x3F
9731#define YSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT 2
Arun Easi1e128c82017-02-15 06:28:22 -08009732 u8 fcp_xfer_size;
Arun Easi1e128c82017-02-15 06:28:22 -08009733};
9734
Tomer Tayara2e76992017-12-27 19:30:05 +02009735/* FCoE 16-bits vlan structure */
Arun Easi1e128c82017-02-15 06:28:22 -08009736struct fcoe_vlan_fields {
9737 __le16 fields;
Tomer Tayara2e76992017-12-27 19:30:05 +02009738#define FCOE_VLAN_FIELDS_VID_MASK 0xFFF
9739#define FCOE_VLAN_FIELDS_VID_SHIFT 0
9740#define FCOE_VLAN_FIELDS_CLI_MASK 0x1
9741#define FCOE_VLAN_FIELDS_CLI_SHIFT 12
9742#define FCOE_VLAN_FIELDS_PRI_MASK 0x7
9743#define FCOE_VLAN_FIELDS_PRI_SHIFT 13
Arun Easi1e128c82017-02-15 06:28:22 -08009744};
9745
Tomer Tayara2e76992017-12-27 19:30:05 +02009746/* FCoE 16-bits vlan union */
Arun Easi1e128c82017-02-15 06:28:22 -08009747union fcoe_vlan_field_union {
9748 struct fcoe_vlan_fields fields;
9749 __le16 val;
9750};
9751
Tomer Tayara2e76992017-12-27 19:30:05 +02009752/* FCoE 16-bits vlan, vif union */
Arun Easi1e128c82017-02-15 06:28:22 -08009753union fcoe_vlan_vif_field_union {
9754 union fcoe_vlan_field_union vlan;
9755 __le16 vif;
9756};
9757
Tomer Tayara2e76992017-12-27 19:30:05 +02009758/* Ethernet context section */
Arun Easi1e128c82017-02-15 06:28:22 -08009759struct pstorm_fcoe_eth_context_section {
9760 u8 remote_addr_3;
9761 u8 remote_addr_2;
9762 u8 remote_addr_1;
9763 u8 remote_addr_0;
9764 u8 local_addr_1;
9765 u8 local_addr_0;
9766 u8 remote_addr_5;
9767 u8 remote_addr_4;
9768 u8 local_addr_5;
9769 u8 local_addr_4;
9770 u8 local_addr_3;
9771 u8 local_addr_2;
9772 union fcoe_vlan_vif_field_union vif_outer_vlan;
9773 __le16 vif_outer_eth_type;
9774 union fcoe_vlan_vif_field_union inner_vlan;
9775 __le16 inner_eth_type;
9776};
9777
Tomer Tayara2e76992017-12-27 19:30:05 +02009778/* The fcoe storm context of Pstorm */
Arun Easi1e128c82017-02-15 06:28:22 -08009779struct pstorm_fcoe_conn_st_ctx {
9780 u8 func_mode;
9781 u8 cos;
9782 u8 conf_version;
9783 u8 rsrv;
9784 __le16 stat_ram_addr;
9785 __le16 mss;
9786 struct regpair abts_cleanup_addr;
9787 struct pstorm_fcoe_eth_context_section eth;
9788 u8 sid_2;
9789 u8 sid_1;
9790 u8 sid_0;
9791 u8 flags;
Tomer Tayara2e76992017-12-27 19:30:05 +02009792#define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_MASK 0x1
9793#define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_SHIFT 0
9794#define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_MASK 0x1
9795#define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_SHIFT 1
9796#define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1
9797#define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 2
9798#define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1
9799#define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT 3
9800#define PSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK 0xF
9801#define PSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT 4
Arun Easi1e128c82017-02-15 06:28:22 -08009802 u8 did_2;
9803 u8 did_1;
9804 u8 did_0;
9805 u8 src_mac_index;
9806 __le16 rec_rr_tov_val;
9807 u8 q_relative_offset;
9808 u8 reserved1;
9809};
9810
Tomer Tayara2e76992017-12-27 19:30:05 +02009811/* The fcoe storm context of Xstorm */
Arun Easi1e128c82017-02-15 06:28:22 -08009812struct xstorm_fcoe_conn_st_ctx {
9813 u8 func_mode;
9814 u8 src_mac_index;
9815 u8 conf_version;
9816 u8 cached_wqes_avail;
9817 __le16 stat_ram_addr;
9818 u8 flags;
Tomer Tayara2e76992017-12-27 19:30:05 +02009819#define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_MASK 0x1
9820#define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_SHIFT 0
9821#define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1
9822#define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 1
9823#define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_MASK 0x1
9824#define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_SHIFT 2
9825#define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_MASK 0x3
9826#define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_SHIFT 3
9827#define XSTORM_FCOE_CONN_ST_CTX_RSRV_MASK 0x7
9828#define XSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT 5
Arun Easi1e128c82017-02-15 06:28:22 -08009829 u8 cached_wqes_offset;
9830 u8 reserved2;
9831 u8 eth_hdr_size;
9832 u8 seq_id;
9833 u8 max_conc_seqs;
9834 __le16 num_pages_in_pbl;
9835 __le16 reserved;
9836 struct regpair sq_pbl_addr;
9837 struct regpair sq_curr_page_addr;
9838 struct regpair sq_next_page_addr;
9839 struct regpair xferq_pbl_addr;
9840 struct regpair xferq_curr_page_addr;
9841 struct regpair xferq_next_page_addr;
9842 struct regpair respq_pbl_addr;
9843 struct regpair respq_curr_page_addr;
9844 struct regpair respq_next_page_addr;
9845 __le16 mtu;
9846 __le16 tx_max_fc_pay_len;
9847 __le16 max_fc_payload_len;
9848 __le16 min_frame_size;
9849 __le16 sq_pbl_next_index;
9850 __le16 respq_pbl_next_index;
9851 u8 fcp_cmd_byte_credit;
9852 u8 fcp_rsp_byte_credit;
9853 __le16 protection_info;
Tomer Tayara2e76992017-12-27 19:30:05 +02009854#define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_MASK 0x1
9855#define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_SHIFT 0
9856#define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1
9857#define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT 1
9858#define XSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1
9859#define XSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT 2
9860#define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_MASK 0x1
9861#define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_SHIFT 3
9862#define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_MASK 0xF
9863#define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_SHIFT 4
9864#define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_MASK 0xFF
9865#define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_SHIFT 8
Arun Easi1e128c82017-02-15 06:28:22 -08009866 __le16 xferq_pbl_next_index;
9867 __le16 page_size;
9868 u8 mid_seq;
9869 u8 fcp_xfer_byte_credit;
9870 u8 reserved1[2];
9871 struct fcoe_wqe cached_wqes[16];
9872};
9873
Tomer Tayar21dd79e2017-12-27 19:30:06 +02009874struct e4_xstorm_fcoe_conn_ag_ctx {
Arun Easi1e128c82017-02-15 06:28:22 -08009875 u8 reserved0;
9876 u8 fcoe_state;
9877 u8 flags0;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02009878#define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
9879#define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
9880#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED1_MASK 0x1
9881#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED1_SHIFT 1
9882#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED2_MASK 0x1
9883#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED2_SHIFT 2
9884#define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
9885#define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
9886#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED3_MASK 0x1
9887#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED3_SHIFT 4
9888#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED4_MASK 0x1
9889#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED4_SHIFT 5
9890#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED5_MASK 0x1
9891#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED5_SHIFT 6
9892#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED6_MASK 0x1
9893#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED6_SHIFT 7
Arun Easi1e128c82017-02-15 06:28:22 -08009894 u8 flags1;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02009895#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED7_MASK 0x1
9896#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED7_SHIFT 0
9897#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED8_MASK 0x1
9898#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED8_SHIFT 1
9899#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED9_MASK 0x1
9900#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED9_SHIFT 2
9901#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT11_MASK 0x1
9902#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT11_SHIFT 3
9903#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT12_MASK 0x1
9904#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT12_SHIFT 4
9905#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT13_MASK 0x1
9906#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT13_SHIFT 5
9907#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT14_MASK 0x1
9908#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT14_SHIFT 6
9909#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT15_MASK 0x1
9910#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT15_SHIFT 7
Arun Easi1e128c82017-02-15 06:28:22 -08009911 u8 flags2;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02009912#define E4_XSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
9913#define E4_XSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 0
9914#define E4_XSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
9915#define E4_XSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 2
9916#define E4_XSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
9917#define E4_XSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 4
9918#define E4_XSTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3
9919#define E4_XSTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 6
Arun Easi1e128c82017-02-15 06:28:22 -08009920 u8 flags3;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02009921#define E4_XSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
9922#define E4_XSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 0
9923#define E4_XSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
9924#define E4_XSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 2
9925#define E4_XSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
9926#define E4_XSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 4
9927#define E4_XSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3
9928#define E4_XSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT 6
Arun Easi1e128c82017-02-15 06:28:22 -08009929 u8 flags4;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02009930#define E4_XSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3
9931#define E4_XSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 0
9932#define E4_XSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3
9933#define E4_XSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 2
9934#define E4_XSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3
9935#define E4_XSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT 4
9936#define E4_XSTORM_FCOE_CONN_AG_CTX_CF11_MASK 0x3
9937#define E4_XSTORM_FCOE_CONN_AG_CTX_CF11_SHIFT 6
Arun Easi1e128c82017-02-15 06:28:22 -08009938 u8 flags5;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02009939#define E4_XSTORM_FCOE_CONN_AG_CTX_CF12_MASK 0x3
9940#define E4_XSTORM_FCOE_CONN_AG_CTX_CF12_SHIFT 0
9941#define E4_XSTORM_FCOE_CONN_AG_CTX_CF13_MASK 0x3
9942#define E4_XSTORM_FCOE_CONN_AG_CTX_CF13_SHIFT 2
9943#define E4_XSTORM_FCOE_CONN_AG_CTX_CF14_MASK 0x3
9944#define E4_XSTORM_FCOE_CONN_AG_CTX_CF14_SHIFT 4
9945#define E4_XSTORM_FCOE_CONN_AG_CTX_CF15_MASK 0x3
9946#define E4_XSTORM_FCOE_CONN_AG_CTX_CF15_SHIFT 6
Arun Easi1e128c82017-02-15 06:28:22 -08009947 u8 flags6;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02009948#define E4_XSTORM_FCOE_CONN_AG_CTX_CF16_MASK 0x3
9949#define E4_XSTORM_FCOE_CONN_AG_CTX_CF16_SHIFT 0
9950#define E4_XSTORM_FCOE_CONN_AG_CTX_CF17_MASK 0x3
9951#define E4_XSTORM_FCOE_CONN_AG_CTX_CF17_SHIFT 2
9952#define E4_XSTORM_FCOE_CONN_AG_CTX_CF18_MASK 0x3
9953#define E4_XSTORM_FCOE_CONN_AG_CTX_CF18_SHIFT 4
9954#define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_MASK 0x3
9955#define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_SHIFT 6
Arun Easi1e128c82017-02-15 06:28:22 -08009956 u8 flags7;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02009957#define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
9958#define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
9959#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED10_MASK 0x3
9960#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED10_SHIFT 2
9961#define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
9962#define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_SHIFT 4
9963#define E4_XSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
9964#define E4_XSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 6
9965#define E4_XSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
9966#define E4_XSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 7
Arun Easi1e128c82017-02-15 06:28:22 -08009967 u8 flags8;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02009968#define E4_XSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
9969#define E4_XSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 0
9970#define E4_XSTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1
9971#define E4_XSTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT 1
9972#define E4_XSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
9973#define E4_XSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 2
9974#define E4_XSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
9975#define E4_XSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 3
9976#define E4_XSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
9977#define E4_XSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 4
9978#define E4_XSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1
9979#define E4_XSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT 5
9980#define E4_XSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1
9981#define E4_XSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT 6
9982#define E4_XSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1
9983#define E4_XSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT 7
Arun Easi1e128c82017-02-15 06:28:22 -08009984 u8 flags9;
Tomer Tayar21dd79e2017-12-27 19:30:06 +02009985#define E4_XSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1
9986#define E4_XSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 0
9987#define E4_XSTORM_FCOE_CONN_AG_CTX_CF11EN_MASK 0x1
9988#define E4_XSTORM_FCOE_CONN_AG_CTX_CF11EN_SHIFT 1
9989#define E4_XSTORM_FCOE_CONN_AG_CTX_CF12EN_MASK 0x1
9990#define E4_XSTORM_FCOE_CONN_AG_CTX_CF12EN_SHIFT 2
9991#define E4_XSTORM_FCOE_CONN_AG_CTX_CF13EN_MASK 0x1
9992#define E4_XSTORM_FCOE_CONN_AG_CTX_CF13EN_SHIFT 3
9993#define E4_XSTORM_FCOE_CONN_AG_CTX_CF14EN_MASK 0x1
9994#define E4_XSTORM_FCOE_CONN_AG_CTX_CF14EN_SHIFT 4
9995#define E4_XSTORM_FCOE_CONN_AG_CTX_CF15EN_MASK 0x1
9996#define E4_XSTORM_FCOE_CONN_AG_CTX_CF15EN_SHIFT 5
9997#define E4_XSTORM_FCOE_CONN_AG_CTX_CF16EN_MASK 0x1
9998#define E4_XSTORM_FCOE_CONN_AG_CTX_CF16EN_SHIFT 6
9999#define E4_XSTORM_FCOE_CONN_AG_CTX_CF17EN_MASK 0x1
10000#define E4_XSTORM_FCOE_CONN_AG_CTX_CF17EN_SHIFT 7
Arun Easi1e128c82017-02-15 06:28:22 -080010001 u8 flags10;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010002#define E4_XSTORM_FCOE_CONN_AG_CTX_CF18EN_MASK 0x1
10003#define E4_XSTORM_FCOE_CONN_AG_CTX_CF18EN_SHIFT 0
10004#define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
10005#define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_SHIFT 1
10006#define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
10007#define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
10008#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED11_MASK 0x1
10009#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED11_SHIFT 3
10010#define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
10011#define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
10012#define E4_XSTORM_FCOE_CONN_AG_CTX_CF23EN_MASK 0x1
10013#define E4_XSTORM_FCOE_CONN_AG_CTX_CF23EN_SHIFT 5
10014#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED12_MASK 0x1
10015#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED12_SHIFT 6
10016#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED13_MASK 0x1
10017#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED13_SHIFT 7
Arun Easi1e128c82017-02-15 06:28:22 -080010018 u8 flags11;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010019#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED14_MASK 0x1
10020#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED14_SHIFT 0
10021#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED15_MASK 0x1
10022#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED15_SHIFT 1
10023#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED16_MASK 0x1
10024#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED16_SHIFT 2
10025#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
10026#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 3
10027#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
10028#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 4
10029#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
10030#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 5
10031#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
10032#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
10033#define E4_XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_MASK 0x1
10034#define E4_XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_SHIFT 7
Arun Easi1e128c82017-02-15 06:28:22 -080010035 u8 flags12;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010036#define E4_XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_MASK 0x1
10037#define E4_XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_SHIFT 0
10038#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE11EN_MASK 0x1
10039#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE11EN_SHIFT 1
10040#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
10041#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
10042#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
10043#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
10044#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE14EN_MASK 0x1
10045#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE14EN_SHIFT 4
10046#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE15EN_MASK 0x1
10047#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE15EN_SHIFT 5
10048#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE16EN_MASK 0x1
10049#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE16EN_SHIFT 6
10050#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE17EN_MASK 0x1
10051#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE17EN_SHIFT 7
Arun Easi1e128c82017-02-15 06:28:22 -080010052 u8 flags13;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010053#define E4_XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_MASK 0x1
10054#define E4_XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_SHIFT 0
10055#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE19EN_MASK 0x1
10056#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE19EN_SHIFT 1
10057#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
10058#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
10059#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
10060#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
10061#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
10062#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
10063#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
10064#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
10065#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
10066#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
10067#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
10068#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
Arun Easi1e128c82017-02-15 06:28:22 -080010069 u8 flags14;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010070#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT16_MASK 0x1
10071#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT16_SHIFT 0
10072#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT17_MASK 0x1
10073#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT17_SHIFT 1
10074#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT18_MASK 0x1
10075#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT18_SHIFT 2
10076#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT19_MASK 0x1
10077#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT19_SHIFT 3
10078#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT20_MASK 0x1
10079#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT20_SHIFT 4
10080#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT21_MASK 0x1
10081#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT21_SHIFT 5
10082#define E4_XSTORM_FCOE_CONN_AG_CTX_CF23_MASK 0x3
10083#define E4_XSTORM_FCOE_CONN_AG_CTX_CF23_SHIFT 6
Arun Easi1e128c82017-02-15 06:28:22 -080010084 u8 byte2;
10085 __le16 physical_q0;
10086 __le16 word1;
10087 __le16 word2;
10088 __le16 sq_cons;
10089 __le16 sq_prod;
10090 __le16 xferq_prod;
10091 __le16 xferq_cons;
10092 u8 byte3;
10093 u8 byte4;
10094 u8 byte5;
10095 u8 byte6;
10096 __le32 remain_io;
10097 __le32 reg1;
10098 __le32 reg2;
10099 __le32 reg3;
10100 __le32 reg4;
10101 __le32 reg5;
10102 __le32 reg6;
10103 __le16 respq_prod;
10104 __le16 respq_cons;
10105 __le16 word9;
10106 __le16 word10;
10107 __le32 reg7;
10108 __le32 reg8;
10109};
10110
Tomer Tayara2e76992017-12-27 19:30:05 +020010111/* The fcoe storm context of Ustorm */
Arun Easi1e128c82017-02-15 06:28:22 -080010112struct ustorm_fcoe_conn_st_ctx {
10113 struct regpair respq_pbl_addr;
10114 __le16 num_pages_in_pbl;
10115 u8 ptu_log_page_size;
10116 u8 log_page_size;
10117 __le16 respq_prod;
10118 u8 reserved[2];
10119};
10120
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010121struct e4_tstorm_fcoe_conn_ag_ctx {
Arun Easi1e128c82017-02-15 06:28:22 -080010122 u8 reserved0;
10123 u8 fcoe_state;
10124 u8 flags0;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010125#define E4_TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
10126#define E4_TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
10127#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
10128#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
10129#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT2_MASK 0x1
10130#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT2_SHIFT 2
10131#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT3_MASK 0x1
10132#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT3_SHIFT 3
10133#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT4_MASK 0x1
10134#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT4_SHIFT 4
10135#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT5_MASK 0x1
10136#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT5_SHIFT 5
10137#define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_MASK 0x3
10138#define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_SHIFT 6
Arun Easi1e128c82017-02-15 06:28:22 -080010139 u8 flags1;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010140#define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
10141#define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 0
10142#define E4_TSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
10143#define E4_TSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 2
10144#define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
10145#define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4
10146#define E4_TSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
10147#define E4_TSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 6
Arun Easi1e128c82017-02-15 06:28:22 -080010148 u8 flags2;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010149#define E4_TSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
10150#define E4_TSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 0
10151#define E4_TSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
10152#define E4_TSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 2
10153#define E4_TSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3
10154#define E4_TSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT 4
10155#define E4_TSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3
10156#define E4_TSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 6
Arun Easi1e128c82017-02-15 06:28:22 -080010157 u8 flags3;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010158#define E4_TSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3
10159#define E4_TSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 0
10160#define E4_TSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3
10161#define E4_TSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT 2
10162#define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_MASK 0x1
10163#define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_SHIFT 4
10164#define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
10165#define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
10166#define E4_TSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
10167#define E4_TSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 6
10168#define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
10169#define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
Arun Easi1e128c82017-02-15 06:28:22 -080010170 u8 flags4;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010171#define E4_TSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
10172#define E4_TSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 0
10173#define E4_TSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
10174#define E4_TSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 1
10175#define E4_TSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
10176#define E4_TSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 2
10177#define E4_TSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1
10178#define E4_TSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT 3
10179#define E4_TSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1
10180#define E4_TSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT 4
10181#define E4_TSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1
10182#define E4_TSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT 5
10183#define E4_TSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1
10184#define E4_TSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 6
10185#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
10186#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7
Arun Easi1e128c82017-02-15 06:28:22 -080010187 u8 flags5;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010188#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
10189#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0
10190#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
10191#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1
10192#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
10193#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2
10194#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
10195#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3
10196#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
10197#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4
10198#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
10199#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5
10200#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
10201#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6
10202#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1
10203#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7
Arun Easi1e128c82017-02-15 06:28:22 -080010204 __le32 reg0;
10205 __le32 reg1;
10206};
10207
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010208struct e4_ustorm_fcoe_conn_ag_ctx {
Arun Easi1e128c82017-02-15 06:28:22 -080010209 u8 byte0;
10210 u8 byte1;
10211 u8 flags0;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010212#define E4_USTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
10213#define E4_USTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0
10214#define E4_USTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
10215#define E4_USTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
10216#define E4_USTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
10217#define E4_USTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2
10218#define E4_USTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
10219#define E4_USTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4
10220#define E4_USTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
10221#define E4_USTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6
Arun Easi1e128c82017-02-15 06:28:22 -080010222 u8 flags1;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010223#define E4_USTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3
10224#define E4_USTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 0
10225#define E4_USTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
10226#define E4_USTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 2
10227#define E4_USTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
10228#define E4_USTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 4
10229#define E4_USTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
10230#define E4_USTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 6
Arun Easi1e128c82017-02-15 06:28:22 -080010231 u8 flags2;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010232#define E4_USTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
10233#define E4_USTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0
10234#define E4_USTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
10235#define E4_USTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1
10236#define E4_USTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
10237#define E4_USTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2
10238#define E4_USTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1
10239#define E4_USTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT 3
10240#define E4_USTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
10241#define E4_USTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 4
10242#define E4_USTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
10243#define E4_USTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 5
10244#define E4_USTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
10245#define E4_USTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 6
10246#define E4_USTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
10247#define E4_USTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7
Arun Easi1e128c82017-02-15 06:28:22 -080010248 u8 flags3;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010249#define E4_USTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
10250#define E4_USTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0
10251#define E4_USTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
10252#define E4_USTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1
10253#define E4_USTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
10254#define E4_USTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2
10255#define E4_USTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
10256#define E4_USTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3
10257#define E4_USTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
10258#define E4_USTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4
10259#define E4_USTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
10260#define E4_USTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5
10261#define E4_USTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
10262#define E4_USTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6
10263#define E4_USTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1
10264#define E4_USTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7
Arun Easi1e128c82017-02-15 06:28:22 -080010265 u8 byte2;
10266 u8 byte3;
10267 __le16 word0;
10268 __le16 word1;
10269 __le32 reg0;
10270 __le32 reg1;
10271 __le32 reg2;
10272 __le32 reg3;
10273 __le16 word2;
10274 __le16 word3;
10275};
10276
Tomer Tayara2e76992017-12-27 19:30:05 +020010277/* The fcoe storm context of Tstorm */
Arun Easi1e128c82017-02-15 06:28:22 -080010278struct tstorm_fcoe_conn_st_ctx {
10279 __le16 stat_ram_addr;
10280 __le16 rx_max_fc_payload_len;
10281 __le16 e_d_tov_val;
10282 u8 flags;
Tomer Tayara2e76992017-12-27 19:30:05 +020010283#define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_MASK 0x1
10284#define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_SHIFT 0
10285#define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_MASK 0x1
10286#define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_SHIFT 1
10287#define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_MASK 0x3F
10288#define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_SHIFT 2
Arun Easi1e128c82017-02-15 06:28:22 -080010289 u8 timers_cleanup_invocation_cnt;
10290 __le32 reserved1[2];
Tomer Tayara2e76992017-12-27 19:30:05 +020010291 __le32 dst_mac_address_bytes_0_to_3;
10292 __le16 dst_mac_address_bytes_4_to_5;
Arun Easi1e128c82017-02-15 06:28:22 -080010293 __le16 ramrod_echo;
10294 u8 flags1;
Tomer Tayara2e76992017-12-27 19:30:05 +020010295#define TSTORM_FCOE_CONN_ST_CTX_MODE_MASK 0x3
10296#define TSTORM_FCOE_CONN_ST_CTX_MODE_SHIFT 0
10297#define TSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK 0x3F
10298#define TSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT 2
10299 u8 cq_relative_offset;
Arun Easi1e128c82017-02-15 06:28:22 -080010300 u8 bdq_resource_id;
10301 u8 reserved0[5];
10302};
10303
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010304struct e4_mstorm_fcoe_conn_ag_ctx {
Arun Easi1e128c82017-02-15 06:28:22 -080010305 u8 byte0;
10306 u8 byte1;
10307 u8 flags0;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010308#define E4_MSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
10309#define E4_MSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0
10310#define E4_MSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
10311#define E4_MSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
10312#define E4_MSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
10313#define E4_MSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2
10314#define E4_MSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
10315#define E4_MSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4
10316#define E4_MSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
10317#define E4_MSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6
Arun Easi1e128c82017-02-15 06:28:22 -080010318 u8 flags1;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010319#define E4_MSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
10320#define E4_MSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0
10321#define E4_MSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
10322#define E4_MSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1
10323#define E4_MSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
10324#define E4_MSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2
10325#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
10326#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3
10327#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
10328#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4
10329#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
10330#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5
10331#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
10332#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6
10333#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
10334#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7
Arun Easi1e128c82017-02-15 06:28:22 -080010335 __le16 word0;
10336 __le16 word1;
10337 __le32 reg0;
10338 __le32 reg1;
10339};
10340
Tomer Tayara2e76992017-12-27 19:30:05 +020010341/* Fast path part of the fcoe storm context of Mstorm */
Arun Easi1e128c82017-02-15 06:28:22 -080010342struct fcoe_mstorm_fcoe_conn_st_ctx_fp {
10343 __le16 xfer_prod;
10344 __le16 reserved1;
10345 u8 protection_info;
10346#define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_MASK 0x1
10347#define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_SHIFT 0
10348#define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_VALID_MASK 0x1
10349#define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_VALID_SHIFT 1
10350#define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_RESERVED0_MASK 0x3F
10351#define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_RESERVED0_SHIFT 2
10352 u8 q_relative_offset;
10353 u8 reserved2[2];
10354};
10355
Tomer Tayara2e76992017-12-27 19:30:05 +020010356/* Non fast path part of the fcoe storm context of Mstorm */
Arun Easi1e128c82017-02-15 06:28:22 -080010357struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp {
10358 __le16 conn_id;
10359 __le16 stat_ram_addr;
10360 __le16 num_pages_in_pbl;
10361 u8 ptu_log_page_size;
10362 u8 log_page_size;
10363 __le16 unsolicited_cq_count;
10364 __le16 cmdq_count;
10365 u8 bdq_resource_id;
10366 u8 reserved0[3];
10367 struct regpair xferq_pbl_addr;
10368 struct regpair reserved1;
10369 struct regpair reserved2[3];
10370};
10371
Tomer Tayara2e76992017-12-27 19:30:05 +020010372/* The fcoe storm context of Mstorm */
Arun Easi1e128c82017-02-15 06:28:22 -080010373struct mstorm_fcoe_conn_st_ctx {
10374 struct fcoe_mstorm_fcoe_conn_st_ctx_fp fp;
10375 struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp non_fp;
10376};
10377
Tomer Tayara2e76992017-12-27 19:30:05 +020010378/* fcoe connection context */
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010379struct e4_fcoe_conn_context {
Arun Easi1e128c82017-02-15 06:28:22 -080010380 struct ystorm_fcoe_conn_st_ctx ystorm_st_context;
10381 struct pstorm_fcoe_conn_st_ctx pstorm_st_context;
10382 struct regpair pstorm_st_padding[2];
10383 struct xstorm_fcoe_conn_st_ctx xstorm_st_context;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010384 struct e4_xstorm_fcoe_conn_ag_ctx xstorm_ag_context;
Arun Easi1e128c82017-02-15 06:28:22 -080010385 struct regpair xstorm_ag_padding[6];
10386 struct ustorm_fcoe_conn_st_ctx ustorm_st_context;
10387 struct regpair ustorm_st_padding[2];
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010388 struct e4_tstorm_fcoe_conn_ag_ctx tstorm_ag_context;
Arun Easi1e128c82017-02-15 06:28:22 -080010389 struct regpair tstorm_ag_padding[2];
10390 struct timers_context timer_context;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010391 struct e4_ustorm_fcoe_conn_ag_ctx ustorm_ag_context;
Arun Easi1e128c82017-02-15 06:28:22 -080010392 struct tstorm_fcoe_conn_st_ctx tstorm_st_context;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010393 struct e4_mstorm_fcoe_conn_ag_ctx mstorm_ag_context;
Arun Easi1e128c82017-02-15 06:28:22 -080010394 struct mstorm_fcoe_conn_st_ctx mstorm_st_context;
10395};
10396
Tomer Tayara2e76992017-12-27 19:30:05 +020010397/* FCoE connection offload params passed by driver to FW in FCoE offload
10398 * ramrod.
10399 */
Arun Easi1e128c82017-02-15 06:28:22 -080010400struct fcoe_conn_offload_ramrod_params {
10401 struct fcoe_conn_offload_ramrod_data offload_ramrod_data;
10402};
10403
Tomer Tayara2e76992017-12-27 19:30:05 +020010404/* FCoE connection terminate params passed by driver to FW in FCoE terminate
10405 * conn ramrod.
10406 */
Arun Easi1e128c82017-02-15 06:28:22 -080010407struct fcoe_conn_terminate_ramrod_params {
10408 struct fcoe_conn_terminate_ramrod_data terminate_ramrod_data;
10409};
10410
Tomer Tayara2e76992017-12-27 19:30:05 +020010411/* FCoE event type */
Arun Easi1e128c82017-02-15 06:28:22 -080010412enum fcoe_event_type {
10413 FCOE_EVENT_INIT_FUNC,
10414 FCOE_EVENT_DESTROY_FUNC,
10415 FCOE_EVENT_STAT_FUNC,
10416 FCOE_EVENT_OFFLOAD_CONN,
10417 FCOE_EVENT_TERMINATE_CONN,
10418 FCOE_EVENT_ERROR,
10419 MAX_FCOE_EVENT_TYPE
10420};
10421
Tomer Tayara2e76992017-12-27 19:30:05 +020010422/* FCoE init params passed by driver to FW in FCoE init ramrod */
Arun Easi1e128c82017-02-15 06:28:22 -080010423struct fcoe_init_ramrod_params {
10424 struct fcoe_init_func_ramrod_data init_ramrod_data;
10425};
10426
Tomer Tayara2e76992017-12-27 19:30:05 +020010427/* FCoE ramrod Command IDs */
Arun Easi1e128c82017-02-15 06:28:22 -080010428enum fcoe_ramrod_cmd_id {
10429 FCOE_RAMROD_CMD_ID_INIT_FUNC,
10430 FCOE_RAMROD_CMD_ID_DESTROY_FUNC,
10431 FCOE_RAMROD_CMD_ID_STAT_FUNC,
10432 FCOE_RAMROD_CMD_ID_OFFLOAD_CONN,
10433 FCOE_RAMROD_CMD_ID_TERMINATE_CONN,
10434 MAX_FCOE_RAMROD_CMD_ID
10435};
10436
Tomer Tayara2e76992017-12-27 19:30:05 +020010437/* FCoE statistics params buffer passed by driver to FW in FCoE statistics
10438 * ramrod.
10439 */
Arun Easi1e128c82017-02-15 06:28:22 -080010440struct fcoe_stat_ramrod_params {
10441 struct fcoe_stat_ramrod_data stat_ramrod_data;
10442};
10443
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010444struct e4_ystorm_fcoe_conn_ag_ctx {
Arun Easi1e128c82017-02-15 06:28:22 -080010445 u8 byte0;
10446 u8 byte1;
10447 u8 flags0;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010448#define E4_YSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
10449#define E4_YSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0
10450#define E4_YSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
10451#define E4_YSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
10452#define E4_YSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
10453#define E4_YSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2
10454#define E4_YSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
10455#define E4_YSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4
10456#define E4_YSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
10457#define E4_YSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6
Arun Easi1e128c82017-02-15 06:28:22 -080010458 u8 flags1;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010459#define E4_YSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
10460#define E4_YSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0
10461#define E4_YSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
10462#define E4_YSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1
10463#define E4_YSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
10464#define E4_YSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2
10465#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
10466#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3
10467#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
10468#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4
10469#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
10470#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5
10471#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
10472#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6
10473#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
10474#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7
Arun Easi1e128c82017-02-15 06:28:22 -080010475 u8 byte2;
10476 u8 byte3;
10477 __le16 word0;
10478 __le32 reg0;
10479 __le32 reg1;
10480 __le16 word1;
10481 __le16 word2;
10482 __le16 word3;
10483 __le16 word4;
10484 __le32 reg2;
10485 __le32 reg3;
10486};
10487
Tomer Tayara2e76992017-12-27 19:30:05 +020010488/* The iscsi storm connection context of Ystorm */
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030010489struct ystorm_iscsi_conn_st_ctx {
10490 __le32 reserved[4];
10491};
10492
Tomer Tayara2e76992017-12-27 19:30:05 +020010493/* Combined iSCSI and TCP storm connection of Pstorm */
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030010494struct pstorm_iscsi_tcp_conn_st_ctx {
10495 __le32 tcp[32];
10496 __le32 iscsi[4];
10497};
10498
Tomer Tayara2e76992017-12-27 19:30:05 +020010499/* The combined tcp and iscsi storm context of Xstorm */
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030010500struct xstorm_iscsi_tcp_conn_st_ctx {
10501 __le32 reserved_iscsi[40];
10502 __le32 reserved_tcp[4];
10503};
10504
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010505struct e4_xstorm_iscsi_conn_ag_ctx {
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030010506 u8 cdu_validation;
10507 u8 state;
10508 u8 flags0;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010509#define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
10510#define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
10511#define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1
10512#define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_SHIFT 1
10513#define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_MASK 0x1
10514#define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_SHIFT 2
10515#define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
10516#define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
10517#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1
10518#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT 4
10519#define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_MASK 0x1
10520#define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_SHIFT 5
10521#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT6_MASK 0x1
10522#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT6_SHIFT 6
10523#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT7_MASK 0x1
10524#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT7_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030010525 u8 flags1;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010526#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT8_MASK 0x1
10527#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT8_SHIFT 0
10528#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT9_MASK 0x1
10529#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT9_SHIFT 1
10530#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT10_MASK 0x1
10531#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT10_SHIFT 2
10532#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT11_MASK 0x1
10533#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT11_SHIFT 3
10534#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT12_MASK 0x1
10535#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT12_SHIFT 4
10536#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT13_MASK 0x1
10537#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT13_SHIFT 5
10538#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT14_MASK 0x1
10539#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT14_SHIFT 6
10540#define E4_XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_MASK 0x1
10541#define E4_XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030010542 u8 flags2;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010543#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
10544#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 0
10545#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
10546#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 2
10547#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
10548#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 4
10549#define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
10550#define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030010551 u8 flags3;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010552#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
10553#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 0
10554#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
10555#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 2
10556#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
10557#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 4
10558#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3
10559#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030010560 u8 flags4;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010561#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3
10562#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT 0
10563#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9_MASK 0x3
10564#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9_SHIFT 2
10565#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF10_MASK 0x3
10566#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF10_SHIFT 4
10567#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF11_MASK 0x3
10568#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF11_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030010569 u8 flags5;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010570#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF12_MASK 0x3
10571#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF12_SHIFT 0
10572#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF13_MASK 0x3
10573#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF13_SHIFT 2
10574#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF14_MASK 0x3
10575#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF14_SHIFT 4
10576#define E4_XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_MASK 0x3
10577#define E4_XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030010578 u8 flags6;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010579#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF16_MASK 0x3
10580#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF16_SHIFT 0
10581#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF17_MASK 0x3
10582#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF17_SHIFT 2
10583#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF18_MASK 0x3
10584#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF18_SHIFT 4
10585#define E4_XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_MASK 0x3
10586#define E4_XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030010587 u8 flags7;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010588#define E4_XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_MASK 0x3
10589#define E4_XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_SHIFT 0
10590#define E4_XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_MASK 0x3
10591#define E4_XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_SHIFT 2
10592#define E4_XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_MASK 0x3
10593#define E4_XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_SHIFT 4
10594#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
10595#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 6
10596#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
10597#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030010598 u8 flags8;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010599#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
10600#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 0
10601#define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
10602#define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 1
10603#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
10604#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 2
10605#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
10606#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 3
10607#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
10608#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 4
10609#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK 0x1
10610#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT 5
10611#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK 0x1
10612#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT 6
10613#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9EN_MASK 0x1
10614#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030010615 u8 flags9;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010616#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF10EN_MASK 0x1
10617#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF10EN_SHIFT 0
10618#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF11EN_MASK 0x1
10619#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF11EN_SHIFT 1
10620#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF12EN_MASK 0x1
10621#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF12EN_SHIFT 2
10622#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF13EN_MASK 0x1
10623#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF13EN_SHIFT 3
10624#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF14EN_MASK 0x1
10625#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF14EN_SHIFT 4
10626#define E4_XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_MASK 0x1
10627#define E4_XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_SHIFT 5
10628#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF16EN_MASK 0x1
10629#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF16EN_SHIFT 6
10630#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF17EN_MASK 0x1
10631#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF17EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030010632 u8 flags10;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010633#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF18EN_MASK 0x1
10634#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF18EN_SHIFT 0
10635#define E4_XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1
10636#define E4_XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT 1
10637#define E4_XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_MASK 0x1
10638#define E4_XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_SHIFT 2
10639#define E4_XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_MASK 0x1
10640#define E4_XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_SHIFT 3
10641#define E4_XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
10642#define E4_XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
10643#define E4_XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_MASK 0x1
10644#define E4_XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_SHIFT 5
10645#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
10646#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 6
10647#define E4_XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_MASK 0x1
10648#define E4_XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030010649 u8 flags11;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010650#define E4_XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1
10651#define E4_XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0
10652#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
10653#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 1
10654#define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_MASK 0x1
10655#define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_SHIFT 2
10656#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
10657#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 3
10658#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
10659#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 4
10660#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
10661#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 5
10662#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
10663#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
10664#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_MASK 0x1
10665#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030010666 u8 flags12;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010667#define E4_XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_MASK 0x1
10668#define E4_XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_SHIFT 0
10669#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_MASK 0x1
10670#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_SHIFT 1
10671#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
10672#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
10673#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
10674#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
10675#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_MASK 0x1
10676#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_SHIFT 4
10677#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_MASK 0x1
10678#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_SHIFT 5
10679#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_MASK 0x1
10680#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_SHIFT 6
10681#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_MASK 0x1
10682#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030010683 u8 flags13;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010684#define E4_XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_MASK 0x1
10685#define E4_XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_SHIFT 0
10686#define E4_XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_MASK 0x1
10687#define E4_XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_SHIFT 1
10688#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
10689#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
10690#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
10691#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
10692#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
10693#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
10694#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
10695#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
10696#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
10697#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
10698#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
10699#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030010700 u8 flags14;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010701#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT16_MASK 0x1
10702#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT16_SHIFT 0
10703#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT17_MASK 0x1
10704#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT17_SHIFT 1
10705#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT18_MASK 0x1
10706#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT18_SHIFT 2
10707#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT19_MASK 0x1
10708#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT19_SHIFT 3
10709#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT20_MASK 0x1
10710#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT20_SHIFT 4
10711#define E4_XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_MASK 0x1
10712#define E4_XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_SHIFT 5
10713#define E4_XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_MASK 0x3
10714#define E4_XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030010715 u8 byte2;
10716 __le16 physical_q0;
10717 __le16 physical_q1;
10718 __le16 dummy_dorq_var;
10719 __le16 sq_cons;
10720 __le16 sq_prod;
10721 __le16 word5;
10722 __le16 slow_io_total_data_tx_update;
10723 u8 byte3;
10724 u8 byte4;
10725 u8 byte5;
10726 u8 byte6;
10727 __le32 reg0;
10728 __le32 reg1;
10729 __le32 reg2;
10730 __le32 more_to_send_seq;
10731 __le32 reg4;
10732 __le32 reg5;
10733 __le32 hq_scan_next_relevant_ack;
10734 __le16 r2tq_prod;
10735 __le16 r2tq_cons;
10736 __le16 hq_prod;
10737 __le16 hq_cons;
10738 __le32 remain_seq;
10739 __le32 bytes_to_next_pdu;
10740 __le32 hq_tcp_seq;
10741 u8 byte7;
10742 u8 byte8;
10743 u8 byte9;
10744 u8 byte10;
10745 u8 byte11;
10746 u8 byte12;
10747 u8 byte13;
10748 u8 byte14;
10749 u8 byte15;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010750 u8 e5_reserved;
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030010751 __le16 word11;
10752 __le32 reg10;
10753 __le32 reg11;
10754 __le32 exp_stat_sn;
Mintz, Yuvalbe086e72017-03-11 18:39:18 +020010755 __le32 ongoing_fast_rxmit_seq;
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030010756 __le32 reg14;
10757 __le32 reg15;
10758 __le32 reg16;
10759 __le32 reg17;
10760};
10761
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010762struct e4_tstorm_iscsi_conn_ag_ctx {
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030010763 u8 reserved0;
10764 u8 state;
10765 u8 flags0;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010766#define E4_TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
10767#define E4_TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
10768#define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
10769#define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
10770#define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT2_MASK 0x1
10771#define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT2_SHIFT 2
10772#define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT3_MASK 0x1
10773#define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT3_SHIFT 3
10774#define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1
10775#define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT 4
10776#define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT5_MASK 0x1
10777#define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT5_SHIFT 5
10778#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
10779#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030010780 u8 flags1;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010781#define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_MASK 0x3
10782#define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_SHIFT 0
10783#define E4_TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_MASK 0x3
10784#define E4_TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_SHIFT 2
10785#define E4_TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
10786#define E4_TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 4
10787#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
10788#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030010789 u8 flags2;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010790#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
10791#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 0
10792#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
10793#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 2
10794#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3
10795#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT 4
10796#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3
10797#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030010798 u8 flags3;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010799#define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
10800#define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
10801#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF10_MASK 0x3
10802#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF10_SHIFT 2
10803#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
10804#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 4
10805#define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_MASK 0x1
10806#define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_SHIFT 5
10807#define E4_TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_MASK 0x1
10808#define E4_TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_SHIFT 6
10809#define E4_TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
10810#define E4_TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030010811 u8 flags4;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010812#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
10813#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 0
10814#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
10815#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 1
10816#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
10817#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 2
10818#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK 0x1
10819#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT 3
10820#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK 0x1
10821#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT 4
10822#define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
10823#define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 5
10824#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF10EN_MASK 0x1
10825#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF10EN_SHIFT 6
10826#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
10827#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030010828 u8 flags5;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010829#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
10830#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 0
10831#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
10832#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 1
10833#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
10834#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 2
10835#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
10836#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 3
10837#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
10838#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 4
10839#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
10840#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 5
10841#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
10842#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 6
10843#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK 0x1
10844#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030010845 __le32 reg0;
10846 __le32 reg1;
10847 __le32 reg2;
10848 __le32 reg3;
10849 __le32 reg4;
10850 __le32 reg5;
10851 __le32 reg6;
10852 __le32 reg7;
10853 __le32 reg8;
Mintz, Yuvalbe086e72017-03-11 18:39:18 +020010854 u8 cid_offload_cnt;
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030010855 u8 byte3;
10856 __le16 word0;
10857};
10858
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010859struct e4_ustorm_iscsi_conn_ag_ctx {
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030010860 u8 byte0;
10861 u8 byte1;
10862 u8 flags0;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010863#define E4_USTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
10864#define E4_USTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0
10865#define E4_USTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
10866#define E4_USTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
10867#define E4_USTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
10868#define E4_USTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2
10869#define E4_USTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
10870#define E4_USTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4
10871#define E4_USTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
10872#define E4_USTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030010873 u8 flags1;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010874#define E4_USTORM_ISCSI_CONN_AG_CTX_CF3_MASK 0x3
10875#define E4_USTORM_ISCSI_CONN_AG_CTX_CF3_SHIFT 0
10876#define E4_USTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
10877#define E4_USTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 2
10878#define E4_USTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
10879#define E4_USTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 4
10880#define E4_USTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
10881#define E4_USTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030010882 u8 flags2;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010883#define E4_USTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
10884#define E4_USTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0
10885#define E4_USTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
10886#define E4_USTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1
10887#define E4_USTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
10888#define E4_USTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2
10889#define E4_USTORM_ISCSI_CONN_AG_CTX_CF3EN_MASK 0x1
10890#define E4_USTORM_ISCSI_CONN_AG_CTX_CF3EN_SHIFT 3
10891#define E4_USTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
10892#define E4_USTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 4
10893#define E4_USTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
10894#define E4_USTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 5
10895#define E4_USTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
10896#define E4_USTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 6
10897#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
10898#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030010899 u8 flags3;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010900#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
10901#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 0
10902#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
10903#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 1
10904#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
10905#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 2
10906#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
10907#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 3
10908#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
10909#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 4
10910#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
10911#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 5
10912#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
10913#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 6
10914#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK 0x1
10915#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030010916 u8 byte2;
10917 u8 byte3;
10918 __le16 word0;
10919 __le16 word1;
10920 __le32 reg0;
10921 __le32 reg1;
10922 __le32 reg2;
10923 __le32 reg3;
10924 __le16 word2;
10925 __le16 word3;
10926};
10927
Tomer Tayara2e76992017-12-27 19:30:05 +020010928/* The iscsi storm connection context of Tstorm */
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030010929struct tstorm_iscsi_conn_st_ctx {
10930 __le32 reserved[40];
10931};
10932
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010933struct e4_mstorm_iscsi_conn_ag_ctx {
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030010934 u8 reserved;
10935 u8 state;
10936 u8 flags0;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010937#define E4_MSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
10938#define E4_MSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0
10939#define E4_MSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
10940#define E4_MSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
10941#define E4_MSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
10942#define E4_MSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2
10943#define E4_MSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
10944#define E4_MSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4
10945#define E4_MSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
10946#define E4_MSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030010947 u8 flags1;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010948#define E4_MSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
10949#define E4_MSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0
10950#define E4_MSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
10951#define E4_MSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1
10952#define E4_MSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
10953#define E4_MSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2
10954#define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
10955#define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 3
10956#define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
10957#define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 4
10958#define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
10959#define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 5
10960#define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
10961#define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 6
10962#define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
10963#define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030010964 __le16 word0;
10965 __le16 word1;
10966 __le32 reg0;
10967 __le32 reg1;
10968};
10969
Tomer Tayara2e76992017-12-27 19:30:05 +020010970/* Combined iSCSI and TCP storm connection of Mstorm */
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030010971struct mstorm_iscsi_tcp_conn_st_ctx {
10972 __le32 reserved_tcp[20];
10973 __le32 reserved_iscsi[8];
10974};
10975
Tomer Tayara2e76992017-12-27 19:30:05 +020010976/* The iscsi storm context of Ustorm */
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030010977struct ustorm_iscsi_conn_st_ctx {
10978 __le32 reserved[52];
10979};
10980
Tomer Tayara2e76992017-12-27 19:30:05 +020010981/* iscsi connection context */
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010982struct e4_iscsi_conn_context {
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030010983 struct ystorm_iscsi_conn_st_ctx ystorm_st_context;
10984 struct regpair ystorm_st_padding[2];
10985 struct pstorm_iscsi_tcp_conn_st_ctx pstorm_st_context;
10986 struct regpair pstorm_st_padding[2];
10987 struct pb_context xpb2_context;
10988 struct xstorm_iscsi_tcp_conn_st_ctx xstorm_st_context;
10989 struct regpair xstorm_st_padding[2];
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010990 struct e4_xstorm_iscsi_conn_ag_ctx xstorm_ag_context;
10991 struct e4_tstorm_iscsi_conn_ag_ctx tstorm_ag_context;
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030010992 struct regpair tstorm_ag_padding[2];
10993 struct timers_context timer_context;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010994 struct e4_ustorm_iscsi_conn_ag_ctx ustorm_ag_context;
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030010995 struct pb_context upb_context;
10996 struct tstorm_iscsi_conn_st_ctx tstorm_st_context;
10997 struct regpair tstorm_st_padding[2];
Tomer Tayar21dd79e2017-12-27 19:30:06 +020010998 struct e4_mstorm_iscsi_conn_ag_ctx mstorm_ag_context;
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030010999 struct mstorm_iscsi_tcp_conn_st_ctx mstorm_st_context;
11000 struct ustorm_iscsi_conn_st_ctx ustorm_st_context;
11001};
11002
Tomer Tayara2e76992017-12-27 19:30:05 +020011003/* iSCSI init params passed by driver to FW in iSCSI init ramrod */
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030011004struct iscsi_init_ramrod_params {
11005 struct iscsi_spe_func_init iscsi_init_spe;
11006 struct tcp_init_params tcp_init;
11007};
11008
Tomer Tayar21dd79e2017-12-27 19:30:06 +020011009struct e4_ystorm_iscsi_conn_ag_ctx {
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030011010 u8 byte0;
11011 u8 byte1;
11012 u8 flags0;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020011013#define E4_YSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
11014#define E4_YSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0
11015#define E4_YSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
11016#define E4_YSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
11017#define E4_YSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
11018#define E4_YSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2
11019#define E4_YSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
11020#define E4_YSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4
11021#define E4_YSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
11022#define E4_YSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030011023 u8 flags1;
Tomer Tayar21dd79e2017-12-27 19:30:06 +020011024#define E4_YSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
11025#define E4_YSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0
11026#define E4_YSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
11027#define E4_YSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1
11028#define E4_YSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
11029#define E4_YSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2
11030#define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
11031#define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 3
11032#define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
11033#define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 4
11034#define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
11035#define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 5
11036#define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
11037#define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 6
11038#define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
11039#define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 7
Yuval Mintz7a9b6b82016-06-03 14:35:33 +030011040 u8 byte2;
11041 u8 byte3;
11042 __le16 word0;
11043 __le32 reg0;
11044 __le32 reg1;
11045 __le16 word1;
11046 __le16 word2;
11047 __le16 word3;
11048 __le16 word4;
11049 __le32 reg2;
11050 __le32 reg3;
11051};
Tomer Tayarc965db42016-09-07 16:36:24 +030011052
11053#define MFW_TRACE_SIGNATURE 0x25071946
11054
11055/* The trace in the buffer */
11056#define MFW_TRACE_EVENTID_MASK 0x00ffff
11057#define MFW_TRACE_PRM_SIZE_MASK 0x0f0000
11058#define MFW_TRACE_PRM_SIZE_SHIFT 16
11059#define MFW_TRACE_ENTRY_SIZE 3
11060
11061struct mcp_trace {
11062 u32 signature; /* Help to identify that the trace is valid */
11063 u32 size; /* the size of the trace buffer in bytes */
11064 u32 curr_level; /* 2 - all will be written to the buffer
11065 * 1 - debug trace will not be written
11066 * 0 - just errors will be written to the buffer
11067 */
11068 u32 modules_mask[2]; /* a bit per module, 1 means write it, 0 means
11069 * mask it.
11070 */
11071
11072 /* Warning: the following pointers are assumed to be 32bits as they are
11073 * used only in the MFW.
11074 */
11075 u32 trace_prod; /* The next trace will be written to this offset */
11076 u32 trace_oldest; /* The oldest valid trace starts at this offset
11077 * (usually very close after the current producer).
11078 */
11079};
11080
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011081#define VF_MAX_STATIC 192
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011082
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011083#define MCP_GLOB_PATH_MAX 2
11084#define MCP_PORT_MAX 2
11085#define MCP_GLOB_PORT_MAX 4
11086#define MCP_GLOB_FUNC_MAX 16
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011087
Tomer Tayarc965db42016-09-07 16:36:24 +030011088typedef u32 offsize_t; /* In DWORDS !!! */
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011089/* Offset from the beginning of the MCP scratchpad */
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011090#define OFFSIZE_OFFSET_SHIFT 0
11091#define OFFSIZE_OFFSET_MASK 0x0000ffff
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011092/* Size of specific element (not the whole array if any) */
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011093#define OFFSIZE_SIZE_SHIFT 16
11094#define OFFSIZE_SIZE_MASK 0xffff0000
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011095
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011096#define SECTION_OFFSET(_offsize) ((((_offsize & \
11097 OFFSIZE_OFFSET_MASK) >> \
11098 OFFSIZE_OFFSET_SHIFT) << 2))
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011099
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011100#define QED_SECTION_SIZE(_offsize) (((_offsize & \
11101 OFFSIZE_SIZE_MASK) >> \
11102 OFFSIZE_SIZE_SHIFT) << 2)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011103
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011104#define SECTION_ADDR(_offsize, idx) (MCP_REG_SCRATCH + \
11105 SECTION_OFFSET(_offsize) + \
11106 (QED_SECTION_SIZE(_offsize) * idx))
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011107
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011108#define SECTION_OFFSIZE_ADDR(_pub_base, _section) \
11109 (_pub_base + offsetof(struct mcp_public_data, sections[_section]))
11110
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011111/* PHY configuration */
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011112struct eth_phy_cfg {
11113 u32 speed;
11114#define ETH_SPEED_AUTONEG 0
11115#define ETH_SPEED_SMARTLINQ 0x8
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011116
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011117 u32 pause;
11118#define ETH_PAUSE_NONE 0x0
11119#define ETH_PAUSE_AUTONEG 0x1
11120#define ETH_PAUSE_RX 0x2
11121#define ETH_PAUSE_TX 0x4
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011122
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011123 u32 adv_speed;
11124 u32 loopback_mode;
11125#define ETH_LOOPBACK_NONE (0)
11126#define ETH_LOOPBACK_INT_PHY (1)
11127#define ETH_LOOPBACK_EXT_PHY (2)
11128#define ETH_LOOPBACK_EXT (3)
11129#define ETH_LOOPBACK_MAC (4)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011130
Sudarsana Reddy Kalluru645874e2017-07-26 06:07:11 -070011131 u32 eee_cfg;
11132#define EEE_CFG_EEE_ENABLED BIT(0)
11133#define EEE_CFG_TX_LPI BIT(1)
11134#define EEE_CFG_ADV_SPEED_1G BIT(2)
11135#define EEE_CFG_ADV_SPEED_10G BIT(3)
11136#define EEE_TX_TIMER_USEC_MASK (0xfffffff0)
11137#define EEE_TX_TIMER_USEC_OFFSET 4
11138#define EEE_TX_TIMER_USEC_BALANCED_TIME (0xa00)
11139#define EEE_TX_TIMER_USEC_AGGRESSIVE_TIME (0x100)
11140#define EEE_TX_TIMER_USEC_LATENCY_TIME (0x6000)
11141
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011142 u32 feature_config_flags;
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011143#define ETH_EEE_MODE_ADV_LPI (1 << 0)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011144};
11145
11146struct port_mf_cfg {
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011147 u32 dynamic_cfg;
11148#define PORT_MF_CFG_OV_TAG_MASK 0x0000ffff
11149#define PORT_MF_CFG_OV_TAG_SHIFT 0
11150#define PORT_MF_CFG_OV_TAG_DEFAULT PORT_MF_CFG_OV_TAG_MASK
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011151
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011152 u32 reserved[1];
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011153};
11154
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011155struct eth_stats {
11156 u64 r64;
11157 u64 r127;
11158 u64 r255;
11159 u64 r511;
11160 u64 r1023;
11161 u64 r1518;
Mintz, Yuval9c79dda2017-03-14 16:23:54 +020011162
11163 union {
11164 struct {
11165 u64 r1522;
11166 u64 r2047;
11167 u64 r4095;
11168 u64 r9216;
11169 u64 r16383;
11170 } bb0;
11171 struct {
11172 u64 unused1;
11173 u64 r1519_to_max;
11174 u64 unused2;
11175 u64 unused3;
11176 u64 unused4;
11177 } ah0;
11178 } u0;
11179
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011180 u64 rfcs;
11181 u64 rxcf;
11182 u64 rxpf;
11183 u64 rxpp;
11184 u64 raln;
11185 u64 rfcr;
11186 u64 rovr;
11187 u64 rjbr;
11188 u64 rund;
11189 u64 rfrg;
11190 u64 t64;
11191 u64 t127;
11192 u64 t255;
11193 u64 t511;
11194 u64 t1023;
11195 u64 t1518;
Mintz, Yuval9c79dda2017-03-14 16:23:54 +020011196
11197 union {
11198 struct {
11199 u64 t2047;
11200 u64 t4095;
11201 u64 t9216;
11202 u64 t16383;
11203 } bb1;
11204 struct {
11205 u64 t1519_to_max;
11206 u64 unused6;
11207 u64 unused7;
11208 u64 unused8;
11209 } ah1;
11210 } u1;
11211
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011212 u64 txpf;
11213 u64 txpp;
Mintz, Yuval9c79dda2017-03-14 16:23:54 +020011214
11215 union {
11216 struct {
11217 u64 tlpiec;
11218 u64 tncl;
11219 } bb2;
11220 struct {
11221 u64 unused9;
11222 u64 unused10;
11223 } ah2;
11224 } u2;
11225
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011226 u64 rbyte;
11227 u64 rxuca;
11228 u64 rxmca;
11229 u64 rxbca;
11230 u64 rxpok;
11231 u64 tbyte;
11232 u64 txuca;
11233 u64 txmca;
11234 u64 txbca;
11235 u64 txcf;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011236};
11237
11238struct brb_stats {
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011239 u64 brb_truncate[8];
11240 u64 brb_discard[8];
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011241};
11242
11243struct port_stats {
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011244 struct brb_stats brb;
11245 struct eth_stats eth;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011246};
11247
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011248struct couple_mode_teaming {
11249 u8 port_cmt[MCP_GLOB_PORT_MAX];
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011250#define PORT_CMT_IN_TEAM (1 << 0)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011251
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011252#define PORT_CMT_PORT_ROLE (1 << 1)
11253#define PORT_CMT_PORT_INACTIVE (0 << 1)
11254#define PORT_CMT_PORT_ACTIVE (1 << 1)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011255
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011256#define PORT_CMT_TEAM_MASK (1 << 2)
11257#define PORT_CMT_TEAM0 (0 << 2)
11258#define PORT_CMT_TEAM1 (1 << 2)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011259};
11260
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011261#define LLDP_CHASSIS_ID_STAT_LEN 4
11262#define LLDP_PORT_ID_STAT_LEN 4
11263#define DCBX_MAX_APP_PROTOCOL 32
11264#define MAX_SYSTEM_LLDP_TLV_DATA 32
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011265
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011266enum _lldp_agent {
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011267 LLDP_NEAREST_BRIDGE = 0,
11268 LLDP_NEAREST_NON_TPMR_BRIDGE,
11269 LLDP_NEAREST_CUSTOMER_BRIDGE,
11270 LLDP_MAX_LLDP_AGENTS
11271};
11272
11273struct lldp_config_params_s {
11274 u32 config;
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011275#define LLDP_CONFIG_TX_INTERVAL_MASK 0x000000ff
11276#define LLDP_CONFIG_TX_INTERVAL_SHIFT 0
11277#define LLDP_CONFIG_HOLD_MASK 0x00000f00
11278#define LLDP_CONFIG_HOLD_SHIFT 8
11279#define LLDP_CONFIG_MAX_CREDIT_MASK 0x0000f000
11280#define LLDP_CONFIG_MAX_CREDIT_SHIFT 12
11281#define LLDP_CONFIG_ENABLE_RX_MASK 0x40000000
11282#define LLDP_CONFIG_ENABLE_RX_SHIFT 30
11283#define LLDP_CONFIG_ENABLE_TX_MASK 0x80000000
11284#define LLDP_CONFIG_ENABLE_TX_SHIFT 31
11285 u32 local_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
11286 u32 local_port_id[LLDP_PORT_ID_STAT_LEN];
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011287};
11288
11289struct lldp_status_params_s {
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011290 u32 prefix_seq_num;
11291 u32 status;
11292 u32 peer_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
11293 u32 peer_port_id[LLDP_PORT_ID_STAT_LEN];
11294 u32 suffix_seq_num;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011295};
11296
11297struct dcbx_ets_feature {
11298 u32 flags;
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011299#define DCBX_ETS_ENABLED_MASK 0x00000001
11300#define DCBX_ETS_ENABLED_SHIFT 0
11301#define DCBX_ETS_WILLING_MASK 0x00000002
11302#define DCBX_ETS_WILLING_SHIFT 1
11303#define DCBX_ETS_ERROR_MASK 0x00000004
11304#define DCBX_ETS_ERROR_SHIFT 2
11305#define DCBX_ETS_CBS_MASK 0x00000008
11306#define DCBX_ETS_CBS_SHIFT 3
11307#define DCBX_ETS_MAX_TCS_MASK 0x000000f0
11308#define DCBX_ETS_MAX_TCS_SHIFT 4
Ariel Eliorb5a9ee72017-04-03 12:21:09 +030011309#define DCBX_OOO_TC_MASK 0x00000f00
11310#define DCBX_OOO_TC_SHIFT 8
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011311 u32 pri_tc_tbl[1];
Ariel Eliorb5a9ee72017-04-03 12:21:09 +030011312#define DCBX_TCP_OOO_TC (4)
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011313
Ariel Eliorb5a9ee72017-04-03 12:21:09 +030011314#define NIG_ETS_ISCSI_OOO_CLIENT_OFFSET (DCBX_TCP_OOO_TC + 1)
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011315#define DCBX_CEE_STRICT_PRIORITY 0xf
11316 u32 tc_bw_tbl[2];
11317 u32 tc_tsa_tbl[2];
11318#define DCBX_ETS_TSA_STRICT 0
11319#define DCBX_ETS_TSA_CBS 1
11320#define DCBX_ETS_TSA_ETS 2
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011321};
11322
Ariel Eliorb5a9ee72017-04-03 12:21:09 +030011323#define DCBX_TCP_OOO_TC (4)
11324#define DCBX_TCP_OOO_K2_4PORT_TC (3)
11325
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011326struct dcbx_app_priority_entry {
11327 u32 entry;
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011328#define DCBX_APP_PRI_MAP_MASK 0x000000ff
11329#define DCBX_APP_PRI_MAP_SHIFT 0
11330#define DCBX_APP_PRI_0 0x01
11331#define DCBX_APP_PRI_1 0x02
11332#define DCBX_APP_PRI_2 0x04
11333#define DCBX_APP_PRI_3 0x08
11334#define DCBX_APP_PRI_4 0x10
11335#define DCBX_APP_PRI_5 0x20
11336#define DCBX_APP_PRI_6 0x40
11337#define DCBX_APP_PRI_7 0x80
11338#define DCBX_APP_SF_MASK 0x00000300
11339#define DCBX_APP_SF_SHIFT 8
11340#define DCBX_APP_SF_ETHTYPE 0
11341#define DCBX_APP_SF_PORT 1
Sudarsana Reddy Kallurufb9ea8a2016-08-08 21:57:41 -040011342#define DCBX_APP_SF_IEEE_MASK 0x0000f000
11343#define DCBX_APP_SF_IEEE_SHIFT 12
11344#define DCBX_APP_SF_IEEE_RESERVED 0
11345#define DCBX_APP_SF_IEEE_ETHTYPE 1
11346#define DCBX_APP_SF_IEEE_TCP_PORT 2
11347#define DCBX_APP_SF_IEEE_UDP_PORT 3
11348#define DCBX_APP_SF_IEEE_TCP_UDP_PORT 4
11349
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011350#define DCBX_APP_PROTOCOL_ID_MASK 0xffff0000
11351#define DCBX_APP_PROTOCOL_ID_SHIFT 16
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011352};
11353
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011354struct dcbx_app_priority_feature {
11355 u32 flags;
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011356#define DCBX_APP_ENABLED_MASK 0x00000001
11357#define DCBX_APP_ENABLED_SHIFT 0
11358#define DCBX_APP_WILLING_MASK 0x00000002
11359#define DCBX_APP_WILLING_SHIFT 1
11360#define DCBX_APP_ERROR_MASK 0x00000004
11361#define DCBX_APP_ERROR_SHIFT 2
11362#define DCBX_APP_MAX_TCS_MASK 0x0000f000
11363#define DCBX_APP_MAX_TCS_SHIFT 12
11364#define DCBX_APP_NUM_ENTRIES_MASK 0x00ff0000
11365#define DCBX_APP_NUM_ENTRIES_SHIFT 16
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011366 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
11367};
11368
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011369struct dcbx_features {
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011370 struct dcbx_ets_feature ets;
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011371 u32 pfc;
11372#define DCBX_PFC_PRI_EN_BITMAP_MASK 0x000000ff
11373#define DCBX_PFC_PRI_EN_BITMAP_SHIFT 0
11374#define DCBX_PFC_PRI_EN_BITMAP_PRI_0 0x01
11375#define DCBX_PFC_PRI_EN_BITMAP_PRI_1 0x02
11376#define DCBX_PFC_PRI_EN_BITMAP_PRI_2 0x04
11377#define DCBX_PFC_PRI_EN_BITMAP_PRI_3 0x08
11378#define DCBX_PFC_PRI_EN_BITMAP_PRI_4 0x10
11379#define DCBX_PFC_PRI_EN_BITMAP_PRI_5 0x20
11380#define DCBX_PFC_PRI_EN_BITMAP_PRI_6 0x40
11381#define DCBX_PFC_PRI_EN_BITMAP_PRI_7 0x80
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011382
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011383#define DCBX_PFC_FLAGS_MASK 0x0000ff00
11384#define DCBX_PFC_FLAGS_SHIFT 8
11385#define DCBX_PFC_CAPS_MASK 0x00000f00
11386#define DCBX_PFC_CAPS_SHIFT 8
11387#define DCBX_PFC_MBC_MASK 0x00004000
11388#define DCBX_PFC_MBC_SHIFT 14
11389#define DCBX_PFC_WILLING_MASK 0x00008000
11390#define DCBX_PFC_WILLING_SHIFT 15
11391#define DCBX_PFC_ENABLED_MASK 0x00010000
11392#define DCBX_PFC_ENABLED_SHIFT 16
11393#define DCBX_PFC_ERROR_MASK 0x00020000
11394#define DCBX_PFC_ERROR_SHIFT 17
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011395
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011396 struct dcbx_app_priority_feature app;
11397};
11398
11399struct dcbx_local_params {
11400 u32 config;
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011401#define DCBX_CONFIG_VERSION_MASK 0x00000007
11402#define DCBX_CONFIG_VERSION_SHIFT 0
11403#define DCBX_CONFIG_VERSION_DISABLED 0
11404#define DCBX_CONFIG_VERSION_IEEE 1
11405#define DCBX_CONFIG_VERSION_CEE 2
11406#define DCBX_CONFIG_VERSION_STATIC 4
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011407
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011408 u32 flags;
11409 struct dcbx_features features;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011410};
11411
11412struct dcbx_mib {
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011413 u32 prefix_seq_num;
11414 u32 flags;
11415 struct dcbx_features features;
11416 u32 suffix_seq_num;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011417};
11418
11419struct lldp_system_tlvs_buffer_s {
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011420 u16 valid;
11421 u16 length;
11422 u32 data[MAX_SYSTEM_LLDP_TLV_DATA];
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011423};
11424
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011425struct dcb_dscp_map {
11426 u32 flags;
11427#define DCB_DSCP_ENABLE_MASK 0x1
11428#define DCB_DSCP_ENABLE_SHIFT 0
11429#define DCB_DSCP_ENABLE 1
11430 u32 dscp_pri_map[8];
11431};
11432
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011433struct public_global {
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011434 u32 max_path;
11435 u32 max_ports;
Mintz, Yuvalbe086e72017-03-11 18:39:18 +020011436#define MODE_1P 1
11437#define MODE_2P 2
11438#define MODE_3P 3
11439#define MODE_4P 4
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011440 u32 debug_mb_offset;
11441 u32 phymod_dbg_mb_offset;
11442 struct couple_mode_teaming cmt;
11443 s32 internal_temperature;
11444 u32 mfw_ver;
11445 u32 running_bundle_id;
11446 s32 external_temperature;
11447 u32 mdump_reason;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011448};
11449
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011450struct fw_flr_mb {
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011451 u32 aggint;
11452 u32 opgen_addr;
11453 u32 accum_ack;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011454};
11455
11456struct public_path {
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011457 struct fw_flr_mb flr_mb;
11458 u32 mcp_vf_disabled[VF_MAX_STATIC / 32];
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011459
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011460 u32 process_kill;
11461#define PROCESS_KILL_COUNTER_MASK 0x0000ffff
11462#define PROCESS_KILL_COUNTER_SHIFT 0
11463#define PROCESS_KILL_GLOB_AEU_BIT_MASK 0xffff0000
11464#define PROCESS_KILL_GLOB_AEU_BIT_SHIFT 16
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011465#define GLOBAL_AEU_BIT(aeu_reg_id, aeu_bit) (aeu_reg_id * 32 + aeu_bit)
11466};
11467
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011468struct public_port {
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011469 u32 validity_map;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011470
11471 u32 link_status;
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011472#define LINK_STATUS_LINK_UP 0x00000001
11473#define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001e
11474#define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (1 << 1)
11475#define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (2 << 1)
11476#define LINK_STATUS_SPEED_AND_DUPLEX_10G (3 << 1)
11477#define LINK_STATUS_SPEED_AND_DUPLEX_20G (4 << 1)
11478#define LINK_STATUS_SPEED_AND_DUPLEX_40G (5 << 1)
11479#define LINK_STATUS_SPEED_AND_DUPLEX_50G (6 << 1)
11480#define LINK_STATUS_SPEED_AND_DUPLEX_100G (7 << 1)
11481#define LINK_STATUS_SPEED_AND_DUPLEX_25G (8 << 1)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011482
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011483#define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011484
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011485#define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
11486#define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011487
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011488#define LINK_STATUS_PFC_ENABLED 0x00000100
11489#define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
11490#define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
11491#define LINK_STATUS_LINK_PARTNER_10G_CAPABLE 0x00000800
11492#define LINK_STATUS_LINK_PARTNER_20G_CAPABLE 0x00001000
11493#define LINK_STATUS_LINK_PARTNER_40G_CAPABLE 0x00002000
11494#define LINK_STATUS_LINK_PARTNER_50G_CAPABLE 0x00004000
11495#define LINK_STATUS_LINK_PARTNER_100G_CAPABLE 0x00008000
11496#define LINK_STATUS_LINK_PARTNER_25G_CAPABLE 0x00010000
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011497
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011498#define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
11499#define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0 << 18)
11500#define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1 << 18)
11501#define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2 << 18)
11502#define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3 << 18)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011503
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011504#define LINK_STATUS_SFP_TX_FAULT 0x00100000
11505#define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00200000
11506#define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00400000
11507#define LINK_STATUS_RX_SIGNAL_PRESENT 0x00800000
11508#define LINK_STATUS_MAC_LOCAL_FAULT 0x01000000
11509#define LINK_STATUS_MAC_REMOTE_FAULT 0x02000000
11510#define LINK_STATUS_UNSUPPORTED_SPD_REQ 0x04000000
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011511
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011512 u32 link_status1;
11513 u32 ext_phy_fw_version;
11514 u32 drv_phy_cfg_addr;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011515
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011516 u32 port_stx;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011517
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011518 u32 stat_nig_timer;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011519
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011520 struct port_mf_cfg port_mf_config;
11521 struct port_stats stats;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011522
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011523 u32 media_type;
11524#define MEDIA_UNSPECIFIED 0x0
11525#define MEDIA_SFPP_10G_FIBER 0x1
11526#define MEDIA_XFP_FIBER 0x2
11527#define MEDIA_DA_TWINAX 0x3
11528#define MEDIA_BASE_T 0x4
11529#define MEDIA_SFP_1G_FIBER 0x5
11530#define MEDIA_MODULE_FIBER 0x6
11531#define MEDIA_KR 0xf0
11532#define MEDIA_NOT_PRESENT 0xff
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011533
11534 u32 lfa_status;
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011535 u32 link_change_count;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011536
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011537 struct lldp_config_params_s lldp_config_params[LLDP_MAX_LLDP_AGENTS];
11538 struct lldp_status_params_s lldp_status_params[LLDP_MAX_LLDP_AGENTS];
11539 struct lldp_system_tlvs_buffer_s system_lldp_tlvs_buf;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011540
11541 /* DCBX related MIB */
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011542 struct dcbx_local_params local_admin_dcbx_mib;
11543 struct dcbx_mib remote_dcbx_mib;
11544 struct dcbx_mib operational_dcbx_mib;
Yuval Mintzfc48b7a2016-02-15 13:22:35 -050011545
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011546 u32 reserved[2];
11547 u32 transceiver_data;
11548#define ETH_TRANSCEIVER_STATE_MASK 0x000000FF
11549#define ETH_TRANSCEIVER_STATE_SHIFT 0x00000000
11550#define ETH_TRANSCEIVER_STATE_UNPLUGGED 0x00000000
11551#define ETH_TRANSCEIVER_STATE_PRESENT 0x00000001
11552#define ETH_TRANSCEIVER_STATE_VALID 0x00000003
11553#define ETH_TRANSCEIVER_STATE_UPDATING 0x00000008
11554
11555 u32 wol_info;
11556 u32 wol_pkt_len;
11557 u32 wol_pkt_details;
11558 struct dcb_dscp_map dcb_dscp_map;
Sudarsana Reddy Kalluru645874e2017-07-26 06:07:11 -070011559
11560 u32 eee_status;
11561#define EEE_ACTIVE_BIT BIT(0)
11562#define EEE_LD_ADV_STATUS_MASK 0x000000f0
11563#define EEE_LD_ADV_STATUS_OFFSET 4
11564#define EEE_1G_ADV BIT(1)
11565#define EEE_10G_ADV BIT(2)
11566#define EEE_LP_ADV_STATUS_MASK 0x00000f00
11567#define EEE_LP_ADV_STATUS_OFFSET 8
11568#define EEE_SUPPORTED_SPEED_MASK 0x0000f000
11569#define EEE_SUPPORTED_SPEED_OFFSET 12
11570#define EEE_1G_SUPPORTED BIT(1)
11571#define EEE_10G_SUPPORTED BIT(2)
11572
11573 u32 eee_remote;
11574#define EEE_REMOTE_TW_TX_MASK 0x0000ffff
11575#define EEE_REMOTE_TW_TX_OFFSET 0
11576#define EEE_REMOTE_TW_RX_MASK 0xffff0000
11577#define EEE_REMOTE_TW_RX_OFFSET 16
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011578};
11579
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011580struct public_func {
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011581 u32 reserved0[2];
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011582
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011583 u32 mtu_size;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011584
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011585 u32 reserved[7];
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011586
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011587 u32 config;
11588#define FUNC_MF_CFG_FUNC_HIDE 0x00000001
11589#define FUNC_MF_CFG_PAUSE_ON_HOST_RING 0x00000002
11590#define FUNC_MF_CFG_PAUSE_ON_HOST_RING_SHIFT 0x00000001
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011591
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011592#define FUNC_MF_CFG_PROTOCOL_MASK 0x000000f0
11593#define FUNC_MF_CFG_PROTOCOL_SHIFT 4
11594#define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000000
Yuval Mintzc5ac9312016-06-03 14:35:34 +030011595#define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000010
Arun Easi1e128c82017-02-15 06:28:22 -080011596#define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000020
Yuval Mintzc5ac9312016-06-03 14:35:34 +030011597#define FUNC_MF_CFG_PROTOCOL_ROCE 0x00000030
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011598#define FUNC_MF_CFG_PROTOCOL_MAX 0x00000030
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011599
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011600#define FUNC_MF_CFG_MIN_BW_MASK 0x0000ff00
11601#define FUNC_MF_CFG_MIN_BW_SHIFT 8
11602#define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
11603#define FUNC_MF_CFG_MAX_BW_MASK 0x00ff0000
11604#define FUNC_MF_CFG_MAX_BW_SHIFT 16
11605#define FUNC_MF_CFG_MAX_BW_DEFAULT 0x00640000
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011606
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011607 u32 status;
11608#define FUNC_STATUS_VLINK_DOWN 0x00000001
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011609
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011610 u32 mac_upper;
11611#define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
11612#define FUNC_MF_CFG_UPPERMAC_SHIFT 0
11613#define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK
11614 u32 mac_lower;
11615#define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011616
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011617 u32 fcoe_wwn_port_name_upper;
11618 u32 fcoe_wwn_port_name_lower;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011619
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011620 u32 fcoe_wwn_node_name_upper;
11621 u32 fcoe_wwn_node_name_lower;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011622
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011623 u32 ovlan_stag;
11624#define FUNC_MF_CFG_OV_STAG_MASK 0x0000ffff
11625#define FUNC_MF_CFG_OV_STAG_SHIFT 0
11626#define FUNC_MF_CFG_OV_STAG_DEFAULT FUNC_MF_CFG_OV_STAG_MASK
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011627
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011628 u32 pf_allocation;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011629
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011630 u32 preserve_data;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011631
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011632 u32 driver_last_activity_ts;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011633
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011634 u32 drv_ack_vf_disabled[VF_MAX_STATIC / 32];
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011635
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011636 u32 drv_id;
11637#define DRV_ID_PDA_COMP_VER_MASK 0x0000ffff
11638#define DRV_ID_PDA_COMP_VER_SHIFT 0
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011639
Tomer Tayar5d24bcf2017-03-28 15:12:52 +030011640#define LOAD_REQ_HSI_VERSION 2
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011641#define DRV_ID_MCP_HSI_VER_MASK 0x00ff0000
11642#define DRV_ID_MCP_HSI_VER_SHIFT 16
Tomer Tayar5d24bcf2017-03-28 15:12:52 +030011643#define DRV_ID_MCP_HSI_VER_CURRENT (LOAD_REQ_HSI_VERSION << \
11644 DRV_ID_MCP_HSI_VER_SHIFT)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011645
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011646#define DRV_ID_DRV_TYPE_MASK 0x7f000000
11647#define DRV_ID_DRV_TYPE_SHIFT 24
11648#define DRV_ID_DRV_TYPE_UNKNOWN (0 << DRV_ID_DRV_TYPE_SHIFT)
11649#define DRV_ID_DRV_TYPE_LINUX (1 << DRV_ID_DRV_TYPE_SHIFT)
Yuval Mintzfc48b7a2016-02-15 13:22:35 -050011650
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011651#define DRV_ID_DRV_INIT_HW_MASK 0x80000000
11652#define DRV_ID_DRV_INIT_HW_SHIFT 31
11653#define DRV_ID_DRV_INIT_HW_FLAG (1 << DRV_ID_DRV_INIT_HW_SHIFT)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011654};
11655
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011656struct mcp_mac {
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011657 u32 mac_upper;
11658 u32 mac_lower;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011659};
11660
11661struct mcp_val64 {
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011662 u32 lo;
11663 u32 hi;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011664};
11665
11666struct mcp_file_att {
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011667 u32 nvm_start_addr;
11668 u32 len;
11669};
11670
11671struct bist_nvm_image_att {
11672 u32 return_code;
11673 u32 image_type;
11674 u32 nvm_start_addr;
11675 u32 len;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011676};
11677
11678#define MCP_DRV_VER_STR_SIZE 16
11679#define MCP_DRV_VER_STR_SIZE_DWORD (MCP_DRV_VER_STR_SIZE / sizeof(u32))
11680#define MCP_DRV_NVM_BUF_LEN 32
11681struct drv_version_stc {
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011682 u32 version;
11683 u8 name[MCP_DRV_VER_STR_SIZE - 4];
11684};
11685
11686struct lan_stats_stc {
11687 u64 ucast_rx_pkts;
11688 u64 ucast_tx_pkts;
11689 u32 fcs_err;
11690 u32 rserved;
11691};
11692
Arun Easi1e128c82017-02-15 06:28:22 -080011693struct fcoe_stats_stc {
11694 u64 rx_pkts;
11695 u64 tx_pkts;
11696 u32 fcs_err;
11697 u32 login_failure;
11698};
11699
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011700struct ocbb_data_stc {
11701 u32 ocbb_host_addr;
11702 u32 ocsd_host_addr;
11703 u32 ocsd_req_update_interval;
11704};
11705
11706#define MAX_NUM_OF_SENSORS 7
11707struct temperature_status_stc {
11708 u32 num_of_sensors;
11709 u32 sensor[MAX_NUM_OF_SENSORS];
11710};
11711
11712/* crash dump configuration header */
11713struct mdump_config_stc {
11714 u32 version;
11715 u32 config;
11716 u32 epoc;
11717 u32 num_of_logs;
11718 u32 valid_logs;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011719};
11720
Tomer Tayar2edbff82016-10-31 07:14:27 +020011721enum resource_id_enum {
11722 RESOURCE_NUM_SB_E = 0,
11723 RESOURCE_NUM_L2_QUEUE_E = 1,
11724 RESOURCE_NUM_VPORT_E = 2,
11725 RESOURCE_NUM_VMQ_E = 3,
11726 RESOURCE_FACTOR_NUM_RSS_PF_E = 4,
11727 RESOURCE_FACTOR_RSS_PER_VF_E = 5,
11728 RESOURCE_NUM_RL_E = 6,
11729 RESOURCE_NUM_PQ_E = 7,
11730 RESOURCE_NUM_VF_E = 8,
11731 RESOURCE_VFC_FILTER_E = 9,
11732 RESOURCE_ILT_E = 10,
11733 RESOURCE_CQS_E = 11,
11734 RESOURCE_GFT_PROFILES_E = 12,
11735 RESOURCE_NUM_TC_E = 13,
11736 RESOURCE_NUM_RSS_ENGINES_E = 14,
11737 RESOURCE_LL2_QUEUE_E = 15,
11738 RESOURCE_RDMA_STATS_QUEUE_E = 16,
Tomer Tayar9c8517c2017-03-28 15:12:55 +030011739 RESOURCE_BDQ_E = 17,
Tomer Tayar2edbff82016-10-31 07:14:27 +020011740 RESOURCE_MAX_NUM,
11741 RESOURCE_NUM_INVALID = 0xFFFFFFFF
11742};
11743
11744/* Resource ID is to be filled by the driver in the MB request
11745 * Size, offset & flags to be filled by the MFW in the MB response
11746 */
11747struct resource_info {
11748 enum resource_id_enum res_id;
11749 u32 size; /* number of allocated resources */
11750 u32 offset; /* Offset of the 1st resource */
11751 u32 vf_size;
11752 u32 vf_offset;
11753 u32 flags;
11754#define RESOURCE_ELEMENT_STRICT (1 << 0)
11755};
11756
Tomer Tayar5d24bcf2017-03-28 15:12:52 +030011757#define DRV_ROLE_NONE 0
11758#define DRV_ROLE_PREBOOT 1
11759#define DRV_ROLE_OS 2
11760#define DRV_ROLE_KDUMP 3
11761
11762struct load_req_stc {
11763 u32 drv_ver_0;
11764 u32 drv_ver_1;
11765 u32 fw_ver;
11766 u32 misc0;
11767#define LOAD_REQ_ROLE_MASK 0x000000FF
11768#define LOAD_REQ_ROLE_SHIFT 0
11769#define LOAD_REQ_LOCK_TO_MASK 0x0000FF00
11770#define LOAD_REQ_LOCK_TO_SHIFT 8
11771#define LOAD_REQ_LOCK_TO_DEFAULT 0
11772#define LOAD_REQ_LOCK_TO_NONE 255
11773#define LOAD_REQ_FORCE_MASK 0x000F0000
11774#define LOAD_REQ_FORCE_SHIFT 16
11775#define LOAD_REQ_FORCE_NONE 0
11776#define LOAD_REQ_FORCE_PF 1
11777#define LOAD_REQ_FORCE_ALL 2
11778#define LOAD_REQ_FLAGS0_MASK 0x00F00000
11779#define LOAD_REQ_FLAGS0_SHIFT 20
11780#define LOAD_REQ_FLAGS0_AVOID_RESET (0x1 << 0)
11781};
11782
11783struct load_rsp_stc {
11784 u32 drv_ver_0;
11785 u32 drv_ver_1;
11786 u32 fw_ver;
11787 u32 misc0;
11788#define LOAD_RSP_ROLE_MASK 0x000000FF
11789#define LOAD_RSP_ROLE_SHIFT 0
11790#define LOAD_RSP_HSI_MASK 0x0000FF00
11791#define LOAD_RSP_HSI_SHIFT 8
11792#define LOAD_RSP_FLAGS0_MASK 0x000F0000
11793#define LOAD_RSP_FLAGS0_SHIFT 16
11794#define LOAD_RSP_FLAGS0_DRV_EXISTS (0x1 << 0)
11795};
11796
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011797union drv_union_data {
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011798 u32 ver_str[MCP_DRV_VER_STR_SIZE_DWORD];
11799 struct mcp_mac wol_mac;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011800
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011801 struct eth_phy_cfg drv_phy_cfg;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011802
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011803 struct mcp_val64 val64;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011804
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011805 u8 raw_data[MCP_DRV_NVM_BUF_LEN];
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011806
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011807 struct mcp_file_att file_att;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011808
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011809 u32 ack_vf_disabled[VF_MAX_STATIC / 32];
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011810
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011811 struct drv_version_stc drv_version;
11812
11813 struct lan_stats_stc lan_stats;
Arun Easi1e128c82017-02-15 06:28:22 -080011814 struct fcoe_stats_stc fcoe_stats;
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011815 struct ocbb_data_stc ocbb_info;
11816 struct temperature_status_stc temp_info;
Tomer Tayar2edbff82016-10-31 07:14:27 +020011817 struct resource_info resource;
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011818 struct bist_nvm_image_att nvm_image_att;
11819 struct mdump_config_stc mdump_config;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011820};
11821
11822struct public_drv_mb {
11823 u32 drv_mb_header;
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011824#define DRV_MSG_CODE_MASK 0xffff0000
11825#define DRV_MSG_CODE_LOAD_REQ 0x10000000
11826#define DRV_MSG_CODE_LOAD_DONE 0x11000000
11827#define DRV_MSG_CODE_INIT_HW 0x12000000
Tomer Tayar5d24bcf2017-03-28 15:12:52 +030011828#define DRV_MSG_CODE_CANCEL_LOAD_REQ 0x13000000
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011829#define DRV_MSG_CODE_UNLOAD_REQ 0x20000000
11830#define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
11831#define DRV_MSG_CODE_INIT_PHY 0x22000000
11832#define DRV_MSG_CODE_LINK_RESET 0x23000000
11833#define DRV_MSG_CODE_SET_DCBX 0x25000000
Sudarsana Kalluru0fefbfb2016-10-31 07:14:21 +020011834#define DRV_MSG_CODE_OV_UPDATE_CURR_CFG 0x26000000
11835#define DRV_MSG_CODE_OV_UPDATE_BUS_NUM 0x27000000
11836#define DRV_MSG_CODE_OV_UPDATE_BOOT_PROGRESS 0x28000000
11837#define DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER 0x29000000
11838#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE 0x31000000
11839#define DRV_MSG_CODE_BW_UPDATE_ACK 0x32000000
11840#define DRV_MSG_CODE_OV_UPDATE_MTU 0x33000000
Tomer Tayar9c8517c2017-03-28 15:12:55 +030011841#define DRV_MSG_GET_RESOURCE_ALLOC_MSG 0x34000000
11842#define DRV_MSG_SET_RESOURCE_VALUE_MSG 0x35000000
Sudarsana Kalluru0fefbfb2016-10-31 07:14:21 +020011843#define DRV_MSG_CODE_OV_UPDATE_WOL 0x38000000
11844#define DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE 0x39000000
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011845
Manish Chopra4b01e512016-04-26 10:56:09 -040011846#define DRV_MSG_CODE_BW_UPDATE_ACK 0x32000000
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011847#define DRV_MSG_CODE_NIG_DRAIN 0x30000000
Mintz, Yuval2a351fd92017-05-29 09:53:09 +030011848#define DRV_MSG_CODE_S_TAG_UPDATE_ACK 0x3b000000
Mintz, Yuval18a69e32017-03-28 15:12:53 +030011849#define DRV_MSG_CODE_INITIATE_PF_FLR 0x02010000
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011850#define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000
11851#define DRV_MSG_CODE_CFG_VF_MSIX 0xc0010000
Mintz, Yuval88072fd2017-05-29 09:53:08 +030011852#define DRV_MSG_CODE_CFG_PF_VFS_MSIX 0xc0020000
Tomer Tayarc965db42016-09-07 16:36:24 +030011853#define DRV_MSG_CODE_NVM_GET_FILE_ATT 0x00030000
11854#define DRV_MSG_CODE_NVM_READ_NVRAM 0x00050000
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011855#define DRV_MSG_CODE_MCP_RESET 0x00090000
11856#define DRV_MSG_CODE_SET_VERSION 0x000f0000
Tomer Tayar41024262016-09-05 14:35:10 +030011857#define DRV_MSG_CODE_MCP_HALT 0x00100000
Sudarsana Kalluru0fefbfb2016-10-31 07:14:21 +020011858#define DRV_MSG_CODE_SET_VMAC 0x00110000
11859#define DRV_MSG_CODE_GET_VMAC 0x00120000
11860#define DRV_MSG_CODE_VMAC_TYPE_SHIFT 4
11861#define DRV_MSG_CODE_VMAC_TYPE_MASK 0x30
11862#define DRV_MSG_CODE_VMAC_TYPE_MAC 1
11863#define DRV_MSG_CODE_VMAC_TYPE_WWNN 2
11864#define DRV_MSG_CODE_VMAC_TYPE_WWPN 3
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011865
Sudarsana Reddy Kalluru6c754242016-08-16 10:51:03 -040011866#define DRV_MSG_CODE_GET_STATS 0x00130000
11867#define DRV_MSG_CODE_STATS_TYPE_LAN 1
11868#define DRV_MSG_CODE_STATS_TYPE_FCOE 2
11869#define DRV_MSG_CODE_STATS_TYPE_ISCSI 3
11870#define DRV_MSG_CODE_STATS_TYPE_RDMA 4
11871
Tomer Tayar41024262016-09-05 14:35:10 +030011872#define DRV_MSG_CODE_MASK_PARITIES 0x001a0000
11873
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011874#define DRV_MSG_CODE_BIST_TEST 0x001e0000
11875#define DRV_MSG_CODE_SET_LED_MODE 0x00200000
Tomer Tayar95691c92017-03-28 15:12:54 +030011876#define DRV_MSG_CODE_RESOURCE_CMD 0x00230000
11877
11878#define RESOURCE_CMD_REQ_RESC_MASK 0x0000001F
11879#define RESOURCE_CMD_REQ_RESC_SHIFT 0
11880#define RESOURCE_CMD_REQ_OPCODE_MASK 0x000000E0
11881#define RESOURCE_CMD_REQ_OPCODE_SHIFT 5
11882#define RESOURCE_OPCODE_REQ 1
11883#define RESOURCE_OPCODE_REQ_WO_AGING 2
11884#define RESOURCE_OPCODE_REQ_W_AGING 3
11885#define RESOURCE_OPCODE_RELEASE 4
11886#define RESOURCE_OPCODE_FORCE_RELEASE 5
11887#define RESOURCE_CMD_REQ_AGE_MASK 0x0000FF00
11888#define RESOURCE_CMD_REQ_AGE_SHIFT 8
11889
11890#define RESOURCE_CMD_RSP_OWNER_MASK 0x000000FF
11891#define RESOURCE_CMD_RSP_OWNER_SHIFT 0
11892#define RESOURCE_CMD_RSP_OPCODE_MASK 0x00000700
11893#define RESOURCE_CMD_RSP_OPCODE_SHIFT 8
11894#define RESOURCE_OPCODE_GNT 1
11895#define RESOURCE_OPCODE_BUSY 2
11896#define RESOURCE_OPCODE_RELEASED 3
11897#define RESOURCE_OPCODE_RELEASED_PREVIOUS 4
11898#define RESOURCE_OPCODE_WRONG_OWNER 5
11899#define RESOURCE_OPCODE_UNKNOWN_CMD 255
11900
11901#define RESOURCE_DUMP 0
11902
Mintz, Yuval6927e822016-10-31 07:14:25 +020011903#define DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL 0x002b0000
Mintz, Yuval14d39642016-10-31 07:14:23 +020011904#define DRV_MSG_CODE_OS_WOL 0x002e0000
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011905
Sudarsana Reddy Kalluru645874e2017-07-26 06:07:11 -070011906#define DRV_MSG_CODE_FEATURE_SUPPORT 0x00300000
11907#define DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT 0x00310000
11908
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011909#define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011910
11911 u32 drv_mb_param;
Sudarsana Kalluru0fefbfb2016-10-31 07:14:21 +020011912#define DRV_MB_PARAM_UNLOAD_WOL_UNKNOWN 0x00000000
11913#define DRV_MB_PARAM_UNLOAD_WOL_MCP 0x00000001
11914#define DRV_MB_PARAM_UNLOAD_WOL_DISABLED 0x00000002
11915#define DRV_MB_PARAM_UNLOAD_WOL_ENABLED 0x00000003
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011916#define DRV_MB_PARAM_DCBX_NOTIFY_MASK 0x000000FF
11917#define DRV_MB_PARAM_DCBX_NOTIFY_SHIFT 3
Tomer Tayarc965db42016-09-07 16:36:24 +030011918
11919#define DRV_MB_PARAM_NVM_LEN_SHIFT 24
11920
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011921#define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT 0
11922#define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK 0x000000FF
11923#define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT 8
11924#define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK 0x0000FF00
Sudarsana Reddy Kalluru6ad8c632016-06-08 06:22:10 -040011925#define DRV_MB_PARAM_LLDP_SEND_MASK 0x00000001
11926#define DRV_MB_PARAM_LLDP_SEND_SHIFT 0
11927
Sudarsana Kalluru0fefbfb2016-10-31 07:14:21 +020011928#define DRV_MB_PARAM_OV_CURR_CFG_SHIFT 0
11929#define DRV_MB_PARAM_OV_CURR_CFG_MASK 0x0000000F
11930#define DRV_MB_PARAM_OV_CURR_CFG_NONE 0
11931#define DRV_MB_PARAM_OV_CURR_CFG_OS 1
11932#define DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC 2
11933#define DRV_MB_PARAM_OV_CURR_CFG_OTHER 3
11934
11935#define DRV_MB_PARAM_OV_STORM_FW_VER_SHIFT 0
11936#define DRV_MB_PARAM_OV_STORM_FW_VER_MASK 0xFFFFFFFF
11937#define DRV_MB_PARAM_OV_STORM_FW_VER_MAJOR_MASK 0xFF000000
11938#define DRV_MB_PARAM_OV_STORM_FW_VER_MINOR_MASK 0x00FF0000
11939#define DRV_MB_PARAM_OV_STORM_FW_VER_BUILD_MASK 0x0000FF00
11940#define DRV_MB_PARAM_OV_STORM_FW_VER_DROP_MASK 0x000000FF
11941
11942#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_SHIFT 0
11943#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_MASK 0xF
11944#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_UNKNOWN 0x1
11945#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED 0x2
11946#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_LOADING 0x3
11947#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED 0x4
11948#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE 0x5
11949
11950#define DRV_MB_PARAM_OV_MTU_SIZE_SHIFT 0
11951#define DRV_MB_PARAM_OV_MTU_SIZE_MASK 0xFFFFFFFF
11952
11953#define DRV_MB_PARAM_WOL_MASK (DRV_MB_PARAM_WOL_DEFAULT | \
11954 DRV_MB_PARAM_WOL_DISABLED | \
11955 DRV_MB_PARAM_WOL_ENABLED)
11956#define DRV_MB_PARAM_WOL_DEFAULT DRV_MB_PARAM_UNLOAD_WOL_MCP
11957#define DRV_MB_PARAM_WOL_DISABLED DRV_MB_PARAM_UNLOAD_WOL_DISABLED
11958#define DRV_MB_PARAM_WOL_ENABLED DRV_MB_PARAM_UNLOAD_WOL_ENABLED
11959
11960#define DRV_MB_PARAM_ESWITCH_MODE_MASK (DRV_MB_PARAM_ESWITCH_MODE_NONE | \
11961 DRV_MB_PARAM_ESWITCH_MODE_VEB | \
11962 DRV_MB_PARAM_ESWITCH_MODE_VEPA)
11963#define DRV_MB_PARAM_ESWITCH_MODE_NONE 0x0
11964#define DRV_MB_PARAM_ESWITCH_MODE_VEB 0x1
11965#define DRV_MB_PARAM_ESWITCH_MODE_VEPA 0x2
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011966
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011967#define DRV_MB_PARAM_SET_LED_MODE_OPER 0x0
11968#define DRV_MB_PARAM_SET_LED_MODE_ON 0x1
11969#define DRV_MB_PARAM_SET_LED_MODE_OFF 0x2
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011970
Tomer Tayar2edbff82016-10-31 07:14:27 +020011971 /* Resource Allocation params - Driver version support */
11972#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000
11973#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 16
11974#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF
11975#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0
11976
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011977#define DRV_MB_PARAM_BIST_REGISTER_TEST 1
11978#define DRV_MB_PARAM_BIST_CLOCK_TEST 2
Mintz, Yuval7a4b21b2016-10-31 07:14:22 +020011979#define DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES 3
11980#define DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX 4
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011981
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011982#define DRV_MB_PARAM_BIST_RC_UNKNOWN 0
11983#define DRV_MB_PARAM_BIST_RC_PASSED 1
11984#define DRV_MB_PARAM_BIST_RC_FAILED 2
11985#define DRV_MB_PARAM_BIST_RC_INVALID_PARAMETER 3
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011986
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011987#define DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT 0
11988#define DRV_MB_PARAM_BIST_TEST_INDEX_MASK 0x000000FF
Mintz, Yuval7a4b21b2016-10-31 07:14:22 +020011989#define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT 8
11990#define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_MASK 0x0000FF00
Sudarsana Reddy Kalluru03dc76c2016-04-28 20:20:52 -040011991
Sudarsana Reddy Kalluru645874e2017-07-26 06:07:11 -070011992#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_MASK 0x0000FFFF
11993#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_OFFSET 0
11994#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE 0x00000002
11995
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020011996 u32 fw_mb_header;
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011997#define FW_MSG_CODE_MASK 0xffff0000
Tomer Tayar95691c92017-03-28 15:12:54 +030011998#define FW_MSG_CODE_UNSUPPORTED 0x00000000
Yuval Mintz351a4ded2016-06-02 10:23:29 +030011999#define FW_MSG_CODE_DRV_LOAD_ENGINE 0x10100000
12000#define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000
12001#define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000
12002#define FW_MSG_CODE_DRV_LOAD_REFUSED_PDA 0x10200000
Tomer Tayar5d24bcf2017-03-28 15:12:52 +030012003#define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1 0x10210000
Yuval Mintz351a4ded2016-06-02 10:23:29 +030012004#define FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG 0x10220000
Tomer Tayar5d24bcf2017-03-28 15:12:52 +030012005#define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI 0x10230000
12006#define FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE 0x10300000
12007#define FW_MSG_CODE_DRV_LOAD_REFUSED_REJECT 0x10310000
Yuval Mintz351a4ded2016-06-02 10:23:29 +030012008#define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000
12009#define FW_MSG_CODE_DRV_UNLOAD_ENGINE 0x20110000
12010#define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20120000
12011#define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20130000
12012#define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
Tomer Tayar2edbff82016-10-31 07:14:27 +020012013#define FW_MSG_CODE_RESOURCE_ALLOC_OK 0x34000000
12014#define FW_MSG_CODE_RESOURCE_ALLOC_UNKNOWN 0x35000000
12015#define FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED 0x36000000
Mintz, Yuval2a351fd92017-05-29 09:53:09 +030012016#define FW_MSG_CODE_S_TAG_UPDATE_ACK_DONE 0x3b000000
Yuval Mintz351a4ded2016-06-02 10:23:29 +030012017#define FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE 0xb0010000
Tomer Tayarc965db42016-09-07 16:36:24 +030012018
12019#define FW_MSG_CODE_NVM_OK 0x00010000
Yuval Mintz351a4ded2016-06-02 10:23:29 +030012020#define FW_MSG_CODE_OK 0x00160000
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020012021
Mintz, Yuval14d39642016-10-31 07:14:23 +020012022#define FW_MSG_CODE_OS_WOL_SUPPORTED 0x00800000
12023#define FW_MSG_CODE_OS_WOL_NOT_SUPPORTED 0x00810000
Mintz, Yuval88072fd2017-05-29 09:53:08 +030012024#define FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE 0x00870000
Yuval Mintz351a4ded2016-06-02 10:23:29 +030012025#define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020012026
Yuval Mintz351a4ded2016-06-02 10:23:29 +030012027 u32 fw_mb_param;
Tomer Tayar9c8517c2017-03-28 15:12:55 +030012028#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000
12029#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 16
12030#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF
12031#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020012032
Mintz, Yuval6927e822016-10-31 07:14:25 +020012033 /* get pf rdma protocol command responce */
12034#define FW_MB_PARAM_GET_PF_RDMA_NONE 0x0
12035#define FW_MB_PARAM_GET_PF_RDMA_ROCE 0x1
12036#define FW_MB_PARAM_GET_PF_RDMA_IWARP 0x2
12037#define FW_MB_PARAM_GET_PF_RDMA_BOTH 0x3
12038
Sudarsana Reddy Kalluru645874e2017-07-26 06:07:11 -070012039/* get MFW feature support response */
12040#define FW_MB_PARAM_FEATURE_SUPPORT_EEE 0x00000002
12041
Tomer Tayarfc561c82017-05-23 09:41:21 +030012042#define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR (1 << 0)
12043
Yuval Mintz351a4ded2016-06-02 10:23:29 +030012044 u32 drv_pulse_mb;
12045#define DRV_PULSE_SEQ_MASK 0x00007fff
12046#define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
12047#define DRV_PULSE_ALWAYS_ALIVE 0x00008000
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020012048
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020012049 u32 mcp_pulse_mb;
Yuval Mintz351a4ded2016-06-02 10:23:29 +030012050#define MCP_PULSE_SEQ_MASK 0x00007fff
12051#define MCP_PULSE_ALWAYS_ALIVE 0x00008000
12052#define MCP_EVENT_MASK 0xffff0000
12053#define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020012054
12055 union drv_union_data union_data;
12056};
12057
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020012058enum MFW_DRV_MSG_TYPE {
12059 MFW_DRV_MSG_LINK_CHANGE,
12060 MFW_DRV_MSG_FLR_FW_ACK_FAILED,
12061 MFW_DRV_MSG_VF_DISABLED,
12062 MFW_DRV_MSG_LLDP_DATA_UPDATED,
12063 MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED,
12064 MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED,
Yuval Mintz351a4ded2016-06-02 10:23:29 +030012065 MFW_DRV_MSG_RESERVED4,
Zvi Nachmani334c03b2016-03-09 09:16:25 +020012066 MFW_DRV_MSG_BW_UPDATE,
Mintz, Yuval2a351fd92017-05-29 09:53:09 +030012067 MFW_DRV_MSG_S_TAG_UPDATE,
Sudarsana Reddy Kalluru6c754242016-08-16 10:51:03 -040012068 MFW_DRV_MSG_GET_LAN_STATS,
12069 MFW_DRV_MSG_GET_FCOE_STATS,
12070 MFW_DRV_MSG_GET_ISCSI_STATS,
12071 MFW_DRV_MSG_GET_RDMA_STATS,
Yuval Mintz351a4ded2016-06-02 10:23:29 +030012072 MFW_DRV_MSG_BW_UPDATE10,
Zvi Nachmani334c03b2016-03-09 09:16:25 +020012073 MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE,
Yuval Mintz351a4ded2016-06-02 10:23:29 +030012074 MFW_DRV_MSG_BW_UPDATE11,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020012075 MFW_DRV_MSG_MAX
12076};
12077
Yuval Mintz351a4ded2016-06-02 10:23:29 +030012078#define MFW_DRV_MSG_MAX_DWORDS(msgs) (((msgs - 1) >> 2) + 1)
12079#define MFW_DRV_MSG_DWORD(msg_id) (msg_id >> 2)
12080#define MFW_DRV_MSG_OFFSET(msg_id) ((msg_id & 0x3) << 3)
12081#define MFW_DRV_MSG_MASK(msg_id) (0xff << MFW_DRV_MSG_OFFSET(msg_id))
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020012082
12083struct public_mfw_mb {
Yuval Mintz351a4ded2016-06-02 10:23:29 +030012084 u32 sup_msgs;
12085 u32 msg[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
12086 u32 ack[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020012087};
12088
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020012089enum public_sections {
Yuval Mintz351a4ded2016-06-02 10:23:29 +030012090 PUBLIC_DRV_MB,
12091 PUBLIC_MFW_MB,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020012092 PUBLIC_GLOBAL,
12093 PUBLIC_PATH,
12094 PUBLIC_PORT,
12095 PUBLIC_FUNC,
12096 PUBLIC_MAX_SECTIONS
12097};
12098
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020012099struct mcp_public_data {
Yuval Mintz351a4ded2016-06-02 10:23:29 +030012100 u32 num_sections;
12101 u32 sections[PUBLIC_MAX_SECTIONS];
12102 struct public_drv_mb drv_mb[MCP_GLOB_FUNC_MAX];
12103 struct public_mfw_mb mfw_mb[MCP_GLOB_FUNC_MAX];
12104 struct public_global global;
12105 struct public_path path[MCP_GLOB_PATH_MAX];
12106 struct public_port port[MCP_GLOB_PORT_MAX];
12107 struct public_func func[MCP_GLOB_FUNC_MAX];
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020012108};
12109
12110struct nvm_cfg_mac_address {
Yuval Mintz351a4ded2016-06-02 10:23:29 +030012111 u32 mac_addr_hi;
12112#define NVM_CFG_MAC_ADDRESS_HI_MASK 0x0000FFFF
12113#define NVM_CFG_MAC_ADDRESS_HI_OFFSET 0
12114 u32 mac_addr_lo;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020012115};
12116
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020012117struct nvm_cfg1_glob {
Yuval Mintz351a4ded2016-06-02 10:23:29 +030012118 u32 generic_cont0;
12119#define NVM_CFG1_GLOB_MF_MODE_MASK 0x00000FF0
12120#define NVM_CFG1_GLOB_MF_MODE_OFFSET 4
12121#define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED 0x0
12122#define NVM_CFG1_GLOB_MF_MODE_DEFAULT 0x1
12123#define NVM_CFG1_GLOB_MF_MODE_SPIO4 0x2
12124#define NVM_CFG1_GLOB_MF_MODE_NPAR1_0 0x3
12125#define NVM_CFG1_GLOB_MF_MODE_NPAR1_5 0x4
12126#define NVM_CFG1_GLOB_MF_MODE_NPAR2_0 0x5
12127#define NVM_CFG1_GLOB_MF_MODE_BD 0x6
12128#define NVM_CFG1_GLOB_MF_MODE_UFP 0x7
12129 u32 engineering_change[3];
12130 u32 manufacturing_id;
12131 u32 serial_number[4];
12132 u32 pcie_cfg;
12133 u32 mgmt_traffic;
12134 u32 core_cfg;
12135#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK 0x000000FF
12136#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET 0
12137#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G 0x0
12138#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G 0x1
12139#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G 0x2
12140#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F 0x3
12141#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E 0x4
12142#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G 0x5
12143#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G 0xB
12144#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G 0xC
12145#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G 0xD
12146#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G 0xE
Mintz, Yuval9c79dda2017-03-14 16:23:54 +020012147#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G 0xF
12148
Yuval Mintz351a4ded2016-06-02 10:23:29 +030012149 u32 e_lane_cfg1;
12150 u32 e_lane_cfg2;
12151 u32 f_lane_cfg1;
12152 u32 f_lane_cfg2;
12153 u32 mps10_preemphasis;
12154 u32 mps10_driver_current;
12155 u32 mps25_preemphasis;
12156 u32 mps25_driver_current;
12157 u32 pci_id;
12158 u32 pci_subsys_id;
12159 u32 bar;
12160 u32 mps10_txfir_main;
12161 u32 mps10_txfir_post;
12162 u32 mps25_txfir_main;
12163 u32 mps25_txfir_post;
12164 u32 manufacture_ver;
12165 u32 manufacture_time;
12166 u32 led_global_settings;
12167 u32 generic_cont1;
12168 u32 mbi_version;
Tomer Tayarae336662017-05-23 09:41:26 +030012169#define NVM_CFG1_GLOB_MBI_VERSION_0_MASK 0x000000FF
12170#define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET 0
12171#define NVM_CFG1_GLOB_MBI_VERSION_1_MASK 0x0000FF00
12172#define NVM_CFG1_GLOB_MBI_VERSION_1_OFFSET 8
12173#define NVM_CFG1_GLOB_MBI_VERSION_2_MASK 0x00FF0000
12174#define NVM_CFG1_GLOB_MBI_VERSION_2_OFFSET 16
Yuval Mintz351a4ded2016-06-02 10:23:29 +030012175 u32 mbi_date;
12176 u32 misc_sig;
12177 u32 device_capabilities;
12178#define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET 0x1
Arun Easi1e128c82017-02-15 06:28:22 -080012179#define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE 0x2
Yuval Mintzc5ac9312016-06-03 14:35:34 +030012180#define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI 0x4
12181#define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE 0x8
Yuval Mintz351a4ded2016-06-02 10:23:29 +030012182 u32 power_dissipated;
12183 u32 power_consumed;
12184 u32 efi_version;
12185 u32 multi_network_modes_capability;
12186 u32 reserved[41];
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020012187};
12188
12189struct nvm_cfg1_path {
Yuval Mintz351a4ded2016-06-02 10:23:29 +030012190 u32 reserved[30];
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020012191};
12192
12193struct nvm_cfg1_port {
Yuval Mintz351a4ded2016-06-02 10:23:29 +030012194 u32 reserved__m_relocated_to_option_123;
12195 u32 reserved__m_relocated_to_option_124;
12196 u32 generic_cont0;
12197#define NVM_CFG1_PORT_DCBX_MODE_MASK 0x000F0000
12198#define NVM_CFG1_PORT_DCBX_MODE_OFFSET 16
12199#define NVM_CFG1_PORT_DCBX_MODE_DISABLED 0x0
12200#define NVM_CFG1_PORT_DCBX_MODE_IEEE 0x1
12201#define NVM_CFG1_PORT_DCBX_MODE_CEE 0x2
12202#define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC 0x3
12203#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK 0x00F00000
12204#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_OFFSET 20
12205#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET 0x1
12206#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_FCOE 0x2
12207#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ISCSI 0x4
12208 u32 pcie_cfg;
12209 u32 features;
12210 u32 speed_cap_mask;
12211#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF
12212#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
12213#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G 0x1
12214#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G 0x2
12215#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G 0x8
12216#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G 0x10
12217#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G 0x20
12218#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40
12219 u32 link_settings;
12220#define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK 0x0000000F
12221#define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET 0
12222#define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG 0x0
12223#define NVM_CFG1_PORT_DRV_LINK_SPEED_1G 0x1
12224#define NVM_CFG1_PORT_DRV_LINK_SPEED_10G 0x2
12225#define NVM_CFG1_PORT_DRV_LINK_SPEED_25G 0x4
12226#define NVM_CFG1_PORT_DRV_LINK_SPEED_40G 0x5
12227#define NVM_CFG1_PORT_DRV_LINK_SPEED_50G 0x6
12228#define NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G 0x7
12229#define NVM_CFG1_PORT_DRV_LINK_SPEED_SMARTLINQ 0x8
12230#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK 0x00000070
12231#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET 4
12232#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG 0x1
12233#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX 0x2
12234#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX 0x4
12235 u32 phy_cfg;
12236 u32 mgmt_traffic;
Sudarsana Reddy Kalluru645874e2017-07-26 06:07:11 -070012237
Yuval Mintz351a4ded2016-06-02 10:23:29 +030012238 u32 ext_phy;
Sudarsana Reddy Kalluru645874e2017-07-26 06:07:11 -070012239 /* EEE power saving mode */
12240#define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK 0x00FF0000
12241#define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET 16
12242#define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED 0x0
12243#define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED 0x1
12244#define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE 0x2
12245#define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY 0x3
12246
Yuval Mintz351a4ded2016-06-02 10:23:29 +030012247 u32 mba_cfg1;
12248 u32 mba_cfg2;
12249 u32 vf_cfg;
12250 struct nvm_cfg_mac_address lldp_mac_address;
12251 u32 led_port_settings;
12252 u32 transceiver_00;
12253 u32 device_ids;
12254 u32 board_cfg;
12255 u32 mnm_10g_cap;
12256 u32 mnm_10g_ctrl;
12257 u32 mnm_10g_misc;
12258 u32 mnm_25g_cap;
12259 u32 mnm_25g_ctrl;
12260 u32 mnm_25g_misc;
12261 u32 mnm_40g_cap;
12262 u32 mnm_40g_ctrl;
12263 u32 mnm_40g_misc;
12264 u32 mnm_50g_cap;
12265 u32 mnm_50g_ctrl;
12266 u32 mnm_50g_misc;
12267 u32 mnm_100g_cap;
12268 u32 mnm_100g_ctrl;
12269 u32 mnm_100g_misc;
12270 u32 reserved[116];
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020012271};
12272
12273struct nvm_cfg1_func {
Yuval Mintz351a4ded2016-06-02 10:23:29 +030012274 struct nvm_cfg_mac_address mac_address;
12275 u32 rsrv1;
12276 u32 rsrv2;
12277 u32 device_id;
12278 u32 cmn_cfg;
12279 u32 pci_cfg;
12280 struct nvm_cfg_mac_address fcoe_node_wwn_mac_addr;
12281 struct nvm_cfg_mac_address fcoe_port_wwn_mac_addr;
12282 u32 preboot_generic_cfg;
12283 u32 reserved[8];
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020012284};
12285
12286struct nvm_cfg1 {
Yuval Mintz351a4ded2016-06-02 10:23:29 +030012287 struct nvm_cfg1_glob glob;
12288 struct nvm_cfg1_path path[MCP_GLOB_PATH_MAX];
12289 struct nvm_cfg1_port port[MCP_GLOB_PORT_MAX];
12290 struct nvm_cfg1_func func[MCP_GLOB_FUNC_MAX];
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020012291};
Tomer Tayarc965db42016-09-07 16:36:24 +030012292
12293enum spad_sections {
12294 SPAD_SECTION_TRACE,
12295 SPAD_SECTION_NVM_CFG,
12296 SPAD_SECTION_PUBLIC,
12297 SPAD_SECTION_PRIVATE,
12298 SPAD_SECTION_MAX
12299};
12300
12301#define MCP_TRACE_SIZE 2048 /* 2kb */
12302
12303/* This section is located at a fixed location in the beginning of the
12304 * scratchpad, to ensure that the MCP trace is not run over during MFW upgrade.
12305 * All the rest of data has a floating location which differs from version to
12306 * version, and is pointed by the mcp_meta_data below.
12307 * Moreover, the spad_layout section is part of the MFW firmware, and is loaded
12308 * with it from nvram in order to clear this portion.
12309 */
12310struct static_init {
12311 u32 num_sections;
12312 offsize_t sections[SPAD_SECTION_MAX];
12313#define SECTION(_sec_) (*((offsize_t *)(STRUCT_OFFSET(sections[_sec_]))))
12314
12315 struct mcp_trace trace;
12316#define MCP_TRACE_P ((struct mcp_trace *)(STRUCT_OFFSET(trace)))
12317 u8 trace_buffer[MCP_TRACE_SIZE];
12318#define MCP_TRACE_BUF ((u8 *)(STRUCT_OFFSET(trace_buffer)))
12319 /* running_mfw has the same definition as in nvm_map.h.
12320 * This bit indicate both the running dir, and the running bundle.
12321 * It is set once when the LIM is loaded.
12322 */
12323 u32 running_mfw;
12324#define RUNNING_MFW (*((u32 *)(STRUCT_OFFSET(running_mfw))))
12325 u32 build_time;
12326#define MFW_BUILD_TIME (*((u32 *)(STRUCT_OFFSET(build_time))))
12327 u32 reset_type;
12328#define RESET_TYPE (*((u32 *)(STRUCT_OFFSET(reset_type))))
12329 u32 mfw_secure_mode;
12330#define MFW_SECURE_MODE (*((u32 *)(STRUCT_OFFSET(mfw_secure_mode))))
12331 u16 pme_status_pf_bitmap;
12332#define PME_STATUS_PF_BITMAP (*((u16 *)(STRUCT_OFFSET(pme_status_pf_bitmap))))
12333 u16 pme_enable_pf_bitmap;
12334#define PME_ENABLE_PF_BITMAP (*((u16 *)(STRUCT_OFFSET(pme_enable_pf_bitmap))))
12335 u32 mim_nvm_addr;
12336 u32 mim_start_addr;
12337 u32 ah_pcie_link_params;
12338#define AH_PCIE_LINK_PARAMS_LINK_SPEED_MASK (0x000000ff)
12339#define AH_PCIE_LINK_PARAMS_LINK_SPEED_SHIFT (0)
12340#define AH_PCIE_LINK_PARAMS_LINK_WIDTH_MASK (0x0000ff00)
12341#define AH_PCIE_LINK_PARAMS_LINK_WIDTH_SHIFT (8)
12342#define AH_PCIE_LINK_PARAMS_ASPM_MODE_MASK (0x00ff0000)
12343#define AH_PCIE_LINK_PARAMS_ASPM_MODE_SHIFT (16)
12344#define AH_PCIE_LINK_PARAMS_ASPM_CAP_MASK (0xff000000)
12345#define AH_PCIE_LINK_PARAMS_ASPM_CAP_SHIFT (24)
12346#define AH_PCIE_LINK_PARAMS (*((u32 *)(STRUCT_OFFSET(ah_pcie_link_params))))
12347
12348 u32 rsrv_persist[5]; /* Persist reserved for MFW upgrades */
12349};
12350
Mintz, Yuval7b6859f2017-05-18 19:41:04 +030012351#define NVM_MAGIC_VALUE 0x669955aa
12352
Tomer Tayarc965db42016-09-07 16:36:24 +030012353enum nvm_image_type {
12354 NVM_TYPE_TIM1 = 0x01,
12355 NVM_TYPE_TIM2 = 0x02,
12356 NVM_TYPE_MIM1 = 0x03,
12357 NVM_TYPE_MIM2 = 0x04,
12358 NVM_TYPE_MBA = 0x05,
12359 NVM_TYPE_MODULES_PN = 0x06,
12360 NVM_TYPE_VPD = 0x07,
12361 NVM_TYPE_MFW_TRACE1 = 0x08,
12362 NVM_TYPE_MFW_TRACE2 = 0x09,
12363 NVM_TYPE_NVM_CFG1 = 0x0a,
12364 NVM_TYPE_L2B = 0x0b,
12365 NVM_TYPE_DIR1 = 0x0c,
12366 NVM_TYPE_EAGLE_FW1 = 0x0d,
12367 NVM_TYPE_FALCON_FW1 = 0x0e,
12368 NVM_TYPE_PCIE_FW1 = 0x0f,
12369 NVM_TYPE_HW_SET = 0x10,
12370 NVM_TYPE_LIM = 0x11,
12371 NVM_TYPE_AVS_FW1 = 0x12,
12372 NVM_TYPE_DIR2 = 0x13,
12373 NVM_TYPE_CCM = 0x14,
12374 NVM_TYPE_EAGLE_FW2 = 0x15,
12375 NVM_TYPE_FALCON_FW2 = 0x16,
12376 NVM_TYPE_PCIE_FW2 = 0x17,
12377 NVM_TYPE_AVS_FW2 = 0x18,
12378 NVM_TYPE_INIT_HW = 0x19,
12379 NVM_TYPE_DEFAULT_CFG = 0x1a,
12380 NVM_TYPE_MDUMP = 0x1b,
12381 NVM_TYPE_META = 0x1c,
12382 NVM_TYPE_ISCSI_CFG = 0x1d,
12383 NVM_TYPE_FCOE_CFG = 0x1f,
12384 NVM_TYPE_ETH_PHY_FW1 = 0x20,
12385 NVM_TYPE_ETH_PHY_FW2 = 0x21,
12386 NVM_TYPE_MAX,
12387};
12388
12389#define DIR_ID_1 (0)
12390
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020012391#endif