blob: c7c08fae383f3313558c8a077b33b5473f40defd [file] [log] [blame]
Ben Skeggs15907002018-05-08 20:39:47 +10001/*
2 * Copyright 2018 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22#include "wndw.h"
23
24#include <nvif/class.h>
25#include <nvif/cl0002.h>
26
27#include <drm/drm_atomic_helper.h>
28#include "nouveau_bo.h"
29
30static void
31nv50_wndw_ctxdma_del(struct nv50_wndw_ctxdma *ctxdma)
32{
33 nvif_object_fini(&ctxdma->object);
34 list_del(&ctxdma->head);
35 kfree(ctxdma);
36}
37
38static struct nv50_wndw_ctxdma *
39nv50_wndw_ctxdma_new(struct nv50_wndw *wndw, struct nouveau_framebuffer *fb)
40{
41 struct nouveau_drm *drm = nouveau_drm(fb->base.dev);
42 struct nv50_wndw_ctxdma *ctxdma;
43 const u8 kind = fb->nvbo->kind;
44 const u32 handle = 0xfb000000 | kind;
45 struct {
46 struct nv_dma_v0 base;
47 union {
48 struct nv50_dma_v0 nv50;
49 struct gf100_dma_v0 gf100;
50 struct gf119_dma_v0 gf119;
51 };
52 } args = {};
53 u32 argc = sizeof(args.base);
54 int ret;
55
56 list_for_each_entry(ctxdma, &wndw->ctxdma.list, head) {
57 if (ctxdma->object.handle == handle)
58 return ctxdma;
59 }
60
61 if (!(ctxdma = kzalloc(sizeof(*ctxdma), GFP_KERNEL)))
62 return ERR_PTR(-ENOMEM);
63 list_add(&ctxdma->head, &wndw->ctxdma.list);
64
65 args.base.target = NV_DMA_V0_TARGET_VRAM;
66 args.base.access = NV_DMA_V0_ACCESS_RDWR;
67 args.base.start = 0;
68 args.base.limit = drm->client.device.info.ram_user - 1;
69
70 if (drm->client.device.info.chipset < 0x80) {
71 args.nv50.part = NV50_DMA_V0_PART_256;
72 argc += sizeof(args.nv50);
73 } else
74 if (drm->client.device.info.chipset < 0xc0) {
75 args.nv50.part = NV50_DMA_V0_PART_256;
76 args.nv50.kind = kind;
77 argc += sizeof(args.nv50);
78 } else
79 if (drm->client.device.info.chipset < 0xd0) {
80 args.gf100.kind = kind;
81 argc += sizeof(args.gf100);
82 } else {
83 args.gf119.page = GF119_DMA_V0_PAGE_LP;
84 args.gf119.kind = kind;
85 argc += sizeof(args.gf119);
86 }
87
88 ret = nvif_object_init(wndw->ctxdma.parent, handle, NV_DMA_IN_MEMORY,
89 &args, argc, &ctxdma->object);
90 if (ret) {
91 nv50_wndw_ctxdma_del(ctxdma);
92 return ERR_PTR(ret);
93 }
94
95 return ctxdma;
96}
97
98int
99nv50_wndw_wait_armed(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
100{
Ben Skeggsccd27db2018-05-08 20:39:47 +1000101 struct nv50_disp *disp = nv50_disp(wndw->plane.dev);
102 if (asyw->set.ntfy) {
103 return wndw->func->ntfy_wait_begun(disp->sync,
104 asyw->ntfy.offset,
105 wndw->wndw.base.device);
106 }
Ben Skeggs15907002018-05-08 20:39:47 +1000107 return 0;
108}
109
Ben Skeggs53e0a3e2018-05-08 20:39:47 +1000110void
111nv50_wndw_flush_clr(struct nv50_wndw *wndw, u32 *interlock, bool flush,
Ben Skeggs15907002018-05-08 20:39:47 +1000112 struct nv50_wndw_atom *asyw)
113{
Ben Skeggsf88bc9d32018-05-08 20:39:47 +1000114 union nv50_wndw_atom_mask clr = {
115 .mask = asyw->clr.mask & ~(flush ? 0 : asyw->set.mask),
116 };
117 if (clr.sema ) wndw->func-> sema_clr(wndw);
118 if (clr.ntfy ) wndw->func-> ntfy_clr(wndw);
Ben Skeggs119608a2018-05-08 20:39:47 +1000119 if (clr.xlut ) wndw->func-> xlut_clr(wndw);
Ben Skeggsf88bc9d32018-05-08 20:39:47 +1000120 if (clr.image) wndw->func->image_clr(wndw);
Ben Skeggs15907002018-05-08 20:39:47 +1000121
Ben Skeggs53e0a3e2018-05-08 20:39:47 +1000122 interlock[wndw->interlock.type] |= wndw->interlock.data;
Ben Skeggs15907002018-05-08 20:39:47 +1000123}
124
Ben Skeggs53e0a3e2018-05-08 20:39:47 +1000125void
126nv50_wndw_flush_set(struct nv50_wndw *wndw, u32 *interlock,
Ben Skeggs15907002018-05-08 20:39:47 +1000127 struct nv50_wndw_atom *asyw)
128{
129 if (interlock) {
130 asyw->image.mode = 0;
131 asyw->image.interval = 1;
132 }
133
134 if (asyw->set.sema ) wndw->func->sema_set (wndw, asyw);
135 if (asyw->set.ntfy ) wndw->func->ntfy_set (wndw, asyw);
136 if (asyw->set.image) wndw->func->image_set(wndw, asyw);
Ben Skeggs119608a2018-05-08 20:39:47 +1000137
138 if (asyw->set.xlut ) {
139 if (asyw->ilut) {
140 asyw->xlut.i.offset =
141 nv50_lut_load(&wndw->ilut,
142 asyw->xlut.i.mode <= 1,
143 asyw->xlut.i.buffer,
144 asyw->ilut);
145 }
146 wndw->func->xlut_set(wndw, asyw);
147 }
148
Ben Skeggs2ce7f382018-05-08 20:39:47 +1000149 if (asyw->set.scale) wndw->func->scale_set(wndw, asyw);
Ben Skeggs15907002018-05-08 20:39:47 +1000150 if (asyw->set.point) {
151 wndw->immd->point(wndw, asyw);
152 wndw->immd->update(wndw, interlock);
153 }
154
Ben Skeggs53e0a3e2018-05-08 20:39:47 +1000155 interlock[wndw->interlock.type] |= wndw->interlock.data;
Ben Skeggs15907002018-05-08 20:39:47 +1000156}
157
Ben Skeggsccd27db2018-05-08 20:39:47 +1000158void
159nv50_wndw_ntfy_enable(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
160{
161 struct nv50_disp *disp = nv50_disp(wndw->plane.dev);
162
163 asyw->ntfy.handle = wndw->wndw.sync.handle;
164 asyw->ntfy.offset = wndw->ntfy;
165 asyw->ntfy.awaken = false;
166 asyw->set.ntfy = true;
167
168 wndw->func->ntfy_reset(disp->sync, wndw->ntfy);
169 wndw->ntfy ^= 0x10;
170}
171
Ben Skeggs15907002018-05-08 20:39:47 +1000172static void
173nv50_wndw_atomic_check_release(struct nv50_wndw *wndw,
174 struct nv50_wndw_atom *asyw,
175 struct nv50_head_atom *asyh)
176{
177 struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev);
178 NV_ATOMIC(drm, "%s release\n", wndw->plane.name);
179 wndw->func->release(wndw, asyw, asyh);
180 asyw->ntfy.handle = 0;
181 asyw->sema.handle = 0;
182}
183
184static int
Ben Skeggs2ce7f382018-05-08 20:39:47 +1000185nv50_wndw_atomic_check_acquire_yuv(struct nv50_wndw_atom *asyw)
186{
187 switch (asyw->state.fb->format->format) {
188 case DRM_FORMAT_YUYV: asyw->image.format = 0x28; break;
189 case DRM_FORMAT_UYVY: asyw->image.format = 0x29; break;
190 default:
191 WARN_ON(1);
192 return -EINVAL;
193 }
194 asyw->image.colorspace = 1;
195 return 0;
196}
197
198static int
Ben Skeggs43c181e2018-05-08 20:39:47 +1000199nv50_wndw_atomic_check_acquire_rgb(struct nv50_wndw_atom *asyw)
200{
201 switch (asyw->state.fb->format->format) {
202 case DRM_FORMAT_C8 : asyw->image.format = 0x1e; break;
203 case DRM_FORMAT_XRGB8888 :
204 case DRM_FORMAT_ARGB8888 : asyw->image.format = 0xcf; break;
205 case DRM_FORMAT_RGB565 : asyw->image.format = 0xe8; break;
206 case DRM_FORMAT_XRGB1555 :
207 case DRM_FORMAT_ARGB1555 : asyw->image.format = 0xe9; break;
208 case DRM_FORMAT_XBGR2101010:
209 case DRM_FORMAT_ABGR2101010: asyw->image.format = 0xd1; break;
210 case DRM_FORMAT_XBGR8888 :
211 case DRM_FORMAT_ABGR8888 : asyw->image.format = 0xd5; break;
Ben Skeggs88b600d2018-05-08 20:39:47 +1000212 case DRM_FORMAT_XRGB2101010:
213 case DRM_FORMAT_ARGB2101010: asyw->image.format = 0xdf; break;
Ben Skeggs43c181e2018-05-08 20:39:47 +1000214 default:
Ben Skeggs43c181e2018-05-08 20:39:47 +1000215 return -EINVAL;
216 }
Ben Skeggs2ce7f382018-05-08 20:39:47 +1000217 asyw->image.colorspace = 0;
Ben Skeggs43c181e2018-05-08 20:39:47 +1000218 return 0;
219}
220
221static int
Ben Skeggse349a052018-05-08 20:39:47 +1000222nv50_wndw_atomic_check_acquire(struct nv50_wndw *wndw, bool modeset,
223 struct nv50_wndw_atom *armw,
Ben Skeggs15907002018-05-08 20:39:47 +1000224 struct nv50_wndw_atom *asyw,
225 struct nv50_head_atom *asyh)
226{
227 struct nouveau_framebuffer *fb = nouveau_framebuffer(asyw->state.fb);
228 struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev);
229 int ret;
230
231 NV_ATOMIC(drm, "%s acquire\n", wndw->plane.name);
232
Ben Skeggse349a052018-05-08 20:39:47 +1000233 if (asyw->state.fb != armw->state.fb || !armw->visible || modeset) {
234 asyw->image.w = fb->base.width;
235 asyw->image.h = fb->base.height;
236 asyw->image.kind = fb->nvbo->kind;
Ben Skeggs15907002018-05-08 20:39:47 +1000237
Ben Skeggse349a052018-05-08 20:39:47 +1000238 ret = nv50_wndw_atomic_check_acquire_rgb(asyw);
Ben Skeggs2ce7f382018-05-08 20:39:47 +1000239 if (ret) {
240 ret = nv50_wndw_atomic_check_acquire_yuv(asyw);
241 if (ret)
242 return ret;
243 }
Ben Skeggs43c181e2018-05-08 20:39:47 +1000244
Ben Skeggse349a052018-05-08 20:39:47 +1000245 if (asyw->image.kind) {
246 asyw->image.layout = 0;
247 if (drm->client.device.info.chipset >= 0xc0)
Ben Skeggsb05d8732018-05-08 20:39:47 +1000248 asyw->image.blockh = fb->nvbo->mode >> 4;
Ben Skeggse349a052018-05-08 20:39:47 +1000249 else
Ben Skeggsb05d8732018-05-08 20:39:47 +1000250 asyw->image.blockh = fb->nvbo->mode;
251 asyw->image.blocks[0] = fb->base.pitches[0] / 64;
252 asyw->image.pitch[0] = 0;
Ben Skeggse349a052018-05-08 20:39:47 +1000253 } else {
254 asyw->image.layout = 1;
Ben Skeggsb05d8732018-05-08 20:39:47 +1000255 asyw->image.blockh = 0;
256 asyw->image.blocks[0] = 0;
Ben Skeggse349a052018-05-08 20:39:47 +1000257 asyw->image.pitch[0] = fb->base.pitches[0];
258 }
Ben Skeggs15907002018-05-08 20:39:47 +1000259
Ben Skeggs45a29452018-05-08 20:39:47 +1000260 if (!(asyh->state.pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC))
261 asyw->image.interval = 1;
Ben Skeggs15907002018-05-08 20:39:47 +1000262 else
263 asyw->image.interval = 0;
Ben Skeggs45a29452018-05-08 20:39:47 +1000264 asyw->image.mode = asyw->image.interval ? 0 : 1;
Ben Skeggse349a052018-05-08 20:39:47 +1000265 asyw->set.image = wndw->func->image_set != NULL;
Ben Skeggs15907002018-05-08 20:39:47 +1000266 }
267
Ben Skeggs2ce7f382018-05-08 20:39:47 +1000268 if (wndw->func->scale_set) {
269 asyw->scale.sx = asyw->state.src_x >> 16;
270 asyw->scale.sy = asyw->state.src_y >> 16;
271 asyw->scale.sw = asyw->state.src_w >> 16;
272 asyw->scale.sh = asyw->state.src_h >> 16;
273 asyw->scale.dw = asyw->state.crtc_w;
274 asyw->scale.dh = asyw->state.crtc_h;
275 if (memcmp(&armw->scale, &asyw->scale, sizeof(asyw->scale)))
276 asyw->set.scale = true;
277 }
278
Ben Skeggse349a052018-05-08 20:39:47 +1000279 if (wndw->immd) {
280 asyw->point.x = asyw->state.crtc_x;
281 asyw->point.y = asyw->state.crtc_y;
282 if (memcmp(&armw->point, &asyw->point, sizeof(asyw->point)))
283 asyw->set.point = true;
284 }
285
286 return wndw->func->acquire(wndw, asyw, asyh);
Ben Skeggs15907002018-05-08 20:39:47 +1000287}
288
Ben Skeggs119608a2018-05-08 20:39:47 +1000289static void
290nv50_wndw_atomic_check_lut(struct nv50_wndw *wndw,
291 struct nv50_wndw_atom *armw,
292 struct nv50_wndw_atom *asyw,
293 struct nv50_head_atom *asyh)
294{
295 struct drm_property_blob *ilut = asyh->state.degamma_lut;
296
297 /* I8 format without an input LUT makes no sense, and the
298 * HW error-checks for this.
299 *
300 * In order to handle legacy gamma, when there's no input
301 * LUT we need to steal the output LUT and use it instead.
302 */
303 if (!ilut && asyw->state.fb->format->format == DRM_FORMAT_C8) {
304 /* This should be an error, but there's legacy clients
305 * that do a modeset before providing a gamma table.
306 *
307 * We keep the window disabled to avoid angering HW.
308 */
309 if (!(ilut = asyh->state.gamma_lut)) {
310 asyw->visible = false;
311 return;
312 }
313
314 if (wndw->func->ilut)
315 asyh->wndw.olut |= BIT(wndw->id);
316 } else {
317 asyh->wndw.olut &= ~BIT(wndw->id);
318 }
319
320 /* Recalculate LUT state. */
321 memset(&asyw->xlut, 0x00, sizeof(asyw->xlut));
322 if ((asyw->ilut = wndw->func->ilut ? ilut : NULL)) {
323 wndw->func->ilut(wndw, asyw);
324 asyw->xlut.handle = wndw->wndw.vram.handle;
325 asyw->xlut.i.buffer = !asyw->xlut.i.buffer;
326 asyw->set.xlut = true;
327 }
328
329 /* Handle setting base SET_OUTPUT_LUT_LO_ENABLE_USE_CORE_LUT. */
330 if (wndw->func->olut_core &&
331 (!armw->visible || (armw->xlut.handle && !asyw->xlut.handle)))
332 asyw->set.xlut = true;
333
334 /* Can't do an immediate flip while changing the LUT. */
335 asyh->state.pageflip_flags &= ~DRM_MODE_PAGE_FLIP_ASYNC;
336}
337
338static int
Ben Skeggs15907002018-05-08 20:39:47 +1000339nv50_wndw_atomic_check(struct drm_plane *plane, struct drm_plane_state *state)
340{
341 struct nouveau_drm *drm = nouveau_drm(plane->dev);
342 struct nv50_wndw *wndw = nv50_wndw(plane);
343 struct nv50_wndw_atom *armw = nv50_wndw_atom(wndw->plane.state);
344 struct nv50_wndw_atom *asyw = nv50_wndw_atom(state);
345 struct nv50_head_atom *harm = NULL, *asyh = NULL;
Ben Skeggs859b4562018-05-08 20:39:47 +1000346 bool modeset = false;
Ben Skeggs15907002018-05-08 20:39:47 +1000347 int ret;
348
349 NV_ATOMIC(drm, "%s atomic_check\n", plane->name);
Ben Skeggs859b4562018-05-08 20:39:47 +1000350
351 /* Fetch the assembly state for the head the window will belong to,
352 * and determine whether the window will be visible.
353 */
Ben Skeggs15907002018-05-08 20:39:47 +1000354 if (asyw->state.crtc) {
355 asyh = nv50_head_atom_get(asyw->state.state, asyw->state.crtc);
356 if (IS_ERR(asyh))
357 return PTR_ERR(asyh);
Ben Skeggs859b4562018-05-08 20:39:47 +1000358 modeset = drm_atomic_crtc_needs_modeset(&asyh->state);
359 asyw->visible = asyh->state.active;
360 } else {
361 asyw->visible = false;
Ben Skeggs15907002018-05-08 20:39:47 +1000362 }
363
Ben Skeggs859b4562018-05-08 20:39:47 +1000364 /* Fetch assembly state for the head the window used to belong to. */
Ben Skeggs15907002018-05-08 20:39:47 +1000365 if (armw->state.crtc) {
366 harm = nv50_head_atom_get(asyw->state.state, armw->state.crtc);
367 if (IS_ERR(harm))
368 return PTR_ERR(harm);
Ben Skeggs15907002018-05-08 20:39:47 +1000369 }
370
Ben Skeggs119608a2018-05-08 20:39:47 +1000371 /* LUT configuration can potentially cause the window to be disabled. */
372 if (asyw->visible && wndw->func->xlut_set &&
373 (!armw->visible ||
374 asyh->state.color_mgmt_changed ||
375 asyw->state.fb->format->format !=
376 armw->state.fb->format->format))
377 nv50_wndw_atomic_check_lut(wndw, armw, asyw, asyh);
378
Ben Skeggs859b4562018-05-08 20:39:47 +1000379 /* Calculate new window state. */
380 if (asyw->visible) {
Ben Skeggse349a052018-05-08 20:39:47 +1000381 ret = nv50_wndw_atomic_check_acquire(wndw, modeset,
382 armw, asyw, asyh);
Ben Skeggs15907002018-05-08 20:39:47 +1000383 if (ret)
384 return ret;
Ben Skeggs119608a2018-05-08 20:39:47 +1000385
386 asyh->wndw.mask |= BIT(wndw->id);
Ben Skeggs15907002018-05-08 20:39:47 +1000387 } else
Ben Skeggs859b4562018-05-08 20:39:47 +1000388 if (armw->visible) {
Ben Skeggs15907002018-05-08 20:39:47 +1000389 nv50_wndw_atomic_check_release(wndw, asyw, harm);
Ben Skeggs119608a2018-05-08 20:39:47 +1000390 harm->wndw.mask &= ~BIT(wndw->id);
Ben Skeggs15907002018-05-08 20:39:47 +1000391 } else {
392 return 0;
393 }
394
Ben Skeggs859b4562018-05-08 20:39:47 +1000395 /* Aside from the obvious case where the window is actively being
396 * disabled, we might also need to temporarily disable the window
397 * when performing certain modeset operations.
398 */
399 if (!asyw->visible || modeset) {
Ben Skeggs15907002018-05-08 20:39:47 +1000400 asyw->clr.ntfy = armw->ntfy.handle != 0;
401 asyw->clr.sema = armw->sema.handle != 0;
Ben Skeggs119608a2018-05-08 20:39:47 +1000402 asyw->clr.xlut = armw->xlut.handle != 0;
Ben Skeggs15907002018-05-08 20:39:47 +1000403 if (wndw->func->image_clr)
Ben Skeggs261fcfa2018-05-08 20:39:47 +1000404 asyw->clr.image = armw->image.handle[0] != 0;
Ben Skeggs15907002018-05-08 20:39:47 +1000405 }
406
407 return 0;
408}
409
410static void
411nv50_wndw_cleanup_fb(struct drm_plane *plane, struct drm_plane_state *old_state)
412{
413 struct nouveau_framebuffer *fb = nouveau_framebuffer(old_state->fb);
414 struct nouveau_drm *drm = nouveau_drm(plane->dev);
415
416 NV_ATOMIC(drm, "%s cleanup: %p\n", plane->name, old_state->fb);
417 if (!old_state->fb)
418 return;
419
420 nouveau_bo_unpin(fb->nvbo);
421}
422
423static int
424nv50_wndw_prepare_fb(struct drm_plane *plane, struct drm_plane_state *state)
425{
426 struct nouveau_framebuffer *fb = nouveau_framebuffer(state->fb);
427 struct nouveau_drm *drm = nouveau_drm(plane->dev);
428 struct nv50_wndw *wndw = nv50_wndw(plane);
429 struct nv50_wndw_atom *asyw = nv50_wndw_atom(state);
430 struct nv50_head_atom *asyh;
431 struct nv50_wndw_ctxdma *ctxdma;
432 int ret;
433
434 NV_ATOMIC(drm, "%s prepare: %p\n", plane->name, state->fb);
435 if (!asyw->state.fb)
436 return 0;
437
438 ret = nouveau_bo_pin(fb->nvbo, TTM_PL_FLAG_VRAM, true);
439 if (ret)
440 return ret;
441
442 ctxdma = nv50_wndw_ctxdma_new(wndw, fb);
443 if (IS_ERR(ctxdma)) {
444 nouveau_bo_unpin(fb->nvbo);
445 return PTR_ERR(ctxdma);
446 }
447
448 asyw->state.fence = reservation_object_get_excl_rcu(fb->nvbo->bo.resv);
Ben Skeggs261fcfa2018-05-08 20:39:47 +1000449 asyw->image.handle[0] = ctxdma->object.handle;
450 asyw->image.offset[0] = fb->nvbo->bo.offset;
Ben Skeggs15907002018-05-08 20:39:47 +1000451
452 if (wndw->func->prepare) {
453 asyh = nv50_head_atom_get(asyw->state.state, asyw->state.crtc);
454 if (IS_ERR(asyh))
455 return PTR_ERR(asyh);
456
457 wndw->func->prepare(wndw, asyh, asyw);
458 }
459
460 return 0;
461}
462
463static const struct drm_plane_helper_funcs
464nv50_wndw_helper = {
465 .prepare_fb = nv50_wndw_prepare_fb,
466 .cleanup_fb = nv50_wndw_cleanup_fb,
467 .atomic_check = nv50_wndw_atomic_check,
468};
469
470static void
471nv50_wndw_atomic_destroy_state(struct drm_plane *plane,
472 struct drm_plane_state *state)
473{
474 struct nv50_wndw_atom *asyw = nv50_wndw_atom(state);
475 __drm_atomic_helper_plane_destroy_state(&asyw->state);
476 kfree(asyw);
477}
478
479static struct drm_plane_state *
480nv50_wndw_atomic_duplicate_state(struct drm_plane *plane)
481{
482 struct nv50_wndw_atom *armw = nv50_wndw_atom(plane->state);
483 struct nv50_wndw_atom *asyw;
484 if (!(asyw = kmalloc(sizeof(*asyw), GFP_KERNEL)))
485 return NULL;
486 __drm_atomic_helper_plane_duplicate_state(plane, &asyw->state);
Ben Skeggs15907002018-05-08 20:39:47 +1000487 asyw->sema = armw->sema;
488 asyw->ntfy = armw->ntfy;
Ben Skeggs119608a2018-05-08 20:39:47 +1000489 asyw->ilut = NULL;
490 asyw->xlut = armw->xlut;
Ben Skeggs15907002018-05-08 20:39:47 +1000491 asyw->image = armw->image;
492 asyw->point = armw->point;
Ben Skeggs15907002018-05-08 20:39:47 +1000493 asyw->clr.mask = 0;
494 asyw->set.mask = 0;
495 return &asyw->state;
496}
497
498static void
499nv50_wndw_reset(struct drm_plane *plane)
500{
501 struct nv50_wndw_atom *asyw;
502
503 if (WARN_ON(!(asyw = kzalloc(sizeof(*asyw), GFP_KERNEL))))
504 return;
505
506 if (plane->state)
507 plane->funcs->atomic_destroy_state(plane, plane->state);
508 plane->state = &asyw->state;
509 plane->state->plane = plane;
510 plane->state->rotation = DRM_MODE_ROTATE_0;
511}
512
513static void
514nv50_wndw_destroy(struct drm_plane *plane)
515{
516 struct nv50_wndw *wndw = nv50_wndw(plane);
517 struct nv50_wndw_ctxdma *ctxdma, *ctxtmp;
518
519 list_for_each_entry_safe(ctxdma, ctxtmp, &wndw->ctxdma.list, head) {
520 nv50_wndw_ctxdma_del(ctxdma);
521 }
522
523 nvif_notify_fini(&wndw->notify);
524 nv50_dmac_destroy(&wndw->wimm);
525 nv50_dmac_destroy(&wndw->wndw);
Ben Skeggs119608a2018-05-08 20:39:47 +1000526
527 nv50_lut_fini(&wndw->ilut);
528
Ben Skeggs15907002018-05-08 20:39:47 +1000529 drm_plane_cleanup(&wndw->plane);
530 kfree(wndw);
531}
532
533const struct drm_plane_funcs
534nv50_wndw = {
535 .update_plane = drm_atomic_helper_update_plane,
536 .disable_plane = drm_atomic_helper_disable_plane,
537 .destroy = nv50_wndw_destroy,
538 .reset = nv50_wndw_reset,
539 .atomic_duplicate_state = nv50_wndw_atomic_duplicate_state,
540 .atomic_destroy_state = nv50_wndw_atomic_destroy_state,
541};
542
543static int
544nv50_wndw_notify(struct nvif_notify *notify)
545{
546 return NVIF_NOTIFY_KEEP;
547}
548
549void
550nv50_wndw_fini(struct nv50_wndw *wndw)
551{
552 nvif_notify_put(&wndw->notify);
553}
554
555void
556nv50_wndw_init(struct nv50_wndw *wndw)
557{
558 nvif_notify_get(&wndw->notify);
559}
560
561int
562nv50_wndw_new_(const struct nv50_wndw_func *func, struct drm_device *dev,
563 enum drm_plane_type type, const char *name, int index,
Ben Skeggs53e0a3e2018-05-08 20:39:47 +1000564 const u32 *format, u32 heads,
565 enum nv50_disp_interlock_type interlock_type, u32 interlock_data,
566 struct nv50_wndw **pwndw)
Ben Skeggs15907002018-05-08 20:39:47 +1000567{
Ben Skeggs119608a2018-05-08 20:39:47 +1000568 struct nouveau_drm *drm = nouveau_drm(dev);
569 struct nvif_mmu *mmu = &drm->client.mmu;
570 struct nv50_disp *disp = nv50_disp(dev);
Ben Skeggs15907002018-05-08 20:39:47 +1000571 struct nv50_wndw *wndw;
572 int nformat;
573 int ret;
574
575 if (!(wndw = *pwndw = kzalloc(sizeof(*wndw), GFP_KERNEL)))
576 return -ENOMEM;
577 wndw->func = func;
578 wndw->id = index;
Ben Skeggs53e0a3e2018-05-08 20:39:47 +1000579 wndw->interlock.type = interlock_type;
580 wndw->interlock.data = interlock_data;
581 wndw->ctxdma.parent = &wndw->wndw.base.user;
Ben Skeggs15907002018-05-08 20:39:47 +1000582
583 wndw->ctxdma.parent = &wndw->wndw.base.user;
584 INIT_LIST_HEAD(&wndw->ctxdma.list);
585
586 for (nformat = 0; format[nformat]; nformat++);
587
Ben Skeggs9d6c2fe2018-05-08 20:39:47 +1000588 ret = drm_universal_plane_init(dev, &wndw->plane, heads, &nv50_wndw,
Ben Skeggs15907002018-05-08 20:39:47 +1000589 format, nformat, NULL,
590 type, "%s-%d", name, index);
591 if (ret) {
592 kfree(*pwndw);
593 *pwndw = NULL;
594 return ret;
595 }
596
597 drm_plane_helper_add(&wndw->plane, &nv50_wndw_helper);
598
Ben Skeggs119608a2018-05-08 20:39:47 +1000599 if (wndw->func->ilut) {
600 ret = nv50_lut_init(disp, mmu, &wndw->ilut);
601 if (ret)
602 return ret;
603 }
604
Ben Skeggs15907002018-05-08 20:39:47 +1000605 wndw->notify.func = nv50_wndw_notify;
606 return 0;
607}