Fabio Estevam | 1f31e25 | 2018-05-14 14:58:47 -0300 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | // |
| 3 | //Copyright (C) 2013 Freescale Semiconductor, Inc. |
Shawn Guo | 117ccd55 | 2013-05-03 11:28:42 +0800 | [diff] [blame] | 4 | |
| 5 | /dts-v1/; |
| 6 | |
Fabio Estevam | 3310670 | 2014-02-06 13:08:08 -0200 | [diff] [blame] | 7 | #include <dt-bindings/gpio/gpio.h> |
Anson Huang | 4291b64 | 2014-01-14 17:30:28 +0800 | [diff] [blame] | 8 | #include <dt-bindings/input/input.h> |
Shawn Guo | 117ccd55 | 2013-05-03 11:28:42 +0800 | [diff] [blame] | 9 | #include "imx6sl.dtsi" |
| 10 | |
| 11 | / { |
| 12 | model = "Freescale i.MX6 SoloLite EVK Board"; |
| 13 | compatible = "fsl,imx6sl-evk", "fsl,imx6sl"; |
| 14 | |
Marco Franchi | ad00e08 | 2018-01-24 11:22:14 -0200 | [diff] [blame] | 15 | memory@80000000 { |
Shawn Guo | 117ccd55 | 2013-05-03 11:28:42 +0800 | [diff] [blame] | 16 | reg = <0x80000000 0x40000000>; |
| 17 | }; |
Peter Chen | 6022232 | 2013-09-10 10:23:16 +0800 | [diff] [blame] | 18 | |
Marco Franchi | 4d9a387 | 2017-12-06 13:15:19 -0200 | [diff] [blame] | 19 | backlight_display: backlight_display { |
Fabio Estevam | e99b077 | 2014-08-19 15:21:14 -0300 | [diff] [blame] | 20 | compatible = "pwm-backlight"; |
| 21 | pwms = <&pwm1 0 5000000>; |
| 22 | brightness-levels = <0 4 8 16 32 64 128 255>; |
| 23 | default-brightness-level = <6>; |
| 24 | }; |
| 25 | |
Fabio Estevam | 3310670 | 2014-02-06 13:08:08 -0200 | [diff] [blame] | 26 | leds { |
| 27 | compatible = "gpio-leds"; |
| 28 | pinctrl-names = "default"; |
| 29 | pinctrl-0 = <&pinctrl_led>; |
| 30 | |
| 31 | user { |
| 32 | label = "debug"; |
| 33 | gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; |
| 34 | linux,default-trigger = "heartbeat"; |
| 35 | }; |
| 36 | }; |
| 37 | |
Marco Franchi | 1876d0d | 2017-12-06 13:15:18 -0200 | [diff] [blame] | 38 | reg_usb_otg1_vbus: regulator-usb-otg1-vbus { |
| 39 | compatible = "regulator-fixed"; |
| 40 | regulator-name = "usb_otg1_vbus"; |
| 41 | regulator-min-microvolt = <5000000>; |
| 42 | regulator-max-microvolt = <5000000>; |
| 43 | gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>; |
| 44 | enable-active-high; |
| 45 | vin-supply = <&swbst_reg>; |
| 46 | }; |
Peter Chen | 6022232 | 2013-09-10 10:23:16 +0800 | [diff] [blame] | 47 | |
Marco Franchi | 1876d0d | 2017-12-06 13:15:18 -0200 | [diff] [blame] | 48 | reg_usb_otg2_vbus: regulator-usb-otg2-vbus { |
| 49 | compatible = "regulator-fixed"; |
| 50 | regulator-name = "usb_otg2_vbus"; |
| 51 | regulator-min-microvolt = <5000000>; |
| 52 | regulator-max-microvolt = <5000000>; |
| 53 | gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; |
| 54 | enable-active-high; |
| 55 | vin-supply = <&swbst_reg>; |
| 56 | }; |
Peter Chen | 6022232 | 2013-09-10 10:23:16 +0800 | [diff] [blame] | 57 | |
Marco Franchi | 1876d0d | 2017-12-06 13:15:18 -0200 | [diff] [blame] | 58 | reg_aud3v: regulator-aud3v { |
| 59 | compatible = "regulator-fixed"; |
| 60 | regulator-name = "wm8962-supply-3v15"; |
| 61 | regulator-min-microvolt = <3150000>; |
| 62 | regulator-max-microvolt = <3150000>; |
| 63 | regulator-boot-on; |
| 64 | }; |
Fabio Estevam | 032de43 | 2014-02-06 08:57:51 -0200 | [diff] [blame] | 65 | |
Marco Franchi | 1876d0d | 2017-12-06 13:15:18 -0200 | [diff] [blame] | 66 | reg_aud4v: regulator-aud4v { |
| 67 | compatible = "regulator-fixed"; |
| 68 | regulator-name = "wm8962-supply-4v2"; |
| 69 | regulator-min-microvolt = <4325000>; |
| 70 | regulator-max-microvolt = <4325000>; |
| 71 | regulator-boot-on; |
| 72 | }; |
Fabio Estevam | 032de43 | 2014-02-06 08:57:51 -0200 | [diff] [blame] | 73 | |
Marco Franchi | 1876d0d | 2017-12-06 13:15:18 -0200 | [diff] [blame] | 74 | reg_lcd_3v3: regulator-lcd-3v3 { |
| 75 | compatible = "regulator-fixed"; |
| 76 | regulator-name = "lcd-3v3"; |
| 77 | gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; |
| 78 | enable-active-high; |
Peter Chen | 6022232 | 2013-09-10 10:23:16 +0800 | [diff] [blame] | 79 | }; |
Fabio Estevam | 032de43 | 2014-02-06 08:57:51 -0200 | [diff] [blame] | 80 | |
Marco Franchi | 4d9a387 | 2017-12-06 13:15:19 -0200 | [diff] [blame] | 81 | reg_lcd_5v: regulator-lcd-5v { |
| 82 | compatible = "regulator-fixed"; |
| 83 | regulator-name = "lcd-5v0"; |
| 84 | regulator-min-microvolt = <5000000>; |
| 85 | regulator-max-microvolt = <5000000>; |
| 86 | }; |
| 87 | |
Fabio Estevam | 032de43 | 2014-02-06 08:57:51 -0200 | [diff] [blame] | 88 | sound { |
| 89 | compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962"; |
| 90 | model = "wm8962-audio"; |
| 91 | ssi-controller = <&ssi2>; |
| 92 | audio-codec = <&codec>; |
| 93 | audio-routing = |
| 94 | "Headphone Jack", "HPOUTL", |
| 95 | "Headphone Jack", "HPOUTR", |
| 96 | "Ext Spk", "SPKOUTL", |
| 97 | "Ext Spk", "SPKOUTR", |
| 98 | "AMIC", "MICBIAS", |
| 99 | "IN3R", "AMIC"; |
| 100 | mux-int-port = <2>; |
| 101 | mux-ext-port = <3>; |
| 102 | }; |
Marco Franchi | 4d9a387 | 2017-12-06 13:15:19 -0200 | [diff] [blame] | 103 | |
| 104 | panel { |
| 105 | compatible = "sii,43wvf1g"; |
| 106 | backlight = <&backlight_display>; |
| 107 | dvdd-supply = <®_lcd_3v3>; |
| 108 | avdd-supply = <®_lcd_5v>; |
| 109 | |
| 110 | port { |
| 111 | panel_in: endpoint { |
| 112 | remote-endpoint = <&display_out>; |
| 113 | }; |
| 114 | }; |
| 115 | }; |
Fabio Estevam | 032de43 | 2014-02-06 08:57:51 -0200 | [diff] [blame] | 116 | }; |
| 117 | |
| 118 | &audmux { |
| 119 | pinctrl-names = "default"; |
| 120 | pinctrl-0 = <&pinctrl_audmux3>; |
| 121 | status = "okay"; |
Shawn Guo | 117ccd55 | 2013-05-03 11:28:42 +0800 | [diff] [blame] | 122 | }; |
| 123 | |
Huang Shijie | d1b5397 | 2013-10-18 10:32:53 +0800 | [diff] [blame] | 124 | &ecspi1 { |
Huang Shijie | d1b5397 | 2013-10-18 10:32:53 +0800 | [diff] [blame] | 125 | cs-gpios = <&gpio4 11 0>; |
| 126 | pinctrl-names = "default"; |
Shawn Guo | fffaa65 | 2013-11-04 10:49:04 +0800 | [diff] [blame] | 127 | pinctrl-0 = <&pinctrl_ecspi1>; |
Huang Shijie | d1b5397 | 2013-10-18 10:32:53 +0800 | [diff] [blame] | 128 | status = "okay"; |
| 129 | |
| 130 | flash: m25p80@0 { |
| 131 | #address-cells = <1>; |
| 132 | #size-cells = <1>; |
Rafał Miłecki | 79826ac | 2015-08-16 08:39:17 +0200 | [diff] [blame] | 133 | compatible = "st,m25p32", "jedec,spi-nor"; |
Huang Shijie | d1b5397 | 2013-10-18 10:32:53 +0800 | [diff] [blame] | 134 | spi-max-frequency = <20000000>; |
| 135 | reg = <0>; |
| 136 | }; |
| 137 | }; |
| 138 | |
Shawn Guo | 117ccd55 | 2013-05-03 11:28:42 +0800 | [diff] [blame] | 139 | &fec { |
Fugang Duan | 01d41c9 | 2014-05-20 14:50:44 +0800 | [diff] [blame] | 140 | pinctrl-names = "default", "sleep"; |
Shawn Guo | fffaa65 | 2013-11-04 10:49:04 +0800 | [diff] [blame] | 141 | pinctrl-0 = <&pinctrl_fec>; |
Fugang Duan | 01d41c9 | 2014-05-20 14:50:44 +0800 | [diff] [blame] | 142 | pinctrl-1 = <&pinctrl_fec_sleep>; |
Shawn Guo | 117ccd55 | 2013-05-03 11:28:42 +0800 | [diff] [blame] | 143 | phy-mode = "rmii"; |
| 144 | status = "okay"; |
| 145 | }; |
| 146 | |
Fabio Estevam | 56df268 | 2014-02-06 08:57:50 -0200 | [diff] [blame] | 147 | &i2c1 { |
| 148 | clock-frequency = <100000>; |
| 149 | pinctrl-names = "default"; |
| 150 | pinctrl-0 = <&pinctrl_i2c1>; |
| 151 | status = "okay"; |
| 152 | |
Rob Herring | 8dccafa | 2017-10-13 12:54:51 -0500 | [diff] [blame] | 153 | pmic: pfuze100@8 { |
Fabio Estevam | 56df268 | 2014-02-06 08:57:50 -0200 | [diff] [blame] | 154 | compatible = "fsl,pfuze100"; |
| 155 | reg = <0x08>; |
| 156 | |
| 157 | regulators { |
| 158 | sw1a_reg: sw1ab { |
| 159 | regulator-min-microvolt = <300000>; |
| 160 | regulator-max-microvolt = <1875000>; |
| 161 | regulator-boot-on; |
| 162 | regulator-always-on; |
| 163 | regulator-ramp-delay = <6250>; |
| 164 | }; |
| 165 | |
| 166 | sw1c_reg: sw1c { |
| 167 | regulator-min-microvolt = <300000>; |
| 168 | regulator-max-microvolt = <1875000>; |
| 169 | regulator-boot-on; |
| 170 | regulator-always-on; |
| 171 | regulator-ramp-delay = <6250>; |
| 172 | }; |
| 173 | |
| 174 | sw2_reg: sw2 { |
| 175 | regulator-min-microvolt = <800000>; |
| 176 | regulator-max-microvolt = <3300000>; |
| 177 | regulator-boot-on; |
| 178 | regulator-always-on; |
| 179 | }; |
| 180 | |
| 181 | sw3a_reg: sw3a { |
| 182 | regulator-min-microvolt = <400000>; |
| 183 | regulator-max-microvolt = <1975000>; |
| 184 | regulator-boot-on; |
| 185 | regulator-always-on; |
| 186 | }; |
| 187 | |
| 188 | sw3b_reg: sw3b { |
| 189 | regulator-min-microvolt = <400000>; |
| 190 | regulator-max-microvolt = <1975000>; |
| 191 | regulator-boot-on; |
| 192 | regulator-always-on; |
| 193 | }; |
| 194 | |
| 195 | sw4_reg: sw4 { |
| 196 | regulator-min-microvolt = <800000>; |
| 197 | regulator-max-microvolt = <3300000>; |
| 198 | }; |
| 199 | |
| 200 | swbst_reg: swbst { |
| 201 | regulator-min-microvolt = <5000000>; |
| 202 | regulator-max-microvolt = <5150000>; |
| 203 | }; |
| 204 | |
| 205 | snvs_reg: vsnvs { |
| 206 | regulator-min-microvolt = <1000000>; |
| 207 | regulator-max-microvolt = <3000000>; |
| 208 | regulator-boot-on; |
| 209 | regulator-always-on; |
| 210 | }; |
| 211 | |
| 212 | vref_reg: vrefddr { |
| 213 | regulator-boot-on; |
| 214 | regulator-always-on; |
| 215 | }; |
| 216 | |
| 217 | vgen1_reg: vgen1 { |
| 218 | regulator-min-microvolt = <800000>; |
| 219 | regulator-max-microvolt = <1550000>; |
Fabio Estevam | d2c3936 | 2014-02-19 08:13:48 -0300 | [diff] [blame] | 220 | regulator-always-on; |
Fabio Estevam | 56df268 | 2014-02-06 08:57:50 -0200 | [diff] [blame] | 221 | }; |
| 222 | |
| 223 | vgen2_reg: vgen2 { |
| 224 | regulator-min-microvolt = <800000>; |
| 225 | regulator-max-microvolt = <1550000>; |
| 226 | }; |
| 227 | |
| 228 | vgen3_reg: vgen3 { |
| 229 | regulator-min-microvolt = <1800000>; |
| 230 | regulator-max-microvolt = <3300000>; |
| 231 | }; |
| 232 | |
| 233 | vgen4_reg: vgen4 { |
| 234 | regulator-min-microvolt = <1800000>; |
| 235 | regulator-max-microvolt = <3300000>; |
| 236 | regulator-always-on; |
| 237 | }; |
| 238 | |
| 239 | vgen5_reg: vgen5 { |
| 240 | regulator-min-microvolt = <1800000>; |
| 241 | regulator-max-microvolt = <3300000>; |
| 242 | regulator-always-on; |
| 243 | }; |
| 244 | |
| 245 | vgen6_reg: vgen6 { |
| 246 | regulator-min-microvolt = <1800000>; |
| 247 | regulator-max-microvolt = <3300000>; |
| 248 | regulator-always-on; |
| 249 | }; |
| 250 | }; |
| 251 | }; |
| 252 | }; |
| 253 | |
Fabio Estevam | 032de43 | 2014-02-06 08:57:51 -0200 | [diff] [blame] | 254 | &i2c2 { |
| 255 | clock-frequency = <100000>; |
| 256 | pinctrl-names = "default"; |
| 257 | pinctrl-0 = <&pinctrl_i2c2>; |
| 258 | status = "okay"; |
| 259 | |
| 260 | codec: wm8962@1a { |
| 261 | compatible = "wlf,wm8962"; |
| 262 | reg = <0x1a>; |
| 263 | clocks = <&clks IMX6SL_CLK_EXTERN_AUDIO>; |
| 264 | DCVDD-supply = <&vgen3_reg>; |
| 265 | DBVDD-supply = <®_aud3v>; |
| 266 | AVDD-supply = <&vgen3_reg>; |
| 267 | CPVDD-supply = <&vgen3_reg>; |
| 268 | MICVDD-supply = <®_aud3v>; |
| 269 | PLLVDD-supply = <&vgen3_reg>; |
| 270 | SPKVDD1-supply = <®_aud4v>; |
| 271 | SPKVDD2-supply = <®_aud4v>; |
| 272 | }; |
| 273 | }; |
| 274 | |
Shawn Guo | 117ccd55 | 2013-05-03 11:28:42 +0800 | [diff] [blame] | 275 | &iomuxc { |
| 276 | pinctrl-names = "default"; |
| 277 | pinctrl-0 = <&pinctrl_hog>; |
| 278 | |
Shawn Guo | fffaa65 | 2013-11-04 10:49:04 +0800 | [diff] [blame] | 279 | imx6sl-evk { |
Shawn Guo | 117ccd55 | 2013-05-03 11:28:42 +0800 | [diff] [blame] | 280 | pinctrl_hog: hoggrp { |
| 281 | fsl,pins = < |
| 282 | MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x17059 |
| 283 | MX6SL_PAD_KEY_COL7__GPIO4_IO06 0x17059 |
| 284 | MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x17059 |
| 285 | MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x17059 |
| 286 | MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 |
Peter Chen | 6022232 | 2013-09-10 10:23:16 +0800 | [diff] [blame] | 287 | MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x80000000 |
| 288 | MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x80000000 |
Fabio Estevam | 032de43 | 2014-02-06 08:57:51 -0200 | [diff] [blame] | 289 | MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0 |
| 290 | >; |
| 291 | }; |
| 292 | |
| 293 | pinctrl_audmux3: audmux3grp { |
| 294 | fsl,pins = < |
| 295 | MX6SL_PAD_AUD_RXD__AUD3_RXD 0x4130b0 |
| 296 | MX6SL_PAD_AUD_TXC__AUD3_TXC 0x4130b0 |
| 297 | MX6SL_PAD_AUD_TXD__AUD3_TXD 0x4110b0 |
| 298 | MX6SL_PAD_AUD_TXFS__AUD3_TXFS 0x4130b0 |
Shawn Guo | 117ccd55 | 2013-05-03 11:28:42 +0800 | [diff] [blame] | 299 | >; |
| 300 | }; |
Shawn Guo | fffaa65 | 2013-11-04 10:49:04 +0800 | [diff] [blame] | 301 | |
| 302 | pinctrl_ecspi1: ecspi1grp { |
| 303 | fsl,pins = < |
| 304 | MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1 |
| 305 | MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1 |
| 306 | MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1 |
Fabio Estevam | 2cd3671 | 2014-04-11 09:09:39 -0300 | [diff] [blame] | 307 | MX6SL_PAD_ECSPI1_SS0__GPIO4_IO11 0x80000000 |
Shawn Guo | fffaa65 | 2013-11-04 10:49:04 +0800 | [diff] [blame] | 308 | >; |
| 309 | }; |
| 310 | |
| 311 | pinctrl_fec: fecgrp { |
| 312 | fsl,pins = < |
| 313 | MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0 |
| 314 | MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x1b0b0 |
| 315 | MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x1b0b0 |
| 316 | MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x1b0b0 |
| 317 | MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x1b0b0 |
| 318 | MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x1b0b0 |
| 319 | MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x1b0b0 |
| 320 | MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x1b0b0 |
| 321 | MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8 |
| 322 | >; |
| 323 | }; |
| 324 | |
Fugang Duan | 01d41c9 | 2014-05-20 14:50:44 +0800 | [diff] [blame] | 325 | pinctrl_fec_sleep: fecgrp-sleep { |
| 326 | fsl,pins = < |
| 327 | MX6SL_PAD_FEC_MDC__GPIO4_IO23 0x3080 |
| 328 | MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25 0x3080 |
| 329 | MX6SL_PAD_FEC_RXD0__GPIO4_IO17 0x3080 |
| 330 | MX6SL_PAD_FEC_RXD1__GPIO4_IO18 0x3080 |
| 331 | MX6SL_PAD_FEC_TX_EN__GPIO4_IO22 0x3080 |
| 332 | MX6SL_PAD_FEC_TXD0__GPIO4_IO24 0x3080 |
| 333 | MX6SL_PAD_FEC_TXD1__GPIO4_IO16 0x3080 |
| 334 | MX6SL_PAD_FEC_REF_CLK__GPIO4_IO26 0x3080 |
| 335 | >; |
| 336 | }; |
| 337 | |
Fabio Estevam | 56df268 | 2014-02-06 08:57:50 -0200 | [diff] [blame] | 338 | pinctrl_i2c1: i2c1grp { |
| 339 | fsl,pins = < |
| 340 | MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1 |
| 341 | MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1 |
| 342 | >; |
| 343 | }; |
| 344 | |
Fabio Estevam | 032de43 | 2014-02-06 08:57:51 -0200 | [diff] [blame] | 345 | |
| 346 | pinctrl_i2c2: i2c2grp { |
| 347 | fsl,pins = < |
| 348 | MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001b8b1 |
| 349 | MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001b8b1 |
| 350 | >; |
| 351 | }; |
| 352 | |
Anson Huang | 4291b64 | 2014-01-14 17:30:28 +0800 | [diff] [blame] | 353 | pinctrl_kpp: kppgrp { |
| 354 | fsl,pins = < |
| 355 | MX6SL_PAD_KEY_ROW0__KEY_ROW0 0x1b010 |
| 356 | MX6SL_PAD_KEY_ROW1__KEY_ROW1 0x1b010 |
| 357 | MX6SL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b0 |
| 358 | MX6SL_PAD_KEY_COL0__KEY_COL0 0x110b0 |
| 359 | MX6SL_PAD_KEY_COL1__KEY_COL1 0x110b0 |
| 360 | MX6SL_PAD_KEY_COL2__KEY_COL2 0x110b0 |
| 361 | >; |
| 362 | }; |
| 363 | |
Fabio Estevam | e99b077 | 2014-08-19 15:21:14 -0300 | [diff] [blame] | 364 | pinctrl_lcd: lcdgrp { |
| 365 | fsl,pins = < |
| 366 | MX6SL_PAD_LCD_DAT0__LCD_DATA00 0x1b0b0 |
| 367 | MX6SL_PAD_LCD_DAT1__LCD_DATA01 0x1b0b0 |
| 368 | MX6SL_PAD_LCD_DAT2__LCD_DATA02 0x1b0b0 |
| 369 | MX6SL_PAD_LCD_DAT3__LCD_DATA03 0x1b0b0 |
| 370 | MX6SL_PAD_LCD_DAT4__LCD_DATA04 0x1b0b0 |
| 371 | MX6SL_PAD_LCD_DAT5__LCD_DATA05 0x1b0b0 |
| 372 | MX6SL_PAD_LCD_DAT6__LCD_DATA06 0x1b0b0 |
| 373 | MX6SL_PAD_LCD_DAT7__LCD_DATA07 0x1b0b0 |
| 374 | MX6SL_PAD_LCD_DAT8__LCD_DATA08 0x1b0b0 |
| 375 | MX6SL_PAD_LCD_DAT9__LCD_DATA09 0x1b0b0 |
| 376 | MX6SL_PAD_LCD_DAT10__LCD_DATA10 0x1b0b0 |
| 377 | MX6SL_PAD_LCD_DAT11__LCD_DATA11 0x1b0b0 |
| 378 | MX6SL_PAD_LCD_DAT12__LCD_DATA12 0x1b0b0 |
| 379 | MX6SL_PAD_LCD_DAT13__LCD_DATA13 0x1b0b0 |
| 380 | MX6SL_PAD_LCD_DAT14__LCD_DATA14 0x1b0b0 |
| 381 | MX6SL_PAD_LCD_DAT15__LCD_DATA15 0x1b0b0 |
| 382 | MX6SL_PAD_LCD_DAT16__LCD_DATA16 0x1b0b0 |
| 383 | MX6SL_PAD_LCD_DAT17__LCD_DATA17 0x1b0b0 |
| 384 | MX6SL_PAD_LCD_DAT18__LCD_DATA18 0x1b0b0 |
| 385 | MX6SL_PAD_LCD_DAT19__LCD_DATA19 0x1b0b0 |
| 386 | MX6SL_PAD_LCD_DAT20__LCD_DATA20 0x1b0b0 |
| 387 | MX6SL_PAD_LCD_DAT21__LCD_DATA21 0x1b0b0 |
| 388 | MX6SL_PAD_LCD_DAT22__LCD_DATA22 0x1b0b0 |
| 389 | MX6SL_PAD_LCD_DAT23__LCD_DATA23 0x1b0b0 |
| 390 | MX6SL_PAD_LCD_CLK__LCD_CLK 0x1b0b0 |
| 391 | MX6SL_PAD_LCD_ENABLE__LCD_ENABLE 0x1b0b0 |
| 392 | MX6SL_PAD_LCD_HSYNC__LCD_HSYNC 0x1b0b0 |
| 393 | MX6SL_PAD_LCD_VSYNC__LCD_VSYNC 0x1b0b0 |
| 394 | >; |
| 395 | }; |
| 396 | |
Fabio Estevam | 1bb9dae5 | 2014-08-19 15:21:13 -0300 | [diff] [blame] | 397 | pinctrl_led: ledgrp { |
| 398 | fsl,pins = < |
| 399 | MX6SL_PAD_HSIC_STROBE__GPIO3_IO20 0x17059 |
| 400 | >; |
| 401 | }; |
| 402 | |
Fabio Estevam | e99b077 | 2014-08-19 15:21:14 -0300 | [diff] [blame] | 403 | pinctrl_pwm1: pwmgrp { |
| 404 | fsl,pins = < |
| 405 | MX6SL_PAD_PWM1__PWM1_OUT 0x110b0 |
| 406 | >; |
| 407 | }; |
| 408 | |
Shawn Guo | fffaa65 | 2013-11-04 10:49:04 +0800 | [diff] [blame] | 409 | pinctrl_uart1: uart1grp { |
| 410 | fsl,pins = < |
| 411 | MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1 |
| 412 | MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1 |
| 413 | >; |
| 414 | }; |
| 415 | |
| 416 | pinctrl_usbotg1: usbotg1grp { |
| 417 | fsl,pins = < |
| 418 | MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059 |
| 419 | >; |
| 420 | }; |
| 421 | |
| 422 | pinctrl_usdhc1: usdhc1grp { |
| 423 | fsl,pins = < |
| 424 | MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059 |
| 425 | MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059 |
| 426 | MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059 |
| 427 | MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059 |
| 428 | MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059 |
| 429 | MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059 |
| 430 | MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059 |
| 431 | MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059 |
| 432 | MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059 |
| 433 | MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059 |
| 434 | >; |
| 435 | }; |
| 436 | |
| 437 | pinctrl_usdhc1_100mhz: usdhc1grp100mhz { |
| 438 | fsl,pins = < |
| 439 | MX6SL_PAD_SD1_CMD__SD1_CMD 0x170b9 |
| 440 | MX6SL_PAD_SD1_CLK__SD1_CLK 0x100b9 |
| 441 | MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170b9 |
| 442 | MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170b9 |
| 443 | MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170b9 |
| 444 | MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170b9 |
| 445 | MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170b9 |
| 446 | MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170b9 |
| 447 | MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170b9 |
| 448 | MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9 |
| 449 | >; |
| 450 | }; |
| 451 | |
| 452 | pinctrl_usdhc1_200mhz: usdhc1grp200mhz { |
| 453 | fsl,pins = < |
| 454 | MX6SL_PAD_SD1_CMD__SD1_CMD 0x170f9 |
| 455 | MX6SL_PAD_SD1_CLK__SD1_CLK 0x100f9 |
| 456 | MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 |
| 457 | MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 |
| 458 | MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 |
| 459 | MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 |
| 460 | MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170f9 |
| 461 | MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170f9 |
| 462 | MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170f9 |
| 463 | MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170f9 |
| 464 | >; |
| 465 | }; |
| 466 | |
| 467 | pinctrl_usdhc2: usdhc2grp { |
| 468 | fsl,pins = < |
| 469 | MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059 |
| 470 | MX6SL_PAD_SD2_CLK__SD2_CLK 0x10059 |
| 471 | MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059 |
| 472 | MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059 |
| 473 | MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059 |
| 474 | MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059 |
| 475 | >; |
| 476 | }; |
| 477 | |
| 478 | pinctrl_usdhc2_100mhz: usdhc2grp100mhz { |
| 479 | fsl,pins = < |
| 480 | MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9 |
| 481 | MX6SL_PAD_SD2_CLK__SD2_CLK 0x100b9 |
| 482 | MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 |
| 483 | MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 |
| 484 | MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 |
| 485 | MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 |
| 486 | >; |
| 487 | }; |
| 488 | |
| 489 | pinctrl_usdhc2_200mhz: usdhc2grp200mhz { |
| 490 | fsl,pins = < |
| 491 | MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9 |
| 492 | MX6SL_PAD_SD2_CLK__SD2_CLK 0x100f9 |
| 493 | MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 |
| 494 | MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 |
| 495 | MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 |
| 496 | MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 |
| 497 | >; |
| 498 | }; |
| 499 | |
| 500 | pinctrl_usdhc3: usdhc3grp { |
| 501 | fsl,pins = < |
| 502 | MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059 |
| 503 | MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059 |
| 504 | MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059 |
| 505 | MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059 |
| 506 | MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059 |
| 507 | MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059 |
| 508 | >; |
| 509 | }; |
| 510 | |
| 511 | pinctrl_usdhc3_100mhz: usdhc3grp100mhz { |
| 512 | fsl,pins = < |
| 513 | MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9 |
| 514 | MX6SL_PAD_SD3_CLK__SD3_CLK 0x100b9 |
| 515 | MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 |
| 516 | MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 |
| 517 | MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 |
| 518 | MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 |
| 519 | >; |
| 520 | }; |
| 521 | |
| 522 | pinctrl_usdhc3_200mhz: usdhc3grp200mhz { |
| 523 | fsl,pins = < |
| 524 | MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9 |
| 525 | MX6SL_PAD_SD3_CLK__SD3_CLK 0x100f9 |
| 526 | MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 |
| 527 | MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 |
| 528 | MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 |
| 529 | MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 |
| 530 | >; |
| 531 | }; |
Shawn Guo | 117ccd55 | 2013-05-03 11:28:42 +0800 | [diff] [blame] | 532 | }; |
| 533 | }; |
| 534 | |
Anson Huang | 4291b64 | 2014-01-14 17:30:28 +0800 | [diff] [blame] | 535 | &kpp { |
| 536 | pinctrl-names = "default"; |
| 537 | pinctrl-0 = <&pinctrl_kpp>; |
| 538 | linux,keymap = < |
| 539 | MATRIX_KEY(0x0, 0x0, KEY_UP) /* ROW0, COL0 */ |
| 540 | MATRIX_KEY(0x0, 0x1, KEY_DOWN) /* ROW0, COL1 */ |
| 541 | MATRIX_KEY(0x0, 0x2, KEY_ENTER) /* ROW0, COL2 */ |
| 542 | MATRIX_KEY(0x1, 0x0, KEY_HOME) /* ROW1, COL0 */ |
| 543 | MATRIX_KEY(0x1, 0x1, KEY_RIGHT) /* ROW1, COL1 */ |
| 544 | MATRIX_KEY(0x1, 0x2, KEY_LEFT) /* ROW1, COL2 */ |
| 545 | MATRIX_KEY(0x2, 0x0, KEY_VOLUMEDOWN) /* ROW2, COL0 */ |
| 546 | MATRIX_KEY(0x2, 0x1, KEY_VOLUMEUP) /* ROW2, COL1 */ |
| 547 | >; |
| 548 | status = "okay"; |
| 549 | }; |
| 550 | |
Fabio Estevam | e99b077 | 2014-08-19 15:21:14 -0300 | [diff] [blame] | 551 | &lcdif { |
| 552 | pinctrl-names = "default"; |
| 553 | pinctrl-0 = <&pinctrl_lcd>; |
Fabio Estevam | e99b077 | 2014-08-19 15:21:14 -0300 | [diff] [blame] | 554 | status = "okay"; |
| 555 | |
Marco Franchi | 4d9a387 | 2017-12-06 13:15:19 -0200 | [diff] [blame] | 556 | port { |
| 557 | display_out: endpoint { |
| 558 | remote-endpoint = <&panel_in>; |
Fabio Estevam | e99b077 | 2014-08-19 15:21:14 -0300 | [diff] [blame] | 559 | }; |
| 560 | }; |
| 561 | }; |
| 562 | |
| 563 | &pwm1 { |
| 564 | pinctrl-names = "default"; |
| 565 | pinctrl-0 = <&pinctrl_pwm1>; |
| 566 | status = "okay"; |
| 567 | }; |
| 568 | |
Robin Gong | 422b067 | 2014-11-12 16:20:37 +0800 | [diff] [blame] | 569 | &snvs_poweroff { |
| 570 | status = "okay"; |
| 571 | }; |
| 572 | |
Fabio Estevam | 032de43 | 2014-02-06 08:57:51 -0200 | [diff] [blame] | 573 | &ssi2 { |
Fabio Estevam | 032de43 | 2014-02-06 08:57:51 -0200 | [diff] [blame] | 574 | status = "okay"; |
| 575 | }; |
| 576 | |
Shawn Guo | 117ccd55 | 2013-05-03 11:28:42 +0800 | [diff] [blame] | 577 | &uart1 { |
| 578 | pinctrl-names = "default"; |
Shawn Guo | fffaa65 | 2013-11-04 10:49:04 +0800 | [diff] [blame] | 579 | pinctrl-0 = <&pinctrl_uart1>; |
Shawn Guo | 117ccd55 | 2013-05-03 11:28:42 +0800 | [diff] [blame] | 580 | status = "okay"; |
| 581 | }; |
| 582 | |
Peter Chen | 6022232 | 2013-09-10 10:23:16 +0800 | [diff] [blame] | 583 | &usbotg1 { |
| 584 | vbus-supply = <®_usb_otg1_vbus>; |
| 585 | pinctrl-names = "default"; |
Shawn Guo | fffaa65 | 2013-11-04 10:49:04 +0800 | [diff] [blame] | 586 | pinctrl-0 = <&pinctrl_usbotg1>; |
Peter Chen | 6022232 | 2013-09-10 10:23:16 +0800 | [diff] [blame] | 587 | disable-over-current; |
| 588 | status = "okay"; |
| 589 | }; |
| 590 | |
| 591 | &usbotg2 { |
| 592 | vbus-supply = <®_usb_otg2_vbus>; |
| 593 | dr_mode = "host"; |
| 594 | disable-over-current; |
| 595 | status = "okay"; |
| 596 | }; |
| 597 | |
Shawn Guo | 117ccd55 | 2013-05-03 11:28:42 +0800 | [diff] [blame] | 598 | &usdhc1 { |
Dong Aisheng | fa87dfd | 2013-10-09 19:20:07 +0800 | [diff] [blame] | 599 | pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
Shawn Guo | fffaa65 | 2013-11-04 10:49:04 +0800 | [diff] [blame] | 600 | pinctrl-0 = <&pinctrl_usdhc1>; |
| 601 | pinctrl-1 = <&pinctrl_usdhc1_100mhz>; |
| 602 | pinctrl-2 = <&pinctrl_usdhc1_200mhz>; |
Shawn Guo | 117ccd55 | 2013-05-03 11:28:42 +0800 | [diff] [blame] | 603 | bus-width = <8>; |
Dong Aisheng | 89c1a8cf | 2015-07-22 20:53:02 +0800 | [diff] [blame] | 604 | cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; |
| 605 | wp-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; |
Shawn Guo | 117ccd55 | 2013-05-03 11:28:42 +0800 | [diff] [blame] | 606 | status = "okay"; |
| 607 | }; |
| 608 | |
| 609 | &usdhc2 { |
Dong Aisheng | fa87dfd | 2013-10-09 19:20:07 +0800 | [diff] [blame] | 610 | pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
Shawn Guo | fffaa65 | 2013-11-04 10:49:04 +0800 | [diff] [blame] | 611 | pinctrl-0 = <&pinctrl_usdhc2>; |
| 612 | pinctrl-1 = <&pinctrl_usdhc2_100mhz>; |
| 613 | pinctrl-2 = <&pinctrl_usdhc2_200mhz>; |
Dong Aisheng | 89c1a8cf | 2015-07-22 20:53:02 +0800 | [diff] [blame] | 614 | cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; |
| 615 | wp-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; |
Shawn Guo | 117ccd55 | 2013-05-03 11:28:42 +0800 | [diff] [blame] | 616 | status = "okay"; |
| 617 | }; |
| 618 | |
| 619 | &usdhc3 { |
Dong Aisheng | fa87dfd | 2013-10-09 19:20:07 +0800 | [diff] [blame] | 620 | pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
Shawn Guo | fffaa65 | 2013-11-04 10:49:04 +0800 | [diff] [blame] | 621 | pinctrl-0 = <&pinctrl_usdhc3>; |
| 622 | pinctrl-1 = <&pinctrl_usdhc3_100mhz>; |
| 623 | pinctrl-2 = <&pinctrl_usdhc3_200mhz>; |
Dong Aisheng | 89c1a8cf | 2015-07-22 20:53:02 +0800 | [diff] [blame] | 624 | cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; |
Shawn Guo | 117ccd55 | 2013-05-03 11:28:42 +0800 | [diff] [blame] | 625 | status = "okay"; |
| 626 | }; |