blob: 8ece4f531006038b2b85a1d15a8e15f501ea89a7 [file] [log] [blame]
Tomi Valkeinen559d6702009-11-03 11:23:50 +02001/*
2 * linux/drivers/video/omap2/dss/dss.h
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#ifndef __OMAP2_DSS_H
24#define __OMAP2_DSS_H
25
Tomi Valkeinen96e2e632012-10-10 15:55:19 +030026#include <linux/interrupt.h>
27
Chandrabhanu Mahapatra702d2672012-09-24 17:12:58 +053028#ifdef pr_fmt
29#undef pr_fmt
Tomi Valkeinen559d6702009-11-03 11:23:50 +020030#endif
31
32#ifdef DSS_SUBSYS_NAME
Chandrabhanu Mahapatra702d2672012-09-24 17:12:58 +053033#define pr_fmt(fmt) DSS_SUBSYS_NAME ": " fmt
Tomi Valkeinen559d6702009-11-03 11:23:50 +020034#else
Chandrabhanu Mahapatra702d2672012-09-24 17:12:58 +053035#define pr_fmt(fmt) fmt
Tomi Valkeinen559d6702009-11-03 11:23:50 +020036#endif
37
Chandrabhanu Mahapatra702d2672012-09-24 17:12:58 +053038#define DSSDBG(format, ...) \
39 pr_debug(format, ## __VA_ARGS__)
Tomi Valkeinen559d6702009-11-03 11:23:50 +020040
41#ifdef DSS_SUBSYS_NAME
42#define DSSERR(format, ...) \
43 printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \
44 ## __VA_ARGS__)
45#else
46#define DSSERR(format, ...) \
47 printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__)
48#endif
49
50#ifdef DSS_SUBSYS_NAME
51#define DSSINFO(format, ...) \
52 printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \
53 ## __VA_ARGS__)
54#else
55#define DSSINFO(format, ...) \
56 printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__)
57#endif
58
59#ifdef DSS_SUBSYS_NAME
60#define DSSWARN(format, ...) \
61 printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \
62 ## __VA_ARGS__)
63#else
64#define DSSWARN(format, ...) \
65 printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__)
66#endif
67
68/* OMAP TRM gives bitfields as start:end, where start is the higher bit
69 number. For example 7:0 */
70#define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
71#define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
72#define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
73#define FLD_MOD(orig, val, start, end) \
74 (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
75
Archit Taneja569969d2011-08-22 17:41:57 +053076enum dss_io_pad_mode {
77 DSS_IO_PAD_MODE_RESET,
78 DSS_IO_PAD_MODE_RFBI,
79 DSS_IO_PAD_MODE_BYPASS,
Tomi Valkeinen559d6702009-11-03 11:23:50 +020080};
81
Mythri P K7ed024a2011-03-09 16:31:38 +053082enum dss_hdmi_venc_clk_source_select {
83 DSS_VENC_TV_CLK = 0,
84 DSS_HDMI_M_PCLK = 1,
85};
86
Archit Taneja6ff8aa32011-08-25 18:35:58 +053087enum dss_dsi_content_type {
88 DSS_DSI_CONTENT_DCS,
89 DSS_DSI_CONTENT_GENERIC,
90};
91
Archit Tanejad9ac7732012-09-22 12:38:19 +053092enum dss_writeback_channel {
93 DSS_WB_LCD1_MGR = 0,
94 DSS_WB_LCD2_MGR = 1,
95 DSS_WB_TV_MGR = 2,
96 DSS_WB_OVL0 = 3,
97 DSS_WB_OVL1 = 4,
98 DSS_WB_OVL2 = 5,
99 DSS_WB_OVL3 = 6,
100 DSS_WB_LCD3_MGR = 7,
101};
102
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200103struct dispc_clock_info {
104 /* rates that we get with dividers below */
105 unsigned long lck;
106 unsigned long pck;
107
108 /* dividers */
109 u16 lck_div;
110 u16 pck_div;
111};
112
113struct dsi_clock_info {
114 /* rates that we get with dividers below */
115 unsigned long fint;
116 unsigned long clkin4ddr;
117 unsigned long clkin;
Taneja, Architea751592011-03-08 05:50:35 -0600118 unsigned long dsi_pll_hsdiv_dispc_clk; /* OMAP3: DSI1_PLL_CLK
119 * OMAP4: PLLx_CLK1 */
120 unsigned long dsi_pll_hsdiv_dsi_clk; /* OMAP3: DSI2_PLL_CLK
121 * OMAP4: PLLx_CLK2 */
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200122 unsigned long lp_clk;
123
124 /* dividers */
125 u16 regn;
126 u16 regm;
Taneja, Architea751592011-03-08 05:50:35 -0600127 u16 regm_dispc; /* OMAP3: REGM3
128 * OMAP4: REGM4 */
129 u16 regm_dsi; /* OMAP3: REGM4
130 * OMAP4: REGM5 */
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200131 u16 lp_clk_div;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200132};
133
Chandrabhanu Mahapatraefa70b32012-06-21 11:07:44 +0530134struct reg_field {
135 u16 reg;
136 u8 high;
137 u8 low;
138};
139
Archit Tanejac56fb3e2012-06-29 14:03:48 +0530140struct dss_lcd_mgr_config {
141 enum dss_io_pad_mode io_pad_mode;
142
143 bool stallmode;
144 bool fifohandcheck;
145
146 struct dispc_clock_info clock_info;
147
148 int video_port_width;
149
150 int lcden_sig_polarity;
151};
152
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200153struct seq_file;
154struct platform_device;
155
156/* core */
Tomi Valkeinen8f46efa2012-10-10 10:46:06 +0300157struct platform_device *dss_get_core_pdev(void);
Tomi Valkeinen00928ea2012-02-20 11:50:06 +0200158int dss_dsi_enable_pads(int dsi_id, unsigned lane_mask);
159void dss_dsi_disable_pads(int dsi_id, unsigned lane_mask);
Tomi Valkeinena8081d32012-03-08 12:52:38 +0200160int dss_set_min_bus_tput(struct device *dev, unsigned long tput);
Tomi Valkeinene40402c2012-03-02 18:01:07 +0200161int dss_debugfs_create_file(const char *name, void (*write)(struct seq_file *));
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200162
163/* display */
164int dss_suspend_all_devices(void);
165int dss_resume_all_devices(void);
166void dss_disable_all_devices(void);
167
Tomi Valkeinen94140f02013-02-13 13:40:19 +0200168int display_init_sysfs(struct platform_device *pdev);
169void display_uninit_sysfs(struct platform_device *pdev);
Tomi Valkeinen3f30b8c2012-11-08 13:13:02 +0200170
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200171/* manager */
Tomi Valkeinen7f7cdbd2013-05-14 10:53:21 +0300172int dss_init_overlay_managers(void);
173void dss_uninit_overlay_managers(void);
174int dss_init_overlay_managers_sysfs(struct platform_device *pdev);
175void dss_uninit_overlay_managers_sysfs(struct platform_device *pdev);
Tomi Valkeinen54540d42011-12-13 13:18:52 +0200176int dss_mgr_simple_check(struct omap_overlay_manager *mgr,
177 const struct omap_overlay_manager_info *info);
Archit Tanejab917fa32012-04-27 01:07:28 +0530178int dss_mgr_check_timings(struct omap_overlay_manager *mgr,
179 const struct omap_video_timings *timings);
Tomi Valkeinen6ac48d12011-12-08 10:32:37 +0200180int dss_mgr_check(struct omap_overlay_manager *mgr,
Tomi Valkeinen6ac48d12011-12-08 10:32:37 +0200181 struct omap_overlay_manager_info *info,
Archit Taneja228b2132012-04-27 01:22:28 +0530182 const struct omap_video_timings *mgr_timings,
Archit Taneja6e543592012-05-23 17:01:35 +0530183 const struct dss_lcd_mgr_config *config,
Tomi Valkeinen6ac48d12011-12-08 10:32:37 +0200184 struct omap_overlay_info **overlay_infos);
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200185
Archit Tanejaf476ae92012-06-29 14:37:03 +0530186static inline bool dss_mgr_is_lcd(enum omap_channel id)
187{
188 if (id == OMAP_DSS_CHANNEL_LCD || id == OMAP_DSS_CHANNEL_LCD2 ||
189 id == OMAP_DSS_CHANNEL_LCD3)
190 return true;
191 else
192 return false;
193}
194
Tomi Valkeinenf6a04922012-08-06 14:44:09 +0300195int dss_manager_kobj_init(struct omap_overlay_manager *mgr,
196 struct platform_device *pdev);
197void dss_manager_kobj_uninit(struct omap_overlay_manager *mgr);
198
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200199/* overlay */
200void dss_init_overlays(struct platform_device *pdev);
201void dss_uninit_overlays(struct platform_device *pdev);
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200202void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr);
Tomi Valkeinen54540d42011-12-13 13:18:52 +0200203int dss_ovl_simple_check(struct omap_overlay *ovl,
204 const struct omap_overlay_info *info);
Archit Taneja228b2132012-04-27 01:22:28 +0530205int dss_ovl_check(struct omap_overlay *ovl, struct omap_overlay_info *info,
206 const struct omap_video_timings *mgr_timings);
Archit Taneja6c6f5102012-06-25 14:58:48 +0530207bool dss_ovl_use_replication(struct dss_lcd_mgr_config config,
208 enum omap_color_mode mode);
Tomi Valkeinen91691512012-08-06 14:40:00 +0300209int dss_overlay_kobj_init(struct omap_overlay *ovl,
210 struct platform_device *pdev);
211void dss_overlay_kobj_uninit(struct omap_overlay *ovl);
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200212
213/* DSS */
Tomi Valkeinen6e7e8f02012-02-17 17:41:13 +0200214int dss_init_platform_driver(void) __init;
Senthilvadivu Guruswamy96c401b2011-01-24 06:21:57 +0000215void dss_uninit_platform_driver(void);
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200216
Tomi Valkeinen5aaee692012-12-12 10:37:03 +0200217unsigned long dss_get_dispc_clk_rate(void);
Tomi Valkeinende09e452012-09-21 12:09:54 +0300218int dss_dpi_select_source(enum omap_channel channel);
Mythri P K7ed024a2011-03-09 16:31:38 +0530219void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select);
Tomi Valkeinen4a61e262011-08-31 14:33:31 +0300220enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void);
Archit Taneja89a35e52011-04-12 13:52:23 +0530221const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src);
Senthilvadivu Guruswamy8b9cb3a2011-01-24 06:21:58 +0000222void dss_dump_clocks(struct seq_file *s);
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200223
Chandrabhanu Mahapatra1b3bcb32012-09-29 11:25:42 +0530224#if defined(CONFIG_OMAP2_DSS_DEBUGFS)
Senthilvadivu Guruswamy8b9cb3a2011-01-24 06:21:58 +0000225void dss_debug_dump_clocks(struct seq_file *s);
226#endif
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200227
Archit Tanejabdb736a2012-11-28 17:01:39 +0530228int dss_get_ctx_loss_count(void);
229
Archit Taneja889b4fd2012-07-20 17:18:49 +0530230void dss_sdi_init(int datapairs);
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200231int dss_sdi_enable(void);
232void dss_sdi_disable(void);
233
Archit Taneja5a8b5722011-05-12 17:26:29 +0530234void dss_select_dsi_clk_source(int dsi_module,
235 enum omap_dss_clk_source clk_src);
Taneja, Architea751592011-03-08 05:50:35 -0600236void dss_select_lcd_clk_source(enum omap_channel channel,
Archit Taneja89a35e52011-04-12 13:52:23 +0530237 enum omap_dss_clk_source clk_src);
238enum omap_dss_clk_source dss_get_dispc_clk_source(void);
Archit Taneja5a8b5722011-05-12 17:26:29 +0530239enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module);
Archit Taneja89a35e52011-04-12 13:52:23 +0530240enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel);
Tomi Valkeinen2f18c4d2010-01-08 18:00:36 +0200241
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200242void dss_set_venc_output(enum omap_dss_venc_type type);
243void dss_set_dac_pwrdn_bgz(bool enable);
244
Tomi Valkeinend0f58bd2013-10-31 14:44:23 +0200245int dss_set_fck_rate(unsigned long rate);
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200246
Tomi Valkeinend0f58bd2013-10-31 14:44:23 +0200247typedef bool (*dss_div_calc_func)(unsigned long fck, void *data);
Tomi Valkeinen688af022013-10-31 16:41:57 +0200248bool dss_div_calc(unsigned long pck, unsigned long fck_min,
249 dss_div_calc_func func, void *data);
Tomi Valkeinen43417822013-03-05 16:34:05 +0200250
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200251/* SDI */
Tomi Valkeinen6e7e8f02012-02-17 17:41:13 +0200252int sdi_init_platform_driver(void) __init;
253void sdi_uninit_platform_driver(void) __exit;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200254
Tomi Valkeinen2ecef242013-12-16 15:13:24 +0200255int sdi_init_port(struct platform_device *pdev, struct device_node *port) __init;
256void sdi_uninit_port(void) __exit;
257
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200258/* DSI */
Tomi Valkeinen989c79a2013-04-18 12:16:39 +0300259
260typedef bool (*dsi_pll_calc_func)(int regn, int regm, unsigned long fint,
261 unsigned long pll, void *data);
262typedef bool (*dsi_hsdiv_calc_func)(int regm_dispc, unsigned long dispc,
263 void *data);
264
Jani Nikula368a1482010-05-07 11:58:41 +0200265#ifdef CONFIG_OMAP2_DSS_DSI
Archit Taneja5a8b5722011-05-12 17:26:29 +0530266
267struct dentry;
268struct file_operations;
269
Tomi Valkeinen6e7e8f02012-02-17 17:41:13 +0200270int dsi_init_platform_driver(void) __init;
271void dsi_uninit_platform_driver(void) __exit;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200272
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +0300273int dsi_runtime_get(struct platform_device *dsidev);
274void dsi_runtime_put(struct platform_device *dsidev);
275
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200276void dsi_dump_clocks(struct seq_file *s);
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200277
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200278void dsi_irq_handler(void);
Archit Tanejaa3b3cc22011-09-08 18:42:16 +0530279u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt);
280
Tomi Valkeinen72658f02013-03-05 16:39:00 +0200281unsigned long dsi_get_pll_clkin(struct platform_device *dsidev);
282
Tomi Valkeinen72658f02013-03-05 16:39:00 +0200283bool dsi_hsdiv_calc(struct platform_device *dsidev, unsigned long pll,
284 unsigned long out_min, dsi_hsdiv_calc_func func, void *data);
285bool dsi_pll_calc(struct platform_device *dsidev, unsigned long clkin,
286 unsigned long pll_min, unsigned long pll_max,
287 dsi_pll_calc_func func, void *data);
288
Archit Tanejaa72b64b2011-05-12 17:26:26 +0530289unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev);
290int dsi_pll_set_clock_div(struct platform_device *dsidev,
291 struct dsi_clock_info *cinfo);
Archit Tanejaa72b64b2011-05-12 17:26:26 +0530292int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
293 bool enable_hsdiv);
294void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes);
Archit Tanejaa72b64b2011-05-12 17:26:26 +0530295void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev);
296void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev);
297struct platform_device *dsi_get_dsidev_from_id(int module);
Jani Nikula368a1482010-05-07 11:58:41 +0200298#else
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +0300299static inline int dsi_runtime_get(struct platform_device *dsidev)
300{
301 return 0;
302}
303static inline void dsi_runtime_put(struct platform_device *dsidev)
304{
305}
Archit Tanejaa3b3cc22011-09-08 18:42:16 +0530306static inline u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
307{
308 WARN("%s: DSI not compiled in, returning pixel_size as 0\n", __func__);
309 return 0;
310}
Archit Tanejaa72b64b2011-05-12 17:26:26 +0530311static inline unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
Taneja, Archit66534e82011-03-08 05:50:34 -0600312{
313 WARN("%s: DSI not compiled in, returning rate as 0\n", __func__);
314 return 0;
315}
Tomi Valkeinen943e4452011-04-30 15:38:15 +0300316static inline int dsi_pll_set_clock_div(struct platform_device *dsidev,
317 struct dsi_clock_info *cinfo)
318{
319 WARN("%s: DSI not compiled in\n", __func__);
320 return -ENODEV;
321}
Tomi Valkeinen943e4452011-04-30 15:38:15 +0300322static inline int dsi_pll_init(struct platform_device *dsidev,
323 bool enable_hsclk, bool enable_hsdiv)
324{
325 WARN("%s: DSI not compiled in\n", __func__);
326 return -ENODEV;
327}
328static inline void dsi_pll_uninit(struct platform_device *dsidev,
329 bool disconnect_lanes)
330{
331}
Archit Tanejaa72b64b2011-05-12 17:26:26 +0530332static inline void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev)
Tomi Valkeinene406f902010-06-09 15:28:12 +0300333{
334}
Archit Tanejaa72b64b2011-05-12 17:26:26 +0530335static inline void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev)
Tomi Valkeinene406f902010-06-09 15:28:12 +0300336{
337}
Archit Tanejaa72b64b2011-05-12 17:26:26 +0530338static inline struct platform_device *dsi_get_dsidev_from_id(int module)
339{
Archit Tanejaa72b64b2011-05-12 17:26:26 +0530340 return NULL;
341}
Tomi Valkeinen989c79a2013-04-18 12:16:39 +0300342
343static inline unsigned long dsi_get_pll_clkin(struct platform_device *dsidev)
344{
345 return 0;
346}
347
348static inline bool dsi_hsdiv_calc(struct platform_device *dsidev,
349 unsigned long pll, unsigned long out_min,
350 dsi_hsdiv_calc_func func, void *data)
351{
352 return false;
353}
354
355static inline bool dsi_pll_calc(struct platform_device *dsidev,
356 unsigned long clkin,
357 unsigned long pll_min, unsigned long pll_max,
358 dsi_pll_calc_func func, void *data)
359{
360 return false;
361}
362
Jani Nikula368a1482010-05-07 11:58:41 +0200363#endif
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200364
365/* DPI */
Tomi Valkeinen6e7e8f02012-02-17 17:41:13 +0200366int dpi_init_platform_driver(void) __init;
367void dpi_uninit_platform_driver(void) __exit;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200368
Tomi Valkeinen2ecef242013-12-16 15:13:24 +0200369int dpi_init_port(struct platform_device *pdev, struct device_node *port) __init;
370void dpi_uninit_port(void) __exit;
371
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200372/* DISPC */
Tomi Valkeinen6e7e8f02012-02-17 17:41:13 +0200373int dispc_init_platform_driver(void) __init;
374void dispc_uninit_platform_driver(void) __exit;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200375void dispc_dump_clocks(struct seq_file *s);
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200376
377void dispc_enable_sidle(void);
378void dispc_disable_sidle(void);
379
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200380void dispc_lcd_enable_signal(bool enable);
381void dispc_pck_free_enable(bool enable);
Tomi Valkeinencd295ae2011-08-16 13:49:15 +0300382void dispc_enable_fifomerge(bool enable);
383void dispc_enable_gamma_table(bool enable);
384void dispc_set_loadmode(enum omap_dss_load_mode mode);
385
Tomi Valkeinen7c284e62013-03-05 16:32:08 +0200386typedef bool (*dispc_div_calc_func)(int lckd, int pckd, unsigned long lck,
387 unsigned long pck, void *data);
388bool dispc_div_calc(unsigned long dispc,
389 unsigned long pck_min, unsigned long pck_max,
390 dispc_div_calc_func func, void *data);
391
Archit Taneja8f366162012-04-16 12:53:44 +0530392bool dispc_mgr_timings_ok(enum omap_channel channel,
Archit Tanejab917fa32012-04-27 01:07:28 +0530393 const struct omap_video_timings *timings);
Tomi Valkeinencd295ae2011-08-16 13:49:15 +0300394unsigned long dispc_fclk_rate(void);
Tomi Valkeinencd295ae2011-08-16 13:49:15 +0300395int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
396 struct dispc_clock_info *cinfo);
397
398
Tomi Valkeinen6f04e1b2011-10-31 08:58:52 +0200399void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high);
Tomi Valkeinen83fa2f22012-01-13 13:17:01 +0200400void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
Tomi Valkeinen3568f2a2012-05-15 15:31:01 +0300401 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
402 bool manual_update);
Tomi Valkeinencd295ae2011-08-16 13:49:15 +0300403
Tomi Valkeinencd295ae2011-08-16 13:49:15 +0300404unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
405unsigned long dispc_mgr_pclk_rate(enum omap_channel channel);
Chandrabhanu Mahapatra8b53d992012-04-23 12:16:50 +0530406unsigned long dispc_core_clk_rate(void);
Archit Tanejaf0d08f82012-06-29 14:00:54 +0530407void dispc_mgr_set_clock_div(enum omap_channel channel,
Tomi Valkeinena8f3fcd2012-10-03 09:09:11 +0200408 const struct dispc_clock_info *cinfo);
Tomi Valkeinen26d9dd02011-08-16 13:45:15 +0300409int dispc_mgr_get_clock_div(enum omap_channel channel,
Sumit Semwalff1b2cd2010-12-02 11:27:11 +0000410 struct dispc_clock_info *cinfo);
Tomi Valkeinen5391e872013-05-16 10:44:13 +0300411void dispc_set_tv_pclk(unsigned long pclk);
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200412
Archit Taneja0b23e5b2012-09-22 12:39:33 +0530413u32 dispc_wb_get_framedone_irq(void);
414bool dispc_wb_go_busy(void);
415void dispc_wb_go(void);
416void dispc_wb_enable(bool enable);
417bool dispc_wb_is_enabled(void);
Archit Tanejad9ac7732012-09-22 12:38:19 +0530418void dispc_wb_set_channel_in(enum dss_writeback_channel channel);
Archit Taneja749feff2012-08-31 12:32:52 +0530419int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
Archit Taneja9e4a0fc2012-08-24 16:59:26 +0530420 bool mem_to_mem, const struct omap_video_timings *timings);
Archit Tanejad9ac7732012-09-22 12:38:19 +0530421
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200422/* VENC */
Tomi Valkeinen6e7e8f02012-02-17 17:41:13 +0200423int venc_init_platform_driver(void) __init;
424void venc_uninit_platform_driver(void) __exit;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200425
Mythri P Kc3198a52011-03-12 12:04:27 +0530426/* HDMI */
Archit Tanejaef269582013-09-12 17:45:57 +0530427int hdmi4_init_platform_driver(void) __init;
428void hdmi4_uninit_platform_driver(void) __exit;
Mythri P Kc3198a52011-03-12 12:04:27 +0530429
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200430/* RFBI */
Tomi Valkeinen6e7e8f02012-02-17 17:41:13 +0200431int rfbi_init_platform_driver(void) __init;
432void rfbi_uninit_platform_driver(void) __exit;
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200433
Tomi Valkeinendfc0fd82009-12-17 14:35:21 +0200434
435#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
436static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr)
437{
438 int b;
439 for (b = 0; b < 32; ++b) {
440 if (irqstatus & (1 << b))
441 irq_arr[b]++;
442 }
443}
444#endif
445
Tomi Valkeinen559d6702009-11-03 11:23:50 +0200446#endif