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gerrit-public.fairphone.software / kernel / msm-5.4 / 302e01b266c56e3faac2e19fe5fb8e43abf5bb94 / . / arch / arm / boot / dts / imx6ul.dtsi
blob: 7e27d76a2d5db1258757666bc5b8f9946feb7c66 [file] [log] [blame]
Frank Lia5fcccb2015-07-10 02:09:45 +0800[diff] [blame]1/*
2 * Copyright 2015 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <dt-bindings/clock/imx6ul-clock.h>
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12#include "imx6ul-pinfunc.h"
13#include "skeleton.dtsi"
14
15/ {
16 aliases {
Fugang Duan01f3dc72015-07-28 15:30:41 +0800[diff] [blame]17 ethernet0 = &fec1;
18 ethernet1 = &fec2;
Frank Lia5fcccb2015-07-10 02:09:45 +0800[diff] [blame]19 gpio0 = &gpio1;
20 gpio1 = &gpio2;
21 gpio2 = &gpio3;
22 gpio3 = &gpio4;
23 gpio4 = &gpio5;
24 i2c0 = &i2c1;
25 i2c1 = &i2c2;
26 i2c2 = &i2c3;
27 i2c3 = &i2c4;
28 mmc0 = &usdhc1;
29 mmc1 = &usdhc2;
30 serial0 = &uart1;
31 serial1 = &uart2;
32 serial2 = &uart3;
33 serial3 = &uart4;
34 serial4 = &uart5;
35 serial5 = &uart6;
36 serial6 = &uart7;
37 serial7 = &uart8;
38 spi0 = &ecspi1;
39 spi1 = &ecspi2;
40 spi2 = &ecspi3;
41 spi3 = &ecspi4;
42 usbphy0 = &usbphy1;
43 usbphy1 = &usbphy2;
44 };
45
46 cpus {
47 #address-cells = <1>;
48 #size-cells = <0>;
49
50 cpu0: cpu@0 {
51 compatible = "arm,cortex-a7";
52 device_type = "cpu";
53 reg = <0>;
54 clock-latency = <61036>; /* two CLK32 periods */
55 operating-points = <
56 /* kHz uV */
57 528000 1250000
58 396000 1150000
59 198000 1150000
60 >;
61 fsl,soc-operating-points = <
62 /* KHz uV */
63 528000 1250000
64 396000 1150000
65 198000 1150000
66 >;
67 clocks = <&clks IMX6UL_CLK_ARM>,
68 <&clks IMX6UL_CLK_PLL2_BUS>,
69 <&clks IMX6UL_CLK_PLL2_PFD2>,
70 <&clks IMX6UL_CA7_SECONDARY_SEL>,
71 <&clks IMX6UL_CLK_STEP>,
72 <&clks IMX6UL_CLK_PLL1_SW>,
73 <&clks IMX6UL_CLK_PLL1_SYS>,
74 <&clks IMX6UL_PLL1_BYPASS>,
75 <&clks IMX6UL_CLK_PLL1>,
76 <&clks IMX6UL_PLL1_BYPASS_SRC>,
77 <&clks IMX6UL_CLK_OSC>;
78 clock-names = "arm", "pll2_bus", "pll2_pfd2_396m",
79 "secondary_sel", "step", "pll1_sw",
80 "pll1_sys", "pll1_bypass", "pll1",
81 "pll1_bypass_src", "osc";
82 arm-supply = <&reg_arm>;
83 soc-supply = <&reg_soc>;
84 };
85 };
86
87 intc: interrupt-controller@00a01000 {
88 compatible = "arm,cortex-a7-gic";
89 #interrupt-cells = <3>;
90 interrupt-controller;
91 reg = <0x00a01000 0x1000>,
92 <0x00a02000 0x1000>,
93 <0x00a04000 0x2000>,
94 <0x00a06000 0x2000>;
95 };
96
97 ckil: clock-cli {
98 compatible = "fixed-clock";
99 #clock-cells = <0>;
100 clock-frequency = <32768>;
101 clock-output-names = "ckil";
102 };
103
104 osc: clock-osc {
105 compatible = "fixed-clock";
106 #clock-cells = <0>;
107 clock-frequency = <24000000>;
108 clock-output-names = "osc";
109 };
110
111 ipp_di0: clock-di0 {
112 compatible = "fixed-clock";
113 #clock-cells = <0>;
114 clock-frequency = <0>;
115 clock-output-names = "ipp_di0";
116 };
117
118 ipp_di1: clock-di1 {
119 compatible = "fixed-clock";
120 #clock-cells = <0>;
121 clock-frequency = <0>;
122 clock-output-names = "ipp_di1";
123 };
124
125 soc {
126 #address-cells = <1>;
127 #size-cells = <1>;
128 compatible = "simple-bus";
Anson Huang18619ff2015-08-04 01:12:12 +0800[diff] [blame]129 interrupt-parent = <&gpc>;
Frank Lia5fcccb2015-07-10 02:09:45 +0800[diff] [blame]130 ranges;
131
132 pmu {
133 compatible = "arm,cortex-a7-pmu";
134 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
135 status = "disabled";
136 };
137
Anson Huang322d09d2015-08-05 01:48:35 +0800[diff] [blame]138 ocram: sram@00900000 {
139 compatible = "mmio-sram";
140 reg = <0x00900000 0x20000>;
141 };
142
Frank Lia5fcccb2015-07-10 02:09:45 +0800[diff] [blame]143 aips1: aips-bus@02000000 {
144 compatible = "fsl,aips-bus", "simple-bus";
145 #address-cells = <1>;
146 #size-cells = <1>;
147 reg = <0x02000000 0x100000>;
148 ranges;
149
150 spba-bus@02000000 {
151 compatible = "fsl,spba-bus", "simple-bus";
152 #address-cells = <1>;
153 #size-cells = <1>;
154 reg = <0x02000000 0x40000>;
155 ranges;
156
157 ecspi1: ecspi@02008000 {
158 #address-cells = <1>;
159 #size-cells = <0>;
160 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
161 reg = <0x02008000 0x4000>;
162 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
163 clocks = <&clks IMX6UL_CLK_ECSPI1>,
164 <&clks IMX6UL_CLK_ECSPI1>;
165 clock-names = "ipg", "per";
166 status = "disabled";
167 };
168
169 ecspi2: ecspi@0200c000 {
170 #address-cells = <1>;
171 #size-cells = <0>;
172 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
173 reg = <0x0200c000 0x4000>;
174 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
175 clocks = <&clks IMX6UL_CLK_ECSPI2>,
176 <&clks IMX6UL_CLK_ECSPI2>;
177 clock-names = "ipg", "per";
178 status = "disabled";
179 };
180
181 ecspi3: ecspi@02010000 {
182 #address-cells = <1>;
183 #size-cells = <0>;
184 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
185 reg = <0x02010000 0x4000>;
186 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
187 clocks = <&clks IMX6UL_CLK_ECSPI3>,
188 <&clks IMX6UL_CLK_ECSPI3>;
189 clock-names = "ipg", "per";
190 status = "disabled";
191 };
192
193 ecspi4: ecspi@02014000 {
194 #address-cells = <1>;
195 #size-cells = <0>;
196 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
197 reg = <0x02014000 0x4000>;
198 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
199 clocks = <&clks IMX6UL_CLK_ECSPI4>,
200 <&clks IMX6UL_CLK_ECSPI4>;
201 clock-names = "ipg", "per";
202 status = "disabled";
203 };
204
205 uart7: serial@02018000 {
206 compatible = "fsl,imx6ul-uart",
207 "fsl,imx6q-uart";
208 reg = <0x02018000 0x4000>;
209 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
210 clocks = <&clks IMX6UL_CLK_UART7_IPG>,
211 <&clks IMX6UL_CLK_UART7_SERIAL>;
212 clock-names = "ipg", "per";
213 status = "disabled";
214 };
215
216 uart1: serial@02020000 {
217 compatible = "fsl,imx6ul-uart",
218 "fsl,imx6q-uart";
219 reg = <0x02020000 0x4000>;
220 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
221 clocks = <&clks IMX6UL_CLK_UART1_IPG>,
222 <&clks IMX6UL_CLK_UART1_SERIAL>;
223 clock-names = "ipg", "per";
224 status = "disabled";
225 };
226
227 uart8: serial@02024000 {
228 compatible = "fsl,imx6ul-uart",
229 "fsl,imx6q-uart";
230 reg = <0x02024000 0x4000>;
231 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
232 clocks = <&clks IMX6UL_CLK_UART8_IPG>,
233 <&clks IMX6UL_CLK_UART8_SERIAL>;
234 clock-names = "ipg", "per";
235 status = "disabled";
236 };
237 };
238
Lothar Waßmann302e01b2016-01-20 11:08:55 +0100[diff] [blame^]239 tsc: tsc@02040000 {
240 compatible = "fsl,imx6ul-tsc";
241 reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
242 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
243 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
244 clocks = <&clks IMX6UL_CLK_IPG>,
245 <&clks IMX6UL_CLK_ADC2>;
246 clock-names = "tsc", "adc";
247 status = "disabled";
248 };
249
Frank Lia5fcccb2015-07-10 02:09:45 +0800[diff] [blame]250 gpt1: gpt@02098000 {
251 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
252 reg = <0x02098000 0x4000>;
253 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
254 clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
255 <&clks IMX6UL_CLK_GPT1_SERIAL>;
256 clock-names = "ipg", "per";
257 };
258
259 gpio1: gpio@0209c000 {
260 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
261 reg = <0x0209c000 0x4000>;
262 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
263 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
264 gpio-controller;
265 #gpio-cells = <2>;
266 interrupt-controller;
267 #interrupt-cells = <2>;
268 };
269
270 gpio2: gpio@020a0000 {
271 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
272 reg = <0x020a0000 0x4000>;
273 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
274 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
275 gpio-controller;
276 #gpio-cells = <2>;
277 interrupt-controller;
278 #interrupt-cells = <2>;
279 };
280
281 gpio3: gpio@020a4000 {
282 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
283 reg = <0x020a4000 0x4000>;
284 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
286 gpio-controller;
287 #gpio-cells = <2>;
288 interrupt-controller;
289 #interrupt-cells = <2>;
290 };
291
292 gpio4: gpio@020a8000 {
293 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
294 reg = <0x020a8000 0x4000>;
295 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
297 gpio-controller;
298 #gpio-cells = <2>;
299 interrupt-controller;
300 #interrupt-cells = <2>;
301 };
302
303 gpio5: gpio@020ac000 {
304 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
305 reg = <0x020ac000 0x4000>;
306 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
307 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
308 gpio-controller;
309 #gpio-cells = <2>;
310 interrupt-controller;
311 #interrupt-cells = <2>;
312 };
313
Fugang Duan01f3dc72015-07-28 15:30:41 +0800[diff] [blame]314 fec2: ethernet@020b4000 {
315 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
316 reg = <0x020b4000 0x4000>;
317 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
318 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
319 clocks = <&clks IMX6UL_CLK_ENET>,
320 <&clks IMX6UL_CLK_ENET_AHB>,
321 <&clks IMX6UL_CLK_ENET_PTP>,
322 <&clks IMX6UL_CLK_ENET2_REF_125M>,
323 <&clks IMX6UL_CLK_ENET2_REF_125M>;
324 clock-names = "ipg", "ahb", "ptp",
325 "enet_clk_ref", "enet_out";
326 fsl,num-tx-queues=<1>;
327 fsl,num-rx-queues=<1>;
328 status = "disabled";
329 };
330
Frank Lia5fcccb2015-07-10 02:09:45 +0800[diff] [blame]331 wdog1: wdog@020bc000 {
332 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
333 reg = <0x020bc000 0x4000>;
334 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
335 clocks = <&clks IMX6UL_CLK_WDOG1>;
336 };
337
338 wdog2: wdog@020c0000 {
339 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
340 reg = <0x020c0000 0x4000>;
341 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
342 clocks = <&clks IMX6UL_CLK_WDOG2>;
343 status = "disabled";
344 };
345
346 clks: ccm@020c4000 {
347 compatible = "fsl,imx6ul-ccm";
348 reg = <0x020c4000 0x4000>;
349 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
350 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
351 #clock-cells = <1>;
352 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
353 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
354 };
355
356 anatop: anatop@020c8000 {
357 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
358 "syscon", "simple-bus";
359 reg = <0x020c8000 0x1000>;
360 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
361 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
362 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
363
364 reg_3p0: regulator-3p0@120 {
365 compatible = "fsl,anatop-regulator";
366 regulator-name = "vdd3p0";
367 regulator-min-microvolt = <2625000>;
368 regulator-max-microvolt = <3400000>;
369 anatop-reg-offset = <0x120>;
370 anatop-vol-bit-shift = <8>;
371 anatop-vol-bit-width = <5>;
372 anatop-min-bit-val = <0>;
373 anatop-min-voltage = <2625000>;
374 anatop-max-voltage = <3400000>;
375 anatop-enable-bit = <0>;
376 };
377
378 reg_arm: regulator-vddcore@140 {
379 compatible = "fsl,anatop-regulator";
380 regulator-name = "cpu";
381 regulator-min-microvolt = <725000>;
382 regulator-max-microvolt = <1450000>;
383 regulator-always-on;
384 anatop-reg-offset = <0x140>;
385 anatop-vol-bit-shift = <0>;
386 anatop-vol-bit-width = <5>;
387 anatop-delay-reg-offset = <0x170>;
388 anatop-delay-bit-shift = <24>;
389 anatop-delay-bit-width = <2>;
390 anatop-min-bit-val = <1>;
391 anatop-min-voltage = <725000>;
392 anatop-max-voltage = <1450000>;
393 };
394
395 reg_soc: regulator-vddsoc@140 {
396 compatible = "fsl,anatop-regulator";
397 regulator-name = "vddsoc";
398 regulator-min-microvolt = <725000>;
399 regulator-max-microvolt = <1450000>;
400 regulator-always-on;
401 anatop-reg-offset = <0x140>;
402 anatop-vol-bit-shift = <18>;
403 anatop-vol-bit-width = <5>;
404 anatop-delay-reg-offset = <0x170>;
405 anatop-delay-bit-shift = <28>;
406 anatop-delay-bit-width = <2>;
407 anatop-min-bit-val = <1>;
408 anatop-min-voltage = <725000>;
409 anatop-max-voltage = <1450000>;
410 };
411 };
412
413 usbphy1: usbphy@020c9000 {
414 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
415 reg = <0x020c9000 0x1000>;
416 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
417 clocks = <&clks IMX6UL_CLK_USBPHY1>;
418 phy-3p0-supply = <&reg_3p0>;
419 fsl,anatop = <&anatop>;
420 };
421
422 usbphy2: usbphy@020ca000 {
423 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
424 reg = <0x020ca000 0x1000>;
425 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
426 clocks = <&clks IMX6UL_CLK_USBPHY2>;
427 phy-3p0-supply = <&reg_3p0>;
428 fsl,anatop = <&anatop>;
429 };
430
Anson Huang5b032872015-08-04 23:54:58 +0800[diff] [blame]431 snvs: snvs@020cc000 {
432 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
433 reg = <0x020cc000 0x4000>;
434
435 snvs_rtc: snvs-rtc-lp {
436 compatible = "fsl,sec-v4.0-mon-rtc-lp";
437 regmap = <&snvs>;
438 offset = <0x34>;
439 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
440 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
441 };
Anson Huang36032572015-08-06 16:16:01 +0800[diff] [blame]442
Anson Huangab0a05d2015-09-06 15:29:34 +0800[diff] [blame]443 snvs_poweroff: snvs-poweroff {
444 compatible = "syscon-poweroff";
445 regmap = <&snvs>;
446 offset = <0x38>;
447 mask = <0x60>;
448 status = "disabled";
449 };
450
Anson Huang36032572015-08-06 16:16:01 +0800[diff] [blame]451 snvs_pwrkey: snvs-powerkey {
452 compatible = "fsl,sec-v4.0-pwrkey";
453 regmap = <&snvs>;
454 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
455 linux,keycode = <KEY_POWER>;
456 wakeup-source;
457 };
Anson Huang5b032872015-08-04 23:54:58 +0800[diff] [blame]458 };
459
Frank Lia5fcccb2015-07-10 02:09:45 +0800[diff] [blame]460 epit1: epit@020d0000 {
461 reg = <0x020d0000 0x4000>;
462 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
463 };
464
465 epit2: epit@020d4000 {
466 reg = <0x020d4000 0x4000>;
467 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
468 };
469
470 src: src@020d8000 {
471 compatible = "fsl,imx6ul-src", "fsl,imx51-src";
472 reg = <0x020d8000 0x4000>;
473 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
474 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
475 #reset-cells = <1>;
476 };
477
478 gpc: gpc@020dc000 {
479 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
480 reg = <0x020dc000 0x4000>;
Anson Huang18619ff2015-08-04 01:12:12 +0800[diff] [blame]481 interrupt-controller;
482 #interrupt-cells = <3>;
Frank Lia5fcccb2015-07-10 02:09:45 +0800[diff] [blame]483 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
Anson Huang18619ff2015-08-04 01:12:12 +0800[diff] [blame]484 interrupt-parent = <&intc>;
Frank Lia5fcccb2015-07-10 02:09:45 +0800[diff] [blame]485 };
486
487 iomuxc: iomuxc@020e0000 {
488 compatible = "fsl,imx6ul-iomuxc";
489 reg = <0x020e0000 0x4000>;
490 };
491
492 gpr: iomuxc-gpr@020e4000 {
493 compatible = "fsl,imx6ul-iomuxc-gpr", "syscon";
494 reg = <0x020e4000 0x4000>;
495 };
496
497 gpt2: gpt@020e8000 {
498 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
499 reg = <0x020e8000 0x4000>;
500 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
501 clocks = <&clks IMX6UL_CLK_DUMMY>,
502 <&clks IMX6UL_CLK_DUMMY>;
503 clock-names = "ipg", "per";
504 };
505
506 pwm5: pwm@020f0000 {
507 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
508 reg = <0x020f0000 0x4000>;
509 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
510 clocks = <&clks IMX6UL_CLK_DUMMY>,
511 <&clks IMX6UL_CLK_DUMMY>;
512 clock-names = "ipg", "per";
513 #pwm-cells = <2>;
514 };
515
516 pwm6: pwm@020f4000 {
517 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
518 reg = <0x020f4000 0x4000>;
519 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
520 clocks = <&clks IMX6UL_CLK_DUMMY>,
521 <&clks IMX6UL_CLK_DUMMY>;
522 clock-names = "ipg", "per";
523 #pwm-cells = <2>;
524 };
525
526 pwm7: pwm@020f8000 {
527 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
528 reg = <0x020f8000 0x4000>;
529 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
530 clocks = <&clks IMX6UL_CLK_DUMMY>,
531 <&clks IMX6UL_CLK_DUMMY>;
532 clock-names = "ipg", "per";
533 #pwm-cells = <2>;
534 };
535
536 pwm8: pwm@020fc000 {
537 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
538 reg = <0x020fc000 0x4000>;
539 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
540 clocks = <&clks IMX6UL_CLK_DUMMY>,
541 <&clks IMX6UL_CLK_DUMMY>;
542 clock-names = "ipg", "per";
543 #pwm-cells = <2>;
544 };
545 };
546
547 aips2: aips-bus@02100000 {
548 compatible = "fsl,aips-bus", "simple-bus";
549 #address-cells = <1>;
550 #size-cells = <1>;
551 reg = <0x02100000 0x100000>;
552 ranges;
553
Frank Licad2cb62015-07-17 04:03:16 +0800[diff] [blame]554 usbotg1: usb@02184000 {
555 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
556 reg = <0x02184000 0x200>;
557 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
558 clocks = <&clks IMX6UL_CLK_USBOH3>;
559 fsl,usbphy = <&usbphy1>;
560 fsl,usbmisc = <&usbmisc 0>;
561 fsl,anatop = <&anatop>;
Peter Chen9493bf52015-09-30 10:17:16 +0800[diff] [blame]562 ahb-burst-config = <0x0>;
Peter Chen2b1a40e2015-09-30 10:17:17 +0800[diff] [blame]563 tx-burst-size-dword = <0x10>;
564 rx-burst-size-dword = <0x10>;
Frank Licad2cb62015-07-17 04:03:16 +0800[diff] [blame]565 status = "disabled";
566 };
567
568 usbotg2: usb@02184200 {
569 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
570 reg = <0x02184200 0x200>;
571 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
572 clocks = <&clks IMX6UL_CLK_USBOH3>;
573 fsl,usbphy = <&usbphy2>;
574 fsl,usbmisc = <&usbmisc 1>;
Peter Chen9493bf52015-09-30 10:17:16 +0800[diff] [blame]575 ahb-burst-config = <0x0>;
Peter Chen2b1a40e2015-09-30 10:17:17 +0800[diff] [blame]576 tx-burst-size-dword = <0x10>;
577 rx-burst-size-dword = <0x10>;
Frank Licad2cb62015-07-17 04:03:16 +0800[diff] [blame]578 status = "disabled";
579 };
580
581 usbmisc: usbmisc@02184800 {
582 #index-cells = <1>;
583 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
584 reg = <0x02184800 0x200>;
585 };
586
Fugang Duan01f3dc72015-07-28 15:30:41 +0800[diff] [blame]587 fec1: ethernet@02188000 {
588 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
589 reg = <0x02188000 0x4000>;
590 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
591 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
592 clocks = <&clks IMX6UL_CLK_ENET>,
593 <&clks IMX6UL_CLK_ENET_AHB>,
594 <&clks IMX6UL_CLK_ENET_PTP>,
595 <&clks IMX6UL_CLK_ENET_REF>,
596 <&clks IMX6UL_CLK_ENET_REF>;
597 clock-names = "ipg", "ahb", "ptp",
598 "enet_clk_ref", "enet_out";
599 fsl,num-tx-queues=<1>;
600 fsl,num-rx-queues=<1>;
601 status = "disabled";
602 };
603
Frank Lia5fcccb2015-07-10 02:09:45 +0800[diff] [blame]604 usdhc1: usdhc@02190000 {
605 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
606 reg = <0x02190000 0x4000>;
607 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
608 clocks = <&clks IMX6UL_CLK_USDHC1>,
609 <&clks IMX6UL_CLK_USDHC1>,
610 <&clks IMX6UL_CLK_USDHC1>;
611 clock-names = "ipg", "ahb", "per";
612 bus-width = <4>;
613 status = "disabled";
614 };
615
616 usdhc2: usdhc@02194000 {
617 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
618 reg = <0x02194000 0x4000>;
619 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
620 clocks = <&clks IMX6UL_CLK_USDHC2>,
621 <&clks IMX6UL_CLK_USDHC2>,
622 <&clks IMX6UL_CLK_USDHC2>;
623 clock-names = "ipg", "ahb", "per";
624 bus-width = <4>;
625 status = "disabled";
626 };
627
Fabio Estevamaab8ec02015-11-04 10:54:50 -0200[diff] [blame]628 adc1: adc@02198000 {
629 compatible = "fsl,imx6ul-adc", "fsl,vf610-adc";
630 reg = <0x02198000 0x4000>;
631 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
632 clocks = <&clks IMX6UL_CLK_ADC1>;
633 num-channels = <2>;
634 clock-names = "adc";
635 fsl,adck-max-frequency = <30000000>, <40000000>,
636 <20000000>;
637 status = "disabled";
638 };
639
Frank Lia5fcccb2015-07-10 02:09:45 +0800[diff] [blame]640 i2c1: i2c@021a0000 {
641 #address-cells = <1>;
642 #size-cells = <0>;
643 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
644 reg = <0x021a0000 0x4000>;
645 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
646 clocks = <&clks IMX6UL_CLK_I2C1>;
647 status = "disabled";
648 };
649
650 i2c2: i2c@021a4000 {
651 #address-cells = <1>;
652 #size-cells = <0>;
653 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
654 reg = <0x021a4000 0x4000>;
655 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
656 clocks = <&clks IMX6UL_CLK_I2C2>;
657 status = "disabled";
658 };
659
660 i2c3: i2c@021a8000 {
661 #address-cells = <1>;
662 #size-cells = <0>;
663 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
664 reg = <0x021a8000 0x4000>;
665 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
666 clocks = <&clks IMX6UL_CLK_I2C3>;
667 status = "disabled";
668 };
669
Anson Huang51a37442015-08-05 01:48:36 +0800[diff] [blame]670 mmdc: mmdc@021b0000 {
671 compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
672 reg = <0x021b0000 0x4000>;
673 };
674
Frank Li5ff807a2015-07-21 03:33:53 +0800[diff] [blame]675 qspi: qspi@021e0000 {
676 #address-cells = <1>;
677 #size-cells = <0>;
678 compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
679 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
680 reg-names = "QuadSPI", "QuadSPI-memory";
681 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
682 clocks = <&clks IMX6UL_CLK_QSPI>,
683 <&clks IMX6UL_CLK_QSPI>;
684 clock-names = "qspi_en", "qspi";
685 status = "disabled";
686 };
687
Frank Lia5fcccb2015-07-10 02:09:45 +0800[diff] [blame]688 uart2: serial@021e8000 {
689 compatible = "fsl,imx6ul-uart",
690 "fsl,imx6q-uart";
691 reg = <0x021e8000 0x4000>;
692 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
693 clocks = <&clks IMX6UL_CLK_UART2_IPG>,
694 <&clks IMX6UL_CLK_UART2_SERIAL>;
695 clock-names = "ipg", "per";
696 status = "disabled";
697 };
698
699 uart3: serial@021ec000 {
700 compatible = "fsl,imx6ul-uart",
701 "fsl,imx6q-uart";
702 reg = <0x021ec000 0x4000>;
703 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
704 clocks = <&clks IMX6UL_CLK_UART3_IPG>,
705 <&clks IMX6UL_CLK_UART3_SERIAL>;
706 clock-names = "ipg", "per";
707 status = "disabled";
708 };
709
710 uart4: serial@021f0000 {
711 compatible = "fsl,imx6ul-uart",
712 "fsl,imx6q-uart";
713 reg = <0x021f0000 0x4000>;
714 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
715 clocks = <&clks IMX6UL_CLK_UART4_IPG>,
716 <&clks IMX6UL_CLK_UART4_SERIAL>;
717 clock-names = "ipg", "per";
718 status = "disabled";
719 };
720
721 uart5: serial@021f4000 {
722 compatible = "fsl,imx6ul-uart",
723 "fsl,imx6q-uart";
724 reg = <0x021f4000 0x4000>;
725 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
726 clocks = <&clks IMX6UL_CLK_UART5_IPG>,
727 <&clks IMX6UL_CLK_UART5_SERIAL>;
728 clock-names = "ipg", "per";
729 status = "disabled";
730 };
731
732 i2c4: i2c@021f8000 {
733 #address-cells = <1>;
734 #size-cells = <0>;
735 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
736 reg = <0x021f8000 0x4000>;
737 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
738 clocks = <&clks IMX6UL_CLK_I2C4>;
739 status = "disabled";
740 };
741
742 uart6: serial@021fc000 {
743 compatible = "fsl,imx6ul-uart",
744 "fsl,imx6q-uart";
745 reg = <0x021fc000 0x4000>;
746 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
747 clocks = <&clks IMX6UL_CLK_UART6_IPG>,
748 <&clks IMX6UL_CLK_UART6_SERIAL>;
749 clock-names = "ipg", "per";
750 status = "disabled";
751 };
752 };
753 };
754};