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gerrit-public.fairphone.software / kernel / msm-5.4 / 30b7d88de034a2b5c4f20c0cd05c792d9b619d70 / . / sound / soc / codecs / rt5665.c
blob: 26bf157ca29369ba4233c7dca32ae6c2f793d452 [file] [log] [blame]
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]1/*
2 * rt5665.c -- RT5665/RT5658 ALSA SoC audio codec driver
3 *
4 * Copyright 2016 Realtek Semiconductor Corp.
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/platform_device.h>
19#include <linux/spi/spi.h>
20#include <linux/acpi.h>
21#include <linux/gpio.h>
22#include <linux/of_gpio.h>
23#include <linux/regulator/consumer.h>
24#include <linux/mutex.h>
25#include <sound/core.h>
26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/jack.h>
29#include <sound/soc.h>
30#include <sound/soc-dapm.h>
31#include <sound/initval.h>
32#include <sound/tlv.h>
33#include <sound/rt5665.h>
34
35#include "rl6231.h"
36#include "rt5665.h"
37
38#define RT5665_NUM_SUPPLIES 3
39
40static const char *rt5665_supply_names[RT5665_NUM_SUPPLIES] = {
41 "AVDD",
42 "MICVDD",
43 "VBAT",
44};
45
46struct rt5665_priv {
47 struct snd_soc_codec *codec;
48 struct rt5665_platform_data pdata;
49 struct regmap *regmap;
50 struct gpio_desc *gpiod_ldo1_en;
51 struct gpio_desc *gpiod_reset;
52 struct snd_soc_jack *hs_jack;
53 struct regulator_bulk_data supplies[RT5665_NUM_SUPPLIES];
54 struct delayed_work jack_detect_work;
55 struct delayed_work calibrate_work;
56 struct delayed_work jd_check_work;
57 struct mutex calibrate_mutex;
58
59 int sysclk;
60 int sysclk_src;
61 int lrck[RT5665_AIFS];
62 int bclk[RT5665_AIFS];
63 int master[RT5665_AIFS];
64 int id;
65
66 int pll_src;
67 int pll_in;
68 int pll_out;
69
70 int jack_type;
71 int irq_work_delay_time;
72 unsigned int sar_adc_value;
73};
74
75static const struct reg_default rt5665_reg[] = {
76 {0x0000, 0x0000},
77 {0x0001, 0xc8c8},
78 {0x0002, 0x8080},
79 {0x0003, 0x8000},
80 {0x0004, 0xc80a},
81 {0x0005, 0x0000},
82 {0x0006, 0x0000},
83 {0x0007, 0x0000},
84 {0x000a, 0x0000},
85 {0x000b, 0x0000},
86 {0x000c, 0x0000},
87 {0x000d, 0x0000},
88 {0x000f, 0x0808},
89 {0x0010, 0x4040},
90 {0x0011, 0x0000},
91 {0x0012, 0x1404},
92 {0x0013, 0x1000},
93 {0x0014, 0xa00a},
94 {0x0015, 0x0404},
95 {0x0016, 0x0404},
96 {0x0017, 0x0011},
97 {0x0018, 0xafaf},
98 {0x0019, 0xafaf},
99 {0x001a, 0xafaf},
100 {0x001b, 0x0011},
101 {0x001c, 0x2f2f},
102 {0x001d, 0x2f2f},
103 {0x001e, 0x2f2f},
104 {0x001f, 0x0000},
105 {0x0020, 0x0000},
106 {0x0021, 0x0000},
107 {0x0022, 0x5757},
108 {0x0023, 0x0039},
109 {0x0026, 0xc0c0},
110 {0x0027, 0xc0c0},
111 {0x0028, 0xc0c0},
112 {0x0029, 0x8080},
113 {0x002a, 0xaaaa},
114 {0x002b, 0xaaaa},
115 {0x002c, 0xaba8},
116 {0x002d, 0x0000},
117 {0x002e, 0x0000},
118 {0x002f, 0x0000},
119 {0x0030, 0x0000},
120 {0x0031, 0x5000},
121 {0x0032, 0x0000},
122 {0x0033, 0x0000},
123 {0x0034, 0x0000},
124 {0x0035, 0x0000},
125 {0x003a, 0x0000},
126 {0x003b, 0x0000},
127 {0x003c, 0x00ff},
128 {0x003d, 0x0000},
129 {0x003e, 0x00ff},
130 {0x003f, 0x0000},
131 {0x0040, 0x0000},
132 {0x0041, 0x00ff},
133 {0x0042, 0x0000},
134 {0x0043, 0x00ff},
135 {0x0044, 0x0c0c},
136 {0x0049, 0xc00b},
137 {0x004a, 0x0000},
138 {0x004b, 0x031f},
139 {0x004d, 0x0000},
140 {0x004e, 0x001f},
141 {0x004f, 0x0000},
142 {0x0050, 0x001f},
143 {0x0052, 0xf000},
144 {0x0061, 0x0000},
145 {0x0062, 0x0000},
146 {0x0063, 0x003e},
147 {0x0064, 0x0000},
148 {0x0065, 0x0000},
149 {0x0066, 0x003f},
150 {0x0067, 0x0000},
151 {0x006b, 0x0000},
152 {0x006d, 0xff00},
153 {0x006e, 0x2808},
154 {0x006f, 0x000a},
155 {0x0070, 0x8000},
156 {0x0071, 0x8000},
157 {0x0072, 0x8000},
158 {0x0073, 0x7000},
159 {0x0074, 0x7770},
160 {0x0075, 0x0002},
161 {0x0076, 0x0001},
162 {0x0078, 0x00f0},
163 {0x0079, 0x0000},
164 {0x007a, 0x0000},
165 {0x007b, 0x0000},
166 {0x007c, 0x0000},
167 {0x007d, 0x0123},
168 {0x007e, 0x4500},
169 {0x007f, 0x8003},
170 {0x0080, 0x0000},
171 {0x0081, 0x0000},
172 {0x0082, 0x0000},
173 {0x0083, 0x0000},
174 {0x0084, 0x0000},
175 {0x0085, 0x0000},
176 {0x0086, 0x0008},
177 {0x0087, 0x0000},
178 {0x0088, 0x0000},
179 {0x0089, 0x0000},
180 {0x008a, 0x0000},
181 {0x008b, 0x0000},
182 {0x008c, 0x0003},
183 {0x008e, 0x0060},
184 {0x008f, 0x1000},
185 {0x0091, 0x0c26},
186 {0x0092, 0x0073},
187 {0x0093, 0x0000},
188 {0x0094, 0x0080},
189 {0x0098, 0x0000},
190 {0x0099, 0x0000},
191 {0x009a, 0x0007},
192 {0x009f, 0x0000},
193 {0x00a0, 0x0000},
194 {0x00a1, 0x0002},
195 {0x00a2, 0x0001},
196 {0x00a3, 0x0002},
197 {0x00a4, 0x0001},
198 {0x00ae, 0x2040},
199 {0x00af, 0x0000},
200 {0x00b6, 0x0000},
201 {0x00b7, 0x0000},
202 {0x00b8, 0x0000},
203 {0x00b9, 0x0000},
204 {0x00ba, 0x0002},
205 {0x00bb, 0x0000},
206 {0x00be, 0x0000},
207 {0x00c0, 0x0000},
208 {0x00c1, 0x0aaa},
209 {0x00c2, 0xaa80},
210 {0x00c3, 0x0003},
211 {0x00c4, 0x0000},
212 {0x00d0, 0x0000},
213 {0x00d1, 0x2244},
214 {0x00d3, 0x3300},
215 {0x00d4, 0x2200},
216 {0x00d9, 0x0809},
217 {0x00da, 0x0000},
218 {0x00db, 0x0008},
219 {0x00dc, 0x00c0},
220 {0x00dd, 0x6724},
221 {0x00de, 0x3131},
222 {0x00df, 0x0008},
223 {0x00e0, 0x4000},
224 {0x00e1, 0x3131},
225 {0x00e2, 0x600c},
226 {0x00ea, 0xb320},
227 {0x00eb, 0x0000},
228 {0x00ec, 0xb300},
229 {0x00ed, 0x0000},
230 {0x00ee, 0xb320},
231 {0x00ef, 0x0000},
232 {0x00f0, 0x0201},
233 {0x00f1, 0x0ddd},
234 {0x00f2, 0x0ddd},
235 {0x00f6, 0x0000},
236 {0x00f7, 0x0000},
237 {0x00f8, 0x0000},
238 {0x00fa, 0x0000},
239 {0x00fb, 0x0000},
240 {0x00fc, 0x0000},
241 {0x00fd, 0x0000},
242 {0x00fe, 0x10ec},
243 {0x00ff, 0x6451},
244 {0x0100, 0xaaaa},
245 {0x0101, 0x000a},
246 {0x010a, 0xaaaa},
247 {0x010b, 0xa0a0},
248 {0x010c, 0xaeae},
249 {0x010d, 0xaaaa},
250 {0x010e, 0xaaaa},
251 {0x010f, 0xaaaa},
252 {0x0110, 0xe002},
253 {0x0111, 0xa402},
254 {0x0112, 0xaaaa},
255 {0x0113, 0x2000},
256 {0x0117, 0x0f00},
257 {0x0125, 0x0410},
258 {0x0132, 0x0000},
259 {0x0133, 0x0000},
260 {0x0137, 0x5540},
261 {0x0138, 0x3700},
262 {0x0139, 0x79a1},
263 {0x013a, 0x2020},
264 {0x013b, 0x2020},
265 {0x013c, 0x2005},
266 {0x013f, 0x0000},
267 {0x0145, 0x0002},
268 {0x0146, 0x0000},
269 {0x0147, 0x0000},
270 {0x0148, 0x0000},
271 {0x0150, 0x0000},
272 {0x0160, 0x4eff},
273 {0x0161, 0x0080},
274 {0x0162, 0x0200},
275 {0x0163, 0x0800},
276 {0x0164, 0x0000},
277 {0x0165, 0x0000},
278 {0x0166, 0x0000},
279 {0x0167, 0x000f},
280 {0x0170, 0x4e87},
281 {0x0171, 0x0080},
282 {0x0172, 0x0200},
283 {0x0173, 0x0800},
284 {0x0174, 0x00ff},
285 {0x0175, 0x0000},
286 {0x0190, 0x413d},
287 {0x0191, 0x4139},
288 {0x0192, 0x4135},
289 {0x0193, 0x413d},
290 {0x0194, 0x0000},
291 {0x0195, 0x0000},
292 {0x0196, 0x0000},
293 {0x0197, 0x0000},
294 {0x0198, 0x0000},
295 {0x0199, 0x0000},
296 {0x01a0, 0x1e64},
297 {0x01a1, 0x06a3},
298 {0x01a2, 0x0000},
299 {0x01a3, 0x0000},
300 {0x01a4, 0x0000},
301 {0x01a5, 0x0000},
302 {0x01a6, 0x0000},
303 {0x01a7, 0x8000},
304 {0x01a8, 0x0000},
305 {0x01a9, 0x0000},
306 {0x01aa, 0x0000},
307 {0x01ab, 0x0000},
308 {0x01b5, 0x0000},
309 {0x01b6, 0x01c3},
310 {0x01b7, 0x02a0},
311 {0x01b8, 0x03e9},
312 {0x01b9, 0x1389},
313 {0x01ba, 0xc351},
314 {0x01bb, 0x0009},
315 {0x01bc, 0x0018},
316 {0x01bd, 0x002a},
317 {0x01be, 0x004c},
318 {0x01bf, 0x0097},
319 {0x01c0, 0x433d},
320 {0x01c1, 0x0000},
321 {0x01c2, 0x0000},
322 {0x01c3, 0x0000},
323 {0x01c4, 0x0000},
324 {0x01c5, 0x0000},
325 {0x01c6, 0x0000},
326 {0x01c7, 0x0000},
327 {0x01c8, 0x40af},
328 {0x01c9, 0x0702},
329 {0x01ca, 0x0000},
330 {0x01cb, 0x0000},
331 {0x01cc, 0x5757},
332 {0x01cd, 0x5757},
333 {0x01ce, 0x5757},
334 {0x01cf, 0x5757},
335 {0x01d0, 0x5757},
336 {0x01d1, 0x5757},
337 {0x01d2, 0x5757},
338 {0x01d3, 0x5757},
339 {0x01d4, 0x5757},
340 {0x01d5, 0x5757},
341 {0x01d6, 0x003c},
342 {0x01da, 0x0000},
343 {0x01db, 0x0000},
344 {0x01dc, 0x0000},
345 {0x01de, 0x7c00},
346 {0x01df, 0x0320},
347 {0x01e0, 0x06a1},
348 {0x01e1, 0x0000},
349 {0x01e2, 0x0000},
350 {0x01e3, 0x0000},
351 {0x01e4, 0x0000},
352 {0x01e6, 0x0001},
353 {0x01e7, 0x0000},
354 {0x01e8, 0x0000},
355 {0x01ea, 0xbf3f},
356 {0x01eb, 0x0000},
357 {0x01ec, 0x0000},
358 {0x01ed, 0x0000},
359 {0x01ee, 0x0000},
360 {0x01ef, 0x0000},
361 {0x01f0, 0x0000},
362 {0x01f1, 0x0000},
363 {0x01f2, 0x0000},
364 {0x01f3, 0x0000},
365 {0x01f4, 0x0000},
366 {0x0200, 0x0000},
367 {0x0201, 0x0000},
368 {0x0202, 0x0000},
369 {0x0203, 0x0000},
370 {0x0204, 0x0000},
371 {0x0205, 0x0000},
372 {0x0206, 0x0000},
373 {0x0207, 0x0000},
374 {0x0208, 0x0000},
375 {0x0210, 0x60b1},
376 {0x0211, 0xa005},
377 {0x0212, 0x024c},
378 {0x0213, 0xf7ff},
379 {0x0214, 0x024c},
380 {0x0215, 0x0102},
381 {0x0216, 0x00a3},
382 {0x0217, 0x0048},
383 {0x0218, 0xa2c0},
384 {0x0219, 0x0400},
385 {0x021a, 0x00c8},
386 {0x021b, 0x00c0},
387 {0x02ff, 0x0110},
388 {0x0300, 0x001f},
389 {0x0301, 0x032c},
390 {0x0302, 0x5f21},
391 {0x0303, 0x4000},
392 {0x0304, 0x4000},
393 {0x0305, 0x06d5},
394 {0x0306, 0x8000},
395 {0x0307, 0x0700},
396 {0x0310, 0x4560},
397 {0x0311, 0xa4a8},
398 {0x0312, 0x7418},
399 {0x0313, 0x0000},
400 {0x0314, 0x0006},
401 {0x0315, 0xffff},
402 {0x0316, 0xc400},
403 {0x0317, 0x0000},
404 {0x0330, 0x00a6},
405 {0x0331, 0x04c3},
406 {0x0332, 0x27c8},
407 {0x0333, 0xbf50},
408 {0x0334, 0x0045},
409 {0x0335, 0x0007},
410 {0x0336, 0x7418},
411 {0x0337, 0x0501},
412 {0x0338, 0x0000},
413 {0x0339, 0x0010},
414 {0x033a, 0x1010},
415 {0x03c0, 0x7e00},
416 {0x03c1, 0x8000},
417 {0x03c2, 0x8000},
418 {0x03c3, 0x8000},
419 {0x03c4, 0x8000},
420 {0x03c5, 0x8000},
421 {0x03c6, 0x8000},
422 {0x03c7, 0x8000},
423 {0x03c8, 0x8000},
424 {0x03c9, 0x8000},
425 {0x03ca, 0x8000},
426 {0x03cb, 0x8000},
427 {0x03cc, 0x8000},
428 {0x03d0, 0x0000},
429 {0x03d1, 0x0000},
430 {0x03d2, 0x0000},
431 {0x03d3, 0x0000},
432 {0x03d4, 0x2000},
433 {0x03d5, 0x2000},
434 {0x03d6, 0x0000},
435 {0x03d7, 0x0000},
436 {0x03d8, 0x2000},
437 {0x03d9, 0x2000},
438 {0x03da, 0x2000},
439 {0x03db, 0x2000},
440 {0x03dc, 0x0000},
441 {0x03dd, 0x0000},
442 {0x03de, 0x0000},
443 {0x03df, 0x2000},
444 {0x03e0, 0x0000},
445 {0x03e1, 0x0000},
446 {0x03e2, 0x0000},
447 {0x03e3, 0x0000},
448 {0x03e4, 0x0000},
449 {0x03e5, 0x0000},
450 {0x03e6, 0x0000},
451 {0x03e7, 0x0000},
452 {0x03e8, 0x0000},
453 {0x03e9, 0x0000},
454 {0x03ea, 0x0000},
455 {0x03eb, 0x0000},
456 {0x03ec, 0x0000},
457 {0x03ed, 0x0000},
458 {0x03ee, 0x0000},
459 {0x03ef, 0x0000},
460 {0x03f0, 0x0800},
461 {0x03f1, 0x0800},
462 {0x03f2, 0x0800},
463 {0x03f3, 0x0800},
464};
465
466static bool rt5665_volatile_register(struct device *dev, unsigned int reg)
467{
468 switch (reg) {
469 case RT5665_RESET:
470 case RT5665_EJD_CTRL_2:
471 case RT5665_GPIO_STA:
472 case RT5665_INT_ST_1:
473 case RT5665_IL_CMD_1:
474 case RT5665_4BTN_IL_CMD_1:
475 case RT5665_PSV_IL_CMD_1:
476 case RT5665_AJD1_CTRL:
477 case RT5665_JD_CTRL_3:
478 case RT5665_STO_NG2_CTRL_1:
479 case RT5665_SAR_IL_CMD_4:
480 case RT5665_DEVICE_ID:
481 case RT5665_STO1_DAC_SIL_DET ... RT5665_STO2_DAC_SIL_DET:
482 case RT5665_MONO_AMP_CALIB_STA1 ... RT5665_MONO_AMP_CALIB_STA6:
483 case RT5665_HP_IMP_SENS_CTRL_12 ... RT5665_HP_IMP_SENS_CTRL_15:
484 case RT5665_HP_CALIB_STA_1 ... RT5665_HP_CALIB_STA_11:
485 return true;
486 default:
487 return false;
488 }
489}
490
491static bool rt5665_readable_register(struct device *dev, unsigned int reg)
492{
493 switch (reg) {
494 case RT5665_RESET:
495 case RT5665_VENDOR_ID:
496 case RT5665_VENDOR_ID_1:
497 case RT5665_DEVICE_ID:
498 case RT5665_LOUT:
499 case RT5665_HP_CTRL_1:
500 case RT5665_HP_CTRL_2:
501 case RT5665_MONO_OUT:
502 case RT5665_HPL_GAIN:
503 case RT5665_HPR_GAIN:
504 case RT5665_MONO_GAIN:
505 case RT5665_CAL_BST_CTRL:
506 case RT5665_CBJ_BST_CTRL:
507 case RT5665_IN1_IN2:
508 case RT5665_IN3_IN4:
509 case RT5665_INL1_INR1_VOL:
510 case RT5665_EJD_CTRL_1:
511 case RT5665_EJD_CTRL_2:
512 case RT5665_EJD_CTRL_3:
513 case RT5665_EJD_CTRL_4:
514 case RT5665_EJD_CTRL_5:
515 case RT5665_EJD_CTRL_6:
516 case RT5665_EJD_CTRL_7:
517 case RT5665_DAC2_CTRL:
518 case RT5665_DAC2_DIG_VOL:
519 case RT5665_DAC1_DIG_VOL:
520 case RT5665_DAC3_DIG_VOL:
521 case RT5665_DAC3_CTRL:
522 case RT5665_STO1_ADC_DIG_VOL:
523 case RT5665_MONO_ADC_DIG_VOL:
524 case RT5665_STO2_ADC_DIG_VOL:
525 case RT5665_STO1_ADC_BOOST:
526 case RT5665_MONO_ADC_BOOST:
527 case RT5665_STO2_ADC_BOOST:
528 case RT5665_HP_IMP_GAIN_1:
529 case RT5665_HP_IMP_GAIN_2:
530 case RT5665_STO1_ADC_MIXER:
531 case RT5665_MONO_ADC_MIXER:
532 case RT5665_STO2_ADC_MIXER:
533 case RT5665_AD_DA_MIXER:
534 case RT5665_STO1_DAC_MIXER:
535 case RT5665_MONO_DAC_MIXER:
536 case RT5665_STO2_DAC_MIXER:
537 case RT5665_A_DAC1_MUX:
538 case RT5665_A_DAC2_MUX:
539 case RT5665_DIG_INF2_DATA:
540 case RT5665_DIG_INF3_DATA:
541 case RT5665_PDM_OUT_CTRL:
542 case RT5665_PDM_DATA_CTRL_1:
543 case RT5665_PDM_DATA_CTRL_2:
544 case RT5665_PDM_DATA_CTRL_3:
545 case RT5665_PDM_DATA_CTRL_4:
546 case RT5665_REC1_GAIN:
547 case RT5665_REC1_L1_MIXER:
548 case RT5665_REC1_L2_MIXER:
549 case RT5665_REC1_R1_MIXER:
550 case RT5665_REC1_R2_MIXER:
551 case RT5665_REC2_GAIN:
552 case RT5665_REC2_L1_MIXER:
553 case RT5665_REC2_L2_MIXER:
554 case RT5665_REC2_R1_MIXER:
555 case RT5665_REC2_R2_MIXER:
556 case RT5665_CAL_REC:
557 case RT5665_ALC_BACK_GAIN:
558 case RT5665_MONOMIX_GAIN:
559 case RT5665_MONOMIX_IN_GAIN:
560 case RT5665_OUT_L_GAIN:
561 case RT5665_OUT_L_MIXER:
562 case RT5665_OUT_R_GAIN:
563 case RT5665_OUT_R_MIXER:
564 case RT5665_LOUT_MIXER:
565 case RT5665_PWR_DIG_1:
566 case RT5665_PWR_DIG_2:
567 case RT5665_PWR_ANLG_1:
568 case RT5665_PWR_ANLG_2:
569 case RT5665_PWR_ANLG_3:
570 case RT5665_PWR_MIXER:
571 case RT5665_PWR_VOL:
572 case RT5665_CLK_DET:
573 case RT5665_HPF_CTRL1:
574 case RT5665_DMIC_CTRL_1:
575 case RT5665_DMIC_CTRL_2:
576 case RT5665_I2S1_SDP:
577 case RT5665_I2S2_SDP:
578 case RT5665_I2S3_SDP:
579 case RT5665_ADDA_CLK_1:
580 case RT5665_ADDA_CLK_2:
581 case RT5665_I2S1_F_DIV_CTRL_1:
582 case RT5665_I2S1_F_DIV_CTRL_2:
583 case RT5665_TDM_CTRL_1:
584 case RT5665_TDM_CTRL_2:
585 case RT5665_TDM_CTRL_3:
586 case RT5665_TDM_CTRL_4:
587 case RT5665_TDM_CTRL_5:
588 case RT5665_TDM_CTRL_6:
589 case RT5665_TDM_CTRL_7:
590 case RT5665_TDM_CTRL_8:
591 case RT5665_GLB_CLK:
592 case RT5665_PLL_CTRL_1:
593 case RT5665_PLL_CTRL_2:
594 case RT5665_ASRC_1:
595 case RT5665_ASRC_2:
596 case RT5665_ASRC_3:
597 case RT5665_ASRC_4:
598 case RT5665_ASRC_5:
599 case RT5665_ASRC_6:
600 case RT5665_ASRC_7:
601 case RT5665_ASRC_8:
602 case RT5665_ASRC_9:
603 case RT5665_ASRC_10:
604 case RT5665_DEPOP_1:
605 case RT5665_DEPOP_2:
606 case RT5665_HP_CHARGE_PUMP_1:
607 case RT5665_HP_CHARGE_PUMP_2:
608 case RT5665_MICBIAS_1:
609 case RT5665_MICBIAS_2:
610 case RT5665_ASRC_12:
611 case RT5665_ASRC_13:
612 case RT5665_ASRC_14:
613 case RT5665_RC_CLK_CTRL:
614 case RT5665_I2S_M_CLK_CTRL_1:
615 case RT5665_I2S2_F_DIV_CTRL_1:
616 case RT5665_I2S2_F_DIV_CTRL_2:
617 case RT5665_I2S3_F_DIV_CTRL_1:
618 case RT5665_I2S3_F_DIV_CTRL_2:
619 case RT5665_EQ_CTRL_1:
620 case RT5665_EQ_CTRL_2:
621 case RT5665_IRQ_CTRL_1:
622 case RT5665_IRQ_CTRL_2:
623 case RT5665_IRQ_CTRL_3:
624 case RT5665_IRQ_CTRL_4:
625 case RT5665_IRQ_CTRL_5:
626 case RT5665_IRQ_CTRL_6:
627 case RT5665_INT_ST_1:
628 case RT5665_GPIO_CTRL_1:
629 case RT5665_GPIO_CTRL_2:
630 case RT5665_GPIO_CTRL_3:
631 case RT5665_GPIO_CTRL_4:
632 case RT5665_GPIO_STA:
633 case RT5665_HP_AMP_DET_CTRL_1:
634 case RT5665_HP_AMP_DET_CTRL_2:
635 case RT5665_MID_HP_AMP_DET:
636 case RT5665_LOW_HP_AMP_DET:
637 case RT5665_SV_ZCD_1:
638 case RT5665_SV_ZCD_2:
639 case RT5665_IL_CMD_1:
640 case RT5665_IL_CMD_2:
641 case RT5665_IL_CMD_3:
642 case RT5665_IL_CMD_4:
643 case RT5665_4BTN_IL_CMD_1:
644 case RT5665_4BTN_IL_CMD_2:
645 case RT5665_4BTN_IL_CMD_3:
646 case RT5665_PSV_IL_CMD_1:
647 case RT5665_ADC_STO1_HP_CTRL_1:
648 case RT5665_ADC_STO1_HP_CTRL_2:
649 case RT5665_ADC_MONO_HP_CTRL_1:
650 case RT5665_ADC_MONO_HP_CTRL_2:
651 case RT5665_ADC_STO2_HP_CTRL_1:
652 case RT5665_ADC_STO2_HP_CTRL_2:
653 case RT5665_AJD1_CTRL:
654 case RT5665_JD1_THD:
655 case RT5665_JD2_THD:
656 case RT5665_JD_CTRL_1:
657 case RT5665_JD_CTRL_2:
658 case RT5665_JD_CTRL_3:
659 case RT5665_DIG_MISC:
660 case RT5665_DUMMY_2:
661 case RT5665_DUMMY_3:
662 case RT5665_DAC_ADC_DIG_VOL1:
663 case RT5665_DAC_ADC_DIG_VOL2:
664 case RT5665_BIAS_CUR_CTRL_1:
665 case RT5665_BIAS_CUR_CTRL_2:
666 case RT5665_BIAS_CUR_CTRL_3:
667 case RT5665_BIAS_CUR_CTRL_4:
668 case RT5665_BIAS_CUR_CTRL_5:
669 case RT5665_BIAS_CUR_CTRL_6:
670 case RT5665_BIAS_CUR_CTRL_7:
671 case RT5665_BIAS_CUR_CTRL_8:
672 case RT5665_BIAS_CUR_CTRL_9:
673 case RT5665_BIAS_CUR_CTRL_10:
674 case RT5665_VREF_REC_OP_FB_CAP_CTRL:
675 case RT5665_CHARGE_PUMP_1:
676 case RT5665_DIG_IN_CTRL_1:
677 case RT5665_DIG_IN_CTRL_2:
678 case RT5665_PAD_DRIVING_CTRL:
679 case RT5665_SOFT_RAMP_DEPOP:
680 case RT5665_PLL:
681 case RT5665_CHOP_DAC:
682 case RT5665_CHOP_ADC:
683 case RT5665_CALIB_ADC_CTRL:
684 case RT5665_VOL_TEST:
685 case RT5665_TEST_MODE_CTRL_1:
686 case RT5665_TEST_MODE_CTRL_2:
687 case RT5665_TEST_MODE_CTRL_3:
688 case RT5665_TEST_MODE_CTRL_4:
689 case RT5665_BASSBACK_CTRL:
690 case RT5665_STO_NG2_CTRL_1:
691 case RT5665_STO_NG2_CTRL_2:
692 case RT5665_STO_NG2_CTRL_3:
693 case RT5665_STO_NG2_CTRL_4:
694 case RT5665_STO_NG2_CTRL_5:
695 case RT5665_STO_NG2_CTRL_6:
696 case RT5665_STO_NG2_CTRL_7:
697 case RT5665_STO_NG2_CTRL_8:
698 case RT5665_MONO_NG2_CTRL_1:
699 case RT5665_MONO_NG2_CTRL_2:
700 case RT5665_MONO_NG2_CTRL_3:
701 case RT5665_MONO_NG2_CTRL_4:
702 case RT5665_MONO_NG2_CTRL_5:
703 case RT5665_MONO_NG2_CTRL_6:
704 case RT5665_STO1_DAC_SIL_DET:
705 case RT5665_MONOL_DAC_SIL_DET:
706 case RT5665_MONOR_DAC_SIL_DET:
707 case RT5665_STO2_DAC_SIL_DET:
708 case RT5665_SIL_PSV_CTRL1:
709 case RT5665_SIL_PSV_CTRL2:
710 case RT5665_SIL_PSV_CTRL3:
711 case RT5665_SIL_PSV_CTRL4:
712 case RT5665_SIL_PSV_CTRL5:
713 case RT5665_SIL_PSV_CTRL6:
714 case RT5665_MONO_AMP_CALIB_CTRL_1:
715 case RT5665_MONO_AMP_CALIB_CTRL_2:
716 case RT5665_MONO_AMP_CALIB_CTRL_3:
717 case RT5665_MONO_AMP_CALIB_CTRL_4:
718 case RT5665_MONO_AMP_CALIB_CTRL_5:
719 case RT5665_MONO_AMP_CALIB_CTRL_6:
720 case RT5665_MONO_AMP_CALIB_CTRL_7:
721 case RT5665_MONO_AMP_CALIB_STA1:
722 case RT5665_MONO_AMP_CALIB_STA2:
723 case RT5665_MONO_AMP_CALIB_STA3:
724 case RT5665_MONO_AMP_CALIB_STA4:
725 case RT5665_MONO_AMP_CALIB_STA6:
726 case RT5665_HP_IMP_SENS_CTRL_01:
727 case RT5665_HP_IMP_SENS_CTRL_02:
728 case RT5665_HP_IMP_SENS_CTRL_03:
729 case RT5665_HP_IMP_SENS_CTRL_04:
730 case RT5665_HP_IMP_SENS_CTRL_05:
731 case RT5665_HP_IMP_SENS_CTRL_06:
732 case RT5665_HP_IMP_SENS_CTRL_07:
733 case RT5665_HP_IMP_SENS_CTRL_08:
734 case RT5665_HP_IMP_SENS_CTRL_09:
735 case RT5665_HP_IMP_SENS_CTRL_10:
736 case RT5665_HP_IMP_SENS_CTRL_11:
737 case RT5665_HP_IMP_SENS_CTRL_12:
738 case RT5665_HP_IMP_SENS_CTRL_13:
739 case RT5665_HP_IMP_SENS_CTRL_14:
740 case RT5665_HP_IMP_SENS_CTRL_15:
741 case RT5665_HP_IMP_SENS_CTRL_16:
742 case RT5665_HP_IMP_SENS_CTRL_17:
743 case RT5665_HP_IMP_SENS_CTRL_18:
744 case RT5665_HP_IMP_SENS_CTRL_19:
745 case RT5665_HP_IMP_SENS_CTRL_20:
746 case RT5665_HP_IMP_SENS_CTRL_21:
747 case RT5665_HP_IMP_SENS_CTRL_22:
748 case RT5665_HP_IMP_SENS_CTRL_23:
749 case RT5665_HP_IMP_SENS_CTRL_24:
750 case RT5665_HP_IMP_SENS_CTRL_25:
751 case RT5665_HP_IMP_SENS_CTRL_26:
752 case RT5665_HP_IMP_SENS_CTRL_27:
753 case RT5665_HP_IMP_SENS_CTRL_28:
754 case RT5665_HP_IMP_SENS_CTRL_29:
755 case RT5665_HP_IMP_SENS_CTRL_30:
756 case RT5665_HP_IMP_SENS_CTRL_31:
757 case RT5665_HP_IMP_SENS_CTRL_32:
758 case RT5665_HP_IMP_SENS_CTRL_33:
759 case RT5665_HP_IMP_SENS_CTRL_34:
760 case RT5665_HP_LOGIC_CTRL_1:
761 case RT5665_HP_LOGIC_CTRL_2:
762 case RT5665_HP_LOGIC_CTRL_3:
763 case RT5665_HP_CALIB_CTRL_1:
764 case RT5665_HP_CALIB_CTRL_2:
765 case RT5665_HP_CALIB_CTRL_3:
766 case RT5665_HP_CALIB_CTRL_4:
767 case RT5665_HP_CALIB_CTRL_5:
768 case RT5665_HP_CALIB_CTRL_6:
769 case RT5665_HP_CALIB_CTRL_7:
770 case RT5665_HP_CALIB_CTRL_9:
771 case RT5665_HP_CALIB_CTRL_10:
772 case RT5665_HP_CALIB_CTRL_11:
773 case RT5665_HP_CALIB_STA_1:
774 case RT5665_HP_CALIB_STA_2:
775 case RT5665_HP_CALIB_STA_3:
776 case RT5665_HP_CALIB_STA_4:
777 case RT5665_HP_CALIB_STA_5:
778 case RT5665_HP_CALIB_STA_6:
779 case RT5665_HP_CALIB_STA_7:
780 case RT5665_HP_CALIB_STA_8:
781 case RT5665_HP_CALIB_STA_9:
782 case RT5665_HP_CALIB_STA_10:
783 case RT5665_HP_CALIB_STA_11:
784 case RT5665_PGM_TAB_CTRL1:
785 case RT5665_PGM_TAB_CTRL2:
786 case RT5665_PGM_TAB_CTRL3:
787 case RT5665_PGM_TAB_CTRL4:
788 case RT5665_PGM_TAB_CTRL5:
789 case RT5665_PGM_TAB_CTRL6:
790 case RT5665_PGM_TAB_CTRL7:
791 case RT5665_PGM_TAB_CTRL8:
792 case RT5665_PGM_TAB_CTRL9:
793 case RT5665_SAR_IL_CMD_1:
794 case RT5665_SAR_IL_CMD_2:
795 case RT5665_SAR_IL_CMD_3:
796 case RT5665_SAR_IL_CMD_4:
797 case RT5665_SAR_IL_CMD_5:
798 case RT5665_SAR_IL_CMD_6:
799 case RT5665_SAR_IL_CMD_7:
800 case RT5665_SAR_IL_CMD_8:
801 case RT5665_SAR_IL_CMD_9:
802 case RT5665_SAR_IL_CMD_10:
803 case RT5665_SAR_IL_CMD_11:
804 case RT5665_SAR_IL_CMD_12:
805 case RT5665_DRC1_CTRL_0:
806 case RT5665_DRC1_CTRL_1:
807 case RT5665_DRC1_CTRL_2:
808 case RT5665_DRC1_CTRL_3:
809 case RT5665_DRC1_CTRL_4:
810 case RT5665_DRC1_CTRL_5:
811 case RT5665_DRC1_CTRL_6:
812 case RT5665_DRC1_HARD_LMT_CTRL_1:
813 case RT5665_DRC1_HARD_LMT_CTRL_2:
814 case RT5665_DRC1_PRIV_1:
815 case RT5665_DRC1_PRIV_2:
816 case RT5665_DRC1_PRIV_3:
817 case RT5665_DRC1_PRIV_4:
818 case RT5665_DRC1_PRIV_5:
819 case RT5665_DRC1_PRIV_6:
820 case RT5665_DRC1_PRIV_7:
821 case RT5665_DRC1_PRIV_8:
822 case RT5665_ALC_PGA_CTRL_1:
823 case RT5665_ALC_PGA_CTRL_2:
824 case RT5665_ALC_PGA_CTRL_3:
825 case RT5665_ALC_PGA_CTRL_4:
826 case RT5665_ALC_PGA_CTRL_5:
827 case RT5665_ALC_PGA_CTRL_6:
828 case RT5665_ALC_PGA_CTRL_7:
829 case RT5665_ALC_PGA_CTRL_8:
830 case RT5665_ALC_PGA_STA_1:
831 case RT5665_ALC_PGA_STA_2:
832 case RT5665_ALC_PGA_STA_3:
833 case RT5665_EQ_AUTO_RCV_CTRL1:
834 case RT5665_EQ_AUTO_RCV_CTRL2:
835 case RT5665_EQ_AUTO_RCV_CTRL3:
836 case RT5665_EQ_AUTO_RCV_CTRL4:
837 case RT5665_EQ_AUTO_RCV_CTRL5:
838 case RT5665_EQ_AUTO_RCV_CTRL6:
839 case RT5665_EQ_AUTO_RCV_CTRL7:
840 case RT5665_EQ_AUTO_RCV_CTRL8:
841 case RT5665_EQ_AUTO_RCV_CTRL9:
842 case RT5665_EQ_AUTO_RCV_CTRL10:
843 case RT5665_EQ_AUTO_RCV_CTRL11:
844 case RT5665_EQ_AUTO_RCV_CTRL12:
845 case RT5665_EQ_AUTO_RCV_CTRL13:
846 case RT5665_ADC_L_EQ_LPF1_A1:
847 case RT5665_R_EQ_LPF1_A1:
848 case RT5665_L_EQ_LPF1_H0:
849 case RT5665_R_EQ_LPF1_H0:
850 case RT5665_L_EQ_BPF1_A1:
851 case RT5665_R_EQ_BPF1_A1:
852 case RT5665_L_EQ_BPF1_A2:
853 case RT5665_R_EQ_BPF1_A2:
854 case RT5665_L_EQ_BPF1_H0:
855 case RT5665_R_EQ_BPF1_H0:
856 case RT5665_L_EQ_BPF2_A1:
857 case RT5665_R_EQ_BPF2_A1:
858 case RT5665_L_EQ_BPF2_A2:
859 case RT5665_R_EQ_BPF2_A2:
860 case RT5665_L_EQ_BPF2_H0:
861 case RT5665_R_EQ_BPF2_H0:
862 case RT5665_L_EQ_BPF3_A1:
863 case RT5665_R_EQ_BPF3_A1:
864 case RT5665_L_EQ_BPF3_A2:
865 case RT5665_R_EQ_BPF3_A2:
866 case RT5665_L_EQ_BPF3_H0:
867 case RT5665_R_EQ_BPF3_H0:
868 case RT5665_L_EQ_BPF4_A1:
869 case RT5665_R_EQ_BPF4_A1:
870 case RT5665_L_EQ_BPF4_A2:
871 case RT5665_R_EQ_BPF4_A2:
872 case RT5665_L_EQ_BPF4_H0:
873 case RT5665_R_EQ_BPF4_H0:
874 case RT5665_L_EQ_HPF1_A1:
875 case RT5665_R_EQ_HPF1_A1:
876 case RT5665_L_EQ_HPF1_H0:
877 case RT5665_R_EQ_HPF1_H0:
878 case RT5665_L_EQ_PRE_VOL:
879 case RT5665_R_EQ_PRE_VOL:
880 case RT5665_L_EQ_POST_VOL:
881 case RT5665_R_EQ_POST_VOL:
882 case RT5665_SCAN_MODE_CTRL:
883 case RT5665_I2C_MODE:
884 return true;
885 default:
886 return false;
887 }
888}
889
890static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -2250, 150, 0);
891static const DECLARE_TLV_DB_SCALE(mono_vol_tlv, -1400, 150, 0);
892static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
893static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
894static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
895static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
896static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
897static const DECLARE_TLV_DB_SCALE(in_bst_tlv, -1200, 75, 0);
898
899/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
900static const DECLARE_TLV_DB_RANGE(bst_tlv,
901 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
902 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
903 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
904 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
905 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
906 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
907 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
908);
909
910/* Interface data select */
911static const char * const rt5665_data_select[] = {
912 "L/R", "R/L", "L/L", "R/R"
913};
914
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]915static SOC_ENUM_SINGLE_DECL(rt5665_if1_1_01_adc_enum,
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]916 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT01_SFT, rt5665_data_select);
917
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]918static SOC_ENUM_SINGLE_DECL(rt5665_if1_1_23_adc_enum,
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]919 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT23_SFT, rt5665_data_select);
920
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]921static SOC_ENUM_SINGLE_DECL(rt5665_if1_1_45_adc_enum,
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]922 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT45_SFT, rt5665_data_select);
923
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]924static SOC_ENUM_SINGLE_DECL(rt5665_if1_1_67_adc_enum,
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]925 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT67_SFT, rt5665_data_select);
926
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]927static SOC_ENUM_SINGLE_DECL(rt5665_if1_2_01_adc_enum,
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]928 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT01_SFT, rt5665_data_select);
929
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]930static SOC_ENUM_SINGLE_DECL(rt5665_if1_2_23_adc_enum,
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]931 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT23_SFT, rt5665_data_select);
932
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]933static SOC_ENUM_SINGLE_DECL(rt5665_if1_2_45_adc_enum,
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]934 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT45_SFT, rt5665_data_select);
935
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]936static SOC_ENUM_SINGLE_DECL(rt5665_if1_2_67_adc_enum,
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]937 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT67_SFT, rt5665_data_select);
938
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]939static SOC_ENUM_SINGLE_DECL(rt5665_if2_1_dac_enum,
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]940 RT5665_DIG_INF2_DATA, RT5665_IF2_1_DAC_SEL_SFT, rt5665_data_select);
941
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]942static SOC_ENUM_SINGLE_DECL(rt5665_if2_1_adc_enum,
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]943 RT5665_DIG_INF2_DATA, RT5665_IF2_1_ADC_SEL_SFT, rt5665_data_select);
944
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]945static SOC_ENUM_SINGLE_DECL(rt5665_if2_2_dac_enum,
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]946 RT5665_DIG_INF2_DATA, RT5665_IF2_2_DAC_SEL_SFT, rt5665_data_select);
947
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]948static SOC_ENUM_SINGLE_DECL(rt5665_if2_2_adc_enum,
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]949 RT5665_DIG_INF2_DATA, RT5665_IF2_2_ADC_SEL_SFT, rt5665_data_select);
950
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]951static SOC_ENUM_SINGLE_DECL(rt5665_if3_dac_enum,
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]952 RT5665_DIG_INF3_DATA, RT5665_IF3_DAC_SEL_SFT, rt5665_data_select);
953
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]954static SOC_ENUM_SINGLE_DECL(rt5665_if3_adc_enum,
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]955 RT5665_DIG_INF3_DATA, RT5665_IF3_ADC_SEL_SFT, rt5665_data_select);
956
957static const struct snd_kcontrol_new rt5665_if1_1_01_adc_swap_mux =
958 SOC_DAPM_ENUM("IF1_1 01 ADC Swap Mux", rt5665_if1_1_01_adc_enum);
959
960static const struct snd_kcontrol_new rt5665_if1_1_23_adc_swap_mux =
961 SOC_DAPM_ENUM("IF1_1 23 ADC Swap Mux", rt5665_if1_1_23_adc_enum);
962
963static const struct snd_kcontrol_new rt5665_if1_1_45_adc_swap_mux =
964 SOC_DAPM_ENUM("IF1_1 45 ADC Swap Mux", rt5665_if1_1_45_adc_enum);
965
966static const struct snd_kcontrol_new rt5665_if1_1_67_adc_swap_mux =
967 SOC_DAPM_ENUM("IF1_1 67 ADC Swap Mux", rt5665_if1_1_67_adc_enum);
968
969static const struct snd_kcontrol_new rt5665_if1_2_01_adc_swap_mux =
970 SOC_DAPM_ENUM("IF1_2 01 ADC Swap Mux", rt5665_if1_2_01_adc_enum);
971
972static const struct snd_kcontrol_new rt5665_if1_2_23_adc_swap_mux =
973 SOC_DAPM_ENUM("IF1_2 23 ADC1 Swap Mux", rt5665_if1_2_23_adc_enum);
974
975static const struct snd_kcontrol_new rt5665_if1_2_45_adc_swap_mux =
976 SOC_DAPM_ENUM("IF1_2 45 ADC1 Swap Mux", rt5665_if1_2_45_adc_enum);
977
978static const struct snd_kcontrol_new rt5665_if1_2_67_adc_swap_mux =
979 SOC_DAPM_ENUM("IF1_2 67 ADC1 Swap Mux", rt5665_if1_2_67_adc_enum);
980
981static const struct snd_kcontrol_new rt5665_if2_1_dac_swap_mux =
982 SOC_DAPM_ENUM("IF2_1 DAC Swap Source", rt5665_if2_1_dac_enum);
983
984static const struct snd_kcontrol_new rt5665_if2_1_adc_swap_mux =
985 SOC_DAPM_ENUM("IF2_1 ADC Swap Source", rt5665_if2_1_adc_enum);
986
987static const struct snd_kcontrol_new rt5665_if2_2_dac_swap_mux =
988 SOC_DAPM_ENUM("IF2_2 DAC Swap Source", rt5665_if2_2_dac_enum);
989
990static const struct snd_kcontrol_new rt5665_if2_2_adc_swap_mux =
991 SOC_DAPM_ENUM("IF2_2 ADC Swap Source", rt5665_if2_2_adc_enum);
992
993static const struct snd_kcontrol_new rt5665_if3_dac_swap_mux =
994 SOC_DAPM_ENUM("IF3 DAC Swap Source", rt5665_if3_dac_enum);
995
996static const struct snd_kcontrol_new rt5665_if3_adc_swap_mux =
997 SOC_DAPM_ENUM("IF3 ADC Swap Source", rt5665_if3_adc_enum);
998
999static int rt5665_hp_vol_put(struct snd_kcontrol *kcontrol,
1000 struct snd_ctl_elem_value *ucontrol)
1001{
1002 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1003 int ret = snd_soc_put_volsw(kcontrol, ucontrol);
1004
1005 if (snd_soc_read(codec, RT5665_STO_NG2_CTRL_1) & RT5665_NG2_EN) {
1006 snd_soc_update_bits(codec, RT5665_STO_NG2_CTRL_1,
1007 RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
1008 snd_soc_update_bits(codec, RT5665_STO_NG2_CTRL_1,
1009 RT5665_NG2_EN_MASK, RT5665_NG2_EN);
1010 }
1011
1012 return ret;
1013}
1014
1015static int rt5665_mono_vol_put(struct snd_kcontrol *kcontrol,
1016 struct snd_ctl_elem_value *ucontrol)
1017{
1018 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1019 int ret = snd_soc_put_volsw(kcontrol, ucontrol);
1020
1021 if (snd_soc_read(codec, RT5665_MONO_NG2_CTRL_1) & RT5665_NG2_EN) {
1022 snd_soc_update_bits(codec, RT5665_MONO_NG2_CTRL_1,
1023 RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
1024 snd_soc_update_bits(codec, RT5665_MONO_NG2_CTRL_1,
1025 RT5665_NG2_EN_MASK, RT5665_NG2_EN);
1026 }
1027
1028 return ret;
1029}
1030
1031/**
1032 * rt5665_sel_asrc_clk_src - select ASRC clock source for a set of filters
1033 * @codec: SoC audio codec device.
1034 * @filter_mask: mask of filters.
1035 * @clk_src: clock source
1036 *
1037 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5665 can
1038 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
1039 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
1040 * ASRC function will track i2s clock and generate a corresponding system clock
1041 * for codec. This function provides an API to select the clock source for a
1042 * set of filters specified by the mask. And the codec driver will turn on ASRC
1043 * for these filters if ASRC is selected as their clock source.
1044 */
1045int rt5665_sel_asrc_clk_src(struct snd_soc_codec *codec,
1046 unsigned int filter_mask, unsigned int clk_src)
1047{
1048 unsigned int asrc2_mask = 0;
1049 unsigned int asrc2_value = 0;
1050 unsigned int asrc3_mask = 0;
1051 unsigned int asrc3_value = 0;
1052
1053 switch (clk_src) {
1054 case RT5665_CLK_SEL_SYS:
1055 case RT5665_CLK_SEL_I2S1_ASRC:
1056 case RT5665_CLK_SEL_I2S2_ASRC:
1057 case RT5665_CLK_SEL_I2S3_ASRC:
1058 case RT5665_CLK_SEL_SYS2:
1059 case RT5665_CLK_SEL_SYS3:
1060 case RT5665_CLK_SEL_SYS4:
1061 break;
1062
1063 default:
1064 return -EINVAL;
1065 }
1066
1067 if (filter_mask & RT5665_DA_STEREO1_FILTER) {
1068 asrc2_mask |= RT5665_DA_STO1_CLK_SEL_MASK;
1069 asrc2_value = (asrc2_value & ~RT5665_DA_STO1_CLK_SEL_MASK)
1070 | (clk_src << RT5665_DA_STO1_CLK_SEL_SFT);
1071 }
1072
1073 if (filter_mask & RT5665_DA_STEREO2_FILTER) {
1074 asrc2_mask |= RT5665_DA_STO2_CLK_SEL_MASK;
1075 asrc2_value = (asrc2_value & ~RT5665_DA_STO2_CLK_SEL_MASK)
1076 | (clk_src << RT5665_DA_STO2_CLK_SEL_SFT);
1077 }
1078
1079 if (filter_mask & RT5665_DA_MONO_L_FILTER) {
1080 asrc2_mask |= RT5665_DA_MONOL_CLK_SEL_MASK;
1081 asrc2_value = (asrc2_value & ~RT5665_DA_MONOL_CLK_SEL_MASK)
1082 | (clk_src << RT5665_DA_MONOL_CLK_SEL_SFT);
1083 }
1084
1085 if (filter_mask & RT5665_DA_MONO_R_FILTER) {
1086 asrc2_mask |= RT5665_DA_MONOR_CLK_SEL_MASK;
1087 asrc2_value = (asrc2_value & ~RT5665_DA_MONOR_CLK_SEL_MASK)
1088 | (clk_src << RT5665_DA_MONOR_CLK_SEL_SFT);
1089 }
1090
1091 if (filter_mask & RT5665_AD_STEREO1_FILTER) {
1092 asrc3_mask |= RT5665_AD_STO1_CLK_SEL_MASK;
1093 asrc3_value = (asrc2_value & ~RT5665_AD_STO1_CLK_SEL_MASK)
1094 | (clk_src << RT5665_AD_STO1_CLK_SEL_SFT);
1095 }
1096
1097 if (filter_mask & RT5665_AD_STEREO2_FILTER) {
1098 asrc3_mask |= RT5665_AD_STO2_CLK_SEL_MASK;
1099 asrc3_value = (asrc2_value & ~RT5665_AD_STO2_CLK_SEL_MASK)
1100 | (clk_src << RT5665_AD_STO2_CLK_SEL_SFT);
1101 }
1102
1103 if (filter_mask & RT5665_AD_MONO_L_FILTER) {
1104 asrc3_mask |= RT5665_AD_MONOL_CLK_SEL_MASK;
1105 asrc3_value = (asrc3_value & ~RT5665_AD_MONOL_CLK_SEL_MASK)
1106 | (clk_src << RT5665_AD_MONOL_CLK_SEL_SFT);
1107 }
1108
1109 if (filter_mask & RT5665_AD_MONO_R_FILTER) {
1110 asrc3_mask |= RT5665_AD_MONOR_CLK_SEL_MASK;
1111 asrc3_value = (asrc3_value & ~RT5665_AD_MONOR_CLK_SEL_MASK)
1112 | (clk_src << RT5665_AD_MONOR_CLK_SEL_SFT);
1113 }
1114
1115 if (asrc2_mask)
1116 snd_soc_update_bits(codec, RT5665_ASRC_2,
1117 asrc2_mask, asrc2_value);
1118
1119 if (asrc3_mask)
1120 snd_soc_update_bits(codec, RT5665_ASRC_3,
1121 asrc3_mask, asrc3_value);
1122
1123 return 0;
1124}
1125EXPORT_SYMBOL_GPL(rt5665_sel_asrc_clk_src);
1126
1127static int rt5665_button_detect(struct snd_soc_codec *codec)
1128{
1129 int btn_type, val;
1130
1131 val = snd_soc_read(codec, RT5665_4BTN_IL_CMD_1);
1132 btn_type = val & 0xfff0;
1133 snd_soc_write(codec, RT5665_4BTN_IL_CMD_1, val);
1134
1135 return btn_type;
1136}
1137
1138static void rt5665_enable_push_button_irq(struct snd_soc_codec *codec,
1139 bool enable)
1140{
1141 if (enable) {
Bard Liao246126b2017-03-08 19:05:33 +0800[diff] [blame]1142 snd_soc_write(codec, RT5665_4BTN_IL_CMD_1, 0x0003);
1143 snd_soc_update_bits(codec, RT5665_SAR_IL_CMD_9, 0x1, 0x1);
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]1144 snd_soc_write(codec, RT5665_IL_CMD_1, 0x0048);
1145 snd_soc_update_bits(codec, RT5665_4BTN_IL_CMD_2,
1146 RT5665_4BTN_IL_MASK | RT5665_4BTN_IL_RST_MASK,
1147 RT5665_4BTN_IL_EN | RT5665_4BTN_IL_NOR);
1148 snd_soc_update_bits(codec, RT5665_IRQ_CTRL_3,
1149 RT5665_IL_IRQ_MASK, RT5665_IL_IRQ_EN);
1150 } else {
1151 snd_soc_update_bits(codec, RT5665_IRQ_CTRL_3,
1152 RT5665_IL_IRQ_MASK, RT5665_IL_IRQ_DIS);
1153 snd_soc_update_bits(codec, RT5665_4BTN_IL_CMD_2,
1154 RT5665_4BTN_IL_MASK, RT5665_4BTN_IL_DIS);
1155 snd_soc_update_bits(codec, RT5665_4BTN_IL_CMD_2,
1156 RT5665_4BTN_IL_RST_MASK, RT5665_4BTN_IL_RST);
1157 }
1158}
1159
1160/**
1161 * rt5665_headset_detect - Detect headset.
1162 * @codec: SoC audio codec device.
1163 * @jack_insert: Jack insert or not.
1164 *
1165 * Detect whether is headset or not when jack inserted.
1166 *
1167 * Returns detect status.
1168 */
1169static int rt5665_headset_detect(struct snd_soc_codec *codec, int jack_insert)
1170{
1171 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
1172 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
1173 unsigned int sar_hs_type, val;
1174
1175 if (jack_insert) {
1176 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
1177 snd_soc_dapm_sync(dapm);
1178
1179 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2, 0x100,
1180 0x100);
1181
1182 regmap_read(rt5665->regmap, RT5665_GPIO_STA, &val);
1183 if (val & 0x4) {
1184 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
1185 0x100, 0);
1186
1187 regmap_read(rt5665->regmap, RT5665_GPIO_STA, &val);
1188 while (val & 0x4) {
1189 usleep_range(10000, 15000);
1190 regmap_read(rt5665->regmap, RT5665_GPIO_STA,
1191 &val);
1192 }
1193 }
1194
1195 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
Bard Liao39841942017-03-08 19:05:30 +0800[diff] [blame]1196 0x1a0, 0x120);
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]1197 regmap_write(rt5665->regmap, RT5665_EJD_CTRL_3, 0x3424);
Bard Liao39841942017-03-08 19:05:30 +0800[diff] [blame]1198 regmap_write(rt5665->regmap, RT5665_IL_CMD_1, 0x0048);
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]1199 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1, 0xa291);
1200
Bard Liao39841942017-03-08 19:05:30 +0800[diff] [blame]1201 usleep_range(10000, 15000);
1202
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]1203 rt5665->sar_adc_value = snd_soc_read(rt5665->codec,
1204 RT5665_SAR_IL_CMD_4) & 0x7ff;
1205
1206 sar_hs_type = rt5665->pdata.sar_hs_type ?
1207 rt5665->pdata.sar_hs_type : 729;
1208
1209 if (rt5665->sar_adc_value > sar_hs_type) {
1210 rt5665->jack_type = SND_JACK_HEADSET;
1211 rt5665_enable_push_button_irq(codec, true);
1212 } else {
1213 rt5665->jack_type = SND_JACK_HEADPHONE;
1214 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1,
1215 0x2291);
1216 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2,
1217 0x100, 0);
1218 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1219 snd_soc_dapm_sync(dapm);
1220 }
1221 } else {
1222 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1, 0x2291);
1223 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2, 0x100, 0);
1224 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1225 snd_soc_dapm_sync(dapm);
1226 if (rt5665->jack_type == SND_JACK_HEADSET)
1227 rt5665_enable_push_button_irq(codec, false);
1228 rt5665->jack_type = 0;
1229 }
1230
1231 dev_dbg(codec->dev, "jack_type = %d\n", rt5665->jack_type);
1232 return rt5665->jack_type;
1233}
1234
1235static irqreturn_t rt5665_irq(int irq, void *data)
1236{
1237 struct rt5665_priv *rt5665 = data;
1238
1239 mod_delayed_work(system_power_efficient_wq,
1240 &rt5665->jack_detect_work, msecs_to_jiffies(250));
1241
1242 return IRQ_HANDLED;
1243}
1244
1245static void rt5665_jd_check_handler(struct work_struct *work)
1246{
1247 struct rt5665_priv *rt5665 = container_of(work, struct rt5665_priv,
Bard Liaof1994a92017-03-08 19:03:10 +0800[diff] [blame]1248 jd_check_work.work);
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]1249
1250 if (snd_soc_read(rt5665->codec, RT5665_AJD1_CTRL) & 0x0010) {
1251 /* jack out */
1252 rt5665->jack_type = rt5665_headset_detect(rt5665->codec, 0);
1253
1254 snd_soc_jack_report(rt5665->hs_jack, rt5665->jack_type,
1255 SND_JACK_HEADSET |
1256 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1257 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1258 } else {
1259 schedule_delayed_work(&rt5665->jd_check_work, 500);
1260 }
1261}
1262
Bard Liao97c415a2017-04-11 20:07:47 +0800[diff] [blame]1263static int rt5665_set_jack_detect(struct snd_soc_codec *codec,
1264 struct snd_soc_jack *hs_jack, void *data)
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]1265{
1266 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
1267
1268 switch (rt5665->pdata.jd_src) {
1269 case RT5665_JD1:
1270 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
1271 RT5665_GP1_PIN_MASK, RT5665_GP1_PIN_IRQ);
1272 regmap_update_bits(rt5665->regmap, RT5665_RC_CLK_CTRL,
1273 0xc000, 0xc000);
1274 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_2,
1275 RT5665_PWR_JD1, RT5665_PWR_JD1);
1276 regmap_update_bits(rt5665->regmap, RT5665_IRQ_CTRL_1, 0x8, 0x8);
1277 break;
1278
1279 case RT5665_JD_NULL:
1280 break;
1281
1282 default:
1283 dev_warn(codec->dev, "Wrong JD source\n");
1284 break;
1285 }
1286
1287 rt5665->hs_jack = hs_jack;
1288
1289 return 0;
1290}
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]1291
1292static void rt5665_jack_detect_handler(struct work_struct *work)
1293{
1294 struct rt5665_priv *rt5665 =
1295 container_of(work, struct rt5665_priv, jack_detect_work.work);
1296 int val, btn_type;
1297
1298 while (!rt5665->codec) {
1299 pr_debug("%s codec = null\n", __func__);
1300 usleep_range(10000, 15000);
1301 }
1302
1303 while (!rt5665->codec->component.card->instantiated) {
1304 pr_debug("%s\n", __func__);
1305 usleep_range(10000, 15000);
1306 }
1307
1308 mutex_lock(&rt5665->calibrate_mutex);
1309
1310 val = snd_soc_read(rt5665->codec, RT5665_AJD1_CTRL) & 0x0010;
1311 if (!val) {
1312 /* jack in */
1313 if (rt5665->jack_type == 0) {
1314 /* jack was out, report jack type */
1315 rt5665->jack_type =
1316 rt5665_headset_detect(rt5665->codec, 1);
1317 } else {
1318 /* jack is already in, report button event */
1319 rt5665->jack_type = SND_JACK_HEADSET;
1320 btn_type = rt5665_button_detect(rt5665->codec);
1321 /**
1322 * rt5665 can report three kinds of button behavior,
1323 * one click, double click and hold. However,
1324 * currently we will report button pressed/released
1325 * event. So all the three button behaviors are
1326 * treated as button pressed.
1327 */
1328 switch (btn_type) {
1329 case 0x8000:
1330 case 0x4000:
1331 case 0x2000:
1332 rt5665->jack_type |= SND_JACK_BTN_0;
1333 break;
1334 case 0x1000:
1335 case 0x0800:
1336 case 0x0400:
1337 rt5665->jack_type |= SND_JACK_BTN_1;
1338 break;
1339 case 0x0200:
1340 case 0x0100:
1341 case 0x0080:
1342 rt5665->jack_type |= SND_JACK_BTN_2;
1343 break;
1344 case 0x0040:
1345 case 0x0020:
1346 case 0x0010:
1347 rt5665->jack_type |= SND_JACK_BTN_3;
1348 break;
1349 case 0x0000: /* unpressed */
1350 break;
1351 default:
1352 btn_type = 0;
1353 dev_err(rt5665->codec->dev,
1354 "Unexpected button code 0x%04x\n",
1355 btn_type);
1356 break;
1357 }
1358 }
1359 } else {
1360 /* jack out */
1361 rt5665->jack_type = rt5665_headset_detect(rt5665->codec, 0);
1362 }
1363
1364 snd_soc_jack_report(rt5665->hs_jack, rt5665->jack_type,
1365 SND_JACK_HEADSET |
1366 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1367 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1368
1369 if (rt5665->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1370 SND_JACK_BTN_2 | SND_JACK_BTN_3))
1371 schedule_delayed_work(&rt5665->jd_check_work, 0);
1372 else
1373 cancel_delayed_work_sync(&rt5665->jd_check_work);
1374
1375 mutex_unlock(&rt5665->calibrate_mutex);
1376}
1377
1378static const struct snd_kcontrol_new rt5665_snd_controls[] = {
1379 /* Headphone Output Volume */
1380 SOC_DOUBLE_R_EXT_TLV("Headphone Playback Volume", RT5665_HPL_GAIN,
1381 RT5665_HPR_GAIN, RT5665_G_HP_SFT, 15, 1, snd_soc_get_volsw,
1382 rt5665_hp_vol_put, hp_vol_tlv),
1383
1384 /* Mono Output Volume */
1385 SOC_SINGLE_EXT_TLV("Mono Playback Volume", RT5665_MONO_GAIN,
1386 RT5665_L_VOL_SFT, 15, 1, snd_soc_get_volsw,
1387 rt5665_mono_vol_put, mono_vol_tlv),
1388
1389 /* Output Volume */
1390 SOC_DOUBLE_TLV("OUT Playback Volume", RT5665_LOUT, RT5665_L_VOL_SFT,
1391 RT5665_R_VOL_SFT, 39, 1, out_vol_tlv),
1392
1393 /* DAC Digital Volume */
1394 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5665_DAC1_DIG_VOL,
1395 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 175, 0, dac_vol_tlv),
1396 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5665_DAC2_DIG_VOL,
1397 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 175, 0, dac_vol_tlv),
1398 SOC_DOUBLE("DAC2 Playback Switch", RT5665_DAC2_CTRL,
1399 RT5665_M_DAC2_L_VOL_SFT, RT5665_M_DAC2_R_VOL_SFT, 1, 1),
1400
1401 /* IN1/IN2/IN3/IN4 Volume */
1402 SOC_SINGLE_TLV("IN1 Boost Volume", RT5665_IN1_IN2,
1403 RT5665_BST1_SFT, 69, 0, in_bst_tlv),
1404 SOC_SINGLE_TLV("IN2 Boost Volume", RT5665_IN1_IN2,
1405 RT5665_BST2_SFT, 69, 0, in_bst_tlv),
1406 SOC_SINGLE_TLV("IN3 Boost Volume", RT5665_IN3_IN4,
1407 RT5665_BST3_SFT, 69, 0, in_bst_tlv),
1408 SOC_SINGLE_TLV("IN4 Boost Volume", RT5665_IN3_IN4,
1409 RT5665_BST4_SFT, 69, 0, in_bst_tlv),
1410 SOC_SINGLE_TLV("CBJ Boost Volume", RT5665_CBJ_BST_CTRL,
1411 RT5665_BST_CBJ_SFT, 8, 0, bst_tlv),
1412
1413 /* INL/INR Volume Control */
1414 SOC_DOUBLE_TLV("IN Capture Volume", RT5665_INL1_INR1_VOL,
1415 RT5665_INL_VOL_SFT, RT5665_INR_VOL_SFT, 31, 1, in_vol_tlv),
1416
1417 /* ADC Digital Volume Control */
1418 SOC_DOUBLE("STO1 ADC Capture Switch", RT5665_STO1_ADC_DIG_VOL,
1419 RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1),
1420 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5665_STO1_ADC_DIG_VOL,
1421 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv),
1422 SOC_DOUBLE("Mono ADC Capture Switch", RT5665_MONO_ADC_DIG_VOL,
1423 RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1),
1424 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5665_MONO_ADC_DIG_VOL,
1425 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv),
1426 SOC_DOUBLE("STO2 ADC Capture Switch", RT5665_STO2_ADC_DIG_VOL,
1427 RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1),
1428 SOC_DOUBLE_TLV("STO2 ADC Capture Volume", RT5665_STO2_ADC_DIG_VOL,
1429 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv),
1430
1431 /* ADC Boost Volume Control */
1432 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5665_STO1_ADC_BOOST,
1433 RT5665_STO1_ADC_L_BST_SFT, RT5665_STO1_ADC_R_BST_SFT,
1434 3, 0, adc_bst_tlv),
1435
1436 SOC_DOUBLE_TLV("Mono ADC Boost Gain Volume", RT5665_MONO_ADC_BOOST,
1437 RT5665_MONO_ADC_L_BST_SFT, RT5665_MONO_ADC_R_BST_SFT,
1438 3, 0, adc_bst_tlv),
1439
1440 SOC_DOUBLE_TLV("STO2 ADC Boost Gain Volume", RT5665_STO2_ADC_BOOST,
1441 RT5665_STO2_ADC_L_BST_SFT, RT5665_STO2_ADC_R_BST_SFT,
1442 3, 0, adc_bst_tlv),
1443};
1444
1445/**
1446 * set_dmic_clk - Set parameter of dmic.
1447 *
1448 * @w: DAPM widget.
1449 * @kcontrol: The kcontrol of this widget.
1450 * @event: Event id.
1451 *
1452 * Choose dmic clock between 1MHz and 3MHz.
1453 * It is better for clock to approximate 3MHz.
1454 */
1455static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1456 struct snd_kcontrol *kcontrol, int event)
1457{
1458 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1459 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
1460 int pd, idx = -EINVAL;
1461
1462 pd = rl6231_get_pre_div(rt5665->regmap,
1463 RT5665_ADDA_CLK_1, RT5665_I2S_PD1_SFT);
1464 idx = rl6231_calc_dmic_clk(rt5665->sysclk / pd);
1465
1466 if (idx < 0)
1467 dev_err(codec->dev, "Failed to set DMIC clock\n");
1468 else {
1469 snd_soc_update_bits(codec, RT5665_DMIC_CTRL_1,
1470 RT5665_DMIC_CLK_MASK, idx << RT5665_DMIC_CLK_SFT);
1471 }
1472 return idx;
1473}
1474
1475static int rt5665_charge_pump_event(struct snd_soc_dapm_widget *w,
1476 struct snd_kcontrol *kcontrol, int event)
1477{
1478 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1479
1480 switch (event) {
1481 case SND_SOC_DAPM_PRE_PMU:
1482 snd_soc_update_bits(codec, RT5665_HP_CHARGE_PUMP_1,
1483 RT5665_PM_HP_MASK | RT5665_OSW_L_MASK,
1484 RT5665_PM_HP_HV | RT5665_OSW_L_EN);
1485 break;
1486 case SND_SOC_DAPM_POST_PMD:
1487 snd_soc_update_bits(codec, RT5665_HP_CHARGE_PUMP_1,
1488 RT5665_PM_HP_MASK | RT5665_OSW_L_MASK,
1489 RT5665_PM_HP_LV | RT5665_OSW_L_DIS);
1490 break;
1491 default:
1492 return 0;
1493 }
1494
1495 return 0;
1496}
1497
1498static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *w,
1499 struct snd_soc_dapm_widget *sink)
1500{
1501 unsigned int val;
1502 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1503
1504 val = snd_soc_read(codec, RT5665_GLB_CLK);
1505 val &= RT5665_SCLK_SRC_MASK;
1506 if (val == RT5665_SCLK_SRC_PLL1)
1507 return 1;
1508 else
1509 return 0;
1510}
1511
1512static int is_using_asrc(struct snd_soc_dapm_widget *w,
1513 struct snd_soc_dapm_widget *sink)
1514{
1515 unsigned int reg, shift, val;
1516 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1517
1518 switch (w->shift) {
1519 case RT5665_ADC_MONO_R_ASRC_SFT:
1520 reg = RT5665_ASRC_3;
1521 shift = RT5665_AD_MONOR_CLK_SEL_SFT;
1522 break;
1523 case RT5665_ADC_MONO_L_ASRC_SFT:
1524 reg = RT5665_ASRC_3;
1525 shift = RT5665_AD_MONOL_CLK_SEL_SFT;
1526 break;
1527 case RT5665_ADC_STO1_ASRC_SFT:
1528 reg = RT5665_ASRC_3;
1529 shift = RT5665_AD_STO1_CLK_SEL_SFT;
1530 break;
1531 case RT5665_ADC_STO2_ASRC_SFT:
1532 reg = RT5665_ASRC_3;
1533 shift = RT5665_AD_STO2_CLK_SEL_SFT;
1534 break;
1535 case RT5665_DAC_MONO_R_ASRC_SFT:
1536 reg = RT5665_ASRC_2;
1537 shift = RT5665_DA_MONOR_CLK_SEL_SFT;
1538 break;
1539 case RT5665_DAC_MONO_L_ASRC_SFT:
1540 reg = RT5665_ASRC_2;
1541 shift = RT5665_DA_MONOL_CLK_SEL_SFT;
1542 break;
1543 case RT5665_DAC_STO1_ASRC_SFT:
1544 reg = RT5665_ASRC_2;
1545 shift = RT5665_DA_STO1_CLK_SEL_SFT;
1546 break;
1547 case RT5665_DAC_STO2_ASRC_SFT:
1548 reg = RT5665_ASRC_2;
1549 shift = RT5665_DA_STO2_CLK_SEL_SFT;
1550 break;
1551 default:
1552 return 0;
1553 }
1554
1555 val = (snd_soc_read(codec, reg) >> shift) & 0xf;
1556 switch (val) {
1557 case RT5665_CLK_SEL_I2S1_ASRC:
1558 case RT5665_CLK_SEL_I2S2_ASRC:
1559 case RT5665_CLK_SEL_I2S3_ASRC:
1560 /* I2S_Pre_Div1 should be 1 in asrc mode */
1561 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
1562 RT5665_I2S_PD1_MASK, RT5665_I2S_PD1_2);
1563 return 1;
1564 default:
1565 return 0;
1566 }
1567
1568}
1569
1570/* Digital Mixer */
1571static const struct snd_kcontrol_new rt5665_sto1_adc_l_mix[] = {
1572 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO1_ADC_MIXER,
1573 RT5665_M_STO1_ADC_L1_SFT, 1, 1),
1574 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO1_ADC_MIXER,
1575 RT5665_M_STO1_ADC_L2_SFT, 1, 1),
1576};
1577
1578static const struct snd_kcontrol_new rt5665_sto1_adc_r_mix[] = {
1579 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO1_ADC_MIXER,
1580 RT5665_M_STO1_ADC_R1_SFT, 1, 1),
1581 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO1_ADC_MIXER,
1582 RT5665_M_STO1_ADC_R2_SFT, 1, 1),
1583};
1584
1585static const struct snd_kcontrol_new rt5665_sto2_adc_l_mix[] = {
1586 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO2_ADC_MIXER,
1587 RT5665_M_STO2_ADC_L1_SFT, 1, 1),
1588 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO2_ADC_MIXER,
1589 RT5665_M_STO2_ADC_L2_SFT, 1, 1),
1590};
1591
1592static const struct snd_kcontrol_new rt5665_sto2_adc_r_mix[] = {
1593 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO2_ADC_MIXER,
1594 RT5665_M_STO2_ADC_R1_SFT, 1, 1),
1595 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO2_ADC_MIXER,
1596 RT5665_M_STO2_ADC_R2_SFT, 1, 1),
1597};
1598
1599static const struct snd_kcontrol_new rt5665_mono_adc_l_mix[] = {
1600 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_MONO_ADC_MIXER,
1601 RT5665_M_MONO_ADC_L1_SFT, 1, 1),
1602 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_MONO_ADC_MIXER,
1603 RT5665_M_MONO_ADC_L2_SFT, 1, 1),
1604};
1605
1606static const struct snd_kcontrol_new rt5665_mono_adc_r_mix[] = {
1607 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_MONO_ADC_MIXER,
1608 RT5665_M_MONO_ADC_R1_SFT, 1, 1),
1609 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_MONO_ADC_MIXER,
1610 RT5665_M_MONO_ADC_R2_SFT, 1, 1),
1611};
1612
1613static const struct snd_kcontrol_new rt5665_dac_l_mix[] = {
1614 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5665_AD_DA_MIXER,
1615 RT5665_M_ADCMIX_L_SFT, 1, 1),
1616 SOC_DAPM_SINGLE("DAC1 Switch", RT5665_AD_DA_MIXER,
1617 RT5665_M_DAC1_L_SFT, 1, 1),
1618};
1619
1620static const struct snd_kcontrol_new rt5665_dac_r_mix[] = {
1621 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5665_AD_DA_MIXER,
1622 RT5665_M_ADCMIX_R_SFT, 1, 1),
1623 SOC_DAPM_SINGLE("DAC1 Switch", RT5665_AD_DA_MIXER,
1624 RT5665_M_DAC1_R_SFT, 1, 1),
1625};
1626
1627static const struct snd_kcontrol_new rt5665_sto1_dac_l_mix[] = {
1628 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO1_DAC_MIXER,
1629 RT5665_M_DAC_L1_STO_L_SFT, 1, 1),
1630 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO1_DAC_MIXER,
1631 RT5665_M_DAC_R1_STO_L_SFT, 1, 1),
1632 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO1_DAC_MIXER,
1633 RT5665_M_DAC_L2_STO_L_SFT, 1, 1),
1634 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO1_DAC_MIXER,
1635 RT5665_M_DAC_R2_STO_L_SFT, 1, 1),
1636};
1637
1638static const struct snd_kcontrol_new rt5665_sto1_dac_r_mix[] = {
1639 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO1_DAC_MIXER,
1640 RT5665_M_DAC_L1_STO_R_SFT, 1, 1),
1641 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO1_DAC_MIXER,
1642 RT5665_M_DAC_R1_STO_R_SFT, 1, 1),
1643 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO1_DAC_MIXER,
1644 RT5665_M_DAC_L2_STO_R_SFT, 1, 1),
1645 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO1_DAC_MIXER,
1646 RT5665_M_DAC_R2_STO_R_SFT, 1, 1),
1647};
1648
1649static const struct snd_kcontrol_new rt5665_sto2_dac_l_mix[] = {
1650 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO2_DAC_MIXER,
1651 RT5665_M_DAC_L1_STO2_L_SFT, 1, 1),
1652 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO2_DAC_MIXER,
1653 RT5665_M_DAC_L2_STO2_L_SFT, 1, 1),
1654 SOC_DAPM_SINGLE("DAC L3 Switch", RT5665_STO2_DAC_MIXER,
1655 RT5665_M_DAC_L3_STO2_L_SFT, 1, 1),
1656};
1657
1658static const struct snd_kcontrol_new rt5665_sto2_dac_r_mix[] = {
1659 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO2_DAC_MIXER,
1660 RT5665_M_DAC_R1_STO2_R_SFT, 1, 1),
1661 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO2_DAC_MIXER,
1662 RT5665_M_DAC_R2_STO2_R_SFT, 1, 1),
1663 SOC_DAPM_SINGLE("DAC R3 Switch", RT5665_STO2_DAC_MIXER,
1664 RT5665_M_DAC_R3_STO2_R_SFT, 1, 1),
1665};
1666
1667static const struct snd_kcontrol_new rt5665_mono_dac_l_mix[] = {
1668 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_MONO_DAC_MIXER,
1669 RT5665_M_DAC_L1_MONO_L_SFT, 1, 1),
1670 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_MONO_DAC_MIXER,
1671 RT5665_M_DAC_R1_MONO_L_SFT, 1, 1),
1672 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONO_DAC_MIXER,
1673 RT5665_M_DAC_L2_MONO_L_SFT, 1, 1),
1674 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_MONO_DAC_MIXER,
1675 RT5665_M_DAC_R2_MONO_L_SFT, 1, 1),
1676};
1677
1678static const struct snd_kcontrol_new rt5665_mono_dac_r_mix[] = {
1679 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_MONO_DAC_MIXER,
1680 RT5665_M_DAC_L1_MONO_R_SFT, 1, 1),
1681 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_MONO_DAC_MIXER,
1682 RT5665_M_DAC_R1_MONO_R_SFT, 1, 1),
1683 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONO_DAC_MIXER,
1684 RT5665_M_DAC_L2_MONO_R_SFT, 1, 1),
1685 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_MONO_DAC_MIXER,
1686 RT5665_M_DAC_R2_MONO_R_SFT, 1, 1),
1687};
1688
1689/* Analog Input Mixer */
1690static const struct snd_kcontrol_new rt5665_rec1_l_mix[] = {
1691 SOC_DAPM_SINGLE("CBJ Switch", RT5665_REC1_L2_MIXER,
1692 RT5665_M_CBJ_RM1_L_SFT, 1, 1),
1693 SOC_DAPM_SINGLE("INL Switch", RT5665_REC1_L2_MIXER,
1694 RT5665_M_INL_RM1_L_SFT, 1, 1),
1695 SOC_DAPM_SINGLE("INR Switch", RT5665_REC1_L2_MIXER,
1696 RT5665_M_INR_RM1_L_SFT, 1, 1),
1697 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC1_L2_MIXER,
1698 RT5665_M_BST4_RM1_L_SFT, 1, 1),
1699 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC1_L2_MIXER,
1700 RT5665_M_BST3_RM1_L_SFT, 1, 1),
1701 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC1_L2_MIXER,
1702 RT5665_M_BST2_RM1_L_SFT, 1, 1),
1703 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC1_L2_MIXER,
1704 RT5665_M_BST1_RM1_L_SFT, 1, 1),
1705};
1706
1707static const struct snd_kcontrol_new rt5665_rec1_r_mix[] = {
1708 SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_REC1_R2_MIXER,
1709 RT5665_M_AEC_REF_RM1_R_SFT, 1, 1),
1710 SOC_DAPM_SINGLE("INR Switch", RT5665_REC1_R2_MIXER,
1711 RT5665_M_INR_RM1_R_SFT, 1, 1),
1712 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC1_R2_MIXER,
1713 RT5665_M_BST4_RM1_R_SFT, 1, 1),
1714 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC1_R2_MIXER,
1715 RT5665_M_BST3_RM1_R_SFT, 1, 1),
1716 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC1_R2_MIXER,
1717 RT5665_M_BST2_RM1_R_SFT, 1, 1),
1718 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC1_R2_MIXER,
1719 RT5665_M_BST1_RM1_R_SFT, 1, 1),
1720};
1721
1722static const struct snd_kcontrol_new rt5665_rec2_l_mix[] = {
1723 SOC_DAPM_SINGLE("INL Switch", RT5665_REC2_L2_MIXER,
1724 RT5665_M_INL_RM2_L_SFT, 1, 1),
1725 SOC_DAPM_SINGLE("INR Switch", RT5665_REC2_L2_MIXER,
1726 RT5665_M_INR_RM2_L_SFT, 1, 1),
1727 SOC_DAPM_SINGLE("CBJ Switch", RT5665_REC2_L2_MIXER,
1728 RT5665_M_CBJ_RM2_L_SFT, 1, 1),
1729 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC2_L2_MIXER,
1730 RT5665_M_BST4_RM2_L_SFT, 1, 1),
1731 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC2_L2_MIXER,
1732 RT5665_M_BST3_RM2_L_SFT, 1, 1),
1733 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC2_L2_MIXER,
1734 RT5665_M_BST2_RM2_L_SFT, 1, 1),
1735 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC2_L2_MIXER,
1736 RT5665_M_BST1_RM2_L_SFT, 1, 1),
1737};
1738
1739static const struct snd_kcontrol_new rt5665_rec2_r_mix[] = {
1740 SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_REC2_R2_MIXER,
1741 RT5665_M_MONOVOL_RM2_R_SFT, 1, 1),
1742 SOC_DAPM_SINGLE("INL Switch", RT5665_REC2_R2_MIXER,
1743 RT5665_M_INL_RM2_R_SFT, 1, 1),
1744 SOC_DAPM_SINGLE("INR Switch", RT5665_REC2_R2_MIXER,
1745 RT5665_M_INR_RM2_R_SFT, 1, 1),
1746 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC2_R2_MIXER,
1747 RT5665_M_BST4_RM2_R_SFT, 1, 1),
1748 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC2_R2_MIXER,
1749 RT5665_M_BST3_RM2_R_SFT, 1, 1),
1750 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC2_R2_MIXER,
1751 RT5665_M_BST2_RM2_R_SFT, 1, 1),
1752 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC2_R2_MIXER,
1753 RT5665_M_BST1_RM2_R_SFT, 1, 1),
1754};
1755
1756static const struct snd_kcontrol_new rt5665_monovol_mix[] = {
1757 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONOMIX_IN_GAIN,
1758 RT5665_M_DAC_L2_MM_SFT, 1, 1),
1759 SOC_DAPM_SINGLE("RECMIX2L Switch", RT5665_MONOMIX_IN_GAIN,
1760 RT5665_M_RECMIC2L_MM_SFT, 1, 1),
1761 SOC_DAPM_SINGLE("BST1 Switch", RT5665_MONOMIX_IN_GAIN,
1762 RT5665_M_BST1_MM_SFT, 1, 1),
1763 SOC_DAPM_SINGLE("BST2 Switch", RT5665_MONOMIX_IN_GAIN,
1764 RT5665_M_BST2_MM_SFT, 1, 1),
1765 SOC_DAPM_SINGLE("BST3 Switch", RT5665_MONOMIX_IN_GAIN,
1766 RT5665_M_BST3_MM_SFT, 1, 1),
1767};
1768
1769static const struct snd_kcontrol_new rt5665_out_l_mix[] = {
1770 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_OUT_L_MIXER,
1771 RT5665_M_DAC_L2_OM_L_SFT, 1, 1),
1772 SOC_DAPM_SINGLE("INL Switch", RT5665_OUT_L_MIXER,
1773 RT5665_M_IN_L_OM_L_SFT, 1, 1),
1774 SOC_DAPM_SINGLE("BST1 Switch", RT5665_OUT_L_MIXER,
1775 RT5665_M_BST1_OM_L_SFT, 1, 1),
1776 SOC_DAPM_SINGLE("BST2 Switch", RT5665_OUT_L_MIXER,
1777 RT5665_M_BST2_OM_L_SFT, 1, 1),
1778 SOC_DAPM_SINGLE("BST3 Switch", RT5665_OUT_L_MIXER,
1779 RT5665_M_BST3_OM_L_SFT, 1, 1),
1780};
1781
1782static const struct snd_kcontrol_new rt5665_out_r_mix[] = {
1783 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_OUT_R_MIXER,
1784 RT5665_M_DAC_R2_OM_R_SFT, 1, 1),
1785 SOC_DAPM_SINGLE("INR Switch", RT5665_OUT_R_MIXER,
1786 RT5665_M_IN_R_OM_R_SFT, 1, 1),
1787 SOC_DAPM_SINGLE("BST2 Switch", RT5665_OUT_R_MIXER,
1788 RT5665_M_BST2_OM_R_SFT, 1, 1),
1789 SOC_DAPM_SINGLE("BST3 Switch", RT5665_OUT_R_MIXER,
1790 RT5665_M_BST3_OM_R_SFT, 1, 1),
1791 SOC_DAPM_SINGLE("BST4 Switch", RT5665_OUT_R_MIXER,
1792 RT5665_M_BST4_OM_R_SFT, 1, 1),
1793};
1794
1795static const struct snd_kcontrol_new rt5665_mono_mix[] = {
1796 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONOMIX_IN_GAIN,
1797 RT5665_M_DAC_L2_MA_SFT, 1, 1),
1798 SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_MONOMIX_IN_GAIN,
1799 RT5665_M_MONOVOL_MA_SFT, 1, 1),
1800};
1801
1802static const struct snd_kcontrol_new rt5665_lout_l_mix[] = {
1803 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_LOUT_MIXER,
1804 RT5665_M_DAC_L2_LM_SFT, 1, 1),
1805 SOC_DAPM_SINGLE("OUTVOL L Switch", RT5665_LOUT_MIXER,
1806 RT5665_M_OV_L_LM_SFT, 1, 1),
1807};
1808
1809static const struct snd_kcontrol_new rt5665_lout_r_mix[] = {
1810 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_LOUT_MIXER,
1811 RT5665_M_DAC_R2_LM_SFT, 1, 1),
1812 SOC_DAPM_SINGLE("OUTVOL R Switch", RT5665_LOUT_MIXER,
1813 RT5665_M_OV_R_LM_SFT, 1, 1),
1814};
1815
1816/*DAC L2, DAC R2*/
1817/*MX-17 [6:4], MX-17 [2:0]*/
1818static const char * const rt5665_dac2_src[] = {
1819 "IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC", "Mono ADC MIX"
1820};
1821
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]1822static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]1823 rt5665_dac_l2_enum, RT5665_DAC2_CTRL,
1824 RT5665_DAC_L2_SEL_SFT, rt5665_dac2_src);
1825
1826static const struct snd_kcontrol_new rt5665_dac_l2_mux =
1827 SOC_DAPM_ENUM("Digital DAC L2 Source", rt5665_dac_l2_enum);
1828
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]1829static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]1830 rt5665_dac_r2_enum, RT5665_DAC2_CTRL,
1831 RT5665_DAC_R2_SEL_SFT, rt5665_dac2_src);
1832
1833static const struct snd_kcontrol_new rt5665_dac_r2_mux =
1834 SOC_DAPM_ENUM("Digital DAC R2 Source", rt5665_dac_r2_enum);
1835
1836/*DAC L3, DAC R3*/
1837/*MX-1B [6:4], MX-1B [2:0]*/
1838static const char * const rt5665_dac3_src[] = {
1839 "IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC", "STO2 ADC MIX"
1840};
1841
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]1842static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]1843 rt5665_dac_l3_enum, RT5665_DAC3_CTRL,
1844 RT5665_DAC_L3_SEL_SFT, rt5665_dac3_src);
1845
1846static const struct snd_kcontrol_new rt5665_dac_l3_mux =
1847 SOC_DAPM_ENUM("Digital DAC L3 Source", rt5665_dac_l3_enum);
1848
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]1849static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]1850 rt5665_dac_r3_enum, RT5665_DAC3_CTRL,
1851 RT5665_DAC_R3_SEL_SFT, rt5665_dac3_src);
1852
1853static const struct snd_kcontrol_new rt5665_dac_r3_mux =
1854 SOC_DAPM_ENUM("Digital DAC R3 Source", rt5665_dac_r3_enum);
1855
1856/* STO1 ADC1 Source */
1857/* MX-26 [13] [5] */
1858static const char * const rt5665_sto1_adc1_src[] = {
1859 "DD Mux", "ADC"
1860};
1861
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]1862static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]1863 rt5665_sto1_adc1l_enum, RT5665_STO1_ADC_MIXER,
1864 RT5665_STO1_ADC1L_SRC_SFT, rt5665_sto1_adc1_src);
1865
1866static const struct snd_kcontrol_new rt5665_sto1_adc1l_mux =
1867 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5665_sto1_adc1l_enum);
1868
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]1869static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]1870 rt5665_sto1_adc1r_enum, RT5665_STO1_ADC_MIXER,
1871 RT5665_STO1_ADC1R_SRC_SFT, rt5665_sto1_adc1_src);
1872
1873static const struct snd_kcontrol_new rt5665_sto1_adc1r_mux =
1874 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5665_sto1_adc1r_enum);
1875
1876/* STO1 ADC Source */
1877/* MX-26 [11:10] [3:2] */
1878static const char * const rt5665_sto1_adc_src[] = {
1879 "ADC1 L", "ADC1 R", "ADC2 L", "ADC2 R"
1880};
1881
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]1882static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]1883 rt5665_sto1_adcl_enum, RT5665_STO1_ADC_MIXER,
1884 RT5665_STO1_ADCL_SRC_SFT, rt5665_sto1_adc_src);
1885
1886static const struct snd_kcontrol_new rt5665_sto1_adcl_mux =
1887 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5665_sto1_adcl_enum);
1888
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]1889static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]1890 rt5665_sto1_adcr_enum, RT5665_STO1_ADC_MIXER,
1891 RT5665_STO1_ADCR_SRC_SFT, rt5665_sto1_adc_src);
1892
1893static const struct snd_kcontrol_new rt5665_sto1_adcr_mux =
1894 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5665_sto1_adcr_enum);
1895
1896/* STO1 ADC2 Source */
1897/* MX-26 [12] [4] */
1898static const char * const rt5665_sto1_adc2_src[] = {
1899 "DAC MIX", "DMIC"
1900};
1901
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]1902static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]1903 rt5665_sto1_adc2l_enum, RT5665_STO1_ADC_MIXER,
1904 RT5665_STO1_ADC2L_SRC_SFT, rt5665_sto1_adc2_src);
1905
1906static const struct snd_kcontrol_new rt5665_sto1_adc2l_mux =
1907 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5665_sto1_adc2l_enum);
1908
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]1909static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]1910 rt5665_sto1_adc2r_enum, RT5665_STO1_ADC_MIXER,
1911 RT5665_STO1_ADC2R_SRC_SFT, rt5665_sto1_adc2_src);
1912
1913static const struct snd_kcontrol_new rt5665_sto1_adc2r_mux =
1914 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5665_sto1_adc2r_enum);
1915
1916/* STO1 DMIC Source */
1917/* MX-26 [8] */
1918static const char * const rt5665_sto1_dmic_src[] = {
1919 "DMIC1", "DMIC2"
1920};
1921
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]1922static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]1923 rt5665_sto1_dmic_enum, RT5665_STO1_ADC_MIXER,
1924 RT5665_STO1_DMIC_SRC_SFT, rt5665_sto1_dmic_src);
1925
1926static const struct snd_kcontrol_new rt5665_sto1_dmic_mux =
1927 SOC_DAPM_ENUM("Stereo1 DMIC Mux", rt5665_sto1_dmic_enum);
1928
1929/* MX-26 [9] */
1930static const char * const rt5665_sto1_dd_l_src[] = {
1931 "STO2 DAC", "MONO DAC"
1932};
1933
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]1934static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]1935 rt5665_sto1_dd_l_enum, RT5665_STO1_ADC_MIXER,
1936 RT5665_STO1_DD_L_SRC_SFT, rt5665_sto1_dd_l_src);
1937
1938static const struct snd_kcontrol_new rt5665_sto1_dd_l_mux =
1939 SOC_DAPM_ENUM("Stereo1 DD L Source", rt5665_sto1_dd_l_enum);
1940
1941/* MX-26 [1:0] */
1942static const char * const rt5665_sto1_dd_r_src[] = {
1943 "STO2 DAC", "MONO DAC", "AEC REF"
1944};
1945
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]1946static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]1947 rt5665_sto1_dd_r_enum, RT5665_STO1_ADC_MIXER,
1948 RT5665_STO1_DD_R_SRC_SFT, rt5665_sto1_dd_r_src);
1949
1950static const struct snd_kcontrol_new rt5665_sto1_dd_r_mux =
1951 SOC_DAPM_ENUM("Stereo1 DD R Source", rt5665_sto1_dd_r_enum);
1952
1953/* MONO ADC L2 Source */
1954/* MX-27 [12] */
1955static const char * const rt5665_mono_adc_l2_src[] = {
1956 "DAC MIXL", "DMIC"
1957};
1958
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]1959static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]1960 rt5665_mono_adc_l2_enum, RT5665_MONO_ADC_MIXER,
1961 RT5665_MONO_ADC_L2_SRC_SFT, rt5665_mono_adc_l2_src);
1962
1963static const struct snd_kcontrol_new rt5665_mono_adc_l2_mux =
1964 SOC_DAPM_ENUM("Mono ADC L2 Source", rt5665_mono_adc_l2_enum);
1965
1966
1967/* MONO ADC L1 Source */
1968/* MX-27 [13] */
1969static const char * const rt5665_mono_adc_l1_src[] = {
1970 "DD Mux", "ADC"
1971};
1972
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]1973static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]1974 rt5665_mono_adc_l1_enum, RT5665_MONO_ADC_MIXER,
1975 RT5665_MONO_ADC_L1_SRC_SFT, rt5665_mono_adc_l1_src);
1976
1977static const struct snd_kcontrol_new rt5665_mono_adc_l1_mux =
1978 SOC_DAPM_ENUM("Mono ADC L1 Source", rt5665_mono_adc_l1_enum);
1979
1980/* MX-27 [9][1]*/
1981static const char * const rt5665_mono_dd_src[] = {
1982 "STO2 DAC", "MONO DAC"
1983};
1984
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]1985static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]1986 rt5665_mono_dd_l_enum, RT5665_MONO_ADC_MIXER,
1987 RT5665_MONO_DD_L_SRC_SFT, rt5665_mono_dd_src);
1988
1989static const struct snd_kcontrol_new rt5665_mono_dd_l_mux =
1990 SOC_DAPM_ENUM("Mono DD L Source", rt5665_mono_dd_l_enum);
1991
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]1992static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]1993 rt5665_mono_dd_r_enum, RT5665_MONO_ADC_MIXER,
1994 RT5665_MONO_DD_R_SRC_SFT, rt5665_mono_dd_src);
1995
1996static const struct snd_kcontrol_new rt5665_mono_dd_r_mux =
1997 SOC_DAPM_ENUM("Mono DD R Source", rt5665_mono_dd_r_enum);
1998
1999/* MONO ADC L Source, MONO ADC R Source*/
2000/* MX-27 [11:10], MX-27 [3:2] */
2001static const char * const rt5665_mono_adc_src[] = {
2002 "ADC1 L", "ADC1 R", "ADC2 L", "ADC2 R"
2003};
2004
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]2005static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]2006 rt5665_mono_adc_l_enum, RT5665_MONO_ADC_MIXER,
2007 RT5665_MONO_ADC_L_SRC_SFT, rt5665_mono_adc_src);
2008
2009static const struct snd_kcontrol_new rt5665_mono_adc_l_mux =
2010 SOC_DAPM_ENUM("Mono ADC L Source", rt5665_mono_adc_l_enum);
2011
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]2012static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]2013 rt5665_mono_adcr_enum, RT5665_MONO_ADC_MIXER,
2014 RT5665_MONO_ADC_R_SRC_SFT, rt5665_mono_adc_src);
2015
2016static const struct snd_kcontrol_new rt5665_mono_adc_r_mux =
2017 SOC_DAPM_ENUM("Mono ADC R Source", rt5665_mono_adcr_enum);
2018
2019/* MONO DMIC L Source */
2020/* MX-27 [8] */
2021static const char * const rt5665_mono_dmic_l_src[] = {
2022 "DMIC1 L", "DMIC2 L"
2023};
2024
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]2025static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]2026 rt5665_mono_dmic_l_enum, RT5665_MONO_ADC_MIXER,
2027 RT5665_MONO_DMIC_L_SRC_SFT, rt5665_mono_dmic_l_src);
2028
2029static const struct snd_kcontrol_new rt5665_mono_dmic_l_mux =
2030 SOC_DAPM_ENUM("Mono DMIC L Source", rt5665_mono_dmic_l_enum);
2031
2032/* MONO ADC R2 Source */
2033/* MX-27 [4] */
2034static const char * const rt5665_mono_adc_r2_src[] = {
2035 "DAC MIXR", "DMIC"
2036};
2037
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]2038static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]2039 rt5665_mono_adc_r2_enum, RT5665_MONO_ADC_MIXER,
2040 RT5665_MONO_ADC_R2_SRC_SFT, rt5665_mono_adc_r2_src);
2041
2042static const struct snd_kcontrol_new rt5665_mono_adc_r2_mux =
2043 SOC_DAPM_ENUM("Mono ADC R2 Source", rt5665_mono_adc_r2_enum);
2044
2045/* MONO ADC R1 Source */
2046/* MX-27 [5] */
2047static const char * const rt5665_mono_adc_r1_src[] = {
2048 "DD Mux", "ADC"
2049};
2050
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]2051static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]2052 rt5665_mono_adc_r1_enum, RT5665_MONO_ADC_MIXER,
2053 RT5665_MONO_ADC_R1_SRC_SFT, rt5665_mono_adc_r1_src);
2054
2055static const struct snd_kcontrol_new rt5665_mono_adc_r1_mux =
2056 SOC_DAPM_ENUM("Mono ADC R1 Source", rt5665_mono_adc_r1_enum);
2057
2058/* MONO DMIC R Source */
2059/* MX-27 [0] */
2060static const char * const rt5665_mono_dmic_r_src[] = {
2061 "DMIC1 R", "DMIC2 R"
2062};
2063
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]2064static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]2065 rt5665_mono_dmic_r_enum, RT5665_MONO_ADC_MIXER,
2066 RT5665_MONO_DMIC_R_SRC_SFT, rt5665_mono_dmic_r_src);
2067
2068static const struct snd_kcontrol_new rt5665_mono_dmic_r_mux =
2069 SOC_DAPM_ENUM("Mono DMIC R Source", rt5665_mono_dmic_r_enum);
2070
2071
2072/* STO2 ADC1 Source */
2073/* MX-28 [13] [5] */
2074static const char * const rt5665_sto2_adc1_src[] = {
2075 "DD Mux", "ADC"
2076};
2077
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]2078static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]2079 rt5665_sto2_adc1l_enum, RT5665_STO2_ADC_MIXER,
2080 RT5665_STO2_ADC1L_SRC_SFT, rt5665_sto2_adc1_src);
2081
2082static const struct snd_kcontrol_new rt5665_sto2_adc1l_mux =
2083 SOC_DAPM_ENUM("Stereo2 ADC1L Source", rt5665_sto2_adc1l_enum);
2084
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]2085static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]2086 rt5665_sto2_adc1r_enum, RT5665_STO2_ADC_MIXER,
2087 RT5665_STO2_ADC1R_SRC_SFT, rt5665_sto2_adc1_src);
2088
2089static const struct snd_kcontrol_new rt5665_sto2_adc1r_mux =
2090 SOC_DAPM_ENUM("Stereo2 ADC1L Source", rt5665_sto2_adc1r_enum);
2091
2092/* STO2 ADC Source */
2093/* MX-28 [11:10] [3:2] */
2094static const char * const rt5665_sto2_adc_src[] = {
2095 "ADC1 L", "ADC1 R", "ADC2 L"
2096};
2097
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]2098static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]2099 rt5665_sto2_adcl_enum, RT5665_STO2_ADC_MIXER,
2100 RT5665_STO2_ADCL_SRC_SFT, rt5665_sto2_adc_src);
2101
2102static const struct snd_kcontrol_new rt5665_sto2_adcl_mux =
2103 SOC_DAPM_ENUM("Stereo2 ADCL Source", rt5665_sto2_adcl_enum);
2104
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]2105static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]2106 rt5665_sto2_adcr_enum, RT5665_STO2_ADC_MIXER,
2107 RT5665_STO2_ADCR_SRC_SFT, rt5665_sto2_adc_src);
2108
2109static const struct snd_kcontrol_new rt5665_sto2_adcr_mux =
2110 SOC_DAPM_ENUM("Stereo2 ADCR Source", rt5665_sto2_adcr_enum);
2111
2112/* STO2 ADC2 Source */
2113/* MX-28 [12] [4] */
2114static const char * const rt5665_sto2_adc2_src[] = {
2115 "DAC MIX", "DMIC"
2116};
2117
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]2118static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]2119 rt5665_sto2_adc2l_enum, RT5665_STO2_ADC_MIXER,
2120 RT5665_STO2_ADC2L_SRC_SFT, rt5665_sto2_adc2_src);
2121
2122static const struct snd_kcontrol_new rt5665_sto2_adc2l_mux =
2123 SOC_DAPM_ENUM("Stereo2 ADC2L Source", rt5665_sto2_adc2l_enum);
2124
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]2125static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]2126 rt5665_sto2_adc2r_enum, RT5665_STO2_ADC_MIXER,
2127 RT5665_STO2_ADC2R_SRC_SFT, rt5665_sto2_adc2_src);
2128
2129static const struct snd_kcontrol_new rt5665_sto2_adc2r_mux =
2130 SOC_DAPM_ENUM("Stereo2 ADC2R Source", rt5665_sto2_adc2r_enum);
2131
2132/* STO2 DMIC Source */
2133/* MX-28 [8] */
2134static const char * const rt5665_sto2_dmic_src[] = {
2135 "DMIC1", "DMIC2"
2136};
2137
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]2138static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]2139 rt5665_sto2_dmic_enum, RT5665_STO2_ADC_MIXER,
2140 RT5665_STO2_DMIC_SRC_SFT, rt5665_sto2_dmic_src);
2141
2142static const struct snd_kcontrol_new rt5665_sto2_dmic_mux =
2143 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5665_sto2_dmic_enum);
2144
2145/* MX-28 [9] */
2146static const char * const rt5665_sto2_dd_l_src[] = {
2147 "STO2 DAC", "MONO DAC"
2148};
2149
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]2150static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]2151 rt5665_sto2_dd_l_enum, RT5665_STO2_ADC_MIXER,
2152 RT5665_STO2_DD_L_SRC_SFT, rt5665_sto2_dd_l_src);
2153
2154static const struct snd_kcontrol_new rt5665_sto2_dd_l_mux =
2155 SOC_DAPM_ENUM("Stereo2 DD L Source", rt5665_sto2_dd_l_enum);
2156
2157/* MX-28 [1] */
2158static const char * const rt5665_sto2_dd_r_src[] = {
2159 "STO2 DAC", "MONO DAC"
2160};
2161
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]2162static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]2163 rt5665_sto2_dd_r_enum, RT5665_STO2_ADC_MIXER,
2164 RT5665_STO2_DD_R_SRC_SFT, rt5665_sto2_dd_r_src);
2165
2166static const struct snd_kcontrol_new rt5665_sto2_dd_r_mux =
2167 SOC_DAPM_ENUM("Stereo2 DD R Source", rt5665_sto2_dd_r_enum);
2168
2169/* DAC R1 Source, DAC L1 Source*/
2170/* MX-29 [11:10], MX-29 [9:8]*/
2171static const char * const rt5665_dac1_src[] = {
2172 "IF1 DAC1", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC"
2173};
2174
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]2175static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]2176 rt5665_dac_r1_enum, RT5665_AD_DA_MIXER,
2177 RT5665_DAC1_R_SEL_SFT, rt5665_dac1_src);
2178
2179static const struct snd_kcontrol_new rt5665_dac_r1_mux =
2180 SOC_DAPM_ENUM("DAC R1 Source", rt5665_dac_r1_enum);
2181
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]2182static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]2183 rt5665_dac_l1_enum, RT5665_AD_DA_MIXER,
2184 RT5665_DAC1_L_SEL_SFT, rt5665_dac1_src);
2185
2186static const struct snd_kcontrol_new rt5665_dac_l1_mux =
2187 SOC_DAPM_ENUM("DAC L1 Source", rt5665_dac_l1_enum);
2188
2189/* DAC Digital Mixer L Source, DAC Digital Mixer R Source*/
2190/* MX-2D [13:12], MX-2D [9:8]*/
2191static const char * const rt5665_dig_dac_mix_src[] = {
2192 "Stereo1 DAC Mixer", "Stereo2 DAC Mixer", "Mono DAC Mixer"
2193};
2194
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]2195static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]2196 rt5665_dig_dac_mixl_enum, RT5665_A_DAC1_MUX,
2197 RT5665_DAC_MIX_L_SFT, rt5665_dig_dac_mix_src);
2198
2199static const struct snd_kcontrol_new rt5665_dig_dac_mixl_mux =
2200 SOC_DAPM_ENUM("DAC Digital Mixer L Source", rt5665_dig_dac_mixl_enum);
2201
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]2202static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]2203 rt5665_dig_dac_mixr_enum, RT5665_A_DAC1_MUX,
2204 RT5665_DAC_MIX_R_SFT, rt5665_dig_dac_mix_src);
2205
2206static const struct snd_kcontrol_new rt5665_dig_dac_mixr_mux =
2207 SOC_DAPM_ENUM("DAC Digital Mixer R Source", rt5665_dig_dac_mixr_enum);
2208
2209/* Analog DAC L1 Source, Analog DAC R1 Source*/
2210/* MX-2D [5:4], MX-2D [1:0]*/
2211static const char * const rt5665_alg_dac1_src[] = {
2212 "Stereo1 DAC Mixer", "DAC1", "DMIC1"
2213};
2214
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]2215static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]2216 rt5665_alg_dac_l1_enum, RT5665_A_DAC1_MUX,
2217 RT5665_A_DACL1_SFT, rt5665_alg_dac1_src);
2218
2219static const struct snd_kcontrol_new rt5665_alg_dac_l1_mux =
2220 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5665_alg_dac_l1_enum);
2221
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]2222static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]2223 rt5665_alg_dac_r1_enum, RT5665_A_DAC1_MUX,
2224 RT5665_A_DACR1_SFT, rt5665_alg_dac1_src);
2225
2226static const struct snd_kcontrol_new rt5665_alg_dac_r1_mux =
2227 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5665_alg_dac_r1_enum);
2228
2229/* Analog DAC LR Source, Analog DAC R2 Source*/
2230/* MX-2E [5:4], MX-2E [0]*/
2231static const char * const rt5665_alg_dac2_src[] = {
2232 "Mono DAC Mixer", "DAC2"
2233};
2234
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]2235static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]2236 rt5665_alg_dac_l2_enum, RT5665_A_DAC2_MUX,
2237 RT5665_A_DACL2_SFT, rt5665_alg_dac2_src);
2238
2239static const struct snd_kcontrol_new rt5665_alg_dac_l2_mux =
2240 SOC_DAPM_ENUM("Analog DAC L2 Source", rt5665_alg_dac_l2_enum);
2241
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]2242static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]2243 rt5665_alg_dac_r2_enum, RT5665_A_DAC2_MUX,
2244 RT5665_A_DACR2_SFT, rt5665_alg_dac2_src);
2245
2246static const struct snd_kcontrol_new rt5665_alg_dac_r2_mux =
2247 SOC_DAPM_ENUM("Analog DAC R2 Source", rt5665_alg_dac_r2_enum);
2248
2249/* Interface2 ADC Data Input*/
2250/* MX-2F [14:12] */
2251static const char * const rt5665_if2_1_adc_in_src[] = {
2252 "STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1",
2253 "IF1 DAC2", "IF2_2 DAC", "IF3 DAC", "DAC1 MIX"
2254};
2255
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]2256static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]2257 rt5665_if2_1_adc_in_enum, RT5665_DIG_INF2_DATA,
Bard Liao83749ab2017-03-20 10:20:53 +0800[diff] [blame]2258 RT5665_IF2_1_ADC_IN_SFT, rt5665_if2_1_adc_in_src);
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]2259
2260static const struct snd_kcontrol_new rt5665_if2_1_adc_in_mux =
2261 SOC_DAPM_ENUM("IF2_1 ADC IN Source", rt5665_if2_1_adc_in_enum);
2262
2263/* MX-2F [6:4] */
2264static const char * const rt5665_if2_2_adc_in_src[] = {
2265 "STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1",
2266 "IF1 DAC2", "IF2_1 DAC", "IF3 DAC", "DAC1 MIX"
2267};
2268
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]2269static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]2270 rt5665_if2_2_adc_in_enum, RT5665_DIG_INF2_DATA,
2271 RT5665_IF2_2_ADC_IN_SFT, rt5665_if2_2_adc_in_src);
2272
2273static const struct snd_kcontrol_new rt5665_if2_2_adc_in_mux =
2274 SOC_DAPM_ENUM("IF2_1 ADC IN Source", rt5665_if2_2_adc_in_enum);
2275
2276/* Interface3 ADC Data Input*/
2277/* MX-30 [6:4] */
2278static const char * const rt5665_if3_adc_in_src[] = {
2279 "STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1",
2280 "IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "DAC1 MIX"
2281};
2282
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]2283static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]2284 rt5665_if3_adc_in_enum, RT5665_DIG_INF3_DATA,
2285 RT5665_IF3_ADC_IN_SFT, rt5665_if3_adc_in_src);
2286
2287static const struct snd_kcontrol_new rt5665_if3_adc_in_mux =
2288 SOC_DAPM_ENUM("IF3 ADC IN Source", rt5665_if3_adc_in_enum);
2289
2290/* PDM 1 L/R*/
2291/* MX-31 [11:10] [9:8] */
2292static const char * const rt5665_pdm_src[] = {
2293 "Stereo1 DAC", "Stereo2 DAC", "Mono DAC"
2294};
2295
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]2296static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]2297 rt5665_pdm_l_enum, RT5665_PDM_OUT_CTRL,
2298 RT5665_PDM1_L_SFT, rt5665_pdm_src);
2299
2300static const struct snd_kcontrol_new rt5665_pdm_l_mux =
2301 SOC_DAPM_ENUM("PDM L Source", rt5665_pdm_l_enum);
2302
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]2303static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]2304 rt5665_pdm_r_enum, RT5665_PDM_OUT_CTRL,
2305 RT5665_PDM1_R_SFT, rt5665_pdm_src);
2306
2307static const struct snd_kcontrol_new rt5665_pdm_r_mux =
2308 SOC_DAPM_ENUM("PDM R Source", rt5665_pdm_r_enum);
2309
2310
2311/* I2S1 TDM ADCDAT Source */
2312/* MX-7a[10] */
2313static const char * const rt5665_if1_1_adc1_data_src[] = {
2314 "STO1 ADC", "IF2_1 DAC",
2315};
2316
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]2317static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]2318 rt5665_if1_1_adc1_data_enum, RT5665_TDM_CTRL_3,
2319 RT5665_IF1_ADC1_SEL_SFT, rt5665_if1_1_adc1_data_src);
2320
2321static const struct snd_kcontrol_new rt5665_if1_1_adc1_mux =
2322 SOC_DAPM_ENUM("IF1_1 ADC1 Source", rt5665_if1_1_adc1_data_enum);
2323
2324/* MX-7a[9] */
2325static const char * const rt5665_if1_1_adc2_data_src[] = {
2326 "STO2 ADC", "IF2_2 DAC",
2327};
2328
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]2329static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]2330 rt5665_if1_1_adc2_data_enum, RT5665_TDM_CTRL_3,
2331 RT5665_IF1_ADC2_SEL_SFT, rt5665_if1_1_adc2_data_src);
2332
2333static const struct snd_kcontrol_new rt5665_if1_1_adc2_mux =
2334 SOC_DAPM_ENUM("IF1_1 ADC2 Source", rt5665_if1_1_adc2_data_enum);
2335
2336/* MX-7a[8] */
2337static const char * const rt5665_if1_1_adc3_data_src[] = {
2338 "MONO ADC", "IF3 DAC",
2339};
2340
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]2341static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]2342 rt5665_if1_1_adc3_data_enum, RT5665_TDM_CTRL_3,
2343 RT5665_IF1_ADC3_SEL_SFT, rt5665_if1_1_adc3_data_src);
2344
2345static const struct snd_kcontrol_new rt5665_if1_1_adc3_mux =
2346 SOC_DAPM_ENUM("IF1_1 ADC3 Source", rt5665_if1_1_adc3_data_enum);
2347
2348/* MX-7b[10] */
2349static const char * const rt5665_if1_2_adc1_data_src[] = {
2350 "STO1 ADC", "IF1 DAC",
2351};
2352
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]2353static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]2354 rt5665_if1_2_adc1_data_enum, RT5665_TDM_CTRL_4,
2355 RT5665_IF1_ADC1_SEL_SFT, rt5665_if1_2_adc1_data_src);
2356
2357static const struct snd_kcontrol_new rt5665_if1_2_adc1_mux =
2358 SOC_DAPM_ENUM("IF1_2 ADC1 Source", rt5665_if1_2_adc1_data_enum);
2359
2360/* MX-7b[9] */
2361static const char * const rt5665_if1_2_adc2_data_src[] = {
2362 "STO2 ADC", "IF2_1 DAC",
2363};
2364
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]2365static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]2366 rt5665_if1_2_adc2_data_enum, RT5665_TDM_CTRL_4,
2367 RT5665_IF1_ADC2_SEL_SFT, rt5665_if1_2_adc2_data_src);
2368
2369static const struct snd_kcontrol_new rt5665_if1_2_adc2_mux =
2370 SOC_DAPM_ENUM("IF1_2 ADC2 Source", rt5665_if1_2_adc2_data_enum);
2371
2372/* MX-7b[8] */
2373static const char * const rt5665_if1_2_adc3_data_src[] = {
2374 "MONO ADC", "IF2_2 DAC",
2375};
2376
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]2377static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]2378 rt5665_if1_2_adc3_data_enum, RT5665_TDM_CTRL_4,
2379 RT5665_IF1_ADC3_SEL_SFT, rt5665_if1_2_adc3_data_src);
2380
2381static const struct snd_kcontrol_new rt5665_if1_2_adc3_mux =
2382 SOC_DAPM_ENUM("IF1_2 ADC3 Source", rt5665_if1_2_adc3_data_enum);
2383
2384/* MX-7b[7] */
2385static const char * const rt5665_if1_2_adc4_data_src[] = {
2386 "DAC1", "IF3 DAC",
2387};
2388
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]2389static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]2390 rt5665_if1_2_adc4_data_enum, RT5665_TDM_CTRL_4,
2391 RT5665_IF1_ADC4_SEL_SFT, rt5665_if1_2_adc4_data_src);
2392
2393static const struct snd_kcontrol_new rt5665_if1_2_adc4_mux =
2394 SOC_DAPM_ENUM("IF1_2 ADC4 Source", rt5665_if1_2_adc4_data_enum);
2395
2396/* MX-7a[4:0] MX-7b[4:0] */
2397static const char * const rt5665_tdm_adc_data_src[] = {
2398 "1234", "1243", "1324", "1342", "1432", "1423",
2399 "2134", "2143", "2314", "2341", "2431", "2413",
2400 "3124", "3142", "3214", "3241", "3412", "3421",
2401 "4123", "4132", "4213", "4231", "4312", "4321"
2402};
2403
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]2404static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]2405 rt5665_tdm1_adc_data_enum, RT5665_TDM_CTRL_3,
2406 RT5665_TDM_ADC_SEL_SFT, rt5665_tdm_adc_data_src);
2407
2408static const struct snd_kcontrol_new rt5665_tdm1_adc_mux =
2409 SOC_DAPM_ENUM("TDM1 ADC Mux", rt5665_tdm1_adc_data_enum);
2410
Arnd Bergmann27a655c2017-05-11 13:44:39 +0200[diff] [blame]2411static SOC_ENUM_SINGLE_DECL(
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]2412 rt5665_tdm2_adc_data_enum, RT5665_TDM_CTRL_4,
2413 RT5665_TDM_ADC_SEL_SFT, rt5665_tdm_adc_data_src);
2414
2415static const struct snd_kcontrol_new rt5665_tdm2_adc_mux =
2416 SOC_DAPM_ENUM("TDM2 ADCDAT Source", rt5665_tdm2_adc_data_enum);
2417
2418/* Out Volume Switch */
2419static const struct snd_kcontrol_new monovol_switch =
2420 SOC_DAPM_SINGLE("Switch", RT5665_MONO_OUT, RT5665_VOL_L_SFT, 1, 1);
2421
2422static const struct snd_kcontrol_new outvol_l_switch =
2423 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_VOL_L_SFT, 1, 1);
2424
2425static const struct snd_kcontrol_new outvol_r_switch =
2426 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_VOL_R_SFT, 1, 1);
2427
2428/* Out Switch */
2429static const struct snd_kcontrol_new mono_switch =
2430 SOC_DAPM_SINGLE("Switch", RT5665_MONO_OUT, RT5665_L_MUTE_SFT, 1, 1);
2431
2432static const struct snd_kcontrol_new hpo_switch =
2433 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5665_HP_CTRL_2,
2434 RT5665_VOL_L_SFT, 1, 0);
2435
2436static const struct snd_kcontrol_new lout_l_switch =
2437 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_L_MUTE_SFT, 1, 1);
2438
2439static const struct snd_kcontrol_new lout_r_switch =
2440 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_R_MUTE_SFT, 1, 1);
2441
2442static const struct snd_kcontrol_new pdm_l_switch =
2443 SOC_DAPM_SINGLE("Switch", RT5665_PDM_OUT_CTRL,
2444 RT5665_M_PDM1_L_SFT, 1, 1);
2445
2446static const struct snd_kcontrol_new pdm_r_switch =
2447 SOC_DAPM_SINGLE("Switch", RT5665_PDM_OUT_CTRL,
2448 RT5665_M_PDM1_R_SFT, 1, 1);
2449
2450static int rt5665_mono_event(struct snd_soc_dapm_widget *w,
2451 struct snd_kcontrol *kcontrol, int event)
2452{
2453 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2454
2455 switch (event) {
2456 case SND_SOC_DAPM_PRE_PMU:
2457 snd_soc_update_bits(codec, RT5665_MONO_NG2_CTRL_1,
2458 RT5665_NG2_EN_MASK, RT5665_NG2_EN);
2459 snd_soc_update_bits(codec, RT5665_MONO_AMP_CALIB_CTRL_1, 0x40,
2460 0x0);
2461 snd_soc_update_bits(codec, RT5665_MONO_OUT, 0x10, 0x10);
2462 snd_soc_update_bits(codec, RT5665_MONO_OUT, 0x20, 0x20);
2463 break;
2464
2465 case SND_SOC_DAPM_POST_PMD:
2466 snd_soc_update_bits(codec, RT5665_MONO_OUT, 0x20, 0);
2467 snd_soc_update_bits(codec, RT5665_MONO_OUT, 0x10, 0);
2468 snd_soc_update_bits(codec, RT5665_MONO_AMP_CALIB_CTRL_1, 0x40,
2469 0x40);
2470 snd_soc_update_bits(codec, RT5665_MONO_NG2_CTRL_1,
2471 RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
2472 break;
2473
2474 default:
2475 return 0;
2476 }
2477
2478 return 0;
2479
2480}
2481
2482static int rt5665_hp_event(struct snd_soc_dapm_widget *w,
2483 struct snd_kcontrol *kcontrol, int event)
2484{
2485 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2486
2487 switch (event) {
2488 case SND_SOC_DAPM_PRE_PMU:
2489 snd_soc_update_bits(codec, RT5665_STO_NG2_CTRL_1,
2490 RT5665_NG2_EN_MASK, RT5665_NG2_EN);
2491 snd_soc_write(codec, RT5665_HP_LOGIC_CTRL_2, 0x0003);
2492 break;
2493
2494 case SND_SOC_DAPM_POST_PMD:
2495 snd_soc_write(codec, RT5665_HP_LOGIC_CTRL_2, 0x0002);
2496 snd_soc_update_bits(codec, RT5665_STO_NG2_CTRL_1,
2497 RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
2498 break;
2499
2500 default:
2501 return 0;
2502 }
2503
2504 return 0;
2505
2506}
2507
2508static int rt5665_lout_event(struct snd_soc_dapm_widget *w,
2509 struct snd_kcontrol *kcontrol, int event)
2510{
2511 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2512
2513 switch (event) {
2514 case SND_SOC_DAPM_POST_PMU:
2515 snd_soc_update_bits(codec, RT5665_DEPOP_1,
2516 RT5665_PUMP_EN, RT5665_PUMP_EN);
2517 break;
2518
2519 case SND_SOC_DAPM_PRE_PMD:
2520 snd_soc_update_bits(codec, RT5665_DEPOP_1,
2521 RT5665_PUMP_EN, 0);
2522 break;
2523
2524 default:
2525 return 0;
2526 }
2527
2528 return 0;
2529
2530}
2531
2532static int set_dmic_power(struct snd_soc_dapm_widget *w,
2533 struct snd_kcontrol *kcontrol, int event)
2534{
2535 switch (event) {
2536 case SND_SOC_DAPM_POST_PMU:
2537 /*Add delay to avoid pop noise*/
2538 msleep(150);
2539 break;
2540
2541 default:
2542 return 0;
2543 }
2544
2545 return 0;
2546}
2547
2548static int rt5655_set_verf(struct snd_soc_dapm_widget *w,
2549 struct snd_kcontrol *kcontrol, int event)
2550{
2551 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2552
2553 switch (event) {
2554 case SND_SOC_DAPM_PRE_PMU:
2555 switch (w->shift) {
2556 case RT5665_PWR_VREF1_BIT:
2557 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2558 RT5665_PWR_FV1, 0);
2559 break;
2560
2561 case RT5665_PWR_VREF2_BIT:
2562 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2563 RT5665_PWR_FV2, 0);
2564 break;
2565
2566 case RT5665_PWR_VREF3_BIT:
2567 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2568 RT5665_PWR_FV3, 0);
2569 break;
2570
2571 default:
2572 break;
2573 }
2574 break;
2575
2576 case SND_SOC_DAPM_POST_PMU:
2577 usleep_range(15000, 20000);
2578 switch (w->shift) {
2579 case RT5665_PWR_VREF1_BIT:
2580 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2581 RT5665_PWR_FV1, RT5665_PWR_FV1);
2582 break;
2583
2584 case RT5665_PWR_VREF2_BIT:
2585 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2586 RT5665_PWR_FV2, RT5665_PWR_FV2);
2587 break;
2588
2589 case RT5665_PWR_VREF3_BIT:
2590 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2591 RT5665_PWR_FV3, RT5665_PWR_FV3);
2592 break;
2593
2594 default:
2595 break;
2596 }
2597 break;
2598
2599 default:
2600 return 0;
2601 }
2602
2603 return 0;
2604}
2605
Bard Liao9b5d3862017-03-16 13:58:41 +0800[diff] [blame]2606static int rt5665_i2s_pin_event(struct snd_soc_dapm_widget *w,
2607 struct snd_kcontrol *kcontrol, int event)
2608{
2609 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2610 unsigned int val1, val2, mask1, mask2 = 0;
2611
2612 switch (w->shift) {
2613 case RT5665_PWR_I2S2_1_BIT:
2614 mask1 = RT5665_GP2_PIN_MASK | RT5665_GP3_PIN_MASK |
2615 RT5665_GP4_PIN_MASK | RT5665_GP5_PIN_MASK;
2616 val1 = RT5665_GP2_PIN_BCLK2 | RT5665_GP3_PIN_LRCK2 |
2617 RT5665_GP4_PIN_DACDAT2_1 | RT5665_GP5_PIN_ADCDAT2_1;
2618 break;
2619 case RT5665_PWR_I2S2_2_BIT:
2620 mask1 = RT5665_GP2_PIN_MASK | RT5665_GP3_PIN_MASK |
2621 RT5665_GP8_PIN_MASK;
2622 val1 = RT5665_GP2_PIN_BCLK2 | RT5665_GP3_PIN_LRCK2 |
2623 RT5665_GP8_PIN_DACDAT2_2;
2624 mask2 = RT5665_GP9_PIN_MASK;
2625 val2 = RT5665_GP9_PIN_ADCDAT2_2;
2626 break;
2627 case RT5665_PWR_I2S3_BIT:
2628 mask1 = RT5665_GP6_PIN_MASK | RT5665_GP7_PIN_MASK |
2629 RT5665_GP8_PIN_MASK;
2630 val1 = RT5665_GP6_PIN_BCLK3 | RT5665_GP7_PIN_LRCK3 |
2631 RT5665_GP8_PIN_DACDAT3;
2632 mask2 = RT5665_GP9_PIN_MASK;
2633 val2 = RT5665_GP9_PIN_ADCDAT3;
2634 break;
2635 }
2636 switch (event) {
2637 case SND_SOC_DAPM_PRE_PMU:
2638 snd_soc_update_bits(codec, RT5665_GPIO_CTRL_1, mask1, val1);
2639 if (mask2)
2640 snd_soc_update_bits(codec, RT5665_GPIO_CTRL_2,
2641 mask2, val2);
2642 break;
2643 case SND_SOC_DAPM_POST_PMD:
2644 snd_soc_update_bits(codec, RT5665_GPIO_CTRL_1, mask1, 0);
2645 if (mask2)
2646 snd_soc_update_bits(codec, RT5665_GPIO_CTRL_2,
2647 mask2, 0);
2648 break;
2649 default:
2650 return 0;
2651 }
2652
2653 return 0;
2654}
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]2655
2656static const struct snd_soc_dapm_widget rt5665_dapm_widgets[] = {
2657 SND_SOC_DAPM_SUPPLY("LDO2", RT5665_PWR_ANLG_3, RT5665_PWR_LDO2_BIT, 0,
2658 NULL, 0),
2659 SND_SOC_DAPM_SUPPLY("PLL", RT5665_PWR_ANLG_3, RT5665_PWR_PLL_BIT, 0,
2660 NULL, 0),
2661 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5665_PWR_VOL,
2662 RT5665_PWR_MIC_DET_BIT, 0, NULL, 0),
2663 SND_SOC_DAPM_SUPPLY("Vref1", RT5665_PWR_ANLG_1, RT5665_PWR_VREF1_BIT, 0,
2664 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
2665 SND_SOC_DAPM_SUPPLY("Vref2", RT5665_PWR_ANLG_1, RT5665_PWR_VREF2_BIT, 0,
2666 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
2667 SND_SOC_DAPM_SUPPLY("Vref3", RT5665_PWR_ANLG_1, RT5665_PWR_VREF3_BIT, 0,
2668 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
2669
2670 /* ASRC */
2671 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5665_ASRC_1,
2672 RT5665_I2S1_ASRC_SFT, 0, NULL, 0),
2673 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5665_ASRC_1,
2674 RT5665_I2S2_ASRC_SFT, 0, NULL, 0),
2675 SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5665_ASRC_1,
2676 RT5665_I2S3_ASRC_SFT, 0, NULL, 0),
2677 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5665_ASRC_1,
2678 RT5665_DAC_STO1_ASRC_SFT, 0, NULL, 0),
2679 SND_SOC_DAPM_SUPPLY_S("DAC STO2 ASRC", 1, RT5665_ASRC_1,
2680 RT5665_DAC_STO2_ASRC_SFT, 0, NULL, 0),
2681 SND_SOC_DAPM_SUPPLY_S("DAC Mono L ASRC", 1, RT5665_ASRC_1,
2682 RT5665_DAC_MONO_L_ASRC_SFT, 0, NULL, 0),
2683 SND_SOC_DAPM_SUPPLY_S("DAC Mono R ASRC", 1, RT5665_ASRC_1,
2684 RT5665_DAC_MONO_R_ASRC_SFT, 0, NULL, 0),
2685 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5665_ASRC_1,
2686 RT5665_ADC_STO1_ASRC_SFT, 0, NULL, 0),
Bard Liao30b7d882017-05-02 11:00:39 +0800[diff] [blame^]2687 SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC", 1, RT5665_ASRC_1,
2688 RT5665_ADC_STO2_ASRC_SFT, 0, NULL, 0),
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]2689 SND_SOC_DAPM_SUPPLY_S("ADC Mono L ASRC", 1, RT5665_ASRC_1,
2690 RT5665_ADC_MONO_L_ASRC_SFT, 0, NULL, 0),
2691 SND_SOC_DAPM_SUPPLY_S("ADC Mono R ASRC", 1, RT5665_ASRC_1,
2692 RT5665_ADC_MONO_R_ASRC_SFT, 0, NULL, 0),
2693 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5665_ASRC_1,
2694 RT5665_DMIC_STO1_ASRC_SFT, 0, NULL, 0),
2695 SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5665_ASRC_1,
2696 RT5665_DMIC_STO2_ASRC_SFT, 0, NULL, 0),
2697 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5665_ASRC_1,
2698 RT5665_DMIC_MONO_L_ASRC_SFT, 0, NULL, 0),
2699 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5665_ASRC_1,
2700 RT5665_DMIC_MONO_R_ASRC_SFT, 0, NULL, 0),
2701
2702 /* Input Side */
2703 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5665_PWR_ANLG_2, RT5665_PWR_MB1_BIT,
2704 0, NULL, 0),
2705 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5665_PWR_ANLG_2, RT5665_PWR_MB2_BIT,
2706 0, NULL, 0),
2707 SND_SOC_DAPM_SUPPLY("MICBIAS3", RT5665_PWR_ANLG_2, RT5665_PWR_MB3_BIT,
2708 0, NULL, 0),
2709
2710 /* Input Lines */
2711 SND_SOC_DAPM_INPUT("DMIC L1"),
2712 SND_SOC_DAPM_INPUT("DMIC R1"),
2713 SND_SOC_DAPM_INPUT("DMIC L2"),
2714 SND_SOC_DAPM_INPUT("DMIC R2"),
2715
2716 SND_SOC_DAPM_INPUT("IN1P"),
2717 SND_SOC_DAPM_INPUT("IN1N"),
2718 SND_SOC_DAPM_INPUT("IN2P"),
2719 SND_SOC_DAPM_INPUT("IN2N"),
2720 SND_SOC_DAPM_INPUT("IN3P"),
2721 SND_SOC_DAPM_INPUT("IN3N"),
2722 SND_SOC_DAPM_INPUT("IN4P"),
2723 SND_SOC_DAPM_INPUT("IN4N"),
2724
2725 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2726 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2727
2728 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2729 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2730 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5665_DMIC_CTRL_1,
2731 RT5665_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
2732 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5665_DMIC_CTRL_1,
2733 RT5665_DMIC_2_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
2734
2735 /* Boost */
2736 SND_SOC_DAPM_PGA("BST1", SND_SOC_NOPM,
2737 0, 0, NULL, 0),
2738 SND_SOC_DAPM_PGA("BST2", SND_SOC_NOPM,
2739 0, 0, NULL, 0),
2740 SND_SOC_DAPM_PGA("BST3", SND_SOC_NOPM,
2741 0, 0, NULL, 0),
2742 SND_SOC_DAPM_PGA("BST4", SND_SOC_NOPM,
2743 0, 0, NULL, 0),
2744 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM,
2745 0, 0, NULL, 0),
2746 SND_SOC_DAPM_SUPPLY("BST1 Power", RT5665_PWR_ANLG_2,
2747 RT5665_PWR_BST1_BIT, 0, NULL, 0),
2748 SND_SOC_DAPM_SUPPLY("BST2 Power", RT5665_PWR_ANLG_2,
2749 RT5665_PWR_BST2_BIT, 0, NULL, 0),
2750 SND_SOC_DAPM_SUPPLY("BST3 Power", RT5665_PWR_ANLG_2,
2751 RT5665_PWR_BST3_BIT, 0, NULL, 0),
2752 SND_SOC_DAPM_SUPPLY("BST4 Power", RT5665_PWR_ANLG_2,
2753 RT5665_PWR_BST4_BIT, 0, NULL, 0),
2754 SND_SOC_DAPM_SUPPLY("BST1P Power", RT5665_PWR_ANLG_2,
2755 RT5665_PWR_BST1_P_BIT, 0, NULL, 0),
2756 SND_SOC_DAPM_SUPPLY("BST2P Power", RT5665_PWR_ANLG_2,
2757 RT5665_PWR_BST2_P_BIT, 0, NULL, 0),
2758 SND_SOC_DAPM_SUPPLY("BST3P Power", RT5665_PWR_ANLG_2,
2759 RT5665_PWR_BST3_P_BIT, 0, NULL, 0),
2760 SND_SOC_DAPM_SUPPLY("BST4P Power", RT5665_PWR_ANLG_2,
2761 RT5665_PWR_BST4_P_BIT, 0, NULL, 0),
2762 SND_SOC_DAPM_SUPPLY("CBJ Power", RT5665_PWR_ANLG_3,
2763 RT5665_PWR_CBJ_BIT, 0, NULL, 0),
2764
2765
2766 /* Input Volume */
2767 SND_SOC_DAPM_PGA("INL VOL", RT5665_PWR_VOL, RT5665_PWR_IN_L_BIT,
2768 0, NULL, 0),
2769 SND_SOC_DAPM_PGA("INR VOL", RT5665_PWR_VOL, RT5665_PWR_IN_R_BIT,
2770 0, NULL, 0),
2771
2772 /* REC Mixer */
2773 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5665_rec1_l_mix,
2774 ARRAY_SIZE(rt5665_rec1_l_mix)),
2775 SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5665_rec1_r_mix,
2776 ARRAY_SIZE(rt5665_rec1_r_mix)),
2777 SND_SOC_DAPM_MIXER("RECMIX2L", SND_SOC_NOPM, 0, 0, rt5665_rec2_l_mix,
2778 ARRAY_SIZE(rt5665_rec2_l_mix)),
2779 SND_SOC_DAPM_MIXER("RECMIX2R", SND_SOC_NOPM, 0, 0, rt5665_rec2_r_mix,
2780 ARRAY_SIZE(rt5665_rec2_r_mix)),
2781 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5665_PWR_ANLG_2,
2782 RT5665_PWR_RM1_L_BIT, 0, NULL, 0),
2783 SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5665_PWR_ANLG_2,
2784 RT5665_PWR_RM1_R_BIT, 0, NULL, 0),
2785 SND_SOC_DAPM_SUPPLY("RECMIX2L Power", RT5665_PWR_MIXER,
2786 RT5665_PWR_RM2_L_BIT, 0, NULL, 0),
2787 SND_SOC_DAPM_SUPPLY("RECMIX2R Power", RT5665_PWR_MIXER,
2788 RT5665_PWR_RM2_R_BIT, 0, NULL, 0),
2789
2790 /* ADCs */
2791 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
2792 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
2793 SND_SOC_DAPM_ADC("ADC2 L", NULL, SND_SOC_NOPM, 0, 0),
2794 SND_SOC_DAPM_ADC("ADC2 R", NULL, SND_SOC_NOPM, 0, 0),
2795
2796 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5665_PWR_DIG_1,
2797 RT5665_PWR_ADC_L1_BIT, 0, NULL, 0),
2798 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5665_PWR_DIG_1,
2799 RT5665_PWR_ADC_R1_BIT, 0, NULL, 0),
2800 SND_SOC_DAPM_SUPPLY("ADC2 L Power", RT5665_PWR_DIG_1,
2801 RT5665_PWR_ADC_L2_BIT, 0, NULL, 0),
2802 SND_SOC_DAPM_SUPPLY("ADC2 R Power", RT5665_PWR_DIG_1,
2803 RT5665_PWR_ADC_R2_BIT, 0, NULL, 0),
2804 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5665_CHOP_ADC,
2805 RT5665_CKGEN_ADC1_SFT, 0, NULL, 0),
2806 SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5665_CHOP_ADC,
2807 RT5665_CKGEN_ADC2_SFT, 0, NULL, 0),
2808
2809 /* ADC Mux */
2810 SND_SOC_DAPM_MUX("Stereo1 DMIC L Mux", SND_SOC_NOPM, 0, 0,
2811 &rt5665_sto1_dmic_mux),
2812 SND_SOC_DAPM_MUX("Stereo1 DMIC R Mux", SND_SOC_NOPM, 0, 0,
2813 &rt5665_sto1_dmic_mux),
2814 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2815 &rt5665_sto1_adc1l_mux),
2816 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2817 &rt5665_sto1_adc1r_mux),
2818 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2819 &rt5665_sto1_adc2l_mux),
2820 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2821 &rt5665_sto1_adc2r_mux),
2822 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
2823 &rt5665_sto1_adcl_mux),
2824 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
2825 &rt5665_sto1_adcr_mux),
2826 SND_SOC_DAPM_MUX("Stereo1 DD L Mux", SND_SOC_NOPM, 0, 0,
2827 &rt5665_sto1_dd_l_mux),
2828 SND_SOC_DAPM_MUX("Stereo1 DD R Mux", SND_SOC_NOPM, 0, 0,
2829 &rt5665_sto1_dd_r_mux),
2830 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2831 &rt5665_mono_adc_l2_mux),
2832 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2833 &rt5665_mono_adc_r2_mux),
2834 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2835 &rt5665_mono_adc_l1_mux),
2836 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2837 &rt5665_mono_adc_r1_mux),
2838 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2839 &rt5665_mono_dmic_l_mux),
2840 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2841 &rt5665_mono_dmic_r_mux),
2842 SND_SOC_DAPM_MUX("Mono ADC L Mux", SND_SOC_NOPM, 0, 0,
2843 &rt5665_mono_adc_l_mux),
2844 SND_SOC_DAPM_MUX("Mono ADC R Mux", SND_SOC_NOPM, 0, 0,
2845 &rt5665_mono_adc_r_mux),
2846 SND_SOC_DAPM_MUX("Mono DD L Mux", SND_SOC_NOPM, 0, 0,
2847 &rt5665_mono_dd_l_mux),
2848 SND_SOC_DAPM_MUX("Mono DD R Mux", SND_SOC_NOPM, 0, 0,
2849 &rt5665_mono_dd_r_mux),
2850 SND_SOC_DAPM_MUX("Stereo2 DMIC L Mux", SND_SOC_NOPM, 0, 0,
2851 &rt5665_sto2_dmic_mux),
2852 SND_SOC_DAPM_MUX("Stereo2 DMIC R Mux", SND_SOC_NOPM, 0, 0,
2853 &rt5665_sto2_dmic_mux),
2854 SND_SOC_DAPM_MUX("Stereo2 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2855 &rt5665_sto2_adc1l_mux),
2856 SND_SOC_DAPM_MUX("Stereo2 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2857 &rt5665_sto2_adc1r_mux),
2858 SND_SOC_DAPM_MUX("Stereo2 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2859 &rt5665_sto2_adc2l_mux),
2860 SND_SOC_DAPM_MUX("Stereo2 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2861 &rt5665_sto2_adc2r_mux),
2862 SND_SOC_DAPM_MUX("Stereo2 ADC L Mux", SND_SOC_NOPM, 0, 0,
2863 &rt5665_sto2_adcl_mux),
2864 SND_SOC_DAPM_MUX("Stereo2 ADC R Mux", SND_SOC_NOPM, 0, 0,
2865 &rt5665_sto2_adcr_mux),
2866 SND_SOC_DAPM_MUX("Stereo2 DD L Mux", SND_SOC_NOPM, 0, 0,
2867 &rt5665_sto2_dd_l_mux),
2868 SND_SOC_DAPM_MUX("Stereo2 DD R Mux", SND_SOC_NOPM, 0, 0,
2869 &rt5665_sto2_dd_r_mux),
2870 /* ADC Mixer */
2871 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5665_PWR_DIG_2,
2872 RT5665_PWR_ADC_S1F_BIT, 0, NULL, 0),
2873 SND_SOC_DAPM_SUPPLY("ADC Stereo2 Filter", RT5665_PWR_DIG_2,
2874 RT5665_PWR_ADC_S2F_BIT, 0, NULL, 0),
2875 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5665_STO1_ADC_DIG_VOL,
2876 RT5665_L_MUTE_SFT, 1, rt5665_sto1_adc_l_mix,
2877 ARRAY_SIZE(rt5665_sto1_adc_l_mix)),
2878 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5665_STO1_ADC_DIG_VOL,
2879 RT5665_R_MUTE_SFT, 1, rt5665_sto1_adc_r_mix,
2880 ARRAY_SIZE(rt5665_sto1_adc_r_mix)),
2881 SND_SOC_DAPM_MIXER("Stereo2 ADC MIXL", RT5665_STO2_ADC_DIG_VOL,
2882 RT5665_L_MUTE_SFT, 1, rt5665_sto2_adc_l_mix,
2883 ARRAY_SIZE(rt5665_sto2_adc_l_mix)),
2884 SND_SOC_DAPM_MIXER("Stereo2 ADC MIXR", RT5665_STO2_ADC_DIG_VOL,
2885 RT5665_R_MUTE_SFT, 1, rt5665_sto2_adc_r_mix,
2886 ARRAY_SIZE(rt5665_sto2_adc_r_mix)),
2887 SND_SOC_DAPM_SUPPLY("ADC Mono Left Filter", RT5665_PWR_DIG_2,
2888 RT5665_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2889 SND_SOC_DAPM_MIXER("Mono ADC MIXL", RT5665_MONO_ADC_DIG_VOL,
2890 RT5665_L_MUTE_SFT, 1, rt5665_mono_adc_l_mix,
2891 ARRAY_SIZE(rt5665_mono_adc_l_mix)),
2892 SND_SOC_DAPM_SUPPLY("ADC Mono Right Filter", RT5665_PWR_DIG_2,
2893 RT5665_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2894 SND_SOC_DAPM_MIXER("Mono ADC MIXR", RT5665_MONO_ADC_DIG_VOL,
2895 RT5665_R_MUTE_SFT, 1, rt5665_mono_adc_r_mix,
2896 ARRAY_SIZE(rt5665_mono_adc_r_mix)),
2897
2898 /* ADC PGA */
2899 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2900 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2901 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2902
2903 /* Digital Interface */
2904 SND_SOC_DAPM_SUPPLY("I2S1_1", RT5665_PWR_DIG_1, RT5665_PWR_I2S1_1_BIT,
2905 0, NULL, 0),
2906 SND_SOC_DAPM_SUPPLY("I2S1_2", RT5665_PWR_DIG_1, RT5665_PWR_I2S1_2_BIT,
2907 0, NULL, 0),
2908 SND_SOC_DAPM_SUPPLY("I2S2_1", RT5665_PWR_DIG_1, RT5665_PWR_I2S2_1_BIT,
Bard Liao9b5d3862017-03-16 13:58:41 +0800[diff] [blame]2909 0, rt5665_i2s_pin_event, SND_SOC_DAPM_PRE_PMU |
2910 SND_SOC_DAPM_POST_PMD),
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]2911 SND_SOC_DAPM_SUPPLY("I2S2_2", RT5665_PWR_DIG_1, RT5665_PWR_I2S2_2_BIT,
Bard Liao9b5d3862017-03-16 13:58:41 +0800[diff] [blame]2912 0, rt5665_i2s_pin_event, SND_SOC_DAPM_PRE_PMU |
2913 SND_SOC_DAPM_POST_PMD),
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]2914 SND_SOC_DAPM_SUPPLY("I2S3", RT5665_PWR_DIG_1, RT5665_PWR_I2S3_BIT,
Bard Liao9b5d3862017-03-16 13:58:41 +0800[diff] [blame]2915 0, rt5665_i2s_pin_event, SND_SOC_DAPM_PRE_PMU |
2916 SND_SOC_DAPM_POST_PMD),
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]2917 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2918 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2919 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2920 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2921 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2922 SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2923 SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2924 SND_SOC_DAPM_PGA("IF1 DAC3 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2925 SND_SOC_DAPM_PGA("IF1 DAC3 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2926
2927 SND_SOC_DAPM_PGA("IF2_1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2928 SND_SOC_DAPM_PGA("IF2_2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2929 SND_SOC_DAPM_PGA("IF2_1 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2930 SND_SOC_DAPM_PGA("IF2_1 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2931 SND_SOC_DAPM_PGA("IF2_2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2932 SND_SOC_DAPM_PGA("IF2_2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2933 SND_SOC_DAPM_PGA("IF2_1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2934 SND_SOC_DAPM_PGA("IF2_2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2935
2936 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2937 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2938 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2939 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2940
2941 /* Digital Interface Select */
2942 SND_SOC_DAPM_MUX("IF1_1_ADC1 Mux", SND_SOC_NOPM, 0, 0,
2943 &rt5665_if1_1_adc1_mux),
2944 SND_SOC_DAPM_MUX("IF1_1_ADC2 Mux", SND_SOC_NOPM, 0, 0,
2945 &rt5665_if1_1_adc2_mux),
2946 SND_SOC_DAPM_MUX("IF1_1_ADC3 Mux", SND_SOC_NOPM, 0, 0,
2947 &rt5665_if1_1_adc3_mux),
2948 SND_SOC_DAPM_PGA("IF1_1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2949 SND_SOC_DAPM_MUX("IF1_2_ADC1 Mux", SND_SOC_NOPM, 0, 0,
2950 &rt5665_if1_2_adc1_mux),
2951 SND_SOC_DAPM_MUX("IF1_2_ADC2 Mux", SND_SOC_NOPM, 0, 0,
2952 &rt5665_if1_2_adc2_mux),
2953 SND_SOC_DAPM_MUX("IF1_2_ADC3 Mux", SND_SOC_NOPM, 0, 0,
2954 &rt5665_if1_2_adc3_mux),
2955 SND_SOC_DAPM_MUX("IF1_2_ADC4 Mux", SND_SOC_NOPM, 0, 0,
2956 &rt5665_if1_2_adc4_mux),
2957 SND_SOC_DAPM_MUX("TDM1 slot 01 Data Mux", SND_SOC_NOPM, 0, 0,
2958 &rt5665_tdm1_adc_mux),
2959 SND_SOC_DAPM_MUX("TDM1 slot 23 Data Mux", SND_SOC_NOPM, 0, 0,
2960 &rt5665_tdm1_adc_mux),
2961 SND_SOC_DAPM_MUX("TDM1 slot 45 Data Mux", SND_SOC_NOPM, 0, 0,
2962 &rt5665_tdm1_adc_mux),
2963 SND_SOC_DAPM_MUX("TDM1 slot 67 Data Mux", SND_SOC_NOPM, 0, 0,
2964 &rt5665_tdm1_adc_mux),
2965 SND_SOC_DAPM_MUX("TDM2 slot 01 Data Mux", SND_SOC_NOPM, 0, 0,
2966 &rt5665_tdm2_adc_mux),
2967 SND_SOC_DAPM_MUX("TDM2 slot 23 Data Mux", SND_SOC_NOPM, 0, 0,
2968 &rt5665_tdm2_adc_mux),
2969 SND_SOC_DAPM_MUX("TDM2 slot 45 Data Mux", SND_SOC_NOPM, 0, 0,
2970 &rt5665_tdm2_adc_mux),
2971 SND_SOC_DAPM_MUX("TDM2 slot 67 Data Mux", SND_SOC_NOPM, 0, 0,
2972 &rt5665_tdm2_adc_mux),
2973 SND_SOC_DAPM_MUX("IF2_1 ADC Mux", SND_SOC_NOPM, 0, 0,
2974 &rt5665_if2_1_adc_in_mux),
2975 SND_SOC_DAPM_MUX("IF2_2 ADC Mux", SND_SOC_NOPM, 0, 0,
2976 &rt5665_if2_2_adc_in_mux),
2977 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
2978 &rt5665_if3_adc_in_mux),
2979 SND_SOC_DAPM_MUX("IF1_1 0 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2980 &rt5665_if1_1_01_adc_swap_mux),
2981 SND_SOC_DAPM_MUX("IF1_1 1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2982 &rt5665_if1_1_01_adc_swap_mux),
2983 SND_SOC_DAPM_MUX("IF1_1 2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2984 &rt5665_if1_1_23_adc_swap_mux),
2985 SND_SOC_DAPM_MUX("IF1_1 3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2986 &rt5665_if1_1_23_adc_swap_mux),
2987 SND_SOC_DAPM_MUX("IF1_1 4 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2988 &rt5665_if1_1_45_adc_swap_mux),
2989 SND_SOC_DAPM_MUX("IF1_1 5 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2990 &rt5665_if1_1_45_adc_swap_mux),
2991 SND_SOC_DAPM_MUX("IF1_1 6 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2992 &rt5665_if1_1_67_adc_swap_mux),
2993 SND_SOC_DAPM_MUX("IF1_1 7 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2994 &rt5665_if1_1_67_adc_swap_mux),
2995 SND_SOC_DAPM_MUX("IF1_2 0 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2996 &rt5665_if1_2_01_adc_swap_mux),
2997 SND_SOC_DAPM_MUX("IF1_2 1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2998 &rt5665_if1_2_01_adc_swap_mux),
2999 SND_SOC_DAPM_MUX("IF1_2 2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3000 &rt5665_if1_2_23_adc_swap_mux),
3001 SND_SOC_DAPM_MUX("IF1_2 3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3002 &rt5665_if1_2_23_adc_swap_mux),
3003 SND_SOC_DAPM_MUX("IF1_2 4 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3004 &rt5665_if1_2_45_adc_swap_mux),
3005 SND_SOC_DAPM_MUX("IF1_2 5 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3006 &rt5665_if1_2_45_adc_swap_mux),
3007 SND_SOC_DAPM_MUX("IF1_2 6 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3008 &rt5665_if1_2_67_adc_swap_mux),
3009 SND_SOC_DAPM_MUX("IF1_2 7 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3010 &rt5665_if1_2_67_adc_swap_mux),
3011 SND_SOC_DAPM_MUX("IF2_1 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
3012 &rt5665_if2_1_dac_swap_mux),
3013 SND_SOC_DAPM_MUX("IF2_1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3014 &rt5665_if2_1_adc_swap_mux),
3015 SND_SOC_DAPM_MUX("IF2_2 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
3016 &rt5665_if2_2_dac_swap_mux),
3017 SND_SOC_DAPM_MUX("IF2_2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3018 &rt5665_if2_2_adc_swap_mux),
3019 SND_SOC_DAPM_MUX("IF3 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
3020 &rt5665_if3_dac_swap_mux),
3021 SND_SOC_DAPM_MUX("IF3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3022 &rt5665_if3_adc_swap_mux),
3023
3024 /* Audio Interface */
3025 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 0", "AIF1_1 Capture",
3026 0, SND_SOC_NOPM, 0, 0),
3027 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 1", "AIF1_1 Capture",
3028 1, SND_SOC_NOPM, 0, 0),
3029 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 2", "AIF1_1 Capture",
3030 2, SND_SOC_NOPM, 0, 0),
3031 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 3", "AIF1_1 Capture",
3032 3, SND_SOC_NOPM, 0, 0),
3033 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 4", "AIF1_1 Capture",
3034 4, SND_SOC_NOPM, 0, 0),
3035 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 5", "AIF1_1 Capture",
3036 5, SND_SOC_NOPM, 0, 0),
3037 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 6", "AIF1_1 Capture",
3038 6, SND_SOC_NOPM, 0, 0),
3039 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 7", "AIF1_1 Capture",
3040 7, SND_SOC_NOPM, 0, 0),
3041 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 0", "AIF1_2 Capture",
3042 0, SND_SOC_NOPM, 0, 0),
3043 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 1", "AIF1_2 Capture",
3044 1, SND_SOC_NOPM, 0, 0),
3045 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 2", "AIF1_2 Capture",
3046 2, SND_SOC_NOPM, 0, 0),
3047 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 3", "AIF1_2 Capture",
3048 3, SND_SOC_NOPM, 0, 0),
3049 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 4", "AIF1_2 Capture",
3050 4, SND_SOC_NOPM, 0, 0),
3051 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 5", "AIF1_2 Capture",
3052 5, SND_SOC_NOPM, 0, 0),
3053 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 6", "AIF1_2 Capture",
3054 6, SND_SOC_NOPM, 0, 0),
3055 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 7", "AIF1_2 Capture",
3056 7, SND_SOC_NOPM, 0, 0),
3057 SND_SOC_DAPM_AIF_OUT("AIF2_1TX", "AIF2_1 Capture",
3058 0, SND_SOC_NOPM, 0, 0),
3059 SND_SOC_DAPM_AIF_OUT("AIF2_2TX", "AIF2_2 Capture",
3060 0, SND_SOC_NOPM, 0, 0),
3061 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture",
3062 0, SND_SOC_NOPM, 0, 0),
3063 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback",
3064 0, SND_SOC_NOPM, 0, 0),
3065 SND_SOC_DAPM_AIF_IN("AIF2_1RX", "AIF2_1 Playback",
3066 0, SND_SOC_NOPM, 0, 0),
3067 SND_SOC_DAPM_AIF_IN("AIF2_2RX", "AIF2_2 Playback",
3068 0, SND_SOC_NOPM, 0, 0),
3069 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback",
3070 0, SND_SOC_NOPM, 0, 0),
3071
3072 /* Output Side */
3073 /* DAC mixer before sound effect */
3074 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
3075 rt5665_dac_l_mix, ARRAY_SIZE(rt5665_dac_l_mix)),
3076 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
3077 rt5665_dac_r_mix, ARRAY_SIZE(rt5665_dac_r_mix)),
3078
3079 /* DAC channel Mux */
3080 SND_SOC_DAPM_MUX("DAC L1 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l1_mux),
3081 SND_SOC_DAPM_MUX("DAC R1 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r1_mux),
3082 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l2_mux),
3083 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r2_mux),
3084 SND_SOC_DAPM_MUX("DAC L3 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l3_mux),
3085 SND_SOC_DAPM_MUX("DAC R3 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r3_mux),
3086
3087 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
3088 &rt5665_alg_dac_l1_mux),
3089 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
3090 &rt5665_alg_dac_r1_mux),
3091 SND_SOC_DAPM_MUX("DAC L2 Source", SND_SOC_NOPM, 0, 0,
3092 &rt5665_alg_dac_l2_mux),
3093 SND_SOC_DAPM_MUX("DAC R2 Source", SND_SOC_NOPM, 0, 0,
3094 &rt5665_alg_dac_r2_mux),
3095
3096 /* DAC Mixer */
3097 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5665_PWR_DIG_2,
3098 RT5665_PWR_DAC_S1F_BIT, 0, NULL, 0),
3099 SND_SOC_DAPM_SUPPLY("DAC Stereo2 Filter", RT5665_PWR_DIG_2,
3100 RT5665_PWR_DAC_S2F_BIT, 0, NULL, 0),
3101 SND_SOC_DAPM_SUPPLY("DAC Mono Left Filter", RT5665_PWR_DIG_2,
3102 RT5665_PWR_DAC_MF_L_BIT, 0, NULL, 0),
3103 SND_SOC_DAPM_SUPPLY("DAC Mono Right Filter", RT5665_PWR_DIG_2,
3104 RT5665_PWR_DAC_MF_R_BIT, 0, NULL, 0),
3105 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
3106 rt5665_sto1_dac_l_mix, ARRAY_SIZE(rt5665_sto1_dac_l_mix)),
3107 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
3108 rt5665_sto1_dac_r_mix, ARRAY_SIZE(rt5665_sto1_dac_r_mix)),
3109 SND_SOC_DAPM_MIXER("Stereo2 DAC MIXL", SND_SOC_NOPM, 0, 0,
3110 rt5665_sto2_dac_l_mix, ARRAY_SIZE(rt5665_sto2_dac_l_mix)),
3111 SND_SOC_DAPM_MIXER("Stereo2 DAC MIXR", SND_SOC_NOPM, 0, 0,
3112 rt5665_sto2_dac_r_mix, ARRAY_SIZE(rt5665_sto2_dac_r_mix)),
3113 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
3114 rt5665_mono_dac_l_mix, ARRAY_SIZE(rt5665_mono_dac_l_mix)),
3115 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
3116 rt5665_mono_dac_r_mix, ARRAY_SIZE(rt5665_mono_dac_r_mix)),
3117 SND_SOC_DAPM_MUX("DAC MIXL", SND_SOC_NOPM, 0, 0,
3118 &rt5665_dig_dac_mixl_mux),
3119 SND_SOC_DAPM_MUX("DAC MIXR", SND_SOC_NOPM, 0, 0,
3120 &rt5665_dig_dac_mixr_mux),
3121
3122 /* DACs */
3123 SND_SOC_DAPM_DAC("DAC L1", NULL, SND_SOC_NOPM, 0, 0),
3124 SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM, 0, 0),
3125
3126 SND_SOC_DAPM_SUPPLY("DAC L2 Power", RT5665_PWR_DIG_1,
3127 RT5665_PWR_DAC_L2_BIT, 0, NULL, 0),
3128 SND_SOC_DAPM_SUPPLY("DAC R2 Power", RT5665_PWR_DIG_1,
3129 RT5665_PWR_DAC_R2_BIT, 0, NULL, 0),
3130 SND_SOC_DAPM_DAC("DAC L2", NULL, SND_SOC_NOPM, 0, 0),
3131 SND_SOC_DAPM_DAC("DAC R2", NULL, SND_SOC_NOPM, 0, 0),
3132 SND_SOC_DAPM_PGA("DAC1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3133
3134 SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 1, RT5665_CHOP_DAC,
3135 RT5665_CKGEN_DAC1_SFT, 0, NULL, 0),
3136 SND_SOC_DAPM_SUPPLY_S("DAC 2 Clock", 1, RT5665_CHOP_DAC,
3137 RT5665_CKGEN_DAC2_SFT, 0, NULL, 0),
3138
3139 /* OUT Mixer */
3140 SND_SOC_DAPM_MIXER("MONOVOL MIX", RT5665_PWR_MIXER, RT5665_PWR_MM_BIT,
3141 0, rt5665_monovol_mix, ARRAY_SIZE(rt5665_monovol_mix)),
3142 SND_SOC_DAPM_MIXER("OUT MIXL", RT5665_PWR_MIXER, RT5665_PWR_OM_L_BIT,
3143 0, rt5665_out_l_mix, ARRAY_SIZE(rt5665_out_l_mix)),
3144 SND_SOC_DAPM_MIXER("OUT MIXR", RT5665_PWR_MIXER, RT5665_PWR_OM_R_BIT,
3145 0, rt5665_out_r_mix, ARRAY_SIZE(rt5665_out_r_mix)),
3146
3147 /* Output Volume */
3148 SND_SOC_DAPM_SWITCH("MONOVOL", RT5665_PWR_VOL, RT5665_PWR_MV_BIT, 0,
3149 &monovol_switch),
3150 SND_SOC_DAPM_SWITCH("OUTVOL L", RT5665_PWR_VOL, RT5665_PWR_OV_L_BIT, 0,
3151 &outvol_l_switch),
3152 SND_SOC_DAPM_SWITCH("OUTVOL R", RT5665_PWR_VOL, RT5665_PWR_OV_R_BIT, 0,
3153 &outvol_r_switch),
3154
3155 /* MONO/HPO/LOUT */
3156 SND_SOC_DAPM_MIXER("Mono MIX", SND_SOC_NOPM, 0, 0, rt5665_mono_mix,
3157 ARRAY_SIZE(rt5665_mono_mix)),
3158 SND_SOC_DAPM_MIXER("LOUT L MIX", SND_SOC_NOPM, 0, 0, rt5665_lout_l_mix,
3159 ARRAY_SIZE(rt5665_lout_l_mix)),
3160 SND_SOC_DAPM_MIXER("LOUT R MIX", SND_SOC_NOPM, 0, 0, rt5665_lout_r_mix,
3161 ARRAY_SIZE(rt5665_lout_r_mix)),
3162 SND_SOC_DAPM_PGA_S("Mono Amp", 1, RT5665_PWR_ANLG_1, RT5665_PWR_MA_BIT,
3163 0, rt5665_mono_event, SND_SOC_DAPM_POST_PMD |
3164 SND_SOC_DAPM_PRE_PMU),
3165 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5665_hp_event,
3166 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
3167 SND_SOC_DAPM_PGA_S("LOUT Amp", 1, RT5665_PWR_ANLG_1,
3168 RT5665_PWR_LM_BIT, 0, rt5665_lout_event,
3169 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD |
3170 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
3171
3172 SND_SOC_DAPM_SUPPLY("Charge Pump", SND_SOC_NOPM, 0, 0,
3173 rt5665_charge_pump_event, SND_SOC_DAPM_PRE_PMU |
3174 SND_SOC_DAPM_POST_PMD),
3175
3176 SND_SOC_DAPM_SWITCH("Mono Playback", SND_SOC_NOPM, 0, 0,
3177 &mono_switch),
3178 SND_SOC_DAPM_SWITCH("HPO Playback", SND_SOC_NOPM, 0, 0,
3179 &hpo_switch),
3180 SND_SOC_DAPM_SWITCH("LOUT L Playback", SND_SOC_NOPM, 0, 0,
3181 &lout_l_switch),
3182 SND_SOC_DAPM_SWITCH("LOUT R Playback", SND_SOC_NOPM, 0, 0,
3183 &lout_r_switch),
3184 SND_SOC_DAPM_SWITCH("PDM L Playback", SND_SOC_NOPM, 0, 0,
3185 &pdm_l_switch),
3186 SND_SOC_DAPM_SWITCH("PDM R Playback", SND_SOC_NOPM, 0, 0,
3187 &pdm_r_switch),
3188
3189 /* PDM */
3190 SND_SOC_DAPM_SUPPLY("PDM Power", RT5665_PWR_DIG_2,
3191 RT5665_PWR_PDM1_BIT, 0, NULL, 0),
3192 SND_SOC_DAPM_MUX("PDM L Mux", SND_SOC_NOPM,
3193 0, 1, &rt5665_pdm_l_mux),
3194 SND_SOC_DAPM_MUX("PDM R Mux", SND_SOC_NOPM,
3195 0, 1, &rt5665_pdm_r_mux),
3196
3197 /* CLK DET */
3198 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5665_CLK_DET, RT5665_SYS_CLK_DET,
3199 0, NULL, 0),
3200 SND_SOC_DAPM_SUPPLY("CLKDET HP", RT5665_CLK_DET, RT5665_HP_CLK_DET,
3201 0, NULL, 0),
3202 SND_SOC_DAPM_SUPPLY("CLKDET MONO", RT5665_CLK_DET, RT5665_MONO_CLK_DET,
3203 0, NULL, 0),
3204 SND_SOC_DAPM_SUPPLY("CLKDET LOUT", RT5665_CLK_DET, RT5665_LOUT_CLK_DET,
3205 0, NULL, 0),
3206 SND_SOC_DAPM_SUPPLY("CLKDET", RT5665_CLK_DET, RT5665_POW_CLK_DET,
3207 0, NULL, 0),
3208
3209 /* Output Lines */
3210 SND_SOC_DAPM_OUTPUT("HPOL"),
3211 SND_SOC_DAPM_OUTPUT("HPOR"),
3212 SND_SOC_DAPM_OUTPUT("LOUTL"),
3213 SND_SOC_DAPM_OUTPUT("LOUTR"),
3214 SND_SOC_DAPM_OUTPUT("MONOOUT"),
3215 SND_SOC_DAPM_OUTPUT("PDML"),
3216 SND_SOC_DAPM_OUTPUT("PDMR"),
3217};
3218
3219static const struct snd_soc_dapm_route rt5665_dapm_routes[] = {
3220 /*PLL*/
3221 {"ADC Stereo1 Filter", NULL, "PLL", is_sys_clk_from_pll},
3222 {"ADC Stereo2 Filter", NULL, "PLL", is_sys_clk_from_pll},
3223 {"ADC Mono Left Filter", NULL, "PLL", is_sys_clk_from_pll},
3224 {"ADC Mono Right Filter", NULL, "PLL", is_sys_clk_from_pll},
3225 {"DAC Stereo1 Filter", NULL, "PLL", is_sys_clk_from_pll},
3226 {"DAC Stereo2 Filter", NULL, "PLL", is_sys_clk_from_pll},
3227 {"DAC Mono Left Filter", NULL, "PLL", is_sys_clk_from_pll},
3228 {"DAC Mono Right Filter", NULL, "PLL", is_sys_clk_from_pll},
3229
3230 /*ASRC*/
3231 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
Bard Liao30b7d882017-05-02 11:00:39 +0800[diff] [blame^]3232 {"ADC Stereo2 Filter", NULL, "ADC STO2 ASRC", is_using_asrc},
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]3233 {"ADC Mono Left Filter", NULL, "ADC Mono L ASRC", is_using_asrc},
3234 {"ADC Mono Right Filter", NULL, "ADC Mono R ASRC", is_using_asrc},
3235 {"DAC Mono Left Filter", NULL, "DAC Mono L ASRC", is_using_asrc},
3236 {"DAC Mono Right Filter", NULL, "DAC Mono R ASRC", is_using_asrc},
3237 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
3238 {"DAC Stereo2 Filter", NULL, "DAC STO2 ASRC", is_using_asrc},
Bard Liao09b50c32017-03-08 19:05:32 +0800[diff] [blame]3239 {"I2S1 ASRC", NULL, "CLKDET"},
3240 {"I2S2 ASRC", NULL, "CLKDET"},
3241 {"I2S3 ASRC", NULL, "CLKDET"},
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]3242
3243 /*Vref*/
3244 {"Mic Det Power", NULL, "Vref2"},
3245 {"MICBIAS1", NULL, "Vref1"},
3246 {"MICBIAS1", NULL, "Vref2"},
3247 {"MICBIAS2", NULL, "Vref1"},
3248 {"MICBIAS2", NULL, "Vref2"},
3249 {"MICBIAS3", NULL, "Vref1"},
3250 {"MICBIAS3", NULL, "Vref2"},
3251
3252 {"Stereo1 DMIC L Mux", NULL, "DMIC STO1 ASRC"},
3253 {"Stereo1 DMIC R Mux", NULL, "DMIC STO1 ASRC"},
3254 {"Stereo2 DMIC L Mux", NULL, "DMIC STO2 ASRC"},
3255 {"Stereo2 DMIC R Mux", NULL, "DMIC STO2 ASRC"},
3256 {"Mono DMIC L Mux", NULL, "DMIC MONO L ASRC"},
3257 {"Mono DMIC R Mux", NULL, "DMIC MONO R ASRC"},
3258
3259 {"I2S1_1", NULL, "I2S1 ASRC"},
3260 {"I2S1_2", NULL, "I2S1 ASRC"},
3261 {"I2S2_1", NULL, "I2S2 ASRC"},
3262 {"I2S2_2", NULL, "I2S2 ASRC"},
3263 {"I2S3", NULL, "I2S3 ASRC"},
3264
3265 {"CLKDET SYS", NULL, "CLKDET"},
3266 {"CLKDET HP", NULL, "CLKDET"},
3267 {"CLKDET MONO", NULL, "CLKDET"},
3268 {"CLKDET LOUT", NULL, "CLKDET"},
3269
3270 {"IN1P", NULL, "LDO2"},
3271 {"IN2P", NULL, "LDO2"},
3272 {"IN3P", NULL, "LDO2"},
3273 {"IN4P", NULL, "LDO2"},
3274
3275 {"DMIC1", NULL, "DMIC L1"},
3276 {"DMIC1", NULL, "DMIC R1"},
3277 {"DMIC2", NULL, "DMIC L2"},
3278 {"DMIC2", NULL, "DMIC R2"},
3279
3280 {"BST1", NULL, "IN1P"},
3281 {"BST1", NULL, "IN1N"},
3282 {"BST1", NULL, "BST1 Power"},
3283 {"BST1", NULL, "BST1P Power"},
3284 {"BST2", NULL, "IN2P"},
3285 {"BST2", NULL, "IN2N"},
3286 {"BST2", NULL, "BST2 Power"},
3287 {"BST2", NULL, "BST2P Power"},
3288 {"BST3", NULL, "IN3P"},
3289 {"BST3", NULL, "IN3N"},
3290 {"BST3", NULL, "BST3 Power"},
3291 {"BST3", NULL, "BST3P Power"},
3292 {"BST4", NULL, "IN4P"},
3293 {"BST4", NULL, "IN4N"},
3294 {"BST4", NULL, "BST4 Power"},
3295 {"BST4", NULL, "BST4P Power"},
3296 {"BST1 CBJ", NULL, "IN1P"},
3297 {"BST1 CBJ", NULL, "IN1N"},
3298 {"BST1 CBJ", NULL, "CBJ Power"},
3299 {"CBJ Power", NULL, "Vref2"},
3300
3301 {"INL VOL", NULL, "IN3P"},
3302 {"INR VOL", NULL, "IN3N"},
3303
3304 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
3305 {"RECMIX1L", "INL Switch", "INL VOL"},
3306 {"RECMIX1L", "INR Switch", "INR VOL"},
3307 {"RECMIX1L", "BST4 Switch", "BST4"},
3308 {"RECMIX1L", "BST3 Switch", "BST3"},
3309 {"RECMIX1L", "BST2 Switch", "BST2"},
3310 {"RECMIX1L", "BST1 Switch", "BST1"},
3311 {"RECMIX1L", NULL, "RECMIX1L Power"},
3312
3313 {"RECMIX1R", "MONOVOL Switch", "MONOVOL"},
3314 {"RECMIX1R", "INR Switch", "INR VOL"},
3315 {"RECMIX1R", "BST4 Switch", "BST4"},
3316 {"RECMIX1R", "BST3 Switch", "BST3"},
3317 {"RECMIX1R", "BST2 Switch", "BST2"},
3318 {"RECMIX1R", "BST1 Switch", "BST1"},
3319 {"RECMIX1R", NULL, "RECMIX1R Power"},
3320
3321 {"RECMIX2L", "CBJ Switch", "BST1 CBJ"},
3322 {"RECMIX2L", "INL Switch", "INL VOL"},
3323 {"RECMIX2L", "INR Switch", "INR VOL"},
3324 {"RECMIX2L", "BST4 Switch", "BST4"},
3325 {"RECMIX2L", "BST3 Switch", "BST3"},
3326 {"RECMIX2L", "BST2 Switch", "BST2"},
3327 {"RECMIX2L", "BST1 Switch", "BST1"},
3328 {"RECMIX2L", NULL, "RECMIX2L Power"},
3329
3330 {"RECMIX2R", "MONOVOL Switch", "MONOVOL"},
3331 {"RECMIX2R", "INL Switch", "INL VOL"},
3332 {"RECMIX2R", "INR Switch", "INR VOL"},
3333 {"RECMIX2R", "BST4 Switch", "BST4"},
3334 {"RECMIX2R", "BST3 Switch", "BST3"},
3335 {"RECMIX2R", "BST2 Switch", "BST2"},
3336 {"RECMIX2R", "BST1 Switch", "BST1"},
3337 {"RECMIX2R", NULL, "RECMIX2R Power"},
3338
3339 {"ADC1 L", NULL, "RECMIX1L"},
3340 {"ADC1 L", NULL, "ADC1 L Power"},
3341 {"ADC1 L", NULL, "ADC1 clock"},
3342 {"ADC1 R", NULL, "RECMIX1R"},
3343 {"ADC1 R", NULL, "ADC1 R Power"},
3344 {"ADC1 R", NULL, "ADC1 clock"},
3345
3346 {"ADC2 L", NULL, "RECMIX2L"},
3347 {"ADC2 L", NULL, "ADC2 L Power"},
3348 {"ADC2 L", NULL, "ADC2 clock"},
3349 {"ADC2 R", NULL, "RECMIX2R"},
3350 {"ADC2 R", NULL, "ADC2 R Power"},
3351 {"ADC2 R", NULL, "ADC2 clock"},
3352
3353 {"DMIC L1", NULL, "DMIC CLK"},
3354 {"DMIC L1", NULL, "DMIC1 Power"},
3355 {"DMIC R1", NULL, "DMIC CLK"},
3356 {"DMIC R1", NULL, "DMIC1 Power"},
3357 {"DMIC L2", NULL, "DMIC CLK"},
3358 {"DMIC L2", NULL, "DMIC2 Power"},
3359 {"DMIC R2", NULL, "DMIC CLK"},
3360 {"DMIC R2", NULL, "DMIC2 Power"},
3361
3362 {"Stereo1 DMIC L Mux", "DMIC1", "DMIC L1"},
3363 {"Stereo1 DMIC L Mux", "DMIC2", "DMIC L2"},
3364
3365 {"Stereo1 DMIC R Mux", "DMIC1", "DMIC R1"},
3366 {"Stereo1 DMIC R Mux", "DMIC2", "DMIC R2"},
3367
3368 {"Mono DMIC L Mux", "DMIC1 L", "DMIC L1"},
3369 {"Mono DMIC L Mux", "DMIC2 L", "DMIC L2"},
3370
3371 {"Mono DMIC R Mux", "DMIC1 R", "DMIC R1"},
3372 {"Mono DMIC R Mux", "DMIC2 R", "DMIC R2"},
3373
3374 {"Stereo2 DMIC L Mux", "DMIC1", "DMIC L1"},
3375 {"Stereo2 DMIC L Mux", "DMIC2", "DMIC L2"},
3376
3377 {"Stereo2 DMIC R Mux", "DMIC1", "DMIC R1"},
3378 {"Stereo2 DMIC R Mux", "DMIC2", "DMIC R2"},
3379
3380 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
3381 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
3382 {"Stereo1 ADC L Mux", "ADC2 L", "ADC2 L"},
3383 {"Stereo1 ADC L Mux", "ADC2 R", "ADC2 R"},
3384 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
3385 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
3386 {"Stereo1 ADC R Mux", "ADC2 L", "ADC2 L"},
3387 {"Stereo1 ADC R Mux", "ADC2 R", "ADC2 R"},
3388
3389 {"Stereo1 DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
3390 {"Stereo1 DD L Mux", "MONO DAC", "Mono DAC MIXL"},
3391
3392 {"Stereo1 DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
3393 {"Stereo1 DD R Mux", "MONO DAC", "Mono DAC MIXR"},
3394
3395 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
3396 {"Stereo1 ADC L1 Mux", "DD Mux", "Stereo1 DD L Mux"},
3397 {"Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC L Mux"},
3398 {"Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL"},
3399
3400 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
3401 {"Stereo1 ADC R1 Mux", "DD Mux", "Stereo1 DD R Mux"},
3402 {"Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC R Mux"},
3403 {"Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR"},
3404
3405 {"Mono ADC L Mux", "ADC1 L", "ADC1 L"},
3406 {"Mono ADC L Mux", "ADC1 R", "ADC1 R"},
3407 {"Mono ADC L Mux", "ADC2 L", "ADC2 L"},
3408 {"Mono ADC L Mux", "ADC2 R", "ADC2 R"},
3409
3410 {"Mono ADC R Mux", "ADC1 L", "ADC1 L"},
3411 {"Mono ADC R Mux", "ADC1 R", "ADC1 R"},
3412 {"Mono ADC R Mux", "ADC2 L", "ADC2 L"},
3413 {"Mono ADC R Mux", "ADC2 R", "ADC2 R"},
3414
3415 {"Mono DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
3416 {"Mono DD L Mux", "MONO DAC", "Mono DAC MIXL"},
3417
3418 {"Mono DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
3419 {"Mono DD R Mux", "MONO DAC", "Mono DAC MIXR"},
3420
3421 {"Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux"},
3422 {"Mono ADC L2 Mux", "DAC MIXL", "DAC MIXL"},
3423 {"Mono ADC L1 Mux", "DD Mux", "Mono DD L Mux"},
3424 {"Mono ADC L1 Mux", "ADC", "Mono ADC L Mux"},
3425
3426 {"Mono ADC R1 Mux", "DD Mux", "Mono DD R Mux"},
3427 {"Mono ADC R1 Mux", "ADC", "Mono ADC R Mux"},
3428 {"Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux"},
3429 {"Mono ADC R2 Mux", "DAC MIXR", "DAC MIXR"},
3430
3431 {"Stereo2 ADC L Mux", "ADC1 L", "ADC1 L"},
3432 {"Stereo2 ADC L Mux", "ADC2 L", "ADC2 L"},
3433 {"Stereo2 ADC L Mux", "ADC1 R", "ADC1 R"},
3434 {"Stereo2 ADC R Mux", "ADC1 L", "ADC1 L"},
3435 {"Stereo2 ADC R Mux", "ADC2 L", "ADC2 L"},
3436 {"Stereo2 ADC R Mux", "ADC1 R", "ADC1 R"},
3437
3438 {"Stereo2 DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
3439 {"Stereo2 DD L Mux", "MONO DAC", "Mono DAC MIXL"},
3440
3441 {"Stereo2 DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
3442 {"Stereo2 DD R Mux", "MONO DAC", "Mono DAC MIXR"},
3443
3444 {"Stereo2 ADC L1 Mux", "ADC", "Stereo2 ADC L Mux"},
3445 {"Stereo2 ADC L1 Mux", "DD Mux", "Stereo2 DD L Mux"},
3446 {"Stereo2 ADC L2 Mux", "DMIC", "Stereo2 DMIC L Mux"},
3447 {"Stereo2 ADC L2 Mux", "DAC MIX", "DAC MIXL"},
3448
3449 {"Stereo2 ADC R1 Mux", "ADC", "Stereo2 ADC R Mux"},
3450 {"Stereo2 ADC R1 Mux", "DD Mux", "Stereo2 DD R Mux"},
3451 {"Stereo2 ADC R2 Mux", "DMIC", "Stereo2 DMIC R Mux"},
3452 {"Stereo2 ADC R2 Mux", "DAC MIX", "DAC MIXR"},
3453
3454 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
3455 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
3456 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
3457
3458 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
3459 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
3460 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
3461
3462 {"Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux"},
3463 {"Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux"},
3464 {"Mono ADC MIXL", NULL, "ADC Mono Left Filter"},
3465
3466 {"Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux"},
3467 {"Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux"},
3468 {"Mono ADC MIXR", NULL, "ADC Mono Right Filter"},
3469
3470 {"Stereo2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC L1 Mux"},
3471 {"Stereo2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC L2 Mux"},
3472 {"Stereo2 ADC MIXL", NULL, "ADC Stereo2 Filter"},
3473
3474 {"Stereo2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC R1 Mux"},
3475 {"Stereo2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC R2 Mux"},
3476 {"Stereo2 ADC MIXR", NULL, "ADC Stereo2 Filter"},
3477
3478 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
3479 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
3480 {"Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL"},
3481 {"Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR"},
3482 {"Mono ADC MIX", NULL, "Mono ADC MIXL"},
3483 {"Mono ADC MIX", NULL, "Mono ADC MIXR"},
3484
3485 {"IF1_1_ADC1 Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3486 {"IF1_1_ADC1 Mux", "IF2_1 DAC", "IF2_1 DAC"},
3487 {"IF1_1_ADC2 Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3488 {"IF1_1_ADC2 Mux", "IF2_2 DAC", "IF2_2 DAC"},
3489 {"IF1_1_ADC3 Mux", "MONO ADC", "Mono ADC MIX"},
3490 {"IF1_1_ADC3 Mux", "IF3 DAC", "IF3 DAC"},
3491 {"IF1_1_ADC4", NULL, "DAC1 MIX"},
3492
3493 {"IF1_2_ADC1 Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3494 {"IF1_2_ADC1 Mux", "IF1 DAC", "IF1 DAC1"},
3495 {"IF1_2_ADC2 Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3496 {"IF1_2_ADC2 Mux", "IF2_1 DAC", "IF2_1 DAC"},
3497 {"IF1_2_ADC3 Mux", "MONO ADC", "Mono ADC MIX"},
3498 {"IF1_2_ADC3 Mux", "IF2_2 DAC", "IF2_2 DAC"},
3499 {"IF1_2_ADC4 Mux", "DAC1", "DAC1 MIX"},
3500 {"IF1_2_ADC4 Mux", "IF3 DAC", "IF3 DAC"},
3501
3502 {"TDM1 slot 01 Data Mux", "1234", "IF1_1_ADC1 Mux"},
3503 {"TDM1 slot 01 Data Mux", "1243", "IF1_1_ADC1 Mux"},
3504 {"TDM1 slot 01 Data Mux", "1324", "IF1_1_ADC1 Mux"},
3505 {"TDM1 slot 01 Data Mux", "1342", "IF1_1_ADC1 Mux"},
3506 {"TDM1 slot 01 Data Mux", "1432", "IF1_1_ADC1 Mux"},
3507 {"TDM1 slot 01 Data Mux", "1423", "IF1_1_ADC1 Mux"},
3508 {"TDM1 slot 01 Data Mux", "2134", "IF1_1_ADC2 Mux"},
3509 {"TDM1 slot 01 Data Mux", "2143", "IF1_1_ADC2 Mux"},
3510 {"TDM1 slot 01 Data Mux", "2314", "IF1_1_ADC2 Mux"},
3511 {"TDM1 slot 01 Data Mux", "2341", "IF1_1_ADC2 Mux"},
3512 {"TDM1 slot 01 Data Mux", "2431", "IF1_1_ADC2 Mux"},
3513 {"TDM1 slot 01 Data Mux", "2413", "IF1_1_ADC2 Mux"},
3514 {"TDM1 slot 01 Data Mux", "3124", "IF1_1_ADC3 Mux"},
3515 {"TDM1 slot 01 Data Mux", "3142", "IF1_1_ADC3 Mux"},
3516 {"TDM1 slot 01 Data Mux", "3214", "IF1_1_ADC3 Mux"},
3517 {"TDM1 slot 01 Data Mux", "3241", "IF1_1_ADC3 Mux"},
3518 {"TDM1 slot 01 Data Mux", "3412", "IF1_1_ADC3 Mux"},
3519 {"TDM1 slot 01 Data Mux", "3421", "IF1_1_ADC3 Mux"},
3520 {"TDM1 slot 01 Data Mux", "4123", "IF1_1_ADC4"},
3521 {"TDM1 slot 01 Data Mux", "4132", "IF1_1_ADC4"},
3522 {"TDM1 slot 01 Data Mux", "4213", "IF1_1_ADC4"},
3523 {"TDM1 slot 01 Data Mux", "4231", "IF1_1_ADC4"},
3524 {"TDM1 slot 01 Data Mux", "4312", "IF1_1_ADC4"},
3525 {"TDM1 slot 01 Data Mux", "4321", "IF1_1_ADC4"},
3526 {"TDM1 slot 01 Data Mux", NULL, "I2S1_1"},
3527
3528 {"TDM1 slot 23 Data Mux", "1234", "IF1_1_ADC2 Mux"},
3529 {"TDM1 slot 23 Data Mux", "1243", "IF1_1_ADC2 Mux"},
3530 {"TDM1 slot 23 Data Mux", "1324", "IF1_1_ADC3 Mux"},
3531 {"TDM1 slot 23 Data Mux", "1342", "IF1_1_ADC3 Mux"},
3532 {"TDM1 slot 23 Data Mux", "1432", "IF1_1_ADC4"},
3533 {"TDM1 slot 23 Data Mux", "1423", "IF1_1_ADC4"},
3534 {"TDM1 slot 23 Data Mux", "2134", "IF1_1_ADC1 Mux"},
3535 {"TDM1 slot 23 Data Mux", "2143", "IF1_1_ADC1 Mux"},
3536 {"TDM1 slot 23 Data Mux", "2314", "IF1_1_ADC3 Mux"},
3537 {"TDM1 slot 23 Data Mux", "2341", "IF1_1_ADC3 Mux"},
3538 {"TDM1 slot 23 Data Mux", "2431", "IF1_1_ADC4"},
3539 {"TDM1 slot 23 Data Mux", "2413", "IF1_1_ADC4"},
3540 {"TDM1 slot 23 Data Mux", "3124", "IF1_1_ADC1 Mux"},
3541 {"TDM1 slot 23 Data Mux", "3142", "IF1_1_ADC1 Mux"},
3542 {"TDM1 slot 23 Data Mux", "3214", "IF1_1_ADC2 Mux"},
3543 {"TDM1 slot 23 Data Mux", "3241", "IF1_1_ADC2 Mux"},
3544 {"TDM1 slot 23 Data Mux", "3412", "IF1_1_ADC4"},
3545 {"TDM1 slot 23 Data Mux", "3421", "IF1_1_ADC4"},
3546 {"TDM1 slot 23 Data Mux", "4123", "IF1_1_ADC1 Mux"},
3547 {"TDM1 slot 23 Data Mux", "4132", "IF1_1_ADC1 Mux"},
3548 {"TDM1 slot 23 Data Mux", "4213", "IF1_1_ADC2 Mux"},
3549 {"TDM1 slot 23 Data Mux", "4231", "IF1_1_ADC2 Mux"},
3550 {"TDM1 slot 23 Data Mux", "4312", "IF1_1_ADC3 Mux"},
3551 {"TDM1 slot 23 Data Mux", "4321", "IF1_1_ADC3 Mux"},
3552 {"TDM1 slot 23 Data Mux", NULL, "I2S1_1"},
3553
3554 {"TDM1 slot 45 Data Mux", "1234", "IF1_1_ADC3 Mux"},
3555 {"TDM1 slot 45 Data Mux", "1243", "IF1_1_ADC4"},
3556 {"TDM1 slot 45 Data Mux", "1324", "IF1_1_ADC2 Mux"},
3557 {"TDM1 slot 45 Data Mux", "1342", "IF1_1_ADC4"},
3558 {"TDM1 slot 45 Data Mux", "1432", "IF1_1_ADC3 Mux"},
3559 {"TDM1 slot 45 Data Mux", "1423", "IF1_1_ADC2 Mux"},
3560 {"TDM1 slot 45 Data Mux", "2134", "IF1_1_ADC3 Mux"},
3561 {"TDM1 slot 45 Data Mux", "2143", "IF1_1_ADC4"},
3562 {"TDM1 slot 45 Data Mux", "2314", "IF1_1_ADC1 Mux"},
3563 {"TDM1 slot 45 Data Mux", "2341", "IF1_1_ADC4"},
3564 {"TDM1 slot 45 Data Mux", "2431", "IF1_1_ADC3 Mux"},
3565 {"TDM1 slot 45 Data Mux", "2413", "IF1_1_ADC1 Mux"},
3566 {"TDM1 slot 45 Data Mux", "3124", "IF1_1_ADC2 Mux"},
3567 {"TDM1 slot 45 Data Mux", "3142", "IF1_1_ADC4"},
3568 {"TDM1 slot 45 Data Mux", "3214", "IF1_1_ADC1 Mux"},
3569 {"TDM1 slot 45 Data Mux", "3241", "IF1_1_ADC4"},
3570 {"TDM1 slot 45 Data Mux", "3412", "IF1_1_ADC1 Mux"},
3571 {"TDM1 slot 45 Data Mux", "3421", "IF1_1_ADC2 Mux"},
3572 {"TDM1 slot 45 Data Mux", "4123", "IF1_1_ADC2 Mux"},
3573 {"TDM1 slot 45 Data Mux", "4132", "IF1_1_ADC3 Mux"},
3574 {"TDM1 slot 45 Data Mux", "4213", "IF1_1_ADC1 Mux"},
3575 {"TDM1 slot 45 Data Mux", "4231", "IF1_1_ADC3 Mux"},
3576 {"TDM1 slot 45 Data Mux", "4312", "IF1_1_ADC1 Mux"},
3577 {"TDM1 slot 45 Data Mux", "4321", "IF1_1_ADC2 Mux"},
3578 {"TDM1 slot 45 Data Mux", NULL, "I2S1_1"},
3579
3580 {"TDM1 slot 67 Data Mux", "1234", "IF1_1_ADC4"},
3581 {"TDM1 slot 67 Data Mux", "1243", "IF1_1_ADC3 Mux"},
3582 {"TDM1 slot 67 Data Mux", "1324", "IF1_1_ADC4"},
3583 {"TDM1 slot 67 Data Mux", "1342", "IF1_1_ADC2 Mux"},
3584 {"TDM1 slot 67 Data Mux", "1432", "IF1_1_ADC2 Mux"},
3585 {"TDM1 slot 67 Data Mux", "1423", "IF1_1_ADC3 Mux"},
3586 {"TDM1 slot 67 Data Mux", "2134", "IF1_1_ADC4"},
3587 {"TDM1 slot 67 Data Mux", "2143", "IF1_1_ADC3 Mux"},
3588 {"TDM1 slot 67 Data Mux", "2314", "IF1_1_ADC4"},
3589 {"TDM1 slot 67 Data Mux", "2341", "IF1_1_ADC1 Mux"},
3590 {"TDM1 slot 67 Data Mux", "2431", "IF1_1_ADC1 Mux"},
3591 {"TDM1 slot 67 Data Mux", "2413", "IF1_1_ADC3 Mux"},
3592 {"TDM1 slot 67 Data Mux", "3124", "IF1_1_ADC4"},
3593 {"TDM1 slot 67 Data Mux", "3142", "IF1_1_ADC2 Mux"},
3594 {"TDM1 slot 67 Data Mux", "3214", "IF1_1_ADC4"},
3595 {"TDM1 slot 67 Data Mux", "3241", "IF1_1_ADC1 Mux"},
3596 {"TDM1 slot 67 Data Mux", "3412", "IF1_1_ADC2 Mux"},
3597 {"TDM1 slot 67 Data Mux", "3421", "IF1_1_ADC1 Mux"},
3598 {"TDM1 slot 67 Data Mux", "4123", "IF1_1_ADC3 Mux"},
3599 {"TDM1 slot 67 Data Mux", "4132", "IF1_1_ADC2 Mux"},
3600 {"TDM1 slot 67 Data Mux", "4213", "IF1_1_ADC3 Mux"},
3601 {"TDM1 slot 67 Data Mux", "4231", "IF1_1_ADC1 Mux"},
3602 {"TDM1 slot 67 Data Mux", "4312", "IF1_1_ADC2 Mux"},
3603 {"TDM1 slot 67 Data Mux", "4321", "IF1_1_ADC1 Mux"},
3604 {"TDM1 slot 67 Data Mux", NULL, "I2S1_1"},
3605
3606
3607 {"TDM2 slot 01 Data Mux", "1234", "IF1_2_ADC1 Mux"},
3608 {"TDM2 slot 01 Data Mux", "1243", "IF1_2_ADC1 Mux"},
3609 {"TDM2 slot 01 Data Mux", "1324", "IF1_2_ADC1 Mux"},
3610 {"TDM2 slot 01 Data Mux", "1342", "IF1_2_ADC1 Mux"},
3611 {"TDM2 slot 01 Data Mux", "1432", "IF1_2_ADC1 Mux"},
3612 {"TDM2 slot 01 Data Mux", "1423", "IF1_2_ADC1 Mux"},
3613 {"TDM2 slot 01 Data Mux", "2134", "IF1_2_ADC2 Mux"},
3614 {"TDM2 slot 01 Data Mux", "2143", "IF1_2_ADC2 Mux"},
3615 {"TDM2 slot 01 Data Mux", "2314", "IF1_2_ADC2 Mux"},
3616 {"TDM2 slot 01 Data Mux", "2341", "IF1_2_ADC2 Mux"},
3617 {"TDM2 slot 01 Data Mux", "2431", "IF1_2_ADC2 Mux"},
3618 {"TDM2 slot 01 Data Mux", "2413", "IF1_2_ADC2 Mux"},
3619 {"TDM2 slot 01 Data Mux", "3124", "IF1_2_ADC3 Mux"},
3620 {"TDM2 slot 01 Data Mux", "3142", "IF1_2_ADC3 Mux"},
3621 {"TDM2 slot 01 Data Mux", "3214", "IF1_2_ADC3 Mux"},
3622 {"TDM2 slot 01 Data Mux", "3241", "IF1_2_ADC3 Mux"},
3623 {"TDM2 slot 01 Data Mux", "3412", "IF1_2_ADC3 Mux"},
3624 {"TDM2 slot 01 Data Mux", "3421", "IF1_2_ADC3 Mux"},
3625 {"TDM2 slot 01 Data Mux", "4123", "IF1_2_ADC4 Mux"},
3626 {"TDM2 slot 01 Data Mux", "4132", "IF1_2_ADC4 Mux"},
3627 {"TDM2 slot 01 Data Mux", "4213", "IF1_2_ADC4 Mux"},
3628 {"TDM2 slot 01 Data Mux", "4231", "IF1_2_ADC4 Mux"},
3629 {"TDM2 slot 01 Data Mux", "4312", "IF1_2_ADC4 Mux"},
3630 {"TDM2 slot 01 Data Mux", "4321", "IF1_2_ADC4 Mux"},
3631 {"TDM2 slot 01 Data Mux", NULL, "I2S1_2"},
3632
3633 {"TDM2 slot 23 Data Mux", "1234", "IF1_2_ADC2 Mux"},
3634 {"TDM2 slot 23 Data Mux", "1243", "IF1_2_ADC2 Mux"},
3635 {"TDM2 slot 23 Data Mux", "1324", "IF1_2_ADC3 Mux"},
3636 {"TDM2 slot 23 Data Mux", "1342", "IF1_2_ADC3 Mux"},
3637 {"TDM2 slot 23 Data Mux", "1432", "IF1_2_ADC4 Mux"},
3638 {"TDM2 slot 23 Data Mux", "1423", "IF1_2_ADC4 Mux"},
3639 {"TDM2 slot 23 Data Mux", "2134", "IF1_2_ADC1 Mux"},
3640 {"TDM2 slot 23 Data Mux", "2143", "IF1_2_ADC1 Mux"},
3641 {"TDM2 slot 23 Data Mux", "2314", "IF1_2_ADC3 Mux"},
3642 {"TDM2 slot 23 Data Mux", "2341", "IF1_2_ADC3 Mux"},
3643 {"TDM2 slot 23 Data Mux", "2431", "IF1_2_ADC4 Mux"},
3644 {"TDM2 slot 23 Data Mux", "2413", "IF1_2_ADC4 Mux"},
3645 {"TDM2 slot 23 Data Mux", "3124", "IF1_2_ADC1 Mux"},
3646 {"TDM2 slot 23 Data Mux", "3142", "IF1_2_ADC1 Mux"},
3647 {"TDM2 slot 23 Data Mux", "3214", "IF1_2_ADC2 Mux"},
3648 {"TDM2 slot 23 Data Mux", "3241", "IF1_2_ADC2 Mux"},
3649 {"TDM2 slot 23 Data Mux", "3412", "IF1_2_ADC4 Mux"},
3650 {"TDM2 slot 23 Data Mux", "3421", "IF1_2_ADC4 Mux"},
3651 {"TDM2 slot 23 Data Mux", "4123", "IF1_2_ADC1 Mux"},
3652 {"TDM2 slot 23 Data Mux", "4132", "IF1_2_ADC1 Mux"},
3653 {"TDM2 slot 23 Data Mux", "4213", "IF1_2_ADC2 Mux"},
3654 {"TDM2 slot 23 Data Mux", "4231", "IF1_2_ADC2 Mux"},
3655 {"TDM2 slot 23 Data Mux", "4312", "IF1_2_ADC3 Mux"},
3656 {"TDM2 slot 23 Data Mux", "4321", "IF1_2_ADC3 Mux"},
3657 {"TDM2 slot 23 Data Mux", NULL, "I2S1_2"},
3658
3659 {"TDM2 slot 45 Data Mux", "1234", "IF1_2_ADC3 Mux"},
3660 {"TDM2 slot 45 Data Mux", "1243", "IF1_2_ADC4 Mux"},
3661 {"TDM2 slot 45 Data Mux", "1324", "IF1_2_ADC2 Mux"},
3662 {"TDM2 slot 45 Data Mux", "1342", "IF1_2_ADC4 Mux"},
3663 {"TDM2 slot 45 Data Mux", "1432", "IF1_2_ADC3 Mux"},
3664 {"TDM2 slot 45 Data Mux", "1423", "IF1_2_ADC2 Mux"},
3665 {"TDM2 slot 45 Data Mux", "2134", "IF1_2_ADC3 Mux"},
3666 {"TDM2 slot 45 Data Mux", "2143", "IF1_2_ADC4 Mux"},
3667 {"TDM2 slot 45 Data Mux", "2314", "IF1_2_ADC1 Mux"},
3668 {"TDM2 slot 45 Data Mux", "2341", "IF1_2_ADC4 Mux"},
3669 {"TDM2 slot 45 Data Mux", "2431", "IF1_2_ADC3 Mux"},
3670 {"TDM2 slot 45 Data Mux", "2413", "IF1_2_ADC1 Mux"},
3671 {"TDM2 slot 45 Data Mux", "3124", "IF1_2_ADC2 Mux"},
3672 {"TDM2 slot 45 Data Mux", "3142", "IF1_2_ADC4 Mux"},
3673 {"TDM2 slot 45 Data Mux", "3214", "IF1_2_ADC1 Mux"},
3674 {"TDM2 slot 45 Data Mux", "3241", "IF1_2_ADC4 Mux"},
3675 {"TDM2 slot 45 Data Mux", "3412", "IF1_2_ADC1 Mux"},
3676 {"TDM2 slot 45 Data Mux", "3421", "IF1_2_ADC2 Mux"},
3677 {"TDM2 slot 45 Data Mux", "4123", "IF1_2_ADC2 Mux"},
3678 {"TDM2 slot 45 Data Mux", "4132", "IF1_2_ADC3 Mux"},
3679 {"TDM2 slot 45 Data Mux", "4213", "IF1_2_ADC1 Mux"},
3680 {"TDM2 slot 45 Data Mux", "4231", "IF1_2_ADC3 Mux"},
3681 {"TDM2 slot 45 Data Mux", "4312", "IF1_2_ADC1 Mux"},
3682 {"TDM2 slot 45 Data Mux", "4321", "IF1_2_ADC2 Mux"},
3683 {"TDM2 slot 45 Data Mux", NULL, "I2S1_2"},
3684
3685 {"TDM2 slot 67 Data Mux", "1234", "IF1_2_ADC4 Mux"},
3686 {"TDM2 slot 67 Data Mux", "1243", "IF1_2_ADC3 Mux"},
3687 {"TDM2 slot 67 Data Mux", "1324", "IF1_2_ADC4 Mux"},
3688 {"TDM2 slot 67 Data Mux", "1342", "IF1_2_ADC2 Mux"},
3689 {"TDM2 slot 67 Data Mux", "1432", "IF1_2_ADC2 Mux"},
3690 {"TDM2 slot 67 Data Mux", "1423", "IF1_2_ADC3 Mux"},
3691 {"TDM2 slot 67 Data Mux", "2134", "IF1_2_ADC4 Mux"},
3692 {"TDM2 slot 67 Data Mux", "2143", "IF1_2_ADC3 Mux"},
3693 {"TDM2 slot 67 Data Mux", "2314", "IF1_2_ADC4 Mux"},
3694 {"TDM2 slot 67 Data Mux", "2341", "IF1_2_ADC1 Mux"},
3695 {"TDM2 slot 67 Data Mux", "2431", "IF1_2_ADC1 Mux"},
3696 {"TDM2 slot 67 Data Mux", "2413", "IF1_2_ADC3 Mux"},
3697 {"TDM2 slot 67 Data Mux", "3124", "IF1_2_ADC4 Mux"},
3698 {"TDM2 slot 67 Data Mux", "3142", "IF1_2_ADC2 Mux"},
3699 {"TDM2 slot 67 Data Mux", "3214", "IF1_2_ADC4 Mux"},
3700 {"TDM2 slot 67 Data Mux", "3241", "IF1_2_ADC1 Mux"},
3701 {"TDM2 slot 67 Data Mux", "3412", "IF1_2_ADC2 Mux"},
3702 {"TDM2 slot 67 Data Mux", "3421", "IF1_2_ADC1 Mux"},
3703 {"TDM2 slot 67 Data Mux", "4123", "IF1_2_ADC3 Mux"},
3704 {"TDM2 slot 67 Data Mux", "4132", "IF1_2_ADC2 Mux"},
3705 {"TDM2 slot 67 Data Mux", "4213", "IF1_2_ADC3 Mux"},
3706 {"TDM2 slot 67 Data Mux", "4231", "IF1_2_ADC1 Mux"},
3707 {"TDM2 slot 67 Data Mux", "4312", "IF1_2_ADC2 Mux"},
3708 {"TDM2 slot 67 Data Mux", "4321", "IF1_2_ADC1 Mux"},
3709 {"TDM2 slot 67 Data Mux", NULL, "I2S1_2"},
3710
3711 {"IF1_1 0 ADC Swap Mux", "L/R", "TDM1 slot 01 Data Mux"},
3712 {"IF1_1 0 ADC Swap Mux", "L/L", "TDM1 slot 01 Data Mux"},
3713 {"IF1_1 1 ADC Swap Mux", "R/L", "TDM1 slot 01 Data Mux"},
3714 {"IF1_1 1 ADC Swap Mux", "R/R", "TDM1 slot 01 Data Mux"},
3715 {"IF1_1 2 ADC Swap Mux", "L/R", "TDM1 slot 23 Data Mux"},
3716 {"IF1_1 2 ADC Swap Mux", "R/L", "TDM1 slot 23 Data Mux"},
3717 {"IF1_1 3 ADC Swap Mux", "L/L", "TDM1 slot 23 Data Mux"},
3718 {"IF1_1 3 ADC Swap Mux", "R/R", "TDM1 slot 23 Data Mux"},
3719 {"IF1_1 4 ADC Swap Mux", "L/R", "TDM1 slot 45 Data Mux"},
3720 {"IF1_1 4 ADC Swap Mux", "R/L", "TDM1 slot 45 Data Mux"},
3721 {"IF1_1 5 ADC Swap Mux", "L/L", "TDM1 slot 45 Data Mux"},
3722 {"IF1_1 5 ADC Swap Mux", "R/R", "TDM1 slot 45 Data Mux"},
3723 {"IF1_1 6 ADC Swap Mux", "L/R", "TDM1 slot 67 Data Mux"},
3724 {"IF1_1 6 ADC Swap Mux", "R/L", "TDM1 slot 67 Data Mux"},
3725 {"IF1_1 7 ADC Swap Mux", "L/L", "TDM1 slot 67 Data Mux"},
3726 {"IF1_1 7 ADC Swap Mux", "R/R", "TDM1 slot 67 Data Mux"},
3727 {"IF1_2 0 ADC Swap Mux", "L/R", "TDM2 slot 01 Data Mux"},
3728 {"IF1_2 0 ADC Swap Mux", "R/L", "TDM2 slot 01 Data Mux"},
3729 {"IF1_2 1 ADC Swap Mux", "L/L", "TDM2 slot 01 Data Mux"},
3730 {"IF1_2 1 ADC Swap Mux", "R/R", "TDM2 slot 01 Data Mux"},
3731 {"IF1_2 2 ADC Swap Mux", "L/R", "TDM2 slot 23 Data Mux"},
3732 {"IF1_2 2 ADC Swap Mux", "R/L", "TDM2 slot 23 Data Mux"},
3733 {"IF1_2 3 ADC Swap Mux", "L/L", "TDM2 slot 23 Data Mux"},
3734 {"IF1_2 3 ADC Swap Mux", "R/R", "TDM2 slot 23 Data Mux"},
3735 {"IF1_2 4 ADC Swap Mux", "L/R", "TDM2 slot 45 Data Mux"},
3736 {"IF1_2 4 ADC Swap Mux", "R/L", "TDM2 slot 45 Data Mux"},
3737 {"IF1_2 5 ADC Swap Mux", "L/L", "TDM2 slot 45 Data Mux"},
3738 {"IF1_2 5 ADC Swap Mux", "R/R", "TDM2 slot 45 Data Mux"},
3739 {"IF1_2 6 ADC Swap Mux", "L/R", "TDM2 slot 67 Data Mux"},
3740 {"IF1_2 6 ADC Swap Mux", "R/L", "TDM2 slot 67 Data Mux"},
3741 {"IF1_2 7 ADC Swap Mux", "L/L", "TDM2 slot 67 Data Mux"},
3742 {"IF1_2 7 ADC Swap Mux", "R/R", "TDM2 slot 67 Data Mux"},
3743
3744 {"IF2_1 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3745 {"IF2_1 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3746 {"IF2_1 ADC Mux", "MONO ADC", "Mono ADC MIX"},
3747 {"IF2_1 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
3748 {"IF2_1 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
3749 {"IF2_1 ADC Mux", "IF2_2 DAC", "IF2_2 DAC"},
3750 {"IF2_1 ADC Mux", "IF3 DAC", "IF3 DAC"},
3751 {"IF2_1 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
3752 {"IF2_1 ADC", NULL, "IF2_1 ADC Mux"},
3753 {"IF2_1 ADC", NULL, "I2S2_1"},
3754
3755 {"IF2_2 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3756 {"IF2_2 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3757 {"IF2_2 ADC Mux", "MONO ADC", "Mono ADC MIX"},
3758 {"IF2_2 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
3759 {"IF2_2 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
3760 {"IF2_2 ADC Mux", "IF2_1 DAC", "IF2_1 DAC"},
3761 {"IF2_2 ADC Mux", "IF3 DAC", "IF3 DAC"},
3762 {"IF2_2 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
3763 {"IF2_2 ADC", NULL, "IF2_2 ADC Mux"},
3764 {"IF2_2 ADC", NULL, "I2S2_2"},
3765
3766 {"IF3 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3767 {"IF3 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3768 {"IF3 ADC Mux", "MONO ADC", "Mono ADC MIX"},
3769 {"IF3 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
3770 {"IF3 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
3771 {"IF3 ADC Mux", "IF2_1 DAC", "IF2_1 DAC"},
3772 {"IF3 ADC Mux", "IF2_2 DAC", "IF2_2 DAC"},
3773 {"IF3 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
3774 {"IF3 ADC", NULL, "IF3 ADC Mux"},
3775 {"IF3 ADC", NULL, "I2S3"},
3776
3777 {"AIF1_1TX slot 0", NULL, "IF1_1 0 ADC Swap Mux"},
3778 {"AIF1_1TX slot 1", NULL, "IF1_1 1 ADC Swap Mux"},
3779 {"AIF1_1TX slot 2", NULL, "IF1_1 2 ADC Swap Mux"},
3780 {"AIF1_1TX slot 3", NULL, "IF1_1 3 ADC Swap Mux"},
3781 {"AIF1_1TX slot 4", NULL, "IF1_1 4 ADC Swap Mux"},
3782 {"AIF1_1TX slot 5", NULL, "IF1_1 5 ADC Swap Mux"},
3783 {"AIF1_1TX slot 6", NULL, "IF1_1 6 ADC Swap Mux"},
3784 {"AIF1_1TX slot 7", NULL, "IF1_1 7 ADC Swap Mux"},
3785 {"AIF1_2TX slot 0", NULL, "IF1_2 0 ADC Swap Mux"},
3786 {"AIF1_2TX slot 1", NULL, "IF1_2 1 ADC Swap Mux"},
3787 {"AIF1_2TX slot 2", NULL, "IF1_2 2 ADC Swap Mux"},
3788 {"AIF1_2TX slot 3", NULL, "IF1_2 3 ADC Swap Mux"},
3789 {"AIF1_2TX slot 4", NULL, "IF1_2 4 ADC Swap Mux"},
3790 {"AIF1_2TX slot 5", NULL, "IF1_2 5 ADC Swap Mux"},
3791 {"AIF1_2TX slot 6", NULL, "IF1_2 6 ADC Swap Mux"},
3792 {"AIF1_2TX slot 7", NULL, "IF1_2 7 ADC Swap Mux"},
3793 {"IF2_1 ADC Swap Mux", "L/R", "IF2_1 ADC"},
3794 {"IF2_1 ADC Swap Mux", "R/L", "IF2_1 ADC"},
3795 {"IF2_1 ADC Swap Mux", "L/L", "IF2_1 ADC"},
3796 {"IF2_1 ADC Swap Mux", "R/R", "IF2_1 ADC"},
3797 {"AIF2_1TX", NULL, "IF2_1 ADC Swap Mux"},
3798 {"IF2_2 ADC Swap Mux", "L/R", "IF2_2 ADC"},
3799 {"IF2_2 ADC Swap Mux", "R/L", "IF2_2 ADC"},
3800 {"IF2_2 ADC Swap Mux", "L/L", "IF2_2 ADC"},
3801 {"IF2_2 ADC Swap Mux", "R/R", "IF2_2 ADC"},
3802 {"AIF2_2TX", NULL, "IF2_2 ADC Swap Mux"},
3803 {"IF3 ADC Swap Mux", "L/R", "IF3 ADC"},
3804 {"IF3 ADC Swap Mux", "R/L", "IF3 ADC"},
3805 {"IF3 ADC Swap Mux", "L/L", "IF3 ADC"},
3806 {"IF3 ADC Swap Mux", "R/R", "IF3 ADC"},
3807 {"AIF3TX", NULL, "IF3 ADC Swap Mux"},
3808
3809 {"IF1 DAC1", NULL, "AIF1RX"},
3810 {"IF1 DAC2", NULL, "AIF1RX"},
3811 {"IF1 DAC3", NULL, "AIF1RX"},
3812 {"IF2_1 DAC Swap Mux", "L/R", "AIF2_1RX"},
3813 {"IF2_1 DAC Swap Mux", "R/L", "AIF2_1RX"},
3814 {"IF2_1 DAC Swap Mux", "L/L", "AIF2_1RX"},
3815 {"IF2_1 DAC Swap Mux", "R/R", "AIF2_1RX"},
3816 {"IF2_2 DAC Swap Mux", "L/R", "AIF2_2RX"},
3817 {"IF2_2 DAC Swap Mux", "R/L", "AIF2_2RX"},
3818 {"IF2_2 DAC Swap Mux", "L/L", "AIF2_2RX"},
3819 {"IF2_2 DAC Swap Mux", "R/R", "AIF2_2RX"},
3820 {"IF2_1 DAC", NULL, "IF2_1 DAC Swap Mux"},
3821 {"IF2_2 DAC", NULL, "IF2_2 DAC Swap Mux"},
3822 {"IF3 DAC Swap Mux", "L/R", "AIF3RX"},
3823 {"IF3 DAC Swap Mux", "R/L", "AIF3RX"},
3824 {"IF3 DAC Swap Mux", "L/L", "AIF3RX"},
3825 {"IF3 DAC Swap Mux", "R/R", "AIF3RX"},
3826 {"IF3 DAC", NULL, "IF3 DAC Swap Mux"},
3827
3828 {"IF1 DAC1", NULL, "I2S1_1"},
3829 {"IF1 DAC2", NULL, "I2S1_1"},
3830 {"IF1 DAC3", NULL, "I2S1_1"},
3831 {"IF2_1 DAC", NULL, "I2S2_1"},
3832 {"IF2_2 DAC", NULL, "I2S2_2"},
3833 {"IF3 DAC", NULL, "I2S3"},
3834
3835 {"IF1 DAC1 L", NULL, "IF1 DAC1"},
3836 {"IF1 DAC1 R", NULL, "IF1 DAC1"},
3837 {"IF1 DAC2 L", NULL, "IF1 DAC2"},
3838 {"IF1 DAC2 R", NULL, "IF1 DAC2"},
3839 {"IF1 DAC3 L", NULL, "IF1 DAC3"},
3840 {"IF1 DAC3 R", NULL, "IF1 DAC3"},
3841 {"IF2_1 DAC L", NULL, "IF2_1 DAC"},
3842 {"IF2_1 DAC R", NULL, "IF2_1 DAC"},
3843 {"IF2_2 DAC L", NULL, "IF2_2 DAC"},
3844 {"IF2_2 DAC R", NULL, "IF2_2 DAC"},
3845 {"IF3 DAC L", NULL, "IF3 DAC"},
3846 {"IF3 DAC R", NULL, "IF3 DAC"},
3847
3848 {"DAC L1 Mux", "IF1 DAC1", "IF1 DAC1 L"},
3849 {"DAC L1 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
3850 {"DAC L1 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
3851 {"DAC L1 Mux", "IF3 DAC", "IF3 DAC L"},
3852 {"DAC L1 Mux", NULL, "DAC Stereo1 Filter"},
3853
3854 {"DAC R1 Mux", "IF1 DAC1", "IF1 DAC1 R"},
3855 {"DAC R1 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
3856 {"DAC R1 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
3857 {"DAC R1 Mux", "IF3 DAC", "IF3 DAC R"},
3858 {"DAC R1 Mux", NULL, "DAC Stereo1 Filter"},
3859
3860 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
3861 {"DAC1 MIXL", "DAC1 Switch", "DAC L1 Mux"},
3862 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
3863 {"DAC1 MIXR", "DAC1 Switch", "DAC R1 Mux"},
3864
3865 {"DAC1 MIX", NULL, "DAC1 MIXL"},
3866 {"DAC1 MIX", NULL, "DAC1 MIXR"},
3867
3868 {"DAC L2 Mux", "IF1 DAC2", "IF1 DAC2 L"},
3869 {"DAC L2 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
3870 {"DAC L2 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
3871 {"DAC L2 Mux", "IF3 DAC", "IF3 DAC L"},
3872 {"DAC L2 Mux", "Mono ADC MIX", "Mono ADC MIXL"},
3873 {"DAC L2 Mux", NULL, "DAC Mono Left Filter"},
3874
3875 {"DAC R2 Mux", "IF1 DAC2", "IF1 DAC2 R"},
3876 {"DAC R2 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
3877 {"DAC R2 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
3878 {"DAC R2 Mux", "IF3 DAC", "IF3 DAC R"},
3879 {"DAC R2 Mux", "Mono ADC MIX", "Mono ADC MIXR"},
3880 {"DAC R2 Mux", NULL, "DAC Mono Right Filter"},
3881
3882 {"DAC L3 Mux", "IF1 DAC2", "IF1 DAC2 L"},
3883 {"DAC L3 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
3884 {"DAC L3 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
3885 {"DAC L3 Mux", "IF3 DAC", "IF3 DAC L"},
3886 {"DAC L3 Mux", "STO2 ADC MIX", "Stereo2 ADC MIXL"},
3887 {"DAC L3 Mux", NULL, "DAC Stereo2 Filter"},
3888
3889 {"DAC R3 Mux", "IF1 DAC2", "IF1 DAC2 R"},
3890 {"DAC R3 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
3891 {"DAC R3 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
3892 {"DAC R3 Mux", "IF3 DAC", "IF3 DAC R"},
3893 {"DAC R3 Mux", "STO2 ADC MIX", "Stereo2 ADC MIXR"},
3894 {"DAC R3 Mux", NULL, "DAC Stereo2 Filter"},
3895
3896 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
3897 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
3898 {"Stereo1 DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
3899 {"Stereo1 DAC MIXL", "DAC R2 Switch", "DAC R2 Mux"},
3900
3901 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
3902 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
3903 {"Stereo1 DAC MIXR", "DAC L2 Switch", "DAC L2 Mux"},
3904 {"Stereo1 DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
3905
3906 {"Stereo2 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
3907 {"Stereo2 DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
3908 {"Stereo2 DAC MIXL", "DAC L3 Switch", "DAC L3 Mux"},
3909
3910 {"Stereo2 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
3911 {"Stereo2 DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
3912 {"Stereo2 DAC MIXR", "DAC R3 Switch", "DAC R3 Mux"},
3913
3914 {"Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
3915 {"Mono DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
3916 {"Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
3917 {"Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Mux"},
3918 {"Mono DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
3919 {"Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
3920 {"Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Mux"},
3921 {"Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
3922
3923 {"DAC MIXL", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
3924 {"DAC MIXL", "Stereo2 DAC Mixer", "Stereo2 DAC MIXL"},
3925 {"DAC MIXL", "Mono DAC Mixer", "Mono DAC MIXL"},
3926 {"DAC MIXR", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
3927 {"DAC MIXR", "Stereo2 DAC Mixer", "Stereo2 DAC MIXR"},
3928 {"DAC MIXR", "Mono DAC Mixer", "Mono DAC MIXR"},
3929
3930 {"DAC L1 Source", "DAC1", "DAC1 MIXL"},
3931 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
3932 {"DAC L1 Source", "DMIC1", "DMIC L1"},
3933 {"DAC R1 Source", "DAC1", "DAC1 MIXR"},
3934 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
3935 {"DAC R1 Source", "DMIC1", "DMIC R1"},
3936
3937 {"DAC L2 Source", "DAC2", "DAC L2 Mux"},
3938 {"DAC L2 Source", "Mono DAC Mixer", "Mono DAC MIXL"},
3939 {"DAC L2 Source", NULL, "DAC L2 Power"},
3940 {"DAC R2 Source", "DAC2", "DAC R2 Mux"},
3941 {"DAC R2 Source", "Mono DAC Mixer", "Mono DAC MIXR"},
3942 {"DAC R2 Source", NULL, "DAC R2 Power"},
3943
3944 {"DAC L1", NULL, "DAC L1 Source"},
3945 {"DAC R1", NULL, "DAC R1 Source"},
3946 {"DAC L2", NULL, "DAC L2 Source"},
3947 {"DAC R2", NULL, "DAC R2 Source"},
3948
3949 {"DAC L1", NULL, "DAC 1 Clock"},
3950 {"DAC R1", NULL, "DAC 1 Clock"},
3951 {"DAC L2", NULL, "DAC 2 Clock"},
3952 {"DAC R2", NULL, "DAC 2 Clock"},
3953
3954 {"MONOVOL MIX", "DAC L2 Switch", "DAC L2"},
3955 {"MONOVOL MIX", "RECMIX2L Switch", "RECMIX2L"},
3956 {"MONOVOL MIX", "BST1 Switch", "BST1"},
3957 {"MONOVOL MIX", "BST2 Switch", "BST2"},
3958 {"MONOVOL MIX", "BST3 Switch", "BST3"},
3959
3960 {"OUT MIXL", "DAC L2 Switch", "DAC L2"},
3961 {"OUT MIXL", "INL Switch", "INL VOL"},
3962 {"OUT MIXL", "BST1 Switch", "BST1"},
3963 {"OUT MIXL", "BST2 Switch", "BST2"},
3964 {"OUT MIXL", "BST3 Switch", "BST3"},
3965 {"OUT MIXR", "DAC R2 Switch", "DAC R2"},
3966 {"OUT MIXR", "INR Switch", "INR VOL"},
3967 {"OUT MIXR", "BST2 Switch", "BST2"},
3968 {"OUT MIXR", "BST3 Switch", "BST3"},
3969 {"OUT MIXR", "BST4 Switch", "BST4"},
3970
3971 {"MONOVOL", "Switch", "MONOVOL MIX"},
3972 {"Mono MIX", "DAC L2 Switch", "DAC L2"},
3973 {"Mono MIX", "MONOVOL Switch", "MONOVOL"},
3974 {"Mono Amp", NULL, "Mono MIX"},
3975 {"Mono Amp", NULL, "Vref2"},
Bard Liao8f365312017-03-08 19:05:31 +0800[diff] [blame]3976 {"Mono Amp", NULL, "Vref3"},
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]3977 {"Mono Amp", NULL, "CLKDET SYS"},
3978 {"Mono Amp", NULL, "CLKDET MONO"},
3979 {"Mono Playback", "Switch", "Mono Amp"},
3980 {"MONOOUT", NULL, "Mono Playback"},
3981
3982 {"HP Amp", NULL, "DAC L1"},
3983 {"HP Amp", NULL, "DAC R1"},
3984 {"HP Amp", NULL, "Charge Pump"},
3985 {"HP Amp", NULL, "CLKDET SYS"},
3986 {"HP Amp", NULL, "CLKDET HP"},
3987 {"HP Amp", NULL, "CBJ Power"},
3988 {"HP Amp", NULL, "Vref2"},
3989 {"HPO Playback", "Switch", "HP Amp"},
3990 {"HPOL", NULL, "HPO Playback"},
3991 {"HPOR", NULL, "HPO Playback"},
3992
3993 {"OUTVOL L", "Switch", "OUT MIXL"},
3994 {"OUTVOL R", "Switch", "OUT MIXR"},
3995 {"LOUT L MIX", "DAC L2 Switch", "DAC L2"},
3996 {"LOUT L MIX", "OUTVOL L Switch", "OUTVOL L"},
3997 {"LOUT R MIX", "DAC R2 Switch", "DAC R2"},
3998 {"LOUT R MIX", "OUTVOL R Switch", "OUTVOL R"},
3999 {"LOUT Amp", NULL, "LOUT L MIX"},
4000 {"LOUT Amp", NULL, "LOUT R MIX"},
4001 {"LOUT Amp", NULL, "Vref1"},
4002 {"LOUT Amp", NULL, "Vref2"},
4003 {"LOUT Amp", NULL, "CLKDET SYS"},
4004 {"LOUT Amp", NULL, "CLKDET LOUT"},
4005 {"LOUT L Playback", "Switch", "LOUT Amp"},
4006 {"LOUT R Playback", "Switch", "LOUT Amp"},
4007 {"LOUTL", NULL, "LOUT L Playback"},
4008 {"LOUTR", NULL, "LOUT R Playback"},
4009
4010 {"PDM L Mux", "Mono DAC", "Mono DAC MIXL"},
4011 {"PDM L Mux", "Stereo1 DAC", "Stereo1 DAC MIXL"},
4012 {"PDM L Mux", "Stereo2 DAC", "Stereo2 DAC MIXL"},
4013 {"PDM L Mux", NULL, "PDM Power"},
4014 {"PDM R Mux", "Mono DAC", "Mono DAC MIXR"},
4015 {"PDM R Mux", "Stereo1 DAC", "Stereo1 DAC MIXR"},
4016 {"PDM R Mux", "Stereo2 DAC", "Stereo2 DAC MIXR"},
4017 {"PDM R Mux", NULL, "PDM Power"},
4018 {"PDM L Playback", "Switch", "PDM L Mux"},
4019 {"PDM R Playback", "Switch", "PDM R Mux"},
4020 {"PDML", NULL, "PDM L Playback"},
4021 {"PDMR", NULL, "PDM R Playback"},
4022};
4023
Bard Liao948059d2017-03-08 19:05:36 +0800[diff] [blame]4024static int rt5665_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
4025 unsigned int rx_mask, int slots, int slot_width)
4026{
4027 struct snd_soc_codec *codec = dai->codec;
4028 unsigned int val = 0;
4029
4030 if (rx_mask || tx_mask)
4031 val |= RT5665_I2S1_MODE_TDM;
4032
4033 switch (slots) {
4034 case 4:
4035 val |= RT5665_TDM_IN_CH_4;
4036 val |= RT5665_TDM_OUT_CH_4;
4037 break;
4038 case 6:
4039 val |= RT5665_TDM_IN_CH_6;
4040 val |= RT5665_TDM_OUT_CH_6;
4041 break;
4042 case 8:
4043 val |= RT5665_TDM_IN_CH_8;
4044 val |= RT5665_TDM_OUT_CH_8;
4045 break;
4046 case 2:
4047 break;
4048 default:
4049 return -EINVAL;
4050 }
4051
4052 switch (slot_width) {
4053 case 20:
4054 val |= RT5665_TDM_IN_LEN_20;
4055 val |= RT5665_TDM_OUT_LEN_20;
4056 break;
4057 case 24:
4058 val |= RT5665_TDM_IN_LEN_24;
4059 val |= RT5665_TDM_OUT_LEN_24;
4060 break;
4061 case 32:
4062 val |= RT5665_TDM_IN_LEN_32;
4063 val |= RT5665_TDM_OUT_LEN_32;
4064 break;
4065 case 16:
4066 break;
4067 default:
4068 return -EINVAL;
4069 }
4070
4071 snd_soc_update_bits(codec, RT5665_TDM_CTRL_1,
4072 RT5665_I2S1_MODE_MASK | RT5665_TDM_IN_CH_MASK |
4073 RT5665_TDM_OUT_CH_MASK | RT5665_TDM_IN_LEN_MASK |
4074 RT5665_TDM_OUT_LEN_MASK, val);
4075
4076 return 0;
4077}
4078
4079
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4080static int rt5665_hw_params(struct snd_pcm_substream *substream,
4081 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
4082{
4083 struct snd_soc_codec *codec = dai->codec;
4084 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
Bard Liao17febfa2017-03-20 10:20:54 +0800[diff] [blame]4085 unsigned int val_len = 0, val_clk, reg_clk, mask_clk, val_bits = 0x0100;
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4086 int pre_div, frame_size;
4087
4088 rt5665->lrck[dai->id] = params_rate(params);
4089 pre_div = rl6231_get_clk_info(rt5665->sysclk, rt5665->lrck[dai->id]);
4090 if (pre_div < 0) {
4091 dev_err(codec->dev, "Unsupported clock setting %d for DAI %d\n",
4092 rt5665->lrck[dai->id], dai->id);
4093 return -EINVAL;
4094 }
4095 frame_size = snd_soc_params_to_frame_size(params);
4096 if (frame_size < 0) {
4097 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
4098 return -EINVAL;
4099 }
4100
4101 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
4102 rt5665->lrck[dai->id], pre_div, dai->id);
4103
4104 switch (params_width(params)) {
4105 case 16:
4106 val_bits = 0x0100;
4107 break;
4108 case 20:
4109 val_len |= RT5665_I2S_DL_20;
4110 val_bits = 0x1300;
4111 break;
4112 case 24:
4113 val_len |= RT5665_I2S_DL_24;
4114 val_bits = 0x2500;
4115 break;
4116 case 8:
4117 val_len |= RT5665_I2S_DL_8;
4118 break;
4119 default:
4120 return -EINVAL;
4121 }
4122
4123 switch (dai->id) {
4124 case RT5665_AIF1_1:
4125 case RT5665_AIF1_2:
Bard Liao948059d2017-03-08 19:05:36 +0800[diff] [blame]4126 if (params_channels(params) > 2)
4127 rt5665_set_tdm_slot(dai, 0xf, 0xf,
4128 params_channels(params), params_width(params));
Bard Liao17febfa2017-03-20 10:20:54 +0800[diff] [blame]4129 reg_clk = RT5665_ADDA_CLK_1;
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4130 mask_clk = RT5665_I2S_PD1_MASK;
4131 val_clk = pre_div << RT5665_I2S_PD1_SFT;
4132 snd_soc_update_bits(codec, RT5665_I2S1_SDP,
4133 RT5665_I2S_DL_MASK, val_len);
4134 break;
4135 case RT5665_AIF2_1:
4136 case RT5665_AIF2_2:
Bard Liao17febfa2017-03-20 10:20:54 +0800[diff] [blame]4137 reg_clk = RT5665_ADDA_CLK_2;
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4138 mask_clk = RT5665_I2S_PD2_MASK;
4139 val_clk = pre_div << RT5665_I2S_PD2_SFT;
4140 snd_soc_update_bits(codec, RT5665_I2S2_SDP,
4141 RT5665_I2S_DL_MASK, val_len);
4142 break;
4143 case RT5665_AIF3:
Bard Liao17febfa2017-03-20 10:20:54 +0800[diff] [blame]4144 reg_clk = RT5665_ADDA_CLK_2;
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4145 mask_clk = RT5665_I2S_PD3_MASK;
4146 val_clk = pre_div << RT5665_I2S_PD3_SFT;
4147 snd_soc_update_bits(codec, RT5665_I2S3_SDP,
4148 RT5665_I2S_DL_MASK, val_len);
4149 break;
4150 default:
4151 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
4152 return -EINVAL;
4153 }
4154
Bard Liao17febfa2017-03-20 10:20:54 +0800[diff] [blame]4155 snd_soc_update_bits(codec, reg_clk, mask_clk, val_clk);
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4156 snd_soc_update_bits(codec, RT5665_STO1_DAC_SIL_DET, 0x3700, val_bits);
4157
4158 switch (rt5665->lrck[dai->id]) {
4159 case 192000:
4160 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
4161 RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK,
4162 RT5665_DAC_OSR_32 | RT5665_ADC_OSR_32);
4163 break;
4164 case 96000:
4165 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
4166 RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK,
4167 RT5665_DAC_OSR_64 | RT5665_ADC_OSR_64);
4168 break;
4169 default:
4170 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
4171 RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK,
4172 RT5665_DAC_OSR_128 | RT5665_ADC_OSR_128);
4173 break;
4174 }
4175
4176 return 0;
4177}
4178
4179static int rt5665_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
4180{
4181 struct snd_soc_codec *codec = dai->codec;
4182 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4183 unsigned int reg_val = 0;
4184
4185 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
4186 case SND_SOC_DAIFMT_CBM_CFM:
4187 rt5665->master[dai->id] = 1;
4188 break;
4189 case SND_SOC_DAIFMT_CBS_CFS:
4190 reg_val |= RT5665_I2S_MS_S;
4191 rt5665->master[dai->id] = 0;
4192 break;
4193 default:
4194 return -EINVAL;
4195 }
4196
4197 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
4198 case SND_SOC_DAIFMT_NB_NF:
4199 break;
4200 case SND_SOC_DAIFMT_IB_NF:
4201 reg_val |= RT5665_I2S_BP_INV;
4202 break;
4203 default:
4204 return -EINVAL;
4205 }
4206
4207 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
4208 case SND_SOC_DAIFMT_I2S:
4209 break;
4210 case SND_SOC_DAIFMT_LEFT_J:
4211 reg_val |= RT5665_I2S_DF_LEFT;
4212 break;
4213 case SND_SOC_DAIFMT_DSP_A:
4214 reg_val |= RT5665_I2S_DF_PCM_A;
4215 break;
4216 case SND_SOC_DAIFMT_DSP_B:
4217 reg_val |= RT5665_I2S_DF_PCM_B;
4218 break;
4219 default:
4220 return -EINVAL;
4221 }
4222
4223 switch (dai->id) {
4224 case RT5665_AIF1_1:
4225 case RT5665_AIF1_2:
4226 snd_soc_update_bits(codec, RT5665_I2S1_SDP,
4227 RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK |
4228 RT5665_I2S_DF_MASK, reg_val);
4229 break;
4230 case RT5665_AIF2_1:
4231 case RT5665_AIF2_2:
4232 snd_soc_update_bits(codec, RT5665_I2S2_SDP,
4233 RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK |
4234 RT5665_I2S_DF_MASK, reg_val);
4235 break;
4236 case RT5665_AIF3:
4237 snd_soc_update_bits(codec, RT5665_I2S3_SDP,
4238 RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK |
4239 RT5665_I2S_DF_MASK, reg_val);
4240 break;
4241 default:
4242 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
4243 return -EINVAL;
4244 }
4245 return 0;
4246}
4247
Bard Liao28d2ca32017-03-09 19:31:14 +0800[diff] [blame]4248static int rt5665_set_codec_sysclk(struct snd_soc_codec *codec, int clk_id,
4249 int source, unsigned int freq, int dir)
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4250{
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4251 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4252 unsigned int reg_val = 0;
4253
4254 if (freq == rt5665->sysclk && clk_id == rt5665->sysclk_src)
4255 return 0;
4256
4257 switch (clk_id) {
4258 case RT5665_SCLK_S_MCLK:
4259 reg_val |= RT5665_SCLK_SRC_MCLK;
4260 break;
4261 case RT5665_SCLK_S_PLL1:
4262 reg_val |= RT5665_SCLK_SRC_PLL1;
4263 break;
4264 case RT5665_SCLK_S_RCCLK:
4265 reg_val |= RT5665_SCLK_SRC_RCCLK;
4266 break;
4267 default:
4268 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
4269 return -EINVAL;
4270 }
4271 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4272 RT5665_SCLK_SRC_MASK, reg_val);
4273 rt5665->sysclk = freq;
4274 rt5665->sysclk_src = clk_id;
4275
Bard Liao28d2ca32017-03-09 19:31:14 +0800[diff] [blame]4276 dev_dbg(codec->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4277
4278 return 0;
4279}
4280
Bard Liaoccd00d52017-03-09 19:31:13 +0800[diff] [blame]4281static int rt5665_set_codec_pll(struct snd_soc_codec *codec, int pll_id,
4282 int source, unsigned int freq_in,
4283 unsigned int freq_out)
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4284{
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4285 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4286 struct rl6231_pll_code pll_code;
4287 int ret;
4288
Bard Liaoccd00d52017-03-09 19:31:13 +0800[diff] [blame]4289 if (source == rt5665->pll_src && freq_in == rt5665->pll_in &&
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4290 freq_out == rt5665->pll_out)
4291 return 0;
4292
4293 if (!freq_in || !freq_out) {
4294 dev_dbg(codec->dev, "PLL disabled\n");
4295
4296 rt5665->pll_in = 0;
4297 rt5665->pll_out = 0;
4298 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4299 RT5665_SCLK_SRC_MASK, RT5665_SCLK_SRC_MCLK);
4300 return 0;
4301 }
4302
Bard Liaoccd00d52017-03-09 19:31:13 +0800[diff] [blame]4303 switch (source) {
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4304 case RT5665_PLL1_S_MCLK:
4305 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4306 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_MCLK);
4307 break;
4308 case RT5665_PLL1_S_BCLK1:
4309 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4310 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK1);
4311 break;
4312 case RT5665_PLL1_S_BCLK2:
4313 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4314 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK2);
4315 break;
4316 case RT5665_PLL1_S_BCLK3:
4317 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4318 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK3);
4319 break;
4320 default:
Bard Liaoccd00d52017-03-09 19:31:13 +0800[diff] [blame]4321 dev_err(codec->dev, "Unknown PLL Source %d\n", source);
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4322 return -EINVAL;
4323 }
4324
4325 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
4326 if (ret < 0) {
4327 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
4328 return ret;
4329 }
4330
4331 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n",
4332 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
4333 pll_code.n_code, pll_code.k_code);
4334
4335 snd_soc_write(codec, RT5665_PLL_CTRL_1,
4336 pll_code.n_code << RT5665_PLL_N_SFT | pll_code.k_code);
4337 snd_soc_write(codec, RT5665_PLL_CTRL_2,
4338 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5665_PLL_M_SFT |
4339 pll_code.m_bp << RT5665_PLL_M_BP_SFT);
4340
4341 rt5665->pll_in = freq_in;
4342 rt5665->pll_out = freq_out;
Bard Liaoccd00d52017-03-09 19:31:13 +0800[diff] [blame]4343 rt5665->pll_src = source;
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4344
4345 return 0;
4346}
4347
4348static int rt5665_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
4349{
4350 struct snd_soc_codec *codec = dai->codec;
4351 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4352
4353 dev_dbg(codec->dev, "%s ratio=%d\n", __func__, ratio);
4354
4355 rt5665->bclk[dai->id] = ratio;
4356
4357 if (ratio == 64) {
4358 switch (dai->id) {
4359 case RT5665_AIF2_1:
4360 case RT5665_AIF2_2:
4361 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
4362 RT5665_I2S_BCLK_MS2_MASK,
4363 RT5665_I2S_BCLK_MS2_64);
4364 break;
4365 case RT5665_AIF3:
4366 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
4367 RT5665_I2S_BCLK_MS3_MASK,
4368 RT5665_I2S_BCLK_MS3_64);
4369 break;
4370 }
4371 }
4372
4373 return 0;
4374}
4375
4376static int rt5665_set_bias_level(struct snd_soc_codec *codec,
4377 enum snd_soc_bias_level level)
4378{
4379 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4380
4381 switch (level) {
4382 case SND_SOC_BIAS_PREPARE:
4383 regmap_update_bits(rt5665->regmap, RT5665_DIG_MISC,
4384 RT5665_DIG_GATE_CTRL, RT5665_DIG_GATE_CTRL);
4385 break;
4386
4387 case SND_SOC_BIAS_STANDBY:
4388 regmap_update_bits(rt5665->regmap, RT5665_PWR_DIG_1,
4389 RT5665_PWR_LDO, RT5665_PWR_LDO);
4390 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
4391 RT5665_PWR_MB, RT5665_PWR_MB);
4392 regmap_update_bits(rt5665->regmap, RT5665_DIG_MISC,
4393 RT5665_DIG_GATE_CTRL, 0);
4394 break;
4395 case SND_SOC_BIAS_OFF:
4396 regmap_update_bits(rt5665->regmap, RT5665_PWR_DIG_1,
4397 RT5665_PWR_LDO, 0);
4398 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
4399 RT5665_PWR_MB, 0);
4400 break;
4401
4402 default:
4403 break;
4404 }
4405
4406 return 0;
4407}
4408
4409static int rt5665_probe(struct snd_soc_codec *codec)
4410{
4411 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4412
4413 rt5665->codec = codec;
4414
4415 schedule_delayed_work(&rt5665->calibrate_work, msecs_to_jiffies(100));
4416
4417 return 0;
4418}
4419
4420static int rt5665_remove(struct snd_soc_codec *codec)
4421{
4422 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4423
4424 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4425
4426 return 0;
4427}
4428
4429#ifdef CONFIG_PM
4430static int rt5665_suspend(struct snd_soc_codec *codec)
4431{
4432 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4433
4434 regcache_cache_only(rt5665->regmap, true);
4435 regcache_mark_dirty(rt5665->regmap);
4436 return 0;
4437}
4438
4439static int rt5665_resume(struct snd_soc_codec *codec)
4440{
4441 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4442
4443 regcache_cache_only(rt5665->regmap, false);
4444 regcache_sync(rt5665->regmap);
4445
4446 return 0;
4447}
4448#else
4449#define rt5665_suspend NULL
4450#define rt5665_resume NULL
4451#endif
4452
4453#define RT5665_STEREO_RATES SNDRV_PCM_RATE_8000_192000
4454#define RT5665_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
4455 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
4456
4457static const struct snd_soc_dai_ops rt5665_aif_dai_ops = {
4458 .hw_params = rt5665_hw_params,
4459 .set_fmt = rt5665_set_dai_fmt,
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4460 .set_tdm_slot = rt5665_set_tdm_slot,
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4461 .set_bclk_ratio = rt5665_set_bclk_ratio,
4462};
4463
4464static struct snd_soc_dai_driver rt5665_dai[] = {
4465 {
4466 .name = "rt5665-aif1_1",
4467 .id = RT5665_AIF1_1,
4468 .playback = {
4469 .stream_name = "AIF1 Playback",
4470 .channels_min = 1,
4471 .channels_max = 8,
4472 .rates = RT5665_STEREO_RATES,
4473 .formats = RT5665_FORMATS,
4474 },
4475 .capture = {
4476 .stream_name = "AIF1_1 Capture",
4477 .channels_min = 1,
4478 .channels_max = 8,
4479 .rates = RT5665_STEREO_RATES,
4480 .formats = RT5665_FORMATS,
4481 },
4482 .ops = &rt5665_aif_dai_ops,
4483 },
4484 {
4485 .name = "rt5665-aif1_2",
4486 .id = RT5665_AIF1_2,
4487 .capture = {
4488 .stream_name = "AIF1_2 Capture",
4489 .channels_min = 1,
4490 .channels_max = 8,
4491 .rates = RT5665_STEREO_RATES,
4492 .formats = RT5665_FORMATS,
4493 },
4494 .ops = &rt5665_aif_dai_ops,
4495 },
4496 {
4497 .name = "rt5665-aif2_1",
4498 .id = RT5665_AIF2_1,
4499 .playback = {
4500 .stream_name = "AIF2_1 Playback",
4501 .channels_min = 1,
4502 .channels_max = 2,
4503 .rates = RT5665_STEREO_RATES,
4504 .formats = RT5665_FORMATS,
4505 },
4506 .capture = {
4507 .stream_name = "AIF2_1 Capture",
4508 .channels_min = 1,
4509 .channels_max = 2,
4510 .rates = RT5665_STEREO_RATES,
4511 .formats = RT5665_FORMATS,
4512 },
4513 .ops = &rt5665_aif_dai_ops,
4514 },
4515 {
4516 .name = "rt5665-aif2_2",
4517 .id = RT5665_AIF2_2,
4518 .playback = {
4519 .stream_name = "AIF2_2 Playback",
4520 .channels_min = 1,
4521 .channels_max = 2,
4522 .rates = RT5665_STEREO_RATES,
4523 .formats = RT5665_FORMATS,
4524 },
4525 .capture = {
4526 .stream_name = "AIF2_2 Capture",
4527 .channels_min = 1,
4528 .channels_max = 2,
4529 .rates = RT5665_STEREO_RATES,
4530 .formats = RT5665_FORMATS,
4531 },
4532 .ops = &rt5665_aif_dai_ops,
4533 },
4534 {
4535 .name = "rt5665-aif3",
4536 .id = RT5665_AIF3,
4537 .playback = {
4538 .stream_name = "AIF3 Playback",
4539 .channels_min = 1,
4540 .channels_max = 2,
4541 .rates = RT5665_STEREO_RATES,
4542 .formats = RT5665_FORMATS,
4543 },
4544 .capture = {
4545 .stream_name = "AIF3 Capture",
4546 .channels_min = 1,
4547 .channels_max = 2,
4548 .rates = RT5665_STEREO_RATES,
4549 .formats = RT5665_FORMATS,
4550 },
4551 .ops = &rt5665_aif_dai_ops,
4552 },
4553};
4554
4555static struct snd_soc_codec_driver soc_codec_dev_rt5665 = {
4556 .probe = rt5665_probe,
4557 .remove = rt5665_remove,
4558 .suspend = rt5665_suspend,
4559 .resume = rt5665_resume,
4560 .set_bias_level = rt5665_set_bias_level,
4561 .idle_bias_off = true,
4562 .component_driver = {
4563 .controls = rt5665_snd_controls,
4564 .num_controls = ARRAY_SIZE(rt5665_snd_controls),
4565 .dapm_widgets = rt5665_dapm_widgets,
4566 .num_dapm_widgets = ARRAY_SIZE(rt5665_dapm_widgets),
4567 .dapm_routes = rt5665_dapm_routes,
4568 .num_dapm_routes = ARRAY_SIZE(rt5665_dapm_routes),
Bard Liaoccd00d52017-03-09 19:31:13 +0800[diff] [blame]4569 },
Bard Liao28d2ca32017-03-09 19:31:14 +0800[diff] [blame]4570 .set_sysclk = rt5665_set_codec_sysclk,
Bard Liaoccd00d52017-03-09 19:31:13 +0800[diff] [blame]4571 .set_pll = rt5665_set_codec_pll,
Bard Liao97c415a2017-04-11 20:07:47 +0800[diff] [blame]4572 .set_jack = rt5665_set_jack_detect,
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4573};
4574
4575
4576static const struct regmap_config rt5665_regmap = {
4577 .reg_bits = 16,
4578 .val_bits = 16,
4579 .max_register = 0x0400,
4580 .volatile_reg = rt5665_volatile_register,
4581 .readable_reg = rt5665_readable_register,
4582 .cache_type = REGCACHE_RBTREE,
4583 .reg_defaults = rt5665_reg,
4584 .num_reg_defaults = ARRAY_SIZE(rt5665_reg),
4585 .use_single_rw = true,
4586};
4587
4588static const struct i2c_device_id rt5665_i2c_id[] = {
4589 {"rt5665", 0},
4590 {}
4591};
4592MODULE_DEVICE_TABLE(i2c, rt5665_i2c_id);
4593
4594static int rt5665_parse_dt(struct rt5665_priv *rt5665, struct device *dev)
4595{
4596 rt5665->pdata.in1_diff = of_property_read_bool(dev->of_node,
4597 "realtek,in1-differential");
4598 rt5665->pdata.in2_diff = of_property_read_bool(dev->of_node,
4599 "realtek,in2-differential");
4600 rt5665->pdata.in3_diff = of_property_read_bool(dev->of_node,
4601 "realtek,in3-differential");
4602 rt5665->pdata.in4_diff = of_property_read_bool(dev->of_node,
4603 "realtek,in4-differential");
4604
4605 of_property_read_u32(dev->of_node, "realtek,dmic1-data-pin",
4606 &rt5665->pdata.dmic1_data_pin);
4607 of_property_read_u32(dev->of_node, "realtek,dmic2-data-pin",
4608 &rt5665->pdata.dmic2_data_pin);
4609 of_property_read_u32(dev->of_node, "realtek,jd-src",
4610 &rt5665->pdata.jd_src);
4611
4612 rt5665->pdata.ldo1_en = of_get_named_gpio(dev->of_node,
4613 "realtek,ldo1-en-gpios", 0);
4614
4615 return 0;
4616}
4617
4618static void rt5665_calibrate(struct rt5665_priv *rt5665)
4619{
4620 int value, count;
4621
4622 mutex_lock(&rt5665->calibrate_mutex);
4623
4624 regcache_cache_bypass(rt5665->regmap, true);
4625
4626 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4627 regmap_write(rt5665->regmap, RT5665_BIAS_CUR_CTRL_8, 0xa602);
4628 regmap_write(rt5665->regmap, RT5665_HP_CHARGE_PUMP_1, 0x0c26);
4629 regmap_write(rt5665->regmap, RT5665_MONOMIX_IN_GAIN, 0x021f);
4630 regmap_write(rt5665->regmap, RT5665_MONO_OUT, 0x480a);
4631 regmap_write(rt5665->regmap, RT5665_PWR_MIXER, 0x083f);
4632 regmap_write(rt5665->regmap, RT5665_PWR_DIG_1, 0x0180);
4633 regmap_write(rt5665->regmap, RT5665_EJD_CTRL_1, 0x4040);
4634 regmap_write(rt5665->regmap, RT5665_HP_LOGIC_CTRL_2, 0x0000);
4635 regmap_write(rt5665->regmap, RT5665_DIG_MISC, 0x0001);
4636 regmap_write(rt5665->regmap, RT5665_MICBIAS_2, 0x0380);
4637 regmap_write(rt5665->regmap, RT5665_GLB_CLK, 0x8000);
4638 regmap_write(rt5665->regmap, RT5665_ADDA_CLK_1, 0x1000);
4639 regmap_write(rt5665->regmap, RT5665_CHOP_DAC, 0x3030);
4640 regmap_write(rt5665->regmap, RT5665_CALIB_ADC_CTRL, 0x3c05);
4641 regmap_write(rt5665->regmap, RT5665_PWR_ANLG_1, 0xaa3e);
4642 usleep_range(15000, 20000);
4643 regmap_write(rt5665->regmap, RT5665_PWR_ANLG_1, 0xfe7e);
4644 regmap_write(rt5665->regmap, RT5665_HP_CALIB_CTRL_2, 0x0321);
4645
4646 regmap_write(rt5665->regmap, RT5665_HP_CALIB_CTRL_1, 0xfc00);
4647 count = 0;
4648 while (true) {
4649 regmap_read(rt5665->regmap, RT5665_HP_CALIB_STA_1, &value);
4650 if (value & 0x8000)
4651 usleep_range(10000, 10005);
4652 else
4653 break;
4654
4655 if (count > 60) {
4656 pr_err("HP Calibration Failure\n");
4657 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4658 regcache_cache_bypass(rt5665->regmap, false);
Axel Lin0c956662016-11-16 21:08:41 +0800[diff] [blame]4659 goto out_unlock;
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4660 }
4661
4662 count++;
4663 }
4664
4665 regmap_write(rt5665->regmap, RT5665_MONO_AMP_CALIB_CTRL_1, 0x9e24);
4666 count = 0;
4667 while (true) {
4668 regmap_read(rt5665->regmap, RT5665_MONO_AMP_CALIB_STA1, &value);
4669 if (value & 0x8000)
4670 usleep_range(10000, 10005);
4671 else
4672 break;
4673
4674 if (count > 60) {
4675 pr_err("MONO Calibration Failure\n");
4676 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4677 regcache_cache_bypass(rt5665->regmap, false);
Axel Lin0c956662016-11-16 21:08:41 +0800[diff] [blame]4678 goto out_unlock;
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4679 }
4680
4681 count++;
4682 }
4683
4684 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4685 regcache_cache_bypass(rt5665->regmap, false);
4686
4687 regcache_mark_dirty(rt5665->regmap);
4688 regcache_sync(rt5665->regmap);
4689
4690 regmap_write(rt5665->regmap, RT5665_BIAS_CUR_CTRL_8, 0xa602);
4691 regmap_write(rt5665->regmap, RT5665_ASRC_8, 0x0120);
4692
Axel Lin0c956662016-11-16 21:08:41 +0800[diff] [blame]4693out_unlock:
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4694 mutex_unlock(&rt5665->calibrate_mutex);
4695}
4696
4697static void rt5665_calibrate_handler(struct work_struct *work)
4698{
4699 struct rt5665_priv *rt5665 = container_of(work, struct rt5665_priv,
4700 calibrate_work.work);
4701
4702 while (!rt5665->codec->component.card->instantiated) {
4703 pr_debug("%s\n", __func__);
4704 usleep_range(10000, 15000);
4705 }
4706
4707 rt5665_calibrate(rt5665);
4708}
4709
4710static int rt5665_i2c_probe(struct i2c_client *i2c,
4711 const struct i2c_device_id *id)
4712{
4713 struct rt5665_platform_data *pdata = dev_get_platdata(&i2c->dev);
4714 struct rt5665_priv *rt5665;
4715 int i, ret;
4716 unsigned int val;
4717
4718 rt5665 = devm_kzalloc(&i2c->dev, sizeof(struct rt5665_priv),
4719 GFP_KERNEL);
4720
4721 if (rt5665 == NULL)
4722 return -ENOMEM;
4723
4724 i2c_set_clientdata(i2c, rt5665);
4725
4726 if (pdata)
4727 rt5665->pdata = *pdata;
4728 else
4729 rt5665_parse_dt(rt5665, &i2c->dev);
4730
4731 for (i = 0; i < ARRAY_SIZE(rt5665->supplies); i++)
4732 rt5665->supplies[i].supply = rt5665_supply_names[i];
4733
4734 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(rt5665->supplies),
4735 rt5665->supplies);
4736 if (ret != 0) {
4737 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
4738 return ret;
4739 }
4740
4741 ret = regulator_bulk_enable(ARRAY_SIZE(rt5665->supplies),
4742 rt5665->supplies);
4743 if (ret != 0) {
4744 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
4745 return ret;
4746 }
4747
4748 if (gpio_is_valid(rt5665->pdata.ldo1_en)) {
Axel Linf2826c12016-11-16 21:08:42 +0800[diff] [blame]4749 if (devm_gpio_request_one(&i2c->dev, rt5665->pdata.ldo1_en,
4750 GPIOF_OUT_INIT_HIGH, "rt5665"))
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4751 dev_err(&i2c->dev, "Fail gpio_request gpio_ldo\n");
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4752 }
4753
4754 /* Sleep for 300 ms miniumum */
4755 usleep_range(300000, 350000);
4756
4757 rt5665->regmap = devm_regmap_init_i2c(i2c, &rt5665_regmap);
4758 if (IS_ERR(rt5665->regmap)) {
4759 ret = PTR_ERR(rt5665->regmap);
4760 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
4761 ret);
4762 return ret;
4763 }
4764
4765 regmap_read(rt5665->regmap, RT5665_DEVICE_ID, &val);
4766 if (val != DEVICE_ID) {
4767 dev_err(&i2c->dev,
4768 "Device with ID register %x is not rt5665\n", val);
4769 return -ENODEV;
4770 }
4771
4772 regmap_read(rt5665->regmap, RT5665_RESET, &val);
4773 switch (val) {
4774 case 0x0:
4775 rt5665->id = CODEC_5666;
4776 break;
4777 case 0x6:
4778 rt5665->id = CODEC_5668;
4779 break;
4780 case 0x3:
4781 default:
4782 rt5665->id = CODEC_5665;
4783 break;
4784 }
4785
4786 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4787
4788 /* line in diff mode*/
4789 if (rt5665->pdata.in1_diff)
4790 regmap_update_bits(rt5665->regmap, RT5665_IN1_IN2,
4791 RT5665_IN1_DF_MASK, RT5665_IN1_DF_MASK);
4792 if (rt5665->pdata.in2_diff)
4793 regmap_update_bits(rt5665->regmap, RT5665_IN1_IN2,
4794 RT5665_IN2_DF_MASK, RT5665_IN2_DF_MASK);
4795 if (rt5665->pdata.in3_diff)
4796 regmap_update_bits(rt5665->regmap, RT5665_IN3_IN4,
4797 RT5665_IN3_DF_MASK, RT5665_IN3_DF_MASK);
4798 if (rt5665->pdata.in4_diff)
4799 regmap_update_bits(rt5665->regmap, RT5665_IN3_IN4,
4800 RT5665_IN4_DF_MASK, RT5665_IN4_DF_MASK);
4801
4802 /* DMIC pin*/
4803 if (rt5665->pdata.dmic1_data_pin != RT5665_DMIC1_NULL ||
4804 rt5665->pdata.dmic2_data_pin != RT5665_DMIC2_NULL) {
4805 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_2,
4806 RT5665_GP9_PIN_MASK, RT5665_GP9_PIN_DMIC1_SCL);
4807 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
4808 RT5665_GP8_PIN_MASK, RT5665_GP8_PIN_DMIC2_SCL);
4809 switch (rt5665->pdata.dmic1_data_pin) {
4810 case RT5665_DMIC1_DATA_IN2N:
4811 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
4812 RT5665_DMIC_1_DP_MASK, RT5665_DMIC_1_DP_IN2N);
4813 break;
4814
4815 case RT5665_DMIC1_DATA_GPIO4:
4816 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
4817 RT5665_DMIC_1_DP_MASK, RT5665_DMIC_1_DP_GPIO4);
4818 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
4819 RT5665_GP4_PIN_MASK, RT5665_GP4_PIN_DMIC1_SDA);
4820 break;
4821
4822 default:
4823 dev_dbg(&i2c->dev, "no DMIC1\n");
4824 break;
4825 }
4826
4827 switch (rt5665->pdata.dmic2_data_pin) {
4828 case RT5665_DMIC2_DATA_IN2P:
4829 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
4830 RT5665_DMIC_2_DP_MASK, RT5665_DMIC_2_DP_IN2P);
4831 break;
4832
4833 case RT5665_DMIC2_DATA_GPIO5:
4834 regmap_update_bits(rt5665->regmap,
4835 RT5665_DMIC_CTRL_1,
4836 RT5665_DMIC_2_DP_MASK,
4837 RT5665_DMIC_2_DP_GPIO5);
4838 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
4839 RT5665_GP5_PIN_MASK, RT5665_GP5_PIN_DMIC2_SDA);
4840 break;
4841
4842 default:
4843 dev_dbg(&i2c->dev, "no DMIC2\n");
4844 break;
4845
4846 }
4847 }
4848
4849 regmap_write(rt5665->regmap, RT5665_HP_LOGIC_CTRL_2, 0x0002);
4850 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
Bard Liao39841942017-03-08 19:05:30 +0800[diff] [blame]4851 0xf000 | RT5665_VREF_POW_MASK, 0xe000 | RT5665_VREF_POW_REG);
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4852 /* Work around for pow_pump */
4853 regmap_update_bits(rt5665->regmap, RT5665_STO1_DAC_SIL_DET,
4854 RT5665_DEB_STO_DAC_MASK, RT5665_DEB_80_MS);
4855
4856 regmap_update_bits(rt5665->regmap, RT5665_HP_CHARGE_PUMP_1,
4857 RT5665_PM_HP_MASK, RT5665_PM_HP_HV);
4858
4859 /* Set GPIO4,8 as input for combo jack */
4860 if (rt5665->id == CODEC_5666) {
4861 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_2,
4862 RT5665_GP4_PF_MASK, RT5665_GP4_PF_IN);
4863 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_3,
4864 RT5665_GP8_PF_MASK, RT5665_GP8_PF_IN);
4865 }
4866
4867 /* Enhance performance*/
4868 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
4869 RT5665_HP_DRIVER_MASK | RT5665_LDO1_DVO_MASK,
Bard Liao593dd5d2017-03-08 19:05:29 +0800[diff] [blame]4870 RT5665_HP_DRIVER_5X | RT5665_LDO1_DVO_12);
Bard Liao33ada142016-11-14 11:00:10 +0800[diff] [blame]4871
4872 INIT_DELAYED_WORK(&rt5665->jack_detect_work,
4873 rt5665_jack_detect_handler);
4874 INIT_DELAYED_WORK(&rt5665->calibrate_work,
4875 rt5665_calibrate_handler);
4876 INIT_DELAYED_WORK(&rt5665->jd_check_work,
4877 rt5665_jd_check_handler);
4878
4879 mutex_init(&rt5665->calibrate_mutex);
4880
4881 if (i2c->irq) {
4882 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
4883 rt5665_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
4884 | IRQF_ONESHOT, "rt5665", rt5665);
4885 if (ret)
4886 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
4887
4888 }
4889
4890 return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5665,
4891 rt5665_dai, ARRAY_SIZE(rt5665_dai));
4892}
4893
4894static int rt5665_i2c_remove(struct i2c_client *i2c)
4895{
4896 snd_soc_unregister_codec(&i2c->dev);
4897
4898 return 0;
4899}
4900
4901static void rt5665_i2c_shutdown(struct i2c_client *client)
4902{
4903 struct rt5665_priv *rt5665 = i2c_get_clientdata(client);
4904
4905 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4906}
4907
4908#ifdef CONFIG_OF
4909static const struct of_device_id rt5665_of_match[] = {
4910 {.compatible = "realtek,rt5665"},
4911 {.compatible = "realtek,rt5666"},
4912 {.compatible = "realtek,rt5668"},
4913 {},
4914};
4915MODULE_DEVICE_TABLE(of, rt5665_of_match);
4916#endif
4917
4918#ifdef CONFIG_ACPI
4919static struct acpi_device_id rt5665_acpi_match[] = {
4920 {"10EC5665", 0,},
4921 {"10EC5666", 0,},
4922 {"10EC5668", 0,},
4923 {},
4924};
4925MODULE_DEVICE_TABLE(acpi, rt5665_acpi_match);
4926#endif
4927
4928struct i2c_driver rt5665_i2c_driver = {
4929 .driver = {
4930 .name = "rt5665",
4931 .of_match_table = of_match_ptr(rt5665_of_match),
4932 .acpi_match_table = ACPI_PTR(rt5665_acpi_match),
4933 },
4934 .probe = rt5665_i2c_probe,
4935 .remove = rt5665_i2c_remove,
4936 .shutdown = rt5665_i2c_shutdown,
4937 .id_table = rt5665_i2c_id,
4938};
4939module_i2c_driver(rt5665_i2c_driver);
4940
4941MODULE_DESCRIPTION("ASoC RT5665 driver");
4942MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
4943MODULE_LICENSE("GPL v2");