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Sujith394cf0a2009-02-09 13:26:54 +05301/*
Sujith Manoharan5b681382011-05-17 13:36:18 +05302 * Copyright (c) 2008-2011 Atheros Communications Inc.
Sujith394cf0a2009-02-09 13:26:54 +05303 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef DEBUG_H
18#define DEBUG_H
19
Luis R. Rodriguez4d6b2282009-09-07 04:52:26 -070020#include "hw.h"
Felix Fietkau545750d2009-11-23 22:21:01 +010021#include "rc.h"
Zefir Kurtisi29942bc2011-12-14 20:16:34 -080022#include "dfs_debug.h"
Luis R. Rodriguez4d6b2282009-09-07 04:52:26 -070023
Sujithfec247c2009-07-27 12:08:16 +053024struct ath_txq;
25struct ath_buf;
Simon Wunderliche93d0832013-01-08 14:48:58 +010026struct fft_sample_tlv;
Sujithfec247c2009-07-27 12:08:16 +053027
Felix Fietkaua830df02009-11-23 22:33:27 +010028#ifdef CONFIG_ATH9K_DEBUGFS
Sujithfec247c2009-07-27 12:08:16 +053029#define TX_STAT_INC(q, c) sc->debug.stats.txstats[q].c++
Sujith Manoharan350e2dc2014-01-13 07:29:30 +053030#define RX_STAT_INC(c) (sc->debug.stats.rxstats.c++)
Felix Fietkau030d6292011-10-07 02:28:13 +020031#define RESET_STAT_INC(sc, type) sc->debug.stats.reset[type]++
Sujith Manoharan3fbaf4c2013-08-01 11:53:17 +053032#define ANT_STAT_INC(i, c) sc->debug.stats.ant_stats[i].c++
Sujith Manoharane3d52912013-08-01 20:57:06 +053033#define ANT_LNA_INC(i, c) sc->debug.stats.ant_stats[i].lna_recv_cnt[c]++;
Sujithfec247c2009-07-27 12:08:16 +053034#else
35#define TX_STAT_INC(q, c) do { } while (0)
Sujith Manoharan350e2dc2014-01-13 07:29:30 +053036#define RX_STAT_INC(c)
Felix Fietkau030d6292011-10-07 02:28:13 +020037#define RESET_STAT_INC(sc, type) do { } while (0)
Sujith Manoharan3fbaf4c2013-08-01 11:53:17 +053038#define ANT_STAT_INC(i, c) do { } while (0)
39#define ANT_LNA_INC(i, c) do { } while (0)
Sujithfec247c2009-07-27 12:08:16 +053040#endif
41
Rajkumar Manoharan124b9792012-07-17 17:16:42 +053042enum ath_reset_type {
43 RESET_TYPE_BB_HANG,
44 RESET_TYPE_BB_WATCHDOG,
45 RESET_TYPE_FATAL_INT,
46 RESET_TYPE_TX_ERROR,
47 RESET_TYPE_TX_HANG,
48 RESET_TYPE_PLL_HANG,
49 RESET_TYPE_MAC_HANG,
50 RESET_TYPE_BEACON_STUCK,
Rajkumar Manoharanb88083b2012-11-20 18:30:00 +053051 RESET_TYPE_MCI,
Rajkumar Manoharan124b9792012-07-17 17:16:42 +053052 __RESET_TYPE_MAX
53};
54
Felix Fietkaua830df02009-11-23 22:33:27 +010055#ifdef CONFIG_ATH9K_DEBUGFS
Sujith394cf0a2009-02-09 13:26:54 +053056
57/**
58 * struct ath_interrupt_stats - Contains statistics about interrupts
59 * @total: Total no. of interrupts generated so far
60 * @rxok: RX with no errors
Luis R. Rodrigueza9616f42010-04-15 17:39:30 -040061 * @rxlp: RX with low priority RX
62 * @rxhp: RX with high priority, uapsd only
Sujith394cf0a2009-02-09 13:26:54 +053063 * @rxeol: RX with no more RXDESC available
64 * @rxorn: RX FIFO overrun
65 * @txok: TX completed at the requested rate
66 * @txurn: TX FIFO underrun
67 * @mib: MIB regs reaching its threshold
68 * @rxphyerr: RX with phy errors
69 * @rx_keycache_miss: RX with key cache misses
70 * @swba: Software Beacon Alert
71 * @bmiss: Beacon Miss
72 * @bnr: Beacon Not Ready
73 * @cst: Carrier Sense TImeout
74 * @gtt: Global TX Timeout
75 * @tim: RX beacon TIM occurrence
76 * @cabend: RX End of CAB traffic
77 * @dtimsync: DTIM sync lossage
78 * @dtim: RX Beacon with DTIM
Luis R. Rodriguez08578b82010-05-13 13:33:44 -040079 * @bb_watchdog: Baseband watchdog
Mohammed Shafi Shajakhan6dde1aa2011-04-22 17:27:01 +053080 * @tsfoor: TSF out of range, indicates that the corrected TSF received
81 * from a beacon differs from the PCU's internal TSF by more than a
82 * (programmable) threshold
Ben Greear462e58f2012-04-12 10:04:00 -070083 * @local_timeout: Internal bus timeout.
Mohammed Shafi Shajakhanc9e6e982012-09-07 15:54:13 +053084 * @mci: MCI interrupt, specific to MCI based BTCOEX chipsets
85 * @gen_timer: Generic hardware timer interrupt
Sujith394cf0a2009-02-09 13:26:54 +053086 */
87struct ath_interrupt_stats {
88 u32 total;
89 u32 rxok;
Luis R. Rodrigueza9616f42010-04-15 17:39:30 -040090 u32 rxlp;
91 u32 rxhp;
Sujith394cf0a2009-02-09 13:26:54 +053092 u32 rxeol;
93 u32 rxorn;
94 u32 txok;
95 u32 txeol;
96 u32 txurn;
97 u32 mib;
98 u32 rxphyerr;
99 u32 rx_keycache_miss;
100 u32 swba;
101 u32 bmiss;
102 u32 bnr;
103 u32 cst;
104 u32 gtt;
105 u32 tim;
106 u32 cabend;
107 u32 dtimsync;
108 u32 dtim;
Luis R. Rodriguez08578b82010-05-13 13:33:44 -0400109 u32 bb_watchdog;
Mohammed Shafi Shajakhan6dde1aa2011-04-22 17:27:01 +0530110 u32 tsfoor;
Sujith Manoharan97ba5152012-06-04 16:27:41 +0530111 u32 mci;
Mohammed Shafi Shajakhanc9e6e982012-09-07 15:54:13 +0530112 u32 gen_timer;
Ben Greear462e58f2012-04-12 10:04:00 -0700113
114 /* Sync-cause stats */
115 u32 sync_cause_all;
116 u32 sync_rtc_irq;
117 u32 sync_mac_irq;
118 u32 eeprom_illegal_access;
119 u32 apb_timeout;
120 u32 pci_mode_conflict;
121 u32 host1_fatal;
122 u32 host1_perr;
123 u32 trcv_fifo_perr;
124 u32 radm_cpl_ep;
125 u32 radm_cpl_dllp_abort;
126 u32 radm_cpl_tlp_abort;
127 u32 radm_cpl_ecrc_err;
128 u32 radm_cpl_timeout;
129 u32 local_timeout;
130 u32 pm_access;
131 u32 mac_awake;
132 u32 mac_asleep;
133 u32 mac_sleep_access;
Sujith394cf0a2009-02-09 13:26:54 +0530134};
135
Ben Greear462e58f2012-04-12 10:04:00 -0700136
Sujithfec247c2009-07-27 12:08:16 +0530137/**
138 * struct ath_tx_stats - Statistics about TX
Ben Greear99c15bf2010-10-01 12:26:30 -0700139 * @tx_pkts_all: No. of total frames transmitted, including ones that
140 may have had errors.
141 * @tx_bytes_all: No. of total bytes transmitted, including ones that
142 may have had errors.
Sujithfec247c2009-07-27 12:08:16 +0530143 * @queued: Total MPDUs (non-aggr) queued
144 * @completed: Total MPDUs (non-aggr) completed
145 * @a_aggr: Total no. of aggregates queued
Ben Greearbda8add2011-01-09 23:11:48 -0800146 * @a_queued_hw: Total AMPDUs queued to hardware
147 * @a_queued_sw: Total AMPDUs queued to software queues
Sujithfec247c2009-07-27 12:08:16 +0530148 * @a_completed: Total AMPDUs completed
149 * @a_retries: No. of AMPDUs retried (SW)
150 * @a_xretries: No. of AMPDUs dropped due to xretries
Ben Greear4d900382013-03-04 15:31:16 -0800151 * @txerr_filtered: No. of frames with TXERR_FILT flag set.
Sujithfec247c2009-07-27 12:08:16 +0530152 * @fifo_underrun: FIFO underrun occurrences
153 Valid only for:
154 - non-aggregate condition.
155 - first packet of aggregate.
156 * @xtxop: No. of frames filtered because of TXOP limit
157 * @timer_exp: Transmit timer expiry
158 * @desc_cfg_err: Descriptor configuration errors
159 * @data_urn: TX data underrun errors
160 * @delim_urn: TX delimiter underrun errors
Ben Greear2dac4fb2011-01-09 23:11:45 -0800161 * @puttxbuf: Number of times hardware was given txbuf to write.
162 * @txstart: Number of times hardware was told to start tx.
163 * @txprocdesc: Number of times tx descriptor was processed
Ben Greeara5a0bca2012-04-03 09:16:55 -0700164 * @txfailed: Out-of-memory or other errors in xmit path.
Sujithfec247c2009-07-27 12:08:16 +0530165 */
166struct ath_tx_stats {
Ben Greear99c15bf2010-10-01 12:26:30 -0700167 u32 tx_pkts_all;
168 u32 tx_bytes_all;
Sujithfec247c2009-07-27 12:08:16 +0530169 u32 queued;
170 u32 completed;
Felix Fietkau5a6f78a2011-05-31 21:21:41 +0200171 u32 xretries;
Sujithfec247c2009-07-27 12:08:16 +0530172 u32 a_aggr;
Ben Greearbda8add2011-01-09 23:11:48 -0800173 u32 a_queued_hw;
174 u32 a_queued_sw;
Sujithfec247c2009-07-27 12:08:16 +0530175 u32 a_completed;
176 u32 a_retries;
177 u32 a_xretries;
Ben Greear4d900382013-03-04 15:31:16 -0800178 u32 txerr_filtered;
Sujithfec247c2009-07-27 12:08:16 +0530179 u32 fifo_underrun;
180 u32 xtxop;
181 u32 timer_exp;
182 u32 desc_cfg_err;
183 u32 data_underrun;
184 u32 delim_underrun;
Ben Greear2dac4fb2011-01-09 23:11:45 -0800185 u32 puttxbuf;
186 u32 txstart;
187 u32 txprocdesc;
Ben Greeara5a0bca2012-04-03 09:16:55 -0700188 u32 txfailed;
Sujithfec247c2009-07-27 12:08:16 +0530189};
190
Sujith Manoharan78ef7312012-11-21 18:13:11 +0530191/*
192 * Various utility macros to print TX/Queue counters.
193 */
194#define PR_QNUM(_n) sc->tx.txq_map[_n]->axq_qnum
195#define TXSTATS sc->debug.stats.txstats
196#define PR(str, elem) \
197 do { \
Zefir Kurtisi5e88ba62013-09-05 14:11:57 +0200198 len += scnprintf(buf + len, size - len, \
199 "%s%13u%11u%10u%10u\n", str, \
200 TXSTATS[PR_QNUM(IEEE80211_AC_BE)].elem,\
201 TXSTATS[PR_QNUM(IEEE80211_AC_BK)].elem,\
202 TXSTATS[PR_QNUM(IEEE80211_AC_VI)].elem,\
203 TXSTATS[PR_QNUM(IEEE80211_AC_VO)].elem); \
Sujith Manoharan78ef7312012-11-21 18:13:11 +0530204 } while(0)
205
Sujith Manoharan350e2dc2014-01-13 07:29:30 +0530206struct ath_rx_rate_stats {
207 struct {
208 u32 ht20_cnt;
209 u32 ht40_cnt;
210 u32 sgi_cnt;
211 u32 lgi_cnt;
212 } ht_stats[24];
213
214 struct {
215 u32 ofdm_cnt;
216 } ofdm_stats[8];
217
218 struct {
219 u32 cck_lp_cnt;
220 u32 cck_sp_cnt;
221 } cck_stats[4];
222};
Ben Greear15072182012-04-03 09:18:59 -0700223
Sujith1395d3f2010-01-08 10:36:11 +0530224/**
225 * struct ath_rx_stats - RX Statistics
Ben Greear99c15bf2010-10-01 12:26:30 -0700226 * @rx_pkts_all: No. of total frames received, including ones that
227 may have had errors.
228 * @rx_bytes_all: No. of total bytes received, including ones that
229 may have had errors.
Sujith1395d3f2010-01-08 10:36:11 +0530230 * @crc_err: No. of frames with incorrect CRC value
231 * @decrypt_crc_err: No. of frames whose CRC check failed after
232 decryption process completed
233 * @phy_err: No. of frames whose reception failed because the PHY
234 encountered an error
235 * @mic_err: No. of frames with incorrect TKIP MIC verification failure
236 * @pre_delim_crc_err: Pre-Frame delimiter CRC error detections
237 * @post_delim_crc_err: Post-Frame delimiter CRC error detections
238 * @decrypt_busy_err: Decryption interruptions counter
239 * @phy_err_stats: Individual PHY error statistics
Ben Greear15072182012-04-03 09:18:59 -0700240 * @rx_len_err: No. of frames discarded due to bad length.
241 * @rx_oom_err: No. of frames dropped due to OOM issues.
242 * @rx_rate_err: No. of frames dropped due to rate errors.
243 * @rx_too_many_frags_err: Frames dropped due to too-many-frags received.
Ben Greear15072182012-04-03 09:18:59 -0700244 * @rx_beacons: No. of beacons received.
245 * @rx_frags: No. of rx-fragements received.
Simon Wunderlich9b99e662013-01-23 17:38:05 +0100246 * @rx_spectral: No of spectral packets received.
Sujith1395d3f2010-01-08 10:36:11 +0530247 */
248struct ath_rx_stats {
Ben Greear99c15bf2010-10-01 12:26:30 -0700249 u32 rx_pkts_all;
250 u32 rx_bytes_all;
Sujith1395d3f2010-01-08 10:36:11 +0530251 u32 crc_err;
252 u32 decrypt_crc_err;
253 u32 phy_err;
254 u32 mic_err;
255 u32 pre_delim_crc_err;
256 u32 post_delim_crc_err;
257 u32 decrypt_busy_err;
258 u32 phy_err_stats[ATH9K_PHYERR_MAX];
Ben Greear15072182012-04-03 09:18:59 -0700259 u32 rx_len_err;
260 u32 rx_oom_err;
261 u32 rx_rate_err;
262 u32 rx_too_many_frags_err;
Ben Greear15072182012-04-03 09:18:59 -0700263 u32 rx_beacons;
264 u32 rx_frags;
Simon Wunderlich9b99e662013-01-23 17:38:05 +0100265 u32 rx_spectral;
Sujith1395d3f2010-01-08 10:36:11 +0530266};
267
Sujith Manoharan3fbaf4c2013-08-01 11:53:17 +0530268#define ANT_MAIN 0
269#define ANT_ALT 1
270
271struct ath_antenna_stats {
272 u32 recv_cnt;
Sujith Manoharane3d52912013-08-01 20:57:06 +0530273 u32 rssi_avg;
274 u32 lna_recv_cnt[4];
275 u32 lna_attempt_cnt[4];
Sujith Manoharan3fbaf4c2013-08-01 11:53:17 +0530276};
277
Sujith394cf0a2009-02-09 13:26:54 +0530278struct ath_stats {
279 struct ath_interrupt_stats istats;
Sujith Manoharan4f7dc952012-12-07 20:25:30 +0530280 struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES];
Sujith1395d3f2010-01-08 10:36:11 +0530281 struct ath_rx_stats rxstats;
Zefir Kurtisi29942bc2011-12-14 20:16:34 -0800282 struct ath_dfs_stats dfs_stats;
Sujith Manoharan3fbaf4c2013-08-01 11:53:17 +0530283 struct ath_antenna_stats ant_stats[2];
Felix Fietkau030d6292011-10-07 02:28:13 +0200284 u32 reset[__RESET_TYPE_MAX];
Sujith394cf0a2009-02-09 13:26:54 +0530285};
286
287struct ath9k_debug {
Sujith394cf0a2009-02-09 13:26:54 +0530288 struct dentry *debugfs_phy;
Felix Fietkau9bff0bc2010-05-11 17:23:02 +0200289 u32 regidx;
Sujith394cf0a2009-02-09 13:26:54 +0530290 struct ath_stats stats;
291};
292
Luis R. Rodriguez4d6b2282009-09-07 04:52:26 -0700293int ath9k_init_debug(struct ath_hw *ah);
Sujith Manoharanaf690092013-05-10 18:41:06 +0530294void ath9k_deinit_debug(struct ath_softc *sc);
Luis R. Rodriguez4d6b2282009-09-07 04:52:26 -0700295
Sujith394cf0a2009-02-09 13:26:54 +0530296void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status);
Felix Fietkau066dae92010-11-07 14:59:39 +0100297void ath_debug_stat_tx(struct ath_softc *sc, struct ath_buf *bf,
Felix Fietkau55797b12011-09-14 21:24:16 +0200298 struct ath_tx_status *ts, struct ath_txq *txq,
299 unsigned int flags);
Felix Fietkau8e6f5aa2010-03-29 20:09:27 -0700300void ath_debug_stat_rx(struct ath_softc *sc, struct ath_rx_status *rs);
Sujith Manoharanc175db82012-11-28 15:08:52 +0530301int ath9k_get_et_sset_count(struct ieee80211_hw *hw,
302 struct ieee80211_vif *vif, int sset);
303void ath9k_get_et_stats(struct ieee80211_hw *hw,
304 struct ieee80211_vif *vif,
305 struct ethtool_stats *stats, u64 *data);
306void ath9k_get_et_strings(struct ieee80211_hw *hw,
307 struct ieee80211_vif *vif,
308 u32 sset, u8 *data);
Sujith Manoharana145daf2012-11-28 15:08:54 +0530309void ath9k_sta_add_debugfs(struct ieee80211_hw *hw,
310 struct ieee80211_vif *vif,
311 struct ieee80211_sta *sta,
312 struct dentry *dir);
Sujith Manoharane3d52912013-08-01 20:57:06 +0530313void ath9k_debug_stat_ant(struct ath_softc *sc,
314 struct ath_hw_antcomb_conf *div_ant_conf,
315 int main_rssi_avg, int alt_rssi_avg);
Felix Fietkau6a4d05d2013-12-19 18:01:48 +0100316void ath9k_debug_sync_cause(struct ath_softc *sc, u32 sync_cause);
317
Sujith394cf0a2009-02-09 13:26:54 +0530318#else
319
Luis R. Rodriguez4d6b2282009-09-07 04:52:26 -0700320static inline int ath9k_init_debug(struct ath_hw *ah)
Sujith394cf0a2009-02-09 13:26:54 +0530321{
322 return 0;
323}
324
Sujith Manoharanaf690092013-05-10 18:41:06 +0530325static inline void ath9k_deinit_debug(struct ath_softc *sc)
326{
327}
Sujith394cf0a2009-02-09 13:26:54 +0530328static inline void ath_debug_stat_interrupt(struct ath_softc *sc,
329 enum ath9k_int status)
330{
331}
Sujithfec247c2009-07-27 12:08:16 +0530332static inline void ath_debug_stat_tx(struct ath_softc *sc,
Felix Fietkau32ffb1f2010-03-31 15:41:36 -0700333 struct ath_buf *bf,
Felix Fietkau3bf63e52011-01-28 17:52:49 +0100334 struct ath_tx_status *ts,
Felix Fietkau55797b12011-09-14 21:24:16 +0200335 struct ath_txq *txq,
336 unsigned int flags)
Sujithfec247c2009-07-27 12:08:16 +0530337{
338}
Sujith1395d3f2010-01-08 10:36:11 +0530339static inline void ath_debug_stat_rx(struct ath_softc *sc,
Felix Fietkau32ffb1f2010-03-31 15:41:36 -0700340 struct ath_rx_status *rs)
Sujith1395d3f2010-01-08 10:36:11 +0530341{
342}
Sujith Manoharane3d52912013-08-01 20:57:06 +0530343static inline void ath9k_debug_stat_ant(struct ath_softc *sc,
344 struct ath_hw_antcomb_conf *div_ant_conf,
345 int main_rssi_avg, int alt_rssi_avg)
346{
347
348}
Sujith1395d3f2010-01-08 10:36:11 +0530349
Felix Fietkau6a4d05d2013-12-19 18:01:48 +0100350static inline void
351ath9k_debug_sync_cause(struct ath_softc *sc, u32 sync_cause)
352{
353}
354
Felix Fietkaua830df02009-11-23 22:33:27 +0100355#endif /* CONFIG_ATH9K_DEBUGFS */
Sujith394cf0a2009-02-09 13:26:54 +0530356
Sujith Manoharan350e2dc2014-01-13 07:29:30 +0530357#ifdef CONFIG_ATH9K_STATION_STATISTICS
358void ath_debug_rate_stats(struct ath_softc *sc,
359 struct ath_rx_status *rs,
360 struct sk_buff *skb);
361#else
362static inline void ath_debug_rate_stats(struct ath_softc *sc,
363 struct ath_rx_status *rs,
364 struct sk_buff *skb)
365{
366}
367#endif /* CONFIG_ATH9K_STATION_STATISTICS */
368
Sujith394cf0a2009-02-09 13:26:54 +0530369#endif /* DEBUG_H */