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Maxime Ripard4790ecf2013-07-17 10:07:10 +02001/*
2 * Copyright 2013 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
Maxime Ripard394c56c2014-09-02 19:25:26 +02006 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
Maxime Ripard4790ecf2013-07-17 10:07:10 +020010 *
Maxime Ripard5186d832014-10-17 11:38:23 +020011 * a) This file is free software; you can redistribute it and/or
Maxime Ripard394c56c2014-09-02 19:25:26 +020012 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
Maxime Ripard5186d832014-10-17 11:38:23 +020016 * This file is distributed in the hope that it will be useful,
Maxime Ripard394c56c2014-09-02 19:25:26 +020017 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
Maxime Ripard5186d832014-10-17 11:38:23 +020022 * License along with this file; if not, write to the Free
Maxime Ripard394c56c2014-09-02 19:25:26 +020023 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
Maxime Ripard4790ecf2013-07-17 10:07:10 +020048 */
49
Maxime Ripard71455702014-12-16 22:59:54 +010050#include "skeleton.dtsi"
Maxime Ripard4790ecf2013-07-17 10:07:10 +020051
Maxime Ripard19882b82014-12-16 22:59:58 +010052#include <dt-bindings/interrupt-controller/arm-gic.h>
Chen-Yu Tsaib6d34242015-01-12 12:34:03 +080053#include <dt-bindings/thermal/thermal.h>
Maxime Ripard19882b82014-12-16 22:59:58 +010054
Maxime Ripard1f9f6a72014-12-16 22:59:56 +010055#include <dt-bindings/dma/sun4i-a10.h>
Maxime Ripard092a0c32014-12-16 22:59:57 +010056#include <dt-bindings/pinctrl/sun4i-a10.h>
Maxime Ripard4790ecf2013-07-17 10:07:10 +020057
58/ {
59 interrupt-parent = <&gic>;
60
Emilio Lópeze751cce2013-11-16 15:17:29 -030061 aliases {
Chen-Yu Tsai18428f72014-02-10 18:35:54 +080062 ethernet0 = &gmac;
Emilio Lópeze751cce2013-11-16 15:17:29 -030063 };
64
Hans de Goede8efc5c22014-11-14 16:34:37 +010065 chosen {
66 #address-cells = <1>;
67 #size-cells = <1>;
68 ranges;
69
Hans de Goedea9f8cda2014-11-18 12:07:13 +010070 framebuffer@0 {
71 compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
72 allwinner,pipeline = "de_be0-lcd0-hdmi";
Hans de Goede678e75d2014-11-16 17:09:32 +010073 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
74 <&ahb_gates 44>;
Hans de Goede8efc5c22014-11-14 16:34:37 +010075 status = "disabled";
76 };
Hans de Goedefd18c7e2015-01-19 14:05:12 +010077
78 framebuffer@1 {
79 compatible = "allwinner,simple-framebuffer",
80 "simple-framebuffer";
81 allwinner,pipeline = "de_be0-lcd0";
82 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
83 status = "disabled";
84 };
85
86 framebuffer@2 {
87 compatible = "allwinner,simple-framebuffer",
88 "simple-framebuffer";
89 allwinner,pipeline = "de_be0-lcd0-tve0";
90 clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
91 <&ahb_gates 44>;
92 status = "disabled";
93 };
Hans de Goede8efc5c22014-11-14 16:34:37 +010094 };
95
Maxime Ripard4790ecf2013-07-17 10:07:10 +020096 cpus {
97 #address-cells = <1>;
98 #size-cells = <0>;
99
Chen-Yu Tsaid96b7162015-01-06 10:35:16 +0800100 cpu0: cpu@0 {
Maxime Ripard4790ecf2013-07-17 10:07:10 +0200101 compatible = "arm,cortex-a7";
102 device_type = "cpu";
103 reg = <0>;
Chen-Yu Tsaid96b7162015-01-06 10:35:16 +0800104 clocks = <&cpu>;
105 clock-latency = <244144>; /* 8 32k periods */
106 operating-points = <
107 /* kHz uV */
Chen-Yu Tsaid96b7162015-01-06 10:35:16 +0800108 960000 1400000
109 912000 1400000
110 864000 1300000
111 720000 1200000
112 528000 1100000
113 312000 1000000
114 144000 900000
115 >;
116 #cooling-cells = <2>;
117 cooling-min-level = <0>;
Chen-Yu Tsai370a9b52015-03-25 00:53:27 +0800118 cooling-max-level = <6>;
Maxime Ripard4790ecf2013-07-17 10:07:10 +0200119 };
120
121 cpu@1 {
122 compatible = "arm,cortex-a7";
123 device_type = "cpu";
124 reg = <1>;
125 };
126 };
127
Chen-Yu Tsaib6d34242015-01-12 12:34:03 +0800128 thermal-zones {
129 cpu_thermal {
130 /* milliseconds */
131 polling-delay-passive = <250>;
132 polling-delay = <1000>;
133 thermal-sensors = <&rtp>;
134
135 cooling-maps {
136 map0 {
137 trip = <&cpu_alert0>;
138 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
139 };
140 };
141
142 trips {
143 cpu_alert0: cpu_alert0 {
144 /* milliCelsius */
145 temperature = <75000>;
146 hysteresis = <2000>;
147 type = "passive";
148 };
149
150 cpu_crit: cpu_crit {
151 /* milliCelsius */
152 temperature = <100000>;
153 hysteresis = <2000>;
154 type = "critical";
155 };
156 };
157 };
158 };
159
Maxime Ripard4790ecf2013-07-17 10:07:10 +0200160 memory {
161 reg = <0x40000000 0x80000000>;
162 };
163
Marc Zyngier79027632014-02-18 14:04:44 +0000164 timer {
165 compatible = "arm,armv7-timer";
Maxime Ripard19882b82014-12-16 22:59:58 +0100166 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
167 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
168 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
169 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
Marc Zyngier79027632014-02-18 14:04:44 +0000170 };
171
Maxime Riparde29ea4d2014-04-17 21:54:41 +0200172 pmu {
173 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
Maxime Ripard19882b82014-12-16 22:59:58 +0100174 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
175 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
Maxime Riparde29ea4d2014-04-17 21:54:41 +0200176 };
177
Maxime Ripard4790ecf2013-07-17 10:07:10 +0200178 clocks {
179 #address-cells = <1>;
180 #size-cells = <1>;
181 ranges;
182
Chen-Yu Tsai06067a22014-02-03 09:51:44 +0800183 osc24M: clk@01c20050 {
Maxime Ripard4790ecf2013-07-17 10:07:10 +0200184 #clock-cells = <0>;
Maxime Ripardbf6534a2014-02-06 09:55:58 +0100185 compatible = "allwinner,sun4i-a10-osc-clk";
Maxime Ripardde7dc932013-07-25 21:12:52 +0200186 reg = <0x01c20050 0x4>;
Maxime Ripard4790ecf2013-07-17 10:07:10 +0200187 clock-frequency = <24000000>;
Chen-Yu Tsai06067a22014-02-03 09:51:44 +0800188 clock-output-names = "osc24M";
Maxime Ripard4790ecf2013-07-17 10:07:10 +0200189 };
190
Chen-Yu Tsai673fac72014-01-01 10:30:47 +0800191 osc32k: clk@0 {
Maxime Ripard4790ecf2013-07-17 10:07:10 +0200192 #clock-cells = <0>;
193 compatible = "fixed-clock";
194 clock-frequency = <32768>;
Chen-Yu Tsai673fac72014-01-01 10:30:47 +0800195 clock-output-names = "osc32k";
Maxime Ripard4790ecf2013-07-17 10:07:10 +0200196 };
Maxime Ripardde7dc932013-07-25 21:12:52 +0200197
Chen-Yu Tsai06067a22014-02-03 09:51:44 +0800198 pll1: clk@01c20000 {
Maxime Ripardde7dc932013-07-25 21:12:52 +0200199 #clock-cells = <0>;
Maxime Ripardbf6534a2014-02-06 09:55:58 +0100200 compatible = "allwinner,sun4i-a10-pll1-clk";
Maxime Ripardde7dc932013-07-25 21:12:52 +0200201 reg = <0x01c20000 0x4>;
202 clocks = <&osc24M>;
Chen-Yu Tsai06067a22014-02-03 09:51:44 +0800203 clock-output-names = "pll1";
Maxime Ripardde7dc932013-07-25 21:12:52 +0200204 };
205
Chen-Yu Tsai06067a22014-02-03 09:51:44 +0800206 pll4: clk@01c20018 {
Maxime Ripardde7dc932013-07-25 21:12:52 +0200207 #clock-cells = <0>;
Emilio López04ebcb52014-03-19 15:19:31 -0300208 compatible = "allwinner,sun7i-a20-pll4-clk";
Emilio Lópezec5589f2013-12-23 00:32:35 -0300209 reg = <0x01c20018 0x4>;
210 clocks = <&osc24M>;
Chen-Yu Tsai06067a22014-02-03 09:51:44 +0800211 clock-output-names = "pll4";
Emilio Lópezec5589f2013-12-23 00:32:35 -0300212 };
213
Chen-Yu Tsai06067a22014-02-03 09:51:44 +0800214 pll5: clk@01c20020 {
Emilio Lópezc3e5e662013-12-23 00:32:38 -0300215 #clock-cells = <1>;
Maxime Ripardbf6534a2014-02-06 09:55:58 +0100216 compatible = "allwinner,sun4i-a10-pll5-clk";
Emilio Lópezc3e5e662013-12-23 00:32:38 -0300217 reg = <0x01c20020 0x4>;
218 clocks = <&osc24M>;
219 clock-output-names = "pll5_ddr", "pll5_other";
220 };
221
Chen-Yu Tsai06067a22014-02-03 09:51:44 +0800222 pll6: clk@01c20028 {
Emilio Lópezc3e5e662013-12-23 00:32:38 -0300223 #clock-cells = <1>;
Maxime Ripardbf6534a2014-02-06 09:55:58 +0100224 compatible = "allwinner,sun4i-a10-pll6-clk";
Emilio Lópezc3e5e662013-12-23 00:32:38 -0300225 reg = <0x01c20028 0x4>;
226 clocks = <&osc24M>;
Chen-Yu Tsai2186df32015-03-25 01:22:09 +0800227 clock-output-names = "pll6_sata", "pll6_other", "pll6",
228 "pll6_div_4";
Maxime Ripardde7dc932013-07-25 21:12:52 +0200229 };
230
Emilio López04ebcb52014-03-19 15:19:31 -0300231 pll8: clk@01c20040 {
232 #clock-cells = <0>;
233 compatible = "allwinner,sun7i-a20-pll4-clk";
234 reg = <0x01c20040 0x4>;
235 clocks = <&osc24M>;
236 clock-output-names = "pll8";
237 };
238
Maxime Ripardde7dc932013-07-25 21:12:52 +0200239 cpu: cpu@01c20054 {
240 #clock-cells = <0>;
Maxime Ripardbf6534a2014-02-06 09:55:58 +0100241 compatible = "allwinner,sun4i-a10-cpu-clk";
Maxime Ripardde7dc932013-07-25 21:12:52 +0200242 reg = <0x01c20054 0x4>;
Emilio Lópezc3e5e662013-12-23 00:32:38 -0300243 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
Chen-Yu Tsai06067a22014-02-03 09:51:44 +0800244 clock-output-names = "cpu";
Maxime Ripardde7dc932013-07-25 21:12:52 +0200245 };
246
247 axi: axi@01c20054 {
248 #clock-cells = <0>;
Maxime Ripardbf6534a2014-02-06 09:55:58 +0100249 compatible = "allwinner,sun4i-a10-axi-clk";
Maxime Ripardde7dc932013-07-25 21:12:52 +0200250 reg = <0x01c20054 0x4>;
251 clocks = <&cpu>;
Chen-Yu Tsai06067a22014-02-03 09:51:44 +0800252 clock-output-names = "axi";
Maxime Ripardde7dc932013-07-25 21:12:52 +0200253 };
254
255 ahb: ahb@01c20054 {
256 #clock-cells = <0>;
Chen-Yu Tsai2186df32015-03-25 01:22:09 +0800257 compatible = "allwinner,sun5i-a13-ahb-clk";
Maxime Ripardde7dc932013-07-25 21:12:52 +0200258 reg = <0x01c20054 0x4>;
Chen-Yu Tsai2186df32015-03-25 01:22:09 +0800259 clocks = <&axi>, <&pll6 3>, <&pll6 1>;
Chen-Yu Tsai06067a22014-02-03 09:51:44 +0800260 clock-output-names = "ahb";
Chen-Yu Tsai2186df32015-03-25 01:22:09 +0800261 /*
262 * Use PLL6 as parent, instead of CPU/AXI
263 * which has rate changes due to cpufreq
264 */
265 assigned-clocks = <&ahb>;
266 assigned-clock-parents = <&pll6 3>;
Maxime Ripardde7dc932013-07-25 21:12:52 +0200267 };
268
Chen-Yu Tsai06067a22014-02-03 09:51:44 +0800269 ahb_gates: clk@01c20060 {
Maxime Ripardde7dc932013-07-25 21:12:52 +0200270 #clock-cells = <1>;
271 compatible = "allwinner,sun7i-a20-ahb-gates-clk";
272 reg = <0x01c20060 0x8>;
273 clocks = <&ahb>;
274 clock-output-names = "ahb_usb0", "ahb_ehci0",
275 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
276 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
277 "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
278 "ahb_nand", "ahb_sdram", "ahb_ace",
279 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
280 "ahb_spi2", "ahb_spi3", "ahb_sata",
281 "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
282 "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
283 "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
284 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
285 "ahb_de_fe1", "ahb_gmac", "ahb_mp",
286 "ahb_mali";
287 };
288
289 apb0: apb0@01c20054 {
290 #clock-cells = <0>;
Maxime Ripardbf6534a2014-02-06 09:55:58 +0100291 compatible = "allwinner,sun4i-a10-apb0-clk";
Maxime Ripardde7dc932013-07-25 21:12:52 +0200292 reg = <0x01c20054 0x4>;
293 clocks = <&ahb>;
Chen-Yu Tsai06067a22014-02-03 09:51:44 +0800294 clock-output-names = "apb0";
Maxime Ripardde7dc932013-07-25 21:12:52 +0200295 };
296
Chen-Yu Tsai06067a22014-02-03 09:51:44 +0800297 apb0_gates: clk@01c20068 {
Maxime Ripardde7dc932013-07-25 21:12:52 +0200298 #clock-cells = <1>;
299 compatible = "allwinner,sun7i-a20-apb0-gates-clk";
300 reg = <0x01c20068 0x4>;
301 clocks = <&apb0>;
302 clock-output-names = "apb0_codec", "apb0_spdif",
303 "apb0_ac97", "apb0_iis0", "apb0_iis1",
304 "apb0_pio", "apb0_ir0", "apb0_ir1",
305 "apb0_iis2", "apb0_keypad";
306 };
307
Emilio Lópezacbcc0f2014-11-06 11:40:30 +0800308 apb1: clk@01c20058 {
Maxime Ripardde7dc932013-07-25 21:12:52 +0200309 #clock-cells = <0>;
Maxime Ripardbf6534a2014-02-06 09:55:58 +0100310 compatible = "allwinner,sun4i-a10-apb1-clk";
Maxime Ripardde7dc932013-07-25 21:12:52 +0200311 reg = <0x01c20058 0x4>;
Emilio Lópezacbcc0f2014-11-06 11:40:30 +0800312 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
Chen-Yu Tsai06067a22014-02-03 09:51:44 +0800313 clock-output-names = "apb1";
Maxime Ripardde7dc932013-07-25 21:12:52 +0200314 };
315
Chen-Yu Tsai06067a22014-02-03 09:51:44 +0800316 apb1_gates: clk@01c2006c {
Maxime Ripardde7dc932013-07-25 21:12:52 +0200317 #clock-cells = <1>;
318 compatible = "allwinner,sun7i-a20-apb1-gates-clk";
319 reg = <0x01c2006c 0x4>;
320 clocks = <&apb1>;
321 clock-output-names = "apb1_i2c0", "apb1_i2c1",
322 "apb1_i2c2", "apb1_i2c3", "apb1_can",
323 "apb1_scr", "apb1_ps20", "apb1_ps21",
324 "apb1_i2c4", "apb1_uart0", "apb1_uart1",
325 "apb1_uart2", "apb1_uart3", "apb1_uart4",
326 "apb1_uart5", "apb1_uart6", "apb1_uart7";
327 };
Emilio López1c92b952013-12-23 00:32:43 -0300328
329 nand_clk: clk@01c20080 {
330 #clock-cells = <0>;
Maxime Ripardbf6534a2014-02-06 09:55:58 +0100331 compatible = "allwinner,sun4i-a10-mod0-clk";
Emilio López1c92b952013-12-23 00:32:43 -0300332 reg = <0x01c20080 0x4>;
333 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
334 clock-output-names = "nand";
335 };
336
337 ms_clk: clk@01c20084 {
338 #clock-cells = <0>;
Maxime Ripardbf6534a2014-02-06 09:55:58 +0100339 compatible = "allwinner,sun4i-a10-mod0-clk";
Emilio López1c92b952013-12-23 00:32:43 -0300340 reg = <0x01c20084 0x4>;
341 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
342 clock-output-names = "ms";
343 };
344
345 mmc0_clk: clk@01c20088 {
Maxime Ripardd8c3a392014-07-11 19:39:06 +0200346 #clock-cells = <1>;
347 compatible = "allwinner,sun4i-a10-mmc-clk";
Emilio López1c92b952013-12-23 00:32:43 -0300348 reg = <0x01c20088 0x4>;
349 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
Maxime Ripardd8c3a392014-07-11 19:39:06 +0200350 clock-output-names = "mmc0",
351 "mmc0_output",
352 "mmc0_sample";
Emilio López1c92b952013-12-23 00:32:43 -0300353 };
354
355 mmc1_clk: clk@01c2008c {
Maxime Ripardd8c3a392014-07-11 19:39:06 +0200356 #clock-cells = <1>;
357 compatible = "allwinner,sun4i-a10-mmc-clk";
Emilio López1c92b952013-12-23 00:32:43 -0300358 reg = <0x01c2008c 0x4>;
359 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
Maxime Ripardd8c3a392014-07-11 19:39:06 +0200360 clock-output-names = "mmc1",
361 "mmc1_output",
362 "mmc1_sample";
Emilio López1c92b952013-12-23 00:32:43 -0300363 };
364
365 mmc2_clk: clk@01c20090 {
Maxime Ripardd8c3a392014-07-11 19:39:06 +0200366 #clock-cells = <1>;
367 compatible = "allwinner,sun4i-a10-mmc-clk";
Emilio López1c92b952013-12-23 00:32:43 -0300368 reg = <0x01c20090 0x4>;
369 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
Maxime Ripardd8c3a392014-07-11 19:39:06 +0200370 clock-output-names = "mmc2",
371 "mmc2_output",
372 "mmc2_sample";
Emilio López1c92b952013-12-23 00:32:43 -0300373 };
374
375 mmc3_clk: clk@01c20094 {
Maxime Ripardd8c3a392014-07-11 19:39:06 +0200376 #clock-cells = <1>;
377 compatible = "allwinner,sun4i-a10-mmc-clk";
Emilio López1c92b952013-12-23 00:32:43 -0300378 reg = <0x01c20094 0x4>;
379 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
Maxime Ripardd8c3a392014-07-11 19:39:06 +0200380 clock-output-names = "mmc3",
381 "mmc3_output",
382 "mmc3_sample";
Emilio López1c92b952013-12-23 00:32:43 -0300383 };
384
385 ts_clk: clk@01c20098 {
386 #clock-cells = <0>;
Maxime Ripardbf6534a2014-02-06 09:55:58 +0100387 compatible = "allwinner,sun4i-a10-mod0-clk";
Emilio López1c92b952013-12-23 00:32:43 -0300388 reg = <0x01c20098 0x4>;
389 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
390 clock-output-names = "ts";
391 };
392
393 ss_clk: clk@01c2009c {
394 #clock-cells = <0>;
Maxime Ripardbf6534a2014-02-06 09:55:58 +0100395 compatible = "allwinner,sun4i-a10-mod0-clk";
Emilio López1c92b952013-12-23 00:32:43 -0300396 reg = <0x01c2009c 0x4>;
397 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
398 clock-output-names = "ss";
399 };
400
401 spi0_clk: clk@01c200a0 {
402 #clock-cells = <0>;
Maxime Ripardbf6534a2014-02-06 09:55:58 +0100403 compatible = "allwinner,sun4i-a10-mod0-clk";
Emilio López1c92b952013-12-23 00:32:43 -0300404 reg = <0x01c200a0 0x4>;
405 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
406 clock-output-names = "spi0";
407 };
408
409 spi1_clk: clk@01c200a4 {
410 #clock-cells = <0>;
Maxime Ripardbf6534a2014-02-06 09:55:58 +0100411 compatible = "allwinner,sun4i-a10-mod0-clk";
Emilio López1c92b952013-12-23 00:32:43 -0300412 reg = <0x01c200a4 0x4>;
413 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
414 clock-output-names = "spi1";
415 };
416
417 spi2_clk: clk@01c200a8 {
418 #clock-cells = <0>;
Maxime Ripardbf6534a2014-02-06 09:55:58 +0100419 compatible = "allwinner,sun4i-a10-mod0-clk";
Emilio López1c92b952013-12-23 00:32:43 -0300420 reg = <0x01c200a8 0x4>;
421 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
422 clock-output-names = "spi2";
423 };
424
425 pata_clk: clk@01c200ac {
426 #clock-cells = <0>;
Maxime Ripardbf6534a2014-02-06 09:55:58 +0100427 compatible = "allwinner,sun4i-a10-mod0-clk";
Emilio López1c92b952013-12-23 00:32:43 -0300428 reg = <0x01c200ac 0x4>;
429 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
430 clock-output-names = "pata";
431 };
432
433 ir0_clk: clk@01c200b0 {
434 #clock-cells = <0>;
Maxime Ripardbf6534a2014-02-06 09:55:58 +0100435 compatible = "allwinner,sun4i-a10-mod0-clk";
Emilio López1c92b952013-12-23 00:32:43 -0300436 reg = <0x01c200b0 0x4>;
437 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
438 clock-output-names = "ir0";
439 };
440
441 ir1_clk: clk@01c200b4 {
442 #clock-cells = <0>;
Maxime Ripardbf6534a2014-02-06 09:55:58 +0100443 compatible = "allwinner,sun4i-a10-mod0-clk";
Emilio López1c92b952013-12-23 00:32:43 -0300444 reg = <0x01c200b4 0x4>;
445 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
446 clock-output-names = "ir1";
447 };
448
Roman Byshko434e41b2014-02-07 16:21:53 +0100449 usb_clk: clk@01c200cc {
450 #clock-cells = <1>;
451 #reset-cells = <1>;
452 compatible = "allwinner,sun4i-a10-usb-clk";
453 reg = <0x01c200cc 0x4>;
454 clocks = <&pll6 1>;
455 clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
456 };
457
Emilio López1c92b952013-12-23 00:32:43 -0300458 spi3_clk: clk@01c200d4 {
459 #clock-cells = <0>;
Maxime Ripardbf6534a2014-02-06 09:55:58 +0100460 compatible = "allwinner,sun4i-a10-mod0-clk";
Emilio López1c92b952013-12-23 00:32:43 -0300461 reg = <0x01c200d4 0x4>;
462 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
463 clock-output-names = "spi3";
464 };
Emilio López118c07a2013-12-23 00:32:44 -0300465
466 mbus_clk: clk@01c2015c {
467 #clock-cells = <0>;
Maxime Ripard7868c5e2014-07-16 23:45:48 +0200468 compatible = "allwinner,sun5i-a13-mbus-clk";
Emilio López118c07a2013-12-23 00:32:44 -0300469 reg = <0x01c2015c 0x4>;
470 clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
471 clock-output-names = "mbus";
472 };
Chen-Yu Tsai0aff0372014-01-01 10:30:48 +0800473
474 /*
Chen-Yu Tsaidaed5a82014-02-10 18:35:48 +0800475 * The following two are dummy clocks, placeholders used in the gmac_tx
476 * clock. The gmac driver will choose one parent depending on the PHY
477 * interface mode, using clk_set_rate auto-reparenting.
478 * The actual TX clock rate is not controlled by the gmac_tx clock.
479 */
480 mii_phy_tx_clk: clk@2 {
481 #clock-cells = <0>;
482 compatible = "fixed-clock";
483 clock-frequency = <25000000>;
484 clock-output-names = "mii_phy_tx";
485 };
486
487 gmac_int_tx_clk: clk@3 {
488 #clock-cells = <0>;
489 compatible = "fixed-clock";
490 clock-frequency = <125000000>;
491 clock-output-names = "gmac_int_tx";
492 };
493
494 gmac_tx_clk: clk@01c20164 {
495 #clock-cells = <0>;
496 compatible = "allwinner,sun7i-a20-gmac-clk";
497 reg = <0x01c20164 0x4>;
498 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
499 clock-output-names = "gmac_tx";
500 };
501
502 /*
Chen-Yu Tsai0aff0372014-01-01 10:30:48 +0800503 * Dummy clock used by output clocks
504 */
505 osc24M_32k: clk@1 {
506 #clock-cells = <0>;
507 compatible = "fixed-factor-clock";
508 clock-div = <750>;
509 clock-mult = <1>;
510 clocks = <&osc24M>;
511 clock-output-names = "osc24M_32k";
512 };
513
514 clk_out_a: clk@01c201f0 {
515 #clock-cells = <0>;
516 compatible = "allwinner,sun7i-a20-out-clk";
517 reg = <0x01c201f0 0x4>;
518 clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
519 clock-output-names = "clk_out_a";
520 };
521
522 clk_out_b: clk@01c201f4 {
523 #clock-cells = <0>;
524 compatible = "allwinner,sun7i-a20-out-clk";
525 reg = <0x01c201f4 0x4>;
526 clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
527 clock-output-names = "clk_out_b";
528 };
Maxime Ripard4790ecf2013-07-17 10:07:10 +0200529 };
530
Maxime Ripardccb4ada2015-03-26 15:53:44 +0100531 /*
532 * Note we use the address where the mmio registers start, not where
533 * the SRAM blocks start, this cannot be changed because that would be
534 * a devicetree ABI change.
535 */
Maxime Ripard4790ecf2013-07-17 10:07:10 +0200536 soc@01c00000 {
537 compatible = "simple-bus";
538 #address-cells = <1>;
539 #size-cells = <1>;
540 ranges;
541
Maxime Ripardccb4ada2015-03-26 15:53:44 +0100542 sram@00000000 {
543 compatible = "allwinner,sun4i-a10-sram";
544 reg = <0x00000000 0x4000>;
545 allwinner,sram-name = "A1";
546 };
547
548 sram@00004000 {
549 compatible = "allwinner,sun4i-a10-sram";
550 reg = <0x00004000 0x4000>;
551 allwinner,sram-name = "A2";
552 };
553
554 sram@00008000 {
555 compatible = "allwinner,sun4i-a10-sram";
556 reg = <0x00008000 0x4000>;
557 allwinner,sram-name = "A3-A4";
558 };
559
560 sram@00010000 {
561 compatible = "allwinner,sun4i-a10-sram";
562 reg = <0x00010000 0x1000>;
563 allwinner,sram-name = "D";
564 };
565
566 sram-controller@01c00000 {
567 compatible = "allwinner,sun4i-a10-sram-controller";
568 reg = <0x01c00000 0x30>;
569 };
570
Carlo Caione8ff973a2014-03-19 20:21:18 +0100571 nmi_intc: interrupt-controller@01c00030 {
572 compatible = "allwinner,sun7i-a20-sc-nmi";
573 interrupt-controller;
574 #interrupt-cells = <2>;
575 reg = <0x01c00030 0x0c>;
Maxime Ripard19882b82014-12-16 22:59:58 +0100576 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
Carlo Caione8ff973a2014-03-19 20:21:18 +0100577 };
578
Emilio López316e0b02014-08-04 17:09:59 -0300579 dma: dma-controller@01c02000 {
580 compatible = "allwinner,sun4i-a10-dma";
581 reg = <0x01c02000 0x1000>;
Maxime Ripard19882b82014-12-16 22:59:58 +0100582 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
Emilio López316e0b02014-08-04 17:09:59 -0300583 clocks = <&ahb_gates 6>;
584 #dma-cells = <2>;
585 };
586
Maxime Ripard36ab3e72014-02-22 22:35:54 +0100587 spi0: spi@01c05000 {
588 compatible = "allwinner,sun4i-a10-spi";
589 reg = <0x01c05000 0x1000>;
Maxime Ripard19882b82014-12-16 22:59:58 +0100590 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
Maxime Ripard36ab3e72014-02-22 22:35:54 +0100591 clocks = <&ahb_gates 20>, <&spi0_clk>;
592 clock-names = "ahb", "mod";
Maxime Ripard1f9f6a72014-12-16 22:59:56 +0100593 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
594 <&dma SUN4I_DMA_DEDICATED 26>;
Emilio Lópezffec7212014-08-04 17:10:02 -0300595 dma-names = "rx", "tx";
Maxime Ripard36ab3e72014-02-22 22:35:54 +0100596 status = "disabled";
597 #address-cells = <1>;
598 #size-cells = <0>;
599 };
600
601 spi1: spi@01c06000 {
602 compatible = "allwinner,sun4i-a10-spi";
603 reg = <0x01c06000 0x1000>;
Maxime Ripard19882b82014-12-16 22:59:58 +0100604 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
Maxime Ripard36ab3e72014-02-22 22:35:54 +0100605 clocks = <&ahb_gates 21>, <&spi1_clk>;
606 clock-names = "ahb", "mod";
Maxime Ripard1f9f6a72014-12-16 22:59:56 +0100607 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
608 <&dma SUN4I_DMA_DEDICATED 8>;
Emilio Lópezffec7212014-08-04 17:10:02 -0300609 dma-names = "rx", "tx";
Maxime Ripard36ab3e72014-02-22 22:35:54 +0100610 status = "disabled";
611 #address-cells = <1>;
612 #size-cells = <0>;
613 };
614
Maxime Ripard2e804d02013-09-11 11:10:06 +0200615 emac: ethernet@01c0b000 {
Maxime Ripard1c70e092014-02-02 14:49:13 +0100616 compatible = "allwinner,sun4i-a10-emac";
Maxime Ripard2e804d02013-09-11 11:10:06 +0200617 reg = <0x01c0b000 0x1000>;
Maxime Ripard19882b82014-12-16 22:59:58 +0100618 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
Maxime Ripard2e804d02013-09-11 11:10:06 +0200619 clocks = <&ahb_gates 17>;
620 status = "disabled";
621 };
622
Aleksei Mamlin92395f52015-01-19 22:35:22 +0300623 mdio: mdio@01c0b080 {
Maxime Ripard1c70e092014-02-02 14:49:13 +0100624 compatible = "allwinner,sun4i-a10-mdio";
Maxime Ripard2e804d02013-09-11 11:10:06 +0200625 reg = <0x01c0b080 0x14>;
626 status = "disabled";
627 #address-cells = <1>;
628 #size-cells = <0>;
629 };
630
Hans de Goededd29ce52014-05-02 17:57:26 +0200631 mmc0: mmc@01c0f000 {
632 compatible = "allwinner,sun5i-a13-mmc";
633 reg = <0x01c0f000 0x1000>;
Maxime Ripardd8c3a392014-07-11 19:39:06 +0200634 clocks = <&ahb_gates 8>,
635 <&mmc0_clk 0>,
636 <&mmc0_clk 1>,
637 <&mmc0_clk 2>;
638 clock-names = "ahb",
639 "mmc",
640 "output",
641 "sample";
Maxime Ripard19882b82014-12-16 22:59:58 +0100642 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
Hans de Goededd29ce52014-05-02 17:57:26 +0200643 status = "disabled";
Hans de Goede4c1bb9c2015-03-10 16:27:09 +0100644 #address-cells = <1>;
645 #size-cells = <0>;
Hans de Goededd29ce52014-05-02 17:57:26 +0200646 };
647
648 mmc1: mmc@01c10000 {
649 compatible = "allwinner,sun5i-a13-mmc";
650 reg = <0x01c10000 0x1000>;
Maxime Ripardd8c3a392014-07-11 19:39:06 +0200651 clocks = <&ahb_gates 9>,
652 <&mmc1_clk 0>,
653 <&mmc1_clk 1>,
654 <&mmc1_clk 2>;
655 clock-names = "ahb",
656 "mmc",
657 "output",
658 "sample";
Maxime Ripard19882b82014-12-16 22:59:58 +0100659 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
Hans de Goededd29ce52014-05-02 17:57:26 +0200660 status = "disabled";
Hans de Goede4c1bb9c2015-03-10 16:27:09 +0100661 #address-cells = <1>;
662 #size-cells = <0>;
Hans de Goededd29ce52014-05-02 17:57:26 +0200663 };
664
665 mmc2: mmc@01c11000 {
666 compatible = "allwinner,sun5i-a13-mmc";
667 reg = <0x01c11000 0x1000>;
Maxime Ripardd8c3a392014-07-11 19:39:06 +0200668 clocks = <&ahb_gates 10>,
669 <&mmc2_clk 0>,
670 <&mmc2_clk 1>,
671 <&mmc2_clk 2>;
672 clock-names = "ahb",
673 "mmc",
674 "output",
675 "sample";
Maxime Ripard19882b82014-12-16 22:59:58 +0100676 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
Hans de Goededd29ce52014-05-02 17:57:26 +0200677 status = "disabled";
Hans de Goede4c1bb9c2015-03-10 16:27:09 +0100678 #address-cells = <1>;
679 #size-cells = <0>;
Hans de Goededd29ce52014-05-02 17:57:26 +0200680 };
681
682 mmc3: mmc@01c12000 {
683 compatible = "allwinner,sun5i-a13-mmc";
684 reg = <0x01c12000 0x1000>;
Maxime Ripardd8c3a392014-07-11 19:39:06 +0200685 clocks = <&ahb_gates 11>,
686 <&mmc3_clk 0>,
687 <&mmc3_clk 1>,
688 <&mmc3_clk 2>;
689 clock-names = "ahb",
690 "mmc",
691 "output",
692 "sample";
Maxime Ripard19882b82014-12-16 22:59:58 +0100693 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
Hans de Goededd29ce52014-05-02 17:57:26 +0200694 status = "disabled";
Hans de Goede4c1bb9c2015-03-10 16:27:09 +0100695 #address-cells = <1>;
696 #size-cells = <0>;
Hans de Goededd29ce52014-05-02 17:57:26 +0200697 };
698
Roman Byshko9debd0a2014-03-01 20:26:25 +0100699 usbphy: phy@01c13400 {
700 #phy-cells = <1>;
701 compatible = "allwinner,sun7i-a20-usb-phy";
702 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
703 reg-names = "phy_ctrl", "pmu1", "pmu2";
704 clocks = <&usb_clk 8>;
705 clock-names = "usb_phy";
Roman Byshko134c60a2014-11-10 19:55:08 +0100706 resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
707 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
Roman Byshko9debd0a2014-03-01 20:26:25 +0100708 status = "disabled";
709 };
710
711 ehci0: usb@01c14000 {
712 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
713 reg = <0x01c14000 0x100>;
Maxime Ripard19882b82014-12-16 22:59:58 +0100714 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
Roman Byshko9debd0a2014-03-01 20:26:25 +0100715 clocks = <&ahb_gates 1>;
716 phys = <&usbphy 1>;
717 phy-names = "usb";
718 status = "disabled";
719 };
720
721 ohci0: usb@01c14400 {
722 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
723 reg = <0x01c14400 0x100>;
Maxime Ripard19882b82014-12-16 22:59:58 +0100724 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
Roman Byshko9debd0a2014-03-01 20:26:25 +0100725 clocks = <&usb_clk 6>, <&ahb_gates 2>;
726 phys = <&usbphy 1>;
727 phy-names = "usb";
728 status = "disabled";
729 };
730
Maxime Ripard36ab3e72014-02-22 22:35:54 +0100731 spi2: spi@01c17000 {
732 compatible = "allwinner,sun4i-a10-spi";
733 reg = <0x01c17000 0x1000>;
Maxime Ripard19882b82014-12-16 22:59:58 +0100734 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
Maxime Ripard36ab3e72014-02-22 22:35:54 +0100735 clocks = <&ahb_gates 22>, <&spi2_clk>;
736 clock-names = "ahb", "mod";
Maxime Ripard1f9f6a72014-12-16 22:59:56 +0100737 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
738 <&dma SUN4I_DMA_DEDICATED 28>;
Emilio Lópezffec7212014-08-04 17:10:02 -0300739 dma-names = "rx", "tx";
Maxime Ripard36ab3e72014-02-22 22:35:54 +0100740 status = "disabled";
741 #address-cells = <1>;
742 #size-cells = <0>;
743 };
744
Hans de Goede902febf2014-03-01 20:26:22 +0100745 ahci: sata@01c18000 {
746 compatible = "allwinner,sun4i-a10-ahci";
747 reg = <0x01c18000 0x1000>;
Maxime Ripard19882b82014-12-16 22:59:58 +0100748 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
Hans de Goede902febf2014-03-01 20:26:22 +0100749 clocks = <&pll6 0>, <&ahb_gates 25>;
750 status = "disabled";
751 };
752
Roman Byshko9debd0a2014-03-01 20:26:25 +0100753 ehci1: usb@01c1c000 {
754 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
755 reg = <0x01c1c000 0x100>;
Maxime Ripard19882b82014-12-16 22:59:58 +0100756 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
Roman Byshko9debd0a2014-03-01 20:26:25 +0100757 clocks = <&ahb_gates 3>;
758 phys = <&usbphy 2>;
759 phy-names = "usb";
760 status = "disabled";
761 };
762
763 ohci1: usb@01c1c400 {
764 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
765 reg = <0x01c1c400 0x100>;
Maxime Ripard19882b82014-12-16 22:59:58 +0100766 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
Roman Byshko9debd0a2014-03-01 20:26:25 +0100767 clocks = <&usb_clk 7>, <&ahb_gates 4>;
768 phys = <&usbphy 2>;
769 phy-names = "usb";
770 status = "disabled";
771 };
772
Maxime Ripard36ab3e72014-02-22 22:35:54 +0100773 spi3: spi@01c1f000 {
774 compatible = "allwinner,sun4i-a10-spi";
775 reg = <0x01c1f000 0x1000>;
Maxime Ripard19882b82014-12-16 22:59:58 +0100776 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
Maxime Ripard36ab3e72014-02-22 22:35:54 +0100777 clocks = <&ahb_gates 23>, <&spi3_clk>;
778 clock-names = "ahb", "mod";
Maxime Ripard1f9f6a72014-12-16 22:59:56 +0100779 dmas = <&dma SUN4I_DMA_DEDICATED 31>,
780 <&dma SUN4I_DMA_DEDICATED 30>;
Emilio Lópezffec7212014-08-04 17:10:02 -0300781 dma-names = "rx", "tx";
Maxime Ripard36ab3e72014-02-22 22:35:54 +0100782 status = "disabled";
783 #address-cells = <1>;
784 #size-cells = <0>;
785 };
786
Maxime Ripard17eac032013-07-24 23:46:11 +0200787 pio: pinctrl@01c20800 {
788 compatible = "allwinner,sun7i-a20-pinctrl";
789 reg = <0x01c20800 0x400>;
Maxime Ripard19882b82014-12-16 22:59:58 +0100790 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
Maxime Ripardde7dc932013-07-25 21:12:52 +0200791 clocks = <&apb0_gates 5>;
Maxime Ripard17eac032013-07-24 23:46:11 +0200792 gpio-controller;
793 interrupt-controller;
Chen-Yu Tsai7d4ff962014-06-30 23:57:51 +0200794 #interrupt-cells = <2>;
Maxime Ripard17eac032013-07-24 23:46:11 +0200795 #size-cells = <0>;
796 #gpio-cells = <3>;
Maxime Ripard9f229ba2013-07-25 00:09:47 +0200797
Alexandre Bellonifd7898a2014-04-28 18:17:12 +0200798 pwm0_pins_a: pwm0@0 {
799 allwinner,pins = "PB2";
800 allwinner,function = "pwm";
Maxime Ripard092a0c32014-12-16 22:59:57 +0100801 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
802 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
Alexandre Bellonifd7898a2014-04-28 18:17:12 +0200803 };
804
805 pwm1_pins_a: pwm1@0 {
806 allwinner,pins = "PI3";
807 allwinner,function = "pwm";
Maxime Ripard092a0c32014-12-16 22:59:57 +0100808 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
809 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
Alexandre Bellonifd7898a2014-04-28 18:17:12 +0200810 };
811
Maxime Ripard9f229ba2013-07-25 00:09:47 +0200812 uart0_pins_a: uart0@0 {
813 allwinner,pins = "PB22", "PB23";
814 allwinner,function = "uart0";
Maxime Ripard092a0c32014-12-16 22:59:57 +0100815 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
816 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
Maxime Ripard9f229ba2013-07-25 00:09:47 +0200817 };
818
Chen-Yu Tsai4261ec42014-01-14 22:49:50 +0800819 uart2_pins_a: uart2@0 {
820 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
821 allwinner,function = "uart2";
Maxime Ripard092a0c32014-12-16 22:59:57 +0100822 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
823 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
Chen-Yu Tsai4261ec42014-01-14 22:49:50 +0800824 };
825
Wills Wang7b5bace2014-08-19 15:33:00 +0800826 uart3_pins_a: uart3@0 {
827 allwinner,pins = "PG6", "PG7", "PG8", "PG9";
828 allwinner,function = "uart3";
Maxime Ripard092a0c32014-12-16 22:59:57 +0100829 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
830 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
Wills Wang7b5bace2014-08-19 15:33:00 +0800831 };
832
Hans de Goede0510e4b2014-10-01 09:26:05 +0200833 uart3_pins_b: uart3@1 {
834 allwinner,pins = "PH0", "PH1";
835 allwinner,function = "uart3";
Maxime Ripard092a0c32014-12-16 22:59:57 +0100836 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
837 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
Hans de Goede0510e4b2014-10-01 09:26:05 +0200838 };
839
Wills Wang7b5bace2014-08-19 15:33:00 +0800840 uart4_pins_a: uart4@0 {
841 allwinner,pins = "PG10", "PG11";
842 allwinner,function = "uart4";
Maxime Ripard092a0c32014-12-16 22:59:57 +0100843 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
844 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
Wills Wang7b5bace2014-08-19 15:33:00 +0800845 };
846
847 uart5_pins_a: uart5@0 {
848 allwinner,pins = "PI10", "PI11";
849 allwinner,function = "uart5";
Maxime Ripard092a0c32014-12-16 22:59:57 +0100850 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
851 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
Wills Wang7b5bace2014-08-19 15:33:00 +0800852 };
853
Maxime Ripard9f229ba2013-07-25 00:09:47 +0200854 uart6_pins_a: uart6@0 {
855 allwinner,pins = "PI12", "PI13";
856 allwinner,function = "uart6";
Maxime Ripard092a0c32014-12-16 22:59:57 +0100857 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
858 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
Maxime Ripard9f229ba2013-07-25 00:09:47 +0200859 };
860
861 uart7_pins_a: uart7@0 {
862 allwinner,pins = "PI20", "PI21";
863 allwinner,function = "uart7";
Maxime Ripard092a0c32014-12-16 22:59:57 +0100864 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
865 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
Maxime Ripard9f229ba2013-07-25 00:09:47 +0200866 };
Maxime Ripard756084c2013-09-11 11:10:07 +0200867
Maxime Riparde5496a32013-08-31 23:08:49 +0200868 i2c0_pins_a: i2c0@0 {
869 allwinner,pins = "PB0", "PB1";
870 allwinner,function = "i2c0";
Maxime Ripard092a0c32014-12-16 22:59:57 +0100871 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
872 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
Maxime Riparde5496a32013-08-31 23:08:49 +0200873 };
874
875 i2c1_pins_a: i2c1@0 {
876 allwinner,pins = "PB18", "PB19";
877 allwinner,function = "i2c1";
Maxime Ripard092a0c32014-12-16 22:59:57 +0100878 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
879 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
Maxime Riparde5496a32013-08-31 23:08:49 +0200880 };
881
882 i2c2_pins_a: i2c2@0 {
883 allwinner,pins = "PB20", "PB21";
884 allwinner,function = "i2c2";
Maxime Ripard092a0c32014-12-16 22:59:57 +0100885 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
886 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
Maxime Riparde5496a32013-08-31 23:08:49 +0200887 };
888
Wills Wang7b5bace2014-08-19 15:33:00 +0800889 i2c3_pins_a: i2c3@0 {
890 allwinner,pins = "PI0", "PI1";
891 allwinner,function = "i2c3";
Maxime Ripard092a0c32014-12-16 22:59:57 +0100892 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
893 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
Wills Wang7b5bace2014-08-19 15:33:00 +0800894 };
895
Maxime Ripard756084c2013-09-11 11:10:07 +0200896 emac_pins_a: emac0@0 {
897 allwinner,pins = "PA0", "PA1", "PA2",
898 "PA3", "PA4", "PA5", "PA6",
899 "PA7", "PA8", "PA9", "PA10",
900 "PA11", "PA12", "PA13", "PA14",
901 "PA15", "PA16";
902 allwinner,function = "emac";
Maxime Ripard092a0c32014-12-16 22:59:57 +0100903 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
904 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
Maxime Ripard756084c2013-09-11 11:10:07 +0200905 };
Chen-Yu Tsaif2e07592014-01-01 10:30:50 +0800906
907 clk_out_a_pins_a: clk_out_a@0 {
908 allwinner,pins = "PI12";
909 allwinner,function = "clk_out_a";
Maxime Ripard092a0c32014-12-16 22:59:57 +0100910 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
911 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
Chen-Yu Tsaif2e07592014-01-01 10:30:50 +0800912 };
913
914 clk_out_b_pins_a: clk_out_b@0 {
915 allwinner,pins = "PI13";
916 allwinner,function = "clk_out_b";
Maxime Ripard092a0c32014-12-16 22:59:57 +0100917 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
918 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
Chen-Yu Tsaif2e07592014-01-01 10:30:50 +0800919 };
Chen-Yu Tsai129ccbc2014-02-10 18:35:50 +0800920
921 gmac_pins_mii_a: gmac_mii@0 {
922 allwinner,pins = "PA0", "PA1", "PA2",
923 "PA3", "PA4", "PA5", "PA6",
924 "PA7", "PA8", "PA9", "PA10",
925 "PA11", "PA12", "PA13", "PA14",
926 "PA15", "PA16";
927 allwinner,function = "gmac";
Maxime Ripard092a0c32014-12-16 22:59:57 +0100928 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
929 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
Chen-Yu Tsai129ccbc2014-02-10 18:35:50 +0800930 };
931
932 gmac_pins_rgmii_a: gmac_rgmii@0 {
933 allwinner,pins = "PA0", "PA1", "PA2",
934 "PA3", "PA4", "PA5", "PA6",
935 "PA7", "PA8", "PA10",
936 "PA11", "PA12", "PA13",
937 "PA15", "PA16";
938 allwinner,function = "gmac";
939 /*
940 * data lines in RGMII mode use DDR mode
941 * and need a higher signal drive strength
942 */
Maxime Ripard092a0c32014-12-16 22:59:57 +0100943 allwinner,drive = <SUN4I_PINCTRL_40_MA>;
944 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
Chen-Yu Tsai129ccbc2014-02-10 18:35:50 +0800945 };
Maxime Ripard412f2c62014-02-22 22:35:58 +0100946
Hans de Goede2dad53b2014-10-01 09:26:04 +0200947 spi0_pins_a: spi0@0 {
948 allwinner,pins = "PI10", "PI11", "PI12", "PI13", "PI14";
949 allwinner,function = "spi0";
Maxime Ripard092a0c32014-12-16 22:59:57 +0100950 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
951 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
Hans de Goede2dad53b2014-10-01 09:26:04 +0200952 };
953
Maxime Ripard412f2c62014-02-22 22:35:58 +0100954 spi1_pins_a: spi1@0 {
955 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
956 allwinner,function = "spi1";
Maxime Ripard092a0c32014-12-16 22:59:57 +0100957 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
958 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
Maxime Ripard412f2c62014-02-22 22:35:58 +0100959 };
960
961 spi2_pins_a: spi2@0 {
962 allwinner,pins = "PC19", "PC20", "PC21", "PC22";
963 allwinner,function = "spi2";
Maxime Ripard092a0c32014-12-16 22:59:57 +0100964 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
965 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
Maxime Ripard412f2c62014-02-22 22:35:58 +0100966 };
Hans de Goede11fbedf2014-05-02 17:57:27 +0200967
Wills Wang7b5bace2014-08-19 15:33:00 +0800968 spi2_pins_b: spi2@1 {
969 allwinner,pins = "PB14", "PB15", "PB16", "PB17";
970 allwinner,function = "spi2";
Maxime Ripard092a0c32014-12-16 22:59:57 +0100971 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
972 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
Wills Wang7b5bace2014-08-19 15:33:00 +0800973 };
974
Hans de Goede11fbedf2014-05-02 17:57:27 +0200975 mmc0_pins_a: mmc0@0 {
976 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
977 allwinner,function = "mmc0";
Maxime Ripard092a0c32014-12-16 22:59:57 +0100978 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
979 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
Hans de Goede11fbedf2014-05-02 17:57:27 +0200980 };
981
982 mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
983 allwinner,pins = "PH1";
984 allwinner,function = "gpio_in";
Maxime Ripard092a0c32014-12-16 22:59:57 +0100985 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
986 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
Hans de Goede11fbedf2014-05-02 17:57:27 +0200987 };
988
Hans de Goede8fa82322014-10-01 16:25:36 +0200989 mmc2_pins_a: mmc2@0 {
990 allwinner,pins = "PC6","PC7","PC8","PC9","PC10","PC11";
991 allwinner,function = "mmc2";
Maxime Ripard092a0c32014-12-16 22:59:57 +0100992 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
993 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
Hans de Goede8fa82322014-10-01 16:25:36 +0200994 };
995
Hans de Goede11fbedf2014-05-02 17:57:27 +0200996 mmc3_pins_a: mmc3@0 {
997 allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9";
998 allwinner,function = "mmc3";
Maxime Ripard092a0c32014-12-16 22:59:57 +0100999 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
1000 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
Hans de Goede11fbedf2014-05-02 17:57:27 +02001001 };
Alexander Bersenev0fc2b7a2014-06-09 00:08:11 +06001002
Marcus Cooper469a22e2015-05-02 13:36:20 +02001003 ir0_rx_pins_a: ir0@0 {
1004 allwinner,pins = "PB4";
Alexander Bersenev0fc2b7a2014-06-09 00:08:11 +06001005 allwinner,function = "ir0";
Maxime Ripard092a0c32014-12-16 22:59:57 +01001006 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1007 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
Alexander Bersenev0fc2b7a2014-06-09 00:08:11 +06001008 };
1009
Marcus Cooper469a22e2015-05-02 13:36:20 +02001010 ir0_tx_pins_a: ir0@1 {
1011 allwinner,pins = "PB3";
1012 allwinner,function = "ir0";
1013 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1014 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1015 };
1016
1017 ir1_rx_pins_a: ir1@0 {
1018 allwinner,pins = "PB23";
1019 allwinner,function = "ir1";
1020 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1021 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1022 };
1023
1024 ir1_tx_pins_a: ir1@1 {
1025 allwinner,pins = "PB22";
Alexander Bersenev0fc2b7a2014-06-09 00:08:11 +06001026 allwinner,function = "ir1";
Maxime Ripard092a0c32014-12-16 22:59:57 +01001027 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1028 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
Alexander Bersenev0fc2b7a2014-06-09 00:08:11 +06001029 };
Vishnu Patekar1e8d1562015-01-25 19:10:09 +05301030
1031 ps20_pins_a: ps20@0 {
1032 allwinner,pins = "PI20", "PI21";
1033 allwinner,function = "ps2";
1034 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1035 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1036 };
1037
1038 ps21_pins_a: ps21@0 {
1039 allwinner,pins = "PH12", "PH13";
1040 allwinner,function = "ps2";
1041 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1042 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
Maxime Ripard4790ecf2013-07-17 10:07:10 +02001043 };
1044 };
Maxime Ripardca5d04d2014-02-07 22:29:26 +01001045
Maxime Ripard4790ecf2013-07-17 10:07:10 +02001046 timer@01c20c00 {
1047 compatible = "allwinner,sun4i-a10-timer";
1048 reg = <0x01c20c00 0x90>;
Maxime Ripard19882b82014-12-16 22:59:58 +01001049 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
1050 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
1051 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
1052 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
1053 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
1054 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
Maxime Ripard4790ecf2013-07-17 10:07:10 +02001055 clocks = <&osc24M>;
1056 };
1057
1058 wdt: watchdog@01c20c90 {
1059 compatible = "allwinner,sun4i-a10-wdt";
1060 reg = <0x01c20c90 0x10>;
1061 };
1062
Carlo Caioneb5d905c2013-10-16 20:30:26 +02001063 rtc: rtc@01c20d00 {
1064 compatible = "allwinner,sun7i-a20-rtc";
1065 reg = <0x01c20d00 0x20>;
Maxime Ripard19882b82014-12-16 22:59:58 +01001066 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
Carlo Caioneb5d905c2013-10-16 20:30:26 +02001067 };
1068
Alexandre Belloni8ec40c22014-04-28 18:17:13 +02001069 pwm: pwm@01c20e00 {
1070 compatible = "allwinner,sun7i-a20-pwm";
1071 reg = <0x01c20e00 0xc>;
1072 clocks = <&osc24M>;
1073 #pwm-cells = <3>;
1074 status = "disabled";
1075 };
1076
Alexander Bersenevc1a0ee32014-06-21 17:04:05 +06001077 ir0: ir@01c21800 {
Hans de Goede1715a382014-06-30 23:57:54 +02001078 compatible = "allwinner,sun4i-a10-ir";
Alexander Bersenevc1a0ee32014-06-21 17:04:05 +06001079 clocks = <&apb0_gates 6>, <&ir0_clk>;
1080 clock-names = "apb", "ir";
Maxime Ripard19882b82014-12-16 22:59:58 +01001081 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
Alexander Bersenevc1a0ee32014-06-21 17:04:05 +06001082 reg = <0x01c21800 0x40>;
1083 status = "disabled";
1084 };
1085
1086 ir1: ir@01c21c00 {
Hans de Goede1715a382014-06-30 23:57:54 +02001087 compatible = "allwinner,sun4i-a10-ir";
Alexander Bersenevc1a0ee32014-06-21 17:04:05 +06001088 clocks = <&apb0_gates 7>, <&ir1_clk>;
1089 clock-names = "apb", "ir";
Maxime Ripard19882b82014-12-16 22:59:58 +01001090 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
Alexander Bersenevc1a0ee32014-06-21 17:04:05 +06001091 reg = <0x01c21c00 0x40>;
1092 status = "disabled";
1093 };
1094
Hans de Goedea6a2d642014-12-23 11:13:22 +01001095 lradc: lradc@01c22800 {
1096 compatible = "allwinner,sun4i-a10-lradc-keys";
1097 reg = <0x01c22800 0x100>;
Maxime Ripard19882b82014-12-16 22:59:58 +01001098 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
Hans de Goedea6a2d642014-12-23 11:13:22 +01001099 status = "disabled";
1100 };
1101
Oliver Schinagl2bad9692013-09-03 12:33:28 +02001102 sid: eeprom@01c23800 {
1103 compatible = "allwinner,sun7i-a20-sid";
1104 reg = <0x01c23800 0x200>;
1105 };
1106
Hans de Goede00f7ed82013-12-31 17:20:52 +01001107 rtp: rtp@01c25000 {
Hans de Goede8bf1b9b2015-03-08 21:53:42 +01001108 compatible = "allwinner,sun5i-a13-ts";
Hans de Goede00f7ed82013-12-31 17:20:52 +01001109 reg = <0x01c25000 0x100>;
Maxime Ripard19882b82014-12-16 22:59:58 +01001110 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
Chen-Yu Tsai41e7afb2015-01-06 10:35:15 +08001111 #thermal-sensor-cells = <0>;
Hans de Goede00f7ed82013-12-31 17:20:52 +01001112 };
1113
Maxime Ripard4790ecf2013-07-17 10:07:10 +02001114 uart0: serial@01c28000 {
1115 compatible = "snps,dw-apb-uart";
1116 reg = <0x01c28000 0x400>;
Maxime Ripard19882b82014-12-16 22:59:58 +01001117 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
Maxime Ripard4790ecf2013-07-17 10:07:10 +02001118 reg-shift = <2>;
1119 reg-io-width = <4>;
Maxime Ripardde7dc932013-07-25 21:12:52 +02001120 clocks = <&apb1_gates 16>;
Maxime Ripard4790ecf2013-07-17 10:07:10 +02001121 status = "disabled";
1122 };
1123
1124 uart1: serial@01c28400 {
1125 compatible = "snps,dw-apb-uart";
1126 reg = <0x01c28400 0x400>;
Maxime Ripard19882b82014-12-16 22:59:58 +01001127 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
Maxime Ripard4790ecf2013-07-17 10:07:10 +02001128 reg-shift = <2>;
1129 reg-io-width = <4>;
Maxime Ripardde7dc932013-07-25 21:12:52 +02001130 clocks = <&apb1_gates 17>;
Maxime Ripard4790ecf2013-07-17 10:07:10 +02001131 status = "disabled";
1132 };
1133
1134 uart2: serial@01c28800 {
1135 compatible = "snps,dw-apb-uart";
1136 reg = <0x01c28800 0x400>;
Maxime Ripard19882b82014-12-16 22:59:58 +01001137 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
Maxime Ripard4790ecf2013-07-17 10:07:10 +02001138 reg-shift = <2>;
1139 reg-io-width = <4>;
Maxime Ripardde7dc932013-07-25 21:12:52 +02001140 clocks = <&apb1_gates 18>;
Maxime Ripard4790ecf2013-07-17 10:07:10 +02001141 status = "disabled";
1142 };
1143
1144 uart3: serial@01c28c00 {
1145 compatible = "snps,dw-apb-uart";
1146 reg = <0x01c28c00 0x400>;
Maxime Ripard19882b82014-12-16 22:59:58 +01001147 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
Maxime Ripard4790ecf2013-07-17 10:07:10 +02001148 reg-shift = <2>;
1149 reg-io-width = <4>;
Maxime Ripardde7dc932013-07-25 21:12:52 +02001150 clocks = <&apb1_gates 19>;
Maxime Ripard4790ecf2013-07-17 10:07:10 +02001151 status = "disabled";
1152 };
1153
1154 uart4: serial@01c29000 {
1155 compatible = "snps,dw-apb-uart";
1156 reg = <0x01c29000 0x400>;
Maxime Ripard19882b82014-12-16 22:59:58 +01001157 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
Maxime Ripard4790ecf2013-07-17 10:07:10 +02001158 reg-shift = <2>;
1159 reg-io-width = <4>;
Maxime Ripardde7dc932013-07-25 21:12:52 +02001160 clocks = <&apb1_gates 20>;
Maxime Ripard4790ecf2013-07-17 10:07:10 +02001161 status = "disabled";
1162 };
1163
1164 uart5: serial@01c29400 {
1165 compatible = "snps,dw-apb-uart";
1166 reg = <0x01c29400 0x400>;
Maxime Ripard19882b82014-12-16 22:59:58 +01001167 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
Maxime Ripard4790ecf2013-07-17 10:07:10 +02001168 reg-shift = <2>;
1169 reg-io-width = <4>;
Maxime Ripardde7dc932013-07-25 21:12:52 +02001170 clocks = <&apb1_gates 21>;
Maxime Ripard4790ecf2013-07-17 10:07:10 +02001171 status = "disabled";
1172 };
1173
1174 uart6: serial@01c29800 {
1175 compatible = "snps,dw-apb-uart";
1176 reg = <0x01c29800 0x400>;
Maxime Ripard19882b82014-12-16 22:59:58 +01001177 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
Maxime Ripard4790ecf2013-07-17 10:07:10 +02001178 reg-shift = <2>;
1179 reg-io-width = <4>;
Maxime Ripardde7dc932013-07-25 21:12:52 +02001180 clocks = <&apb1_gates 22>;
Maxime Ripard4790ecf2013-07-17 10:07:10 +02001181 status = "disabled";
1182 };
1183
1184 uart7: serial@01c29c00 {
1185 compatible = "snps,dw-apb-uart";
1186 reg = <0x01c29c00 0x400>;
Maxime Ripard19882b82014-12-16 22:59:58 +01001187 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
Maxime Ripard4790ecf2013-07-17 10:07:10 +02001188 reg-shift = <2>;
1189 reg-io-width = <4>;
Maxime Ripardde7dc932013-07-25 21:12:52 +02001190 clocks = <&apb1_gates 23>;
Maxime Ripard4790ecf2013-07-17 10:07:10 +02001191 status = "disabled";
1192 };
1193
Maxime Ripard428abbb2013-08-31 23:07:24 +02001194 i2c0: i2c@01c2ac00 {
Maxime Ripardd2755452014-03-31 14:54:58 +02001195 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
Maxime Ripard428abbb2013-08-31 23:07:24 +02001196 reg = <0x01c2ac00 0x400>;
Maxime Ripard19882b82014-12-16 22:59:58 +01001197 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
Maxime Ripard428abbb2013-08-31 23:07:24 +02001198 clocks = <&apb1_gates 0>;
Maxime Ripard428abbb2013-08-31 23:07:24 +02001199 status = "disabled";
Hans de Goeded1412ae2014-04-13 13:41:05 +02001200 #address-cells = <1>;
1201 #size-cells = <0>;
Maxime Ripard428abbb2013-08-31 23:07:24 +02001202 };
1203
1204 i2c1: i2c@01c2b000 {
Maxime Ripardd2755452014-03-31 14:54:58 +02001205 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
Maxime Ripard428abbb2013-08-31 23:07:24 +02001206 reg = <0x01c2b000 0x400>;
Maxime Ripard19882b82014-12-16 22:59:58 +01001207 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
Maxime Ripard428abbb2013-08-31 23:07:24 +02001208 clocks = <&apb1_gates 1>;
Maxime Ripard428abbb2013-08-31 23:07:24 +02001209 status = "disabled";
Hans de Goeded1412ae2014-04-13 13:41:05 +02001210 #address-cells = <1>;
1211 #size-cells = <0>;
Maxime Ripard428abbb2013-08-31 23:07:24 +02001212 };
1213
1214 i2c2: i2c@01c2b400 {
Maxime Ripardd2755452014-03-31 14:54:58 +02001215 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
Maxime Ripard428abbb2013-08-31 23:07:24 +02001216 reg = <0x01c2b400 0x400>;
Maxime Ripard19882b82014-12-16 22:59:58 +01001217 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
Maxime Ripard428abbb2013-08-31 23:07:24 +02001218 clocks = <&apb1_gates 2>;
Maxime Ripard428abbb2013-08-31 23:07:24 +02001219 status = "disabled";
Hans de Goeded1412ae2014-04-13 13:41:05 +02001220 #address-cells = <1>;
1221 #size-cells = <0>;
Maxime Ripard428abbb2013-08-31 23:07:24 +02001222 };
1223
1224 i2c3: i2c@01c2b800 {
Maxime Ripardd2755452014-03-31 14:54:58 +02001225 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
Maxime Ripard428abbb2013-08-31 23:07:24 +02001226 reg = <0x01c2b800 0x400>;
Maxime Ripard19882b82014-12-16 22:59:58 +01001227 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
Maxime Ripard428abbb2013-08-31 23:07:24 +02001228 clocks = <&apb1_gates 3>;
Maxime Ripard428abbb2013-08-31 23:07:24 +02001229 status = "disabled";
Hans de Goeded1412ae2014-04-13 13:41:05 +02001230 #address-cells = <1>;
1231 #size-cells = <0>;
Maxime Ripard428abbb2013-08-31 23:07:24 +02001232 };
1233
Maxime Riparda3867042014-04-18 21:13:08 +02001234 i2c4: i2c@01c2c000 {
Maxime Ripardd2755452014-03-31 14:54:58 +02001235 compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
Maxime Riparda3867042014-04-18 21:13:08 +02001236 reg = <0x01c2c000 0x400>;
Maxime Ripard19882b82014-12-16 22:59:58 +01001237 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
Maxime Ripard428abbb2013-08-31 23:07:24 +02001238 clocks = <&apb1_gates 15>;
Maxime Ripard428abbb2013-08-31 23:07:24 +02001239 status = "disabled";
Hans de Goeded1412ae2014-04-13 13:41:05 +02001240 #address-cells = <1>;
1241 #size-cells = <0>;
Maxime Ripard428abbb2013-08-31 23:07:24 +02001242 };
1243
Chen-Yu Tsaic40b8d52014-02-10 18:35:49 +08001244 gmac: ethernet@01c50000 {
1245 compatible = "allwinner,sun7i-a20-gmac";
1246 reg = <0x01c50000 0x10000>;
Maxime Ripard19882b82014-12-16 22:59:58 +01001247 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
Chen-Yu Tsaic40b8d52014-02-10 18:35:49 +08001248 interrupt-names = "macirq";
1249 clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
1250 clock-names = "stmmaceth", "allwinner_gmac_tx";
1251 snps,pbl = <2>;
1252 snps,fixed-burst;
1253 snps,force_sf_dma_mode;
1254 status = "disabled";
1255 #address-cells = <1>;
1256 #size-cells = <0>;
1257 };
1258
Maxime Ripard31f8ad32013-11-07 12:01:48 +01001259 hstimer@01c60000 {
1260 compatible = "allwinner,sun7i-a20-hstimer";
1261 reg = <0x01c60000 0x1000>;
Maxime Ripard19882b82014-12-16 22:59:58 +01001262 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
1263 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
1264 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
1265 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
Maxime Ripard31f8ad32013-11-07 12:01:48 +01001266 clocks = <&ahb_gates 28>;
1267 };
1268
Maxime Ripard4790ecf2013-07-17 10:07:10 +02001269 gic: interrupt-controller@01c81000 {
1270 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
1271 reg = <0x01c81000 0x1000>,
1272 <0x01c82000 0x1000>,
1273 <0x01c84000 0x2000>,
1274 <0x01c86000 0x2000>;
1275 interrupt-controller;
1276 #interrupt-cells = <3>;
Maxime Ripard19882b82014-12-16 22:59:58 +01001277 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
Maxime Ripard4790ecf2013-07-17 10:07:10 +02001278 };
Vishnu Patekar196654a2015-01-25 19:10:08 +05301279
1280 ps20: ps2@01c2a000 {
1281 compatible = "allwinner,sun4i-a10-ps2";
1282 reg = <0x01c2a000 0x400>;
1283 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1284 clocks = <&apb1_gates 6>;
1285 status = "disabled";
1286 };
1287
1288 ps21: ps2@01c2a400 {
1289 compatible = "allwinner,sun4i-a10-ps2";
1290 reg = <0x01c2a400 0x400>;
1291 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1292 clocks = <&apb1_gates 7>;
1293 status = "disabled";
Maxime Ripard4790ecf2013-07-17 10:07:10 +02001294 };
1295 };
1296};