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Jesse Barnes79e53942008-11-07 14:24:08 -08001/*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
Chris Wilsonf899fc62010-07-20 15:44:45 -07003 * Copyright © 2006-2008,2010 Intel Corporation
Jesse Barnes79e53942008-11-07 14:24:08 -08004 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
Chris Wilsonf899fc62010-07-20 15:44:45 -070027 * Chris Wilson <chris@chris-wilson.co.uk>
Jesse Barnes79e53942008-11-07 14:24:08 -080028 */
29#include <linux/i2c.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080030#include <linux/i2c-algo-bit.h>
Paul Gortmaker2d1a8a42011-08-30 18:16:33 -040031#include <linux/export.h>
David Howells760285e2012-10-02 18:01:07 +010032#include <drm/drmP.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080033#include "intel_drv.h"
David Howells760285e2012-10-02 18:01:07 +010034#include <drm/i915_drm.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080035#include "i915_drv.h"
36
Jani Nikula5ea6e5e2015-04-01 10:55:04 +030037struct gmbus_pin {
Daniel Kurtz2ed06c92012-03-28 02:36:15 +080038 const char *name;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020039 i915_reg_t reg;
Daniel Kurtz2ed06c92012-03-28 02:36:15 +080040};
41
Jani Nikula5ea6e5e2015-04-01 10:55:04 +030042/* Map gmbus pin pairs to names and registers. */
43static const struct gmbus_pin gmbus_pins[] = {
44 [GMBUS_PIN_SSC] = { "ssc", GPIOB },
45 [GMBUS_PIN_VGADDC] = { "vga", GPIOA },
46 [GMBUS_PIN_PANEL] = { "panel", GPIOC },
47 [GMBUS_PIN_DPC] = { "dpc", GPIOD },
48 [GMBUS_PIN_DPB] = { "dpb", GPIOE },
49 [GMBUS_PIN_DPD] = { "dpd", GPIOF },
Daniel Kurtz2ed06c92012-03-28 02:36:15 +080050};
51
Jani Nikulac1bad5b2015-05-06 15:33:43 +030052static const struct gmbus_pin gmbus_pins_bdw[] = {
53 [GMBUS_PIN_VGADDC] = { "vga", GPIOA },
54 [GMBUS_PIN_DPC] = { "dpc", GPIOD },
55 [GMBUS_PIN_DPB] = { "dpb", GPIOE },
56 [GMBUS_PIN_DPD] = { "dpd", GPIOF },
57};
58
Jani Nikula6364e672015-05-06 15:33:44 +030059static const struct gmbus_pin gmbus_pins_skl[] = {
60 [GMBUS_PIN_DPC] = { "dpc", GPIOD },
61 [GMBUS_PIN_DPB] = { "dpb", GPIOE },
62 [GMBUS_PIN_DPD] = { "dpd", GPIOF },
63};
64
Jani Nikula4c272832015-04-01 10:58:05 +030065static const struct gmbus_pin gmbus_pins_bxt[] = {
Ville Syrjäläb2e8c6c2015-11-04 23:20:00 +020066 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
67 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
68 [GMBUS_PIN_3_BXT] = { "misc", GPIOD },
Jani Nikula4c272832015-04-01 10:58:05 +030069};
70
71/* pin is expected to be valid */
72static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
73 unsigned int pin)
74{
Ander Conselvan de Oliveiracc3f90f2016-12-02 10:23:49 +020075 if (IS_GEN9_LP(dev_priv))
Jani Nikula4c272832015-04-01 10:58:05 +030076 return &gmbus_pins_bxt[pin];
Rodrigo Vivib976dc52017-01-23 10:32:37 -080077 else if (IS_GEN9_BC(dev_priv))
Jani Nikula6364e672015-05-06 15:33:44 +030078 return &gmbus_pins_skl[pin];
Jani Nikulac1bad5b2015-05-06 15:33:43 +030079 else if (IS_BROADWELL(dev_priv))
80 return &gmbus_pins_bdw[pin];
Jani Nikula4c272832015-04-01 10:58:05 +030081 else
82 return &gmbus_pins[pin];
83}
84
Jani Nikula88ac7932015-03-27 00:20:22 +020085bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
86 unsigned int pin)
87{
Jani Nikula4c272832015-04-01 10:58:05 +030088 unsigned int size;
89
Ander Conselvan de Oliveiracc3f90f2016-12-02 10:23:49 +020090 if (IS_GEN9_LP(dev_priv))
Jani Nikula4c272832015-04-01 10:58:05 +030091 size = ARRAY_SIZE(gmbus_pins_bxt);
Rodrigo Vivib976dc52017-01-23 10:32:37 -080092 else if (IS_GEN9_BC(dev_priv))
Jani Nikula6364e672015-05-06 15:33:44 +030093 size = ARRAY_SIZE(gmbus_pins_skl);
Jani Nikulac1bad5b2015-05-06 15:33:43 +030094 else if (IS_BROADWELL(dev_priv))
95 size = ARRAY_SIZE(gmbus_pins_bdw);
Jani Nikula4c272832015-04-01 10:58:05 +030096 else
97 size = ARRAY_SIZE(gmbus_pins);
98
Ville Syrjäläf0f59a02015-11-18 15:33:26 +020099 return pin < size &&
100 i915_mmio_reg_valid(get_gmbus_pin(dev_priv, pin)->reg);
Jani Nikula88ac7932015-03-27 00:20:22 +0200101}
102
Chris Wilsonf899fc62010-07-20 15:44:45 -0700103/* Intel GPIO access functions */
104
Jean Delvare1849ecb2012-01-28 11:07:09 +0100105#define I2C_RISEFALL_TIME 10
Chris Wilsonf899fc62010-07-20 15:44:45 -0700106
Chris Wilsone957d772010-09-24 12:52:03 +0100107static inline struct intel_gmbus *
108to_intel_gmbus(struct i2c_adapter *i2c)
109{
110 return container_of(i2c, struct intel_gmbus, adapter);
111}
112
Chris Wilsonf899fc62010-07-20 15:44:45 -0700113void
Tvrtko Ursulinaf6dc742016-12-01 14:16:44 +0000114intel_i2c_reset(struct drm_i915_private *dev_priv)
Shaohua Li0ba0e9e2009-04-07 11:02:28 +0800115{
Ville Syrjälä699fc402015-09-18 20:03:38 +0300116 I915_WRITE(GMBUS0, 0);
117 I915_WRITE(GMBUS4, 0);
Chris Wilsonf899fc62010-07-20 15:44:45 -0700118}
119
120static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
121{
Chris Wilsonb222f262010-09-11 21:48:25 +0100122 u32 val;
Shaohua Li0ba0e9e2009-04-07 11:02:28 +0800123
124 /* When using bit bashing for I2C, this bit needs to be set to 1 */
Joonas Lahtinen2d1fe072016-04-07 11:08:05 +0300125 if (!IS_PINEVIEW(dev_priv))
Shaohua Li0ba0e9e2009-04-07 11:02:28 +0800126 return;
Chris Wilsonb222f262010-09-11 21:48:25 +0100127
128 val = I915_READ(DSPCLK_GATE_D);
Shaohua Li0ba0e9e2009-04-07 11:02:28 +0800129 if (enable)
Chris Wilsonb222f262010-09-11 21:48:25 +0100130 val |= DPCUNIT_CLOCK_GATE_DISABLE;
Shaohua Li0ba0e9e2009-04-07 11:02:28 +0800131 else
Chris Wilsonb222f262010-09-11 21:48:25 +0100132 val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
133 I915_WRITE(DSPCLK_GATE_D, val);
Shaohua Li0ba0e9e2009-04-07 11:02:28 +0800134}
135
Daniel Vetter36c785f2012-02-14 22:37:22 +0100136static u32 get_reserved(struct intel_gmbus *bus)
Chris Wilsone957d772010-09-24 12:52:03 +0100137{
Daniel Vetter36c785f2012-02-14 22:37:22 +0100138 struct drm_i915_private *dev_priv = bus->dev_priv;
Chris Wilsone957d772010-09-24 12:52:03 +0100139 u32 reserved = 0;
140
141 /* On most chips, these bits must be preserved in software. */
Jani Nikula2a307c22016-11-30 17:43:04 +0200142 if (!IS_I830(dev_priv) && !IS_I845G(dev_priv))
Daniel Vetter36c785f2012-02-14 22:37:22 +0100143 reserved = I915_READ_NOTRACE(bus->gpio_reg) &
Yuanhan Liudb5e4172010-11-08 09:58:16 +0000144 (GPIO_DATA_PULLUP_DISABLE |
145 GPIO_CLOCK_PULLUP_DISABLE);
Chris Wilsone957d772010-09-24 12:52:03 +0100146
147 return reserved;
148}
149
Jesse Barnes79e53942008-11-07 14:24:08 -0800150static int get_clock(void *data)
151{
Daniel Vetter36c785f2012-02-14 22:37:22 +0100152 struct intel_gmbus *bus = data;
153 struct drm_i915_private *dev_priv = bus->dev_priv;
154 u32 reserved = get_reserved(bus);
155 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
156 I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
157 return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
Jesse Barnes79e53942008-11-07 14:24:08 -0800158}
159
160static int get_data(void *data)
161{
Daniel Vetter36c785f2012-02-14 22:37:22 +0100162 struct intel_gmbus *bus = data;
163 struct drm_i915_private *dev_priv = bus->dev_priv;
164 u32 reserved = get_reserved(bus);
165 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
166 I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
167 return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
Jesse Barnes79e53942008-11-07 14:24:08 -0800168}
169
170static void set_clock(void *data, int state_high)
171{
Daniel Vetter36c785f2012-02-14 22:37:22 +0100172 struct intel_gmbus *bus = data;
173 struct drm_i915_private *dev_priv = bus->dev_priv;
174 u32 reserved = get_reserved(bus);
Chris Wilsone957d772010-09-24 12:52:03 +0100175 u32 clock_bits;
Jesse Barnes79e53942008-11-07 14:24:08 -0800176
177 if (state_high)
178 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
179 else
180 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
181 GPIO_CLOCK_VAL_MASK;
Chris Wilsonf899fc62010-07-20 15:44:45 -0700182
Daniel Vetter36c785f2012-02-14 22:37:22 +0100183 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits);
184 POSTING_READ(bus->gpio_reg);
Jesse Barnes79e53942008-11-07 14:24:08 -0800185}
186
187static void set_data(void *data, int state_high)
188{
Daniel Vetter36c785f2012-02-14 22:37:22 +0100189 struct intel_gmbus *bus = data;
190 struct drm_i915_private *dev_priv = bus->dev_priv;
191 u32 reserved = get_reserved(bus);
Chris Wilsone957d772010-09-24 12:52:03 +0100192 u32 data_bits;
Jesse Barnes79e53942008-11-07 14:24:08 -0800193
194 if (state_high)
195 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
196 else
197 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
198 GPIO_DATA_VAL_MASK;
199
Daniel Vetter36c785f2012-02-14 22:37:22 +0100200 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits);
201 POSTING_READ(bus->gpio_reg);
Jesse Barnes79e53942008-11-07 14:24:08 -0800202}
203
Daniel Kurtz489fbc12012-03-28 02:36:13 +0800204static int
205intel_gpio_pre_xfer(struct i2c_adapter *adapter)
206{
207 struct intel_gmbus *bus = container_of(adapter,
208 struct intel_gmbus,
209 adapter);
210 struct drm_i915_private *dev_priv = bus->dev_priv;
211
Tvrtko Ursulinaf6dc742016-12-01 14:16:44 +0000212 intel_i2c_reset(dev_priv);
Daniel Kurtz489fbc12012-03-28 02:36:13 +0800213 intel_i2c_quirk_set(dev_priv, true);
214 set_data(bus, 1);
215 set_clock(bus, 1);
216 udelay(I2C_RISEFALL_TIME);
217 return 0;
218}
219
220static void
221intel_gpio_post_xfer(struct i2c_adapter *adapter)
222{
223 struct intel_gmbus *bus = container_of(adapter,
224 struct intel_gmbus,
225 adapter);
226 struct drm_i915_private *dev_priv = bus->dev_priv;
227
228 set_data(bus, 1);
229 set_clock(bus, 1);
230 intel_i2c_quirk_set(dev_priv, false);
231}
232
Daniel Kurtz2ed06c92012-03-28 02:36:15 +0800233static void
Jani Nikula5ea6e5e2015-04-01 10:55:04 +0300234intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin)
Eric Anholtf0217c42009-12-01 11:56:30 -0800235{
Daniel Vetter36c785f2012-02-14 22:37:22 +0100236 struct drm_i915_private *dev_priv = bus->dev_priv;
Daniel Vetter36c785f2012-02-14 22:37:22 +0100237 struct i2c_algo_bit_data *algo;
Eric Anholtf0217c42009-12-01 11:56:30 -0800238
Daniel Vetterc167a6f2012-02-28 00:43:09 +0100239 algo = &bus->bit_algo;
Daniel Vetter36c785f2012-02-14 22:37:22 +0100240
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200241 bus->gpio_reg = _MMIO(dev_priv->gpio_mmio_base +
242 i915_mmio_reg_offset(get_gmbus_pin(dev_priv, pin)->reg));
Daniel Vetterc167a6f2012-02-28 00:43:09 +0100243 bus->adapter.algo_data = algo;
Daniel Vetter36c785f2012-02-14 22:37:22 +0100244 algo->setsda = set_data;
245 algo->setscl = set_clock;
246 algo->getsda = get_data;
247 algo->getscl = get_clock;
Daniel Kurtz489fbc12012-03-28 02:36:13 +0800248 algo->pre_xfer = intel_gpio_pre_xfer;
249 algo->post_xfer = intel_gpio_post_xfer;
Daniel Vetter36c785f2012-02-14 22:37:22 +0100250 algo->udelay = I2C_RISEFALL_TIME;
251 algo->timeout = usecs_to_jiffies(2200);
252 algo->data = bus;
Jesse Barnes79e53942008-11-07 14:24:08 -0800253}
254
Chris Wilson4e6c2d52016-08-19 17:45:02 +0100255static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en)
Daniel Vetter61168c52012-12-01 13:53:43 +0100256{
Daniel Vetter28c70f12012-12-01 13:53:45 +0100257 DEFINE_WAIT(wait);
Chris Wilson4e6c2d52016-08-19 17:45:02 +0100258 u32 gmbus2;
259 int ret;
Jiri Kosinac12aba52013-03-19 09:56:57 +0100260
Daniel Vetter28c70f12012-12-01 13:53:45 +0100261 /* Important: The hw handles only the first bit, so set only one! Since
262 * we also need to check for NAKs besides the hw ready/idle signal, we
Chris Wilson4e6c2d52016-08-19 17:45:02 +0100263 * need to wake up periodically and check that ourselves.
264 */
265 if (!HAS_GMBUS_IRQ(dev_priv))
266 irq_en = 0;
Daniel Vetter28c70f12012-12-01 13:53:45 +0100267
Chris Wilson4e6c2d52016-08-19 17:45:02 +0100268 add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
269 I915_WRITE_FW(GMBUS4, irq_en);
Daniel Vetter28c70f12012-12-01 13:53:45 +0100270
Chris Wilson4e6c2d52016-08-19 17:45:02 +0100271 status |= GMBUS_SATOER;
272 ret = wait_for_us((gmbus2 = I915_READ_FW(GMBUS2)) & status, 2);
273 if (ret)
274 ret = wait_for((gmbus2 = I915_READ_FW(GMBUS2)) & status, 50);
Daniel Vetter28c70f12012-12-01 13:53:45 +0100275
Chris Wilson4e6c2d52016-08-19 17:45:02 +0100276 I915_WRITE_FW(GMBUS4, 0);
277 remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
Daniel Vetter61168c52012-12-01 13:53:43 +0100278
279 if (gmbus2 & GMBUS_SATOER)
280 return -ENXIO;
Chris Wilson4e6c2d52016-08-19 17:45:02 +0100281
282 return ret;
Daniel Vetter61168c52012-12-01 13:53:43 +0100283}
284
285static int
Daniel Vetter2c438c02012-12-01 13:53:46 +0100286gmbus_wait_idle(struct drm_i915_private *dev_priv)
287{
Chris Wilson4e6c2d52016-08-19 17:45:02 +0100288 DEFINE_WAIT(wait);
289 u32 irq_enable;
Daniel Vetter2c438c02012-12-01 13:53:46 +0100290 int ret;
Daniel Vetter2c438c02012-12-01 13:53:46 +0100291
Daniel Vetter2c438c02012-12-01 13:53:46 +0100292 /* Important: The hw handles only the first bit, so set only one! */
Chris Wilson4e6c2d52016-08-19 17:45:02 +0100293 irq_enable = 0;
294 if (HAS_GMBUS_IRQ(dev_priv))
295 irq_enable = GMBUS_IDLE_EN;
Daniel Vetter2c438c02012-12-01 13:53:46 +0100296
Chris Wilson4e6c2d52016-08-19 17:45:02 +0100297 add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
298 I915_WRITE_FW(GMBUS4, irq_enable);
Daniel Vetter2c438c02012-12-01 13:53:46 +0100299
Chris Wilson4e6c2d52016-08-19 17:45:02 +0100300 ret = intel_wait_for_register_fw(dev_priv,
301 GMBUS2, GMBUS_ACTIVE, 0,
302 10);
Daniel Vetter2c438c02012-12-01 13:53:46 +0100303
Chris Wilson4e6c2d52016-08-19 17:45:02 +0100304 I915_WRITE_FW(GMBUS4, 0);
305 remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
306
307 return ret;
Daniel Vetter2c438c02012-12-01 13:53:46 +0100308}
309
310static int
Dmitry Torokhov9535c472015-04-21 09:49:11 -0700311gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
312 unsigned short addr, u8 *buf, unsigned int len,
313 u32 gmbus1_index)
Daniel Kurtz924a93e2012-03-28 02:36:10 +0800314{
Chris Wilson4e6c2d52016-08-19 17:45:02 +0100315 I915_WRITE_FW(GMBUS1,
316 gmbus1_index |
317 GMBUS_CYCLE_WAIT |
318 (len << GMBUS_BYTE_COUNT_SHIFT) |
319 (addr << GMBUS_SLAVE_ADDR_SHIFT) |
320 GMBUS_SLAVE_READ | GMBUS_SW_RDY);
Daniel Kurtz79985ee2012-04-13 19:47:53 +0800321 while (len) {
Daniel Kurtz90e6b262012-03-30 19:46:41 +0800322 int ret;
Daniel Kurtz924a93e2012-03-28 02:36:10 +0800323 u32 val, loop = 0;
324
Chris Wilson4e6c2d52016-08-19 17:45:02 +0100325 ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
Daniel Kurtz90e6b262012-03-30 19:46:41 +0800326 if (ret)
Daniel Vetter61168c52012-12-01 13:53:43 +0100327 return ret;
Daniel Kurtz924a93e2012-03-28 02:36:10 +0800328
Chris Wilson4e6c2d52016-08-19 17:45:02 +0100329 val = I915_READ_FW(GMBUS3);
Daniel Kurtz924a93e2012-03-28 02:36:10 +0800330 do {
331 *buf++ = val & 0xff;
332 val >>= 8;
333 } while (--len && ++loop < 4);
Daniel Kurtz79985ee2012-04-13 19:47:53 +0800334 }
Daniel Kurtz924a93e2012-03-28 02:36:10 +0800335
336 return 0;
337}
338
339static int
Dmitry Torokhov9535c472015-04-21 09:49:11 -0700340gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
341 u32 gmbus1_index)
342{
343 u8 *buf = msg->buf;
344 unsigned int rx_size = msg->len;
345 unsigned int len;
346 int ret;
347
348 do {
349 len = min(rx_size, GMBUS_BYTE_COUNT_MAX);
350
351 ret = gmbus_xfer_read_chunk(dev_priv, msg->addr,
352 buf, len, gmbus1_index);
353 if (ret)
354 return ret;
355
356 rx_size -= len;
357 buf += len;
358 } while (rx_size != 0);
359
360 return 0;
361}
362
363static int
364gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
365 unsigned short addr, u8 *buf, unsigned int len)
Daniel Kurtz924a93e2012-03-28 02:36:10 +0800366{
Dmitry Torokhov9535c472015-04-21 09:49:11 -0700367 unsigned int chunk_size = len;
Daniel Kurtz924a93e2012-03-28 02:36:10 +0800368 u32 val, loop;
369
370 val = loop = 0;
Daniel Kurtz26883c32012-03-30 19:46:36 +0800371 while (len && loop < 4) {
372 val |= *buf++ << (8 * loop++);
373 len -= 1;
374 }
Daniel Kurtz924a93e2012-03-28 02:36:10 +0800375
Chris Wilson4e6c2d52016-08-19 17:45:02 +0100376 I915_WRITE_FW(GMBUS3, val);
377 I915_WRITE_FW(GMBUS1,
378 GMBUS_CYCLE_WAIT |
379 (chunk_size << GMBUS_BYTE_COUNT_SHIFT) |
380 (addr << GMBUS_SLAVE_ADDR_SHIFT) |
381 GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
Daniel Kurtz924a93e2012-03-28 02:36:10 +0800382 while (len) {
Daniel Kurtz90e6b262012-03-30 19:46:41 +0800383 int ret;
Daniel Kurtz90e6b262012-03-30 19:46:41 +0800384
Daniel Kurtz924a93e2012-03-28 02:36:10 +0800385 val = loop = 0;
386 do {
387 val |= *buf++ << (8 * loop);
388 } while (--len && ++loop < 4);
389
Chris Wilson4e6c2d52016-08-19 17:45:02 +0100390 I915_WRITE_FW(GMBUS3, val);
Daniel Kurtz7a39a9d2012-03-30 19:46:37 +0800391
Chris Wilson4e6c2d52016-08-19 17:45:02 +0100392 ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
Daniel Kurtz90e6b262012-03-30 19:46:41 +0800393 if (ret)
Daniel Vetter61168c52012-12-01 13:53:43 +0100394 return ret;
Daniel Kurtz924a93e2012-03-28 02:36:10 +0800395 }
Dmitry Torokhov9535c472015-04-21 09:49:11 -0700396
397 return 0;
398}
399
400static int
401gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg)
402{
403 u8 *buf = msg->buf;
404 unsigned int tx_size = msg->len;
405 unsigned int len;
406 int ret;
407
408 do {
409 len = min(tx_size, GMBUS_BYTE_COUNT_MAX);
410
411 ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len);
412 if (ret)
413 return ret;
414
415 buf += len;
416 tx_size -= len;
417 } while (tx_size != 0);
418
Daniel Kurtz924a93e2012-03-28 02:36:10 +0800419 return 0;
420}
421
Daniel Kurtz56f9eac2012-03-30 19:46:40 +0800422/*
423 * The gmbus controller can combine a 1 or 2 byte write with a read that
424 * immediately follows it by using an "INDEX" cycle.
425 */
426static bool
427gmbus_is_index_read(struct i2c_msg *msgs, int i, int num)
428{
429 return (i + 1 < num &&
430 !(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 &&
431 (msgs[i + 1].flags & I2C_M_RD));
432}
433
434static int
435gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
436{
Daniel Kurtz56f9eac2012-03-30 19:46:40 +0800437 u32 gmbus1_index = 0;
438 u32 gmbus5 = 0;
439 int ret;
440
441 if (msgs[0].len == 2)
442 gmbus5 = GMBUS_2BYTE_INDEX_EN |
443 msgs[0].buf[1] | (msgs[0].buf[0] << 8);
444 if (msgs[0].len == 1)
445 gmbus1_index = GMBUS_CYCLE_INDEX |
446 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
447
448 /* GMBUS5 holds 16-bit index */
449 if (gmbus5)
Chris Wilson4e6c2d52016-08-19 17:45:02 +0100450 I915_WRITE_FW(GMBUS5, gmbus5);
Daniel Kurtz56f9eac2012-03-30 19:46:40 +0800451
452 ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);
453
454 /* Clear GMBUS5 after each index transfer */
455 if (gmbus5)
Chris Wilson4e6c2d52016-08-19 17:45:02 +0100456 I915_WRITE_FW(GMBUS5, 0);
Daniel Kurtz56f9eac2012-03-30 19:46:40 +0800457
458 return ret;
459}
460
Daniel Kurtz924a93e2012-03-28 02:36:10 +0800461static int
Jani Nikulabffce902015-12-01 16:29:26 +0200462do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
Chris Wilsonf899fc62010-07-20 15:44:45 -0700463{
464 struct intel_gmbus *bus = container_of(adapter,
465 struct intel_gmbus,
466 adapter);
Daniel Vetterc2b91522012-02-14 22:37:19 +0100467 struct drm_i915_private *dev_priv = bus->dev_priv;
Ville Syrjälä699fc402015-09-18 20:03:38 +0300468 int i = 0, inc, try = 0;
Daniel Kurtz72d66af2012-03-30 19:46:39 +0800469 int ret = 0;
Chris Wilsonf899fc62010-07-20 15:44:45 -0700470
Jani Nikula3f5f1552015-06-02 19:21:15 +0300471retry:
Chris Wilson4e6c2d52016-08-19 17:45:02 +0100472 I915_WRITE_FW(GMBUS0, bus->reg0);
Chris Wilsonf899fc62010-07-20 15:44:45 -0700473
Jani Nikula3f5f1552015-06-02 19:21:15 +0300474 for (; i < num; i += inc) {
475 inc = 1;
Daniel Kurtz56f9eac2012-03-30 19:46:40 +0800476 if (gmbus_is_index_read(msgs, i, num)) {
477 ret = gmbus_xfer_index_read(dev_priv, &msgs[i]);
Jani Nikula3f5f1552015-06-02 19:21:15 +0300478 inc = 2; /* an index read is two msgs */
Daniel Kurtz56f9eac2012-03-30 19:46:40 +0800479 } else if (msgs[i].flags & I2C_M_RD) {
480 ret = gmbus_xfer_read(dev_priv, &msgs[i], 0);
481 } else {
Daniel Kurtz72d66af2012-03-30 19:46:39 +0800482 ret = gmbus_xfer_write(dev_priv, &msgs[i]);
Daniel Kurtz56f9eac2012-03-30 19:46:40 +0800483 }
Chris Wilsonf899fc62010-07-20 15:44:45 -0700484
Jani Nikula0aeb9042015-12-01 16:29:25 +0200485 if (!ret)
Chris Wilson4e6c2d52016-08-19 17:45:02 +0100486 ret = gmbus_wait(dev_priv,
487 GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN);
Daniel Kurtz924a93e2012-03-28 02:36:10 +0800488 if (ret == -ETIMEDOUT)
489 goto timeout;
Jani Nikula0aeb9042015-12-01 16:29:25 +0200490 else if (ret)
Daniel Kurtz924a93e2012-03-28 02:36:10 +0800491 goto clear_err;
Chris Wilsonf899fc62010-07-20 15:44:45 -0700492 }
493
Daniel Kurtz72d66af2012-03-30 19:46:39 +0800494 /* Generate a STOP condition on the bus. Note that gmbus can't generata
495 * a STOP on the very first cycle. To simplify the code we
496 * unconditionally generate the STOP condition with an additional gmbus
497 * cycle. */
Chris Wilson4e6c2d52016-08-19 17:45:02 +0100498 I915_WRITE_FW(GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
Daniel Kurtz72d66af2012-03-30 19:46:39 +0800499
Benson Leungcaae7452012-02-09 12:03:17 -0800500 /* Mark the GMBUS interface as disabled after waiting for idle.
501 * We will re-enable it at the start of the next xfer,
502 * till then let it sleep.
Chris Wilson7f58aab2011-03-30 16:20:43 +0100503 */
Daniel Vetter2c438c02012-12-01 13:53:46 +0100504 if (gmbus_wait_idle(dev_priv)) {
Daniel Kurtz56fa6d62012-04-13 19:47:54 +0800505 DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n",
Daniel Kurtze646d572012-03-30 19:46:38 +0800506 adapter->name);
Daniel Kurtz72d66af2012-03-30 19:46:39 +0800507 ret = -ETIMEDOUT;
508 }
Chris Wilson4e6c2d52016-08-19 17:45:02 +0100509 I915_WRITE_FW(GMBUS0, 0);
Daniel Kurtz72d66af2012-03-30 19:46:39 +0800510 ret = ret ?: i;
Yufeng Shen8a8ed1f2012-02-13 17:36:54 -0500511 goto out;
Chris Wilsonf899fc62010-07-20 15:44:45 -0700512
Daniel Kurtze646d572012-03-30 19:46:38 +0800513clear_err:
514 /*
515 * Wait for bus to IDLE before clearing NAK.
516 * If we clear the NAK while bus is still active, then it will stay
517 * active and the next transaction may fail.
Daniel Vetter65e81862012-05-21 20:19:48 +0200518 *
519 * If no ACK is received during the address phase of a transaction, the
520 * adapter must report -ENXIO. It is not clear what to return if no ACK
521 * is received at other times. But we have to be careful to not return
522 * spurious -ENXIO because that will prevent i2c and drm edid functions
523 * from retrying. So return -ENXIO only when gmbus properly quiescents -
524 * timing out seems to happen when there _is_ a ddc chip present, but
525 * it's slow responding and only answers on the 2nd retry.
Daniel Kurtze646d572012-03-30 19:46:38 +0800526 */
Daniel Vetter65e81862012-05-21 20:19:48 +0200527 ret = -ENXIO;
Daniel Vetter2c438c02012-12-01 13:53:46 +0100528 if (gmbus_wait_idle(dev_priv)) {
Daniel Kurtz56fa6d62012-04-13 19:47:54 +0800529 DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n",
530 adapter->name);
Daniel Vetter65e81862012-05-21 20:19:48 +0200531 ret = -ETIMEDOUT;
532 }
Daniel Kurtze646d572012-03-30 19:46:38 +0800533
534 /* Toggle the Software Clear Interrupt bit. This has the effect
535 * of resetting the GMBUS controller and so clearing the
536 * BUS_ERROR raised by the slave's NAK.
537 */
Chris Wilson4e6c2d52016-08-19 17:45:02 +0100538 I915_WRITE_FW(GMBUS1, GMBUS_SW_CLR_INT);
539 I915_WRITE_FW(GMBUS1, 0);
540 I915_WRITE_FW(GMBUS0, 0);
Daniel Kurtze646d572012-03-30 19:46:38 +0800541
Daniel Kurtz56fa6d62012-04-13 19:47:54 +0800542 DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n",
Daniel Kurtze646d572012-03-30 19:46:38 +0800543 adapter->name, msgs[i].addr,
544 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
545
Jani Nikula3f5f1552015-06-02 19:21:15 +0300546 /*
547 * Passive adapters sometimes NAK the first probe. Retry the first
548 * message once on -ENXIO for GMBUS transfers; the bit banging algorithm
549 * has retries internally. See also the retry loop in
550 * drm_do_probe_ddc_edid, which bails out on the first -ENXIO.
551 */
552 if (ret == -ENXIO && i == 0 && try++ == 0) {
553 DRM_DEBUG_KMS("GMBUS [%s] NAK on first message, retry\n",
554 adapter->name);
555 goto retry;
556 }
557
Daniel Kurtze646d572012-03-30 19:46:38 +0800558 goto out;
559
Chris Wilsonf899fc62010-07-20 15:44:45 -0700560timeout:
Ville Syrjälä70677802016-03-07 17:57:00 +0200561 DRM_DEBUG_KMS("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
562 bus->adapter.name, bus->reg0 & 0xff);
Chris Wilson4e6c2d52016-08-19 17:45:02 +0100563 I915_WRITE_FW(GMBUS0, 0);
Chris Wilson7f58aab2011-03-30 16:20:43 +0100564
Jani Nikulabffce902015-12-01 16:29:26 +0200565 /*
566 * Hardware may not support GMBUS over these pins? Try GPIO bitbanging
567 * instead. Use EAGAIN to have i2c core retry.
568 */
Jani Nikulabffce902015-12-01 16:29:26 +0200569 ret = -EAGAIN;
Daniel Kurtz489fbc12012-03-28 02:36:13 +0800570
Yufeng Shen8a8ed1f2012-02-13 17:36:54 -0500571out:
Jani Nikulabffce902015-12-01 16:29:26 +0200572 return ret;
573}
Ville Syrjäläf0ab43e2015-11-09 16:48:19 +0100574
Jani Nikulabffce902015-12-01 16:29:26 +0200575static int
576gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
577{
578 struct intel_gmbus *bus = container_of(adapter, struct intel_gmbus,
579 adapter);
580 struct drm_i915_private *dev_priv = bus->dev_priv;
581 int ret;
582
583 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
584 mutex_lock(&dev_priv->gmbus_mutex);
585
Ville Syrjälä3e4d44e2016-03-07 17:56:59 +0200586 if (bus->force_bit) {
Jani Nikulabffce902015-12-01 16:29:26 +0200587 ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
Ville Syrjälä3e4d44e2016-03-07 17:56:59 +0200588 if (ret < 0)
589 bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY;
590 } else {
Jani Nikulabffce902015-12-01 16:29:26 +0200591 ret = do_gmbus_xfer(adapter, msgs, num);
Ville Syrjälä3e4d44e2016-03-07 17:56:59 +0200592 if (ret == -EAGAIN)
593 bus->force_bit |= GMBUS_FORCE_BIT_RETRY;
594 }
Jani Nikulabffce902015-12-01 16:29:26 +0200595
596 mutex_unlock(&dev_priv->gmbus_mutex);
Ville Syrjäläf0ab43e2015-11-09 16:48:19 +0100597 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
598
Yufeng Shen8a8ed1f2012-02-13 17:36:54 -0500599 return ret;
Chris Wilsonf899fc62010-07-20 15:44:45 -0700600}
601
602static u32 gmbus_func(struct i2c_adapter *adapter)
603{
Daniel Vetterf6f808c2012-02-14 18:58:49 +0100604 return i2c_bit_algo.functionality(adapter) &
605 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
Chris Wilsonf899fc62010-07-20 15:44:45 -0700606 /* I2C_FUNC_10BIT_ADDR | */
607 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
608 I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
609}
610
611static const struct i2c_algorithm gmbus_algorithm = {
612 .master_xfer = gmbus_xfer,
613 .functionality = gmbus_func
614};
615
616/**
617 * intel_gmbus_setup - instantiate all Intel i2c GMBuses
Tvrtko Ursulin40196442016-12-01 14:16:42 +0000618 * @dev_priv: i915 device private
Chris Wilsonf899fc62010-07-20 15:44:45 -0700619 */
Tvrtko Ursulin40196442016-12-01 14:16:42 +0000620int intel_setup_gmbus(struct drm_i915_private *dev_priv)
Chris Wilsonf899fc62010-07-20 15:44:45 -0700621{
David Weinehall52a05c32016-08-22 13:32:44 +0300622 struct pci_dev *pdev = dev_priv->drm.pdev;
Jani Nikula5ea6e5e2015-04-01 10:55:04 +0300623 struct intel_gmbus *bus;
624 unsigned int pin;
625 int ret;
Chris Wilsonf899fc62010-07-20 15:44:45 -0700626
Tvrtko Ursulin6e266952016-10-13 11:02:53 +0100627 if (HAS_PCH_NOP(dev_priv))
Ben Widawskyab5c6082013-04-05 13:12:41 -0700628 return 0;
Ville Syrjäläb2e8c6c2015-11-04 23:20:00 +0200629
Tvrtko Ursulin920a14b2016-10-14 10:13:44 +0100630 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
Ville Syrjäläd8112152013-01-24 15:29:55 +0200631 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200632 else if (!HAS_GMCH_DISPLAY(dev_priv))
633 dev_priv->gpio_mmio_base =
634 i915_mmio_reg_offset(PCH_GPIOA) -
635 i915_mmio_reg_offset(GPIOA);
Daniel Vetter110447fc2012-03-23 23:43:36 +0100636
Yufeng Shen8a8ed1f2012-02-13 17:36:54 -0500637 mutex_init(&dev_priv->gmbus_mutex);
Daniel Vetter28c70f12012-12-01 13:53:45 +0100638 init_waitqueue_head(&dev_priv->gmbus_wait_queue);
Yufeng Shen8a8ed1f2012-02-13 17:36:54 -0500639
Jani Nikula5ea6e5e2015-04-01 10:55:04 +0300640 for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
Jani Nikula88ac7932015-03-27 00:20:22 +0200641 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
Jani Nikula5ea6e5e2015-04-01 10:55:04 +0300642 continue;
643
644 bus = &dev_priv->gmbus[pin];
Chris Wilsonf899fc62010-07-20 15:44:45 -0700645
646 bus->adapter.owner = THIS_MODULE;
647 bus->adapter.class = I2C_CLASS_DDC;
648 snprintf(bus->adapter.name,
Jean Delvare69669452010-11-05 18:51:34 +0100649 sizeof(bus->adapter.name),
650 "i915 gmbus %s",
Jani Nikula4c272832015-04-01 10:58:05 +0300651 get_gmbus_pin(dev_priv, pin)->name);
Chris Wilsonf899fc62010-07-20 15:44:45 -0700652
David Weinehall52a05c32016-08-22 13:32:44 +0300653 bus->adapter.dev.parent = &pdev->dev;
Daniel Vetterc2b91522012-02-14 22:37:19 +0100654 bus->dev_priv = dev_priv;
Chris Wilsonf899fc62010-07-20 15:44:45 -0700655
656 bus->adapter.algo = &gmbus_algorithm;
Chris Wilsonf899fc62010-07-20 15:44:45 -0700657
Ville Syrjälä8b1f1652016-03-07 17:56:57 +0200658 /*
659 * We wish to retry with bit banging
660 * after a timed out GMBUS attempt.
661 */
662 bus->adapter.retries = 1;
663
Chris Wilsone957d772010-09-24 12:52:03 +0100664 /* By default use a conservative clock rate */
Jani Nikula5ea6e5e2015-04-01 10:55:04 +0300665 bus->reg0 = pin | GMBUS_RATE_100KHZ;
Chris Wilsoncb8ea752010-09-28 13:35:47 +0100666
Daniel Vetter83ee9e62012-05-13 14:44:20 +0200667 /* gmbus seems to be broken on i830 */
Tvrtko Ursulin50a0bc92016-10-13 11:02:58 +0100668 if (IS_I830(dev_priv))
Chris Wilsonf2ce9fa2012-11-10 15:58:21 +0000669 bus->force_bit = 1;
Daniel Vetter83ee9e62012-05-13 14:44:20 +0200670
Jani Nikula5ea6e5e2015-04-01 10:55:04 +0300671 intel_gpio_setup(bus, pin);
Jani Nikulacee25162012-08-13 17:33:02 +0300672
673 ret = i2c_add_adapter(&bus->adapter);
674 if (ret)
675 goto err;
Chris Wilsonf899fc62010-07-20 15:44:45 -0700676 }
677
Tvrtko Ursulinaf6dc742016-12-01 14:16:44 +0000678 intel_i2c_reset(dev_priv);
Chris Wilsonf899fc62010-07-20 15:44:45 -0700679
680 return 0;
681
682err:
Rasmus Villemoes2417c8c2016-02-09 21:11:13 +0100683 while (pin--) {
Jani Nikula88ac7932015-03-27 00:20:22 +0200684 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
Jani Nikula5ea6e5e2015-04-01 10:55:04 +0300685 continue;
686
687 bus = &dev_priv->gmbus[pin];
Chris Wilsonf899fc62010-07-20 15:44:45 -0700688 i2c_del_adapter(&bus->adapter);
689 }
Chris Wilsonf899fc62010-07-20 15:44:45 -0700690 return ret;
691}
692
Daniel Kurtz3bd7d902012-03-28 02:36:14 +0800693struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
Jani Nikula0184df42015-03-27 00:20:20 +0200694 unsigned int pin)
Daniel Kurtz3bd7d902012-03-28 02:36:14 +0800695{
Jani Nikula88ac7932015-03-27 00:20:22 +0200696 if (WARN_ON(!intel_gmbus_is_valid_pin(dev_priv, pin)))
Jani Nikula5ea6e5e2015-04-01 10:55:04 +0300697 return NULL;
698
699 return &dev_priv->gmbus[pin].adapter;
Daniel Kurtz3bd7d902012-03-28 02:36:14 +0800700}
701
Chris Wilsone957d772010-09-24 12:52:03 +0100702void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
703{
704 struct intel_gmbus *bus = to_intel_gmbus(adapter);
705
Adam Jacksond5090b92011-06-16 16:36:28 -0400706 bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed;
Chris Wilsone957d772010-09-24 12:52:03 +0100707}
708
709void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
710{
711 struct intel_gmbus *bus = to_intel_gmbus(adapter);
Ville Syrjäläade754e2016-03-07 17:56:58 +0200712 struct drm_i915_private *dev_priv = bus->dev_priv;
713
714 mutex_lock(&dev_priv->gmbus_mutex);
Chris Wilsone957d772010-09-24 12:52:03 +0100715
Chris Wilsonf2ce9fa2012-11-10 15:58:21 +0000716 bus->force_bit += force_bit ? 1 : -1;
717 DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n",
718 force_bit ? "en" : "dis", adapter->name,
719 bus->force_bit);
Ville Syrjäläade754e2016-03-07 17:56:58 +0200720
721 mutex_unlock(&dev_priv->gmbus_mutex);
Chris Wilsone957d772010-09-24 12:52:03 +0100722}
723
Tvrtko Ursulin40196442016-12-01 14:16:42 +0000724void intel_teardown_gmbus(struct drm_i915_private *dev_priv)
Chris Wilsonf899fc62010-07-20 15:44:45 -0700725{
Jani Nikula5ea6e5e2015-04-01 10:55:04 +0300726 struct intel_gmbus *bus;
727 unsigned int pin;
Chris Wilsonf899fc62010-07-20 15:44:45 -0700728
Jani Nikula5ea6e5e2015-04-01 10:55:04 +0300729 for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
Jani Nikula88ac7932015-03-27 00:20:22 +0200730 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
Jani Nikula5ea6e5e2015-04-01 10:55:04 +0300731 continue;
732
733 bus = &dev_priv->gmbus[pin];
Chris Wilsonf899fc62010-07-20 15:44:45 -0700734 i2c_del_adapter(&bus->adapter);
735 }
Jesse Barnes79e53942008-11-07 14:24:08 -0800736}