blob: 31ff57a654bad9e54f5823459a21a7a8948ae275 [file] [log] [blame]
Ezequiel Garciafa0d6542013-04-02 01:37:41 +00001/*
Miquel Raynala9d58a12017-12-22 17:14:10 +01002 * Marvell EBU Armada SoCs thermal sensor driver
Ezequiel Garciafa0d6542013-04-02 01:37:41 +00003 *
4 * Copyright (C) 2013 Marvell
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16#include <linux/device.h>
17#include <linux/err.h>
18#include <linux/io.h>
19#include <linux/kernel.h>
20#include <linux/of.h>
21#include <linux/module.h>
22#include <linux/delay.h>
23#include <linux/platform_device.h>
24#include <linux/of_device.h>
25#include <linux/thermal.h>
Miquel Raynal64163682017-12-22 17:14:12 +010026#include <linux/iopoll.h>
Ezequiel Garciafa0d6542013-04-02 01:37:41 +000027
Ezequiel Garciafa0d6542013-04-02 01:37:41 +000028/* Thermal Manager Control and Status Register */
29#define PMU_TDC0_SW_RST_MASK (0x1 << 1)
30#define PMU_TM_DISABLE_OFFS 0
31#define PMU_TM_DISABLE_MASK (0x1 << PMU_TM_DISABLE_OFFS)
32#define PMU_TDC0_REF_CAL_CNT_OFFS 11
33#define PMU_TDC0_REF_CAL_CNT_MASK (0x1ff << PMU_TDC0_REF_CAL_CNT_OFFS)
34#define PMU_TDC0_OTF_CAL_MASK (0x1 << 30)
35#define PMU_TDC0_START_CAL_MASK (0x1 << 25)
36
Ezequiel Garciae2d5f052014-05-06 13:59:50 -030037#define A375_UNIT_CONTROL_SHIFT 27
38#define A375_UNIT_CONTROL_MASK 0x7
39#define A375_READOUT_INVERT BIT(15)
40#define A375_HW_RESETn BIT(8)
41
Miquel Raynal2f28e4c2017-12-22 17:14:06 +010042/* Legacy bindings */
43#define LEGACY_CONTROL_MEM_LEN 0x4
44
45/* Current bindings with the 2 control registers under the same memory area */
46#define LEGACY_CONTROL1_OFFSET 0x0
47#define CONTROL0_OFFSET 0x0
48#define CONTROL1_OFFSET 0x4
49
Miquel Raynal8c0b8882017-12-22 17:14:11 +010050/* Errata fields */
51#define CONTROL0_TSEN_TC_TRIM_MASK 0x7
52#define CONTROL0_TSEN_TC_TRIM_VAL 0x3
53
Baruch Siach2ff12792017-12-22 17:14:08 +010054#define CONTROL0_TSEN_START BIT(0)
55#define CONTROL0_TSEN_RESET BIT(1)
56#define CONTROL0_TSEN_ENABLE BIT(2)
57
Baruch Siachccf8f522017-12-22 17:14:09 +010058#define CONTROL1_EXT_TSEN_SW_RESET BIT(7)
59#define CONTROL1_EXT_TSEN_HW_RESETn BIT(8)
60
Miquel Raynal64163682017-12-22 17:14:12 +010061#define STATUS_POLL_PERIOD_US 1000
62#define STATUS_POLL_TIMEOUT_US 100000
63
Ezequiel Garcia66fdb7b2014-05-06 13:59:45 -030064struct armada_thermal_data;
Ezequiel Garciafa0d6542013-04-02 01:37:41 +000065
66/* Marvell EBU Thermal Sensor Dev Structure */
67struct armada_thermal_priv {
Miquel Raynal8371b8a2017-12-22 17:14:07 +010068 void __iomem *status;
Miquel Raynal2f28e4c2017-12-22 17:14:06 +010069 void __iomem *control0;
70 void __iomem *control1;
Miquel Raynal8d987612018-07-16 16:41:44 +020071 char zone_name[THERMAL_NAME_LENGTH];
Ezequiel Garcia66fdb7b2014-05-06 13:59:45 -030072 struct armada_thermal_data *data;
Ezequiel Garciafa0d6542013-04-02 01:37:41 +000073};
74
Ezequiel Garcia66fdb7b2014-05-06 13:59:45 -030075struct armada_thermal_data {
Miquel Raynal8b4c2712018-07-16 16:41:47 +020076 /* Initialize the thermal IC */
77 void (*init)(struct platform_device *pdev,
78 struct armada_thermal_priv *priv);
Ezequiel Garciafa0d6542013-04-02 01:37:41 +000079
80 /* Test for a valid sensor value (optional) */
81 bool (*is_valid)(struct armada_thermal_priv *);
Ezequiel Garcia9484bc62014-05-06 13:59:46 -030082
Baruch Siach0cf3a1a2017-09-14 18:06:57 +030083 /* Formula coeficients: temp = (b - m * reg) / div */
Baruch Siach2ff12792017-12-22 17:14:08 +010084 s64 coef_b;
85 s64 coef_m;
86 u32 coef_div;
Ezequiel Garciafd2c94d2014-05-06 13:59:49 -030087 bool inverted;
Baruch Siach2ff12792017-12-22 17:14:08 +010088 bool signed_sample;
Ezequiel Garcia1fcacca2014-05-06 13:59:47 -030089
90 /* Register shift and mask to access the sensor temperature */
91 unsigned int temp_shift;
92 unsigned int temp_mask;
Miquel Raynal27d92f22017-12-22 17:14:05 +010093 u32 is_valid_bit;
Miquel Raynal2f28e4c2017-12-22 17:14:06 +010094 bool needs_control0;
Ezequiel Garciafa0d6542013-04-02 01:37:41 +000095};
96
Miquel Raynal8b4c2712018-07-16 16:41:47 +020097static void armadaxp_init(struct platform_device *pdev,
98 struct armada_thermal_priv *priv)
Ezequiel Garciafa0d6542013-04-02 01:37:41 +000099{
Miquel Raynal2f28e4c2017-12-22 17:14:06 +0100100 u32 reg;
Ezequiel Garciafa0d6542013-04-02 01:37:41 +0000101
Miquel Raynal2f28e4c2017-12-22 17:14:06 +0100102 reg = readl_relaxed(priv->control1);
Ezequiel Garciafa0d6542013-04-02 01:37:41 +0000103 reg |= PMU_TDC0_OTF_CAL_MASK;
Ezequiel Garciafa0d6542013-04-02 01:37:41 +0000104
105 /* Reference calibration value */
106 reg &= ~PMU_TDC0_REF_CAL_CNT_MASK;
107 reg |= (0xf1 << PMU_TDC0_REF_CAL_CNT_OFFS);
Ezequiel Garciafa0d6542013-04-02 01:37:41 +0000108
109 /* Reset the sensor */
Miquel Raynal931d3c52018-07-16 16:41:45 +0200110 reg |= PMU_TDC0_SW_RST_MASK;
Ezequiel Garciafa0d6542013-04-02 01:37:41 +0000111
Miquel Raynal2f28e4c2017-12-22 17:14:06 +0100112 writel(reg, priv->control1);
Ezequiel Garciafa0d6542013-04-02 01:37:41 +0000113
114 /* Enable the sensor */
Miquel Raynal8371b8a2017-12-22 17:14:07 +0100115 reg = readl_relaxed(priv->status);
Ezequiel Garciafa0d6542013-04-02 01:37:41 +0000116 reg &= ~PMU_TM_DISABLE_MASK;
Miquel Raynal8371b8a2017-12-22 17:14:07 +0100117 writel(reg, priv->status);
Ezequiel Garciafa0d6542013-04-02 01:37:41 +0000118}
119
Miquel Raynal8b4c2712018-07-16 16:41:47 +0200120static void armada370_init(struct platform_device *pdev,
121 struct armada_thermal_priv *priv)
Ezequiel Garciafa0d6542013-04-02 01:37:41 +0000122{
Miquel Raynal2f28e4c2017-12-22 17:14:06 +0100123 u32 reg;
Ezequiel Garciafa0d6542013-04-02 01:37:41 +0000124
Miquel Raynal2f28e4c2017-12-22 17:14:06 +0100125 reg = readl_relaxed(priv->control1);
Ezequiel Garciafa0d6542013-04-02 01:37:41 +0000126 reg |= PMU_TDC0_OTF_CAL_MASK;
Ezequiel Garciafa0d6542013-04-02 01:37:41 +0000127
128 /* Reference calibration value */
129 reg &= ~PMU_TDC0_REF_CAL_CNT_MASK;
130 reg |= (0xf1 << PMU_TDC0_REF_CAL_CNT_OFFS);
Ezequiel Garciafa0d6542013-04-02 01:37:41 +0000131
132 reg &= ~PMU_TDC0_START_CAL_MASK;
Miquel Raynal931d3c52018-07-16 16:41:45 +0200133
Miquel Raynal2f28e4c2017-12-22 17:14:06 +0100134 writel(reg, priv->control1);
Ezequiel Garciafa0d6542013-04-02 01:37:41 +0000135
Baruch Siach7f3be012017-12-22 17:14:04 +0100136 msleep(10);
Ezequiel Garciafa0d6542013-04-02 01:37:41 +0000137}
138
Miquel Raynal8b4c2712018-07-16 16:41:47 +0200139static void armada375_init(struct platform_device *pdev,
140 struct armada_thermal_priv *priv)
Ezequiel Garciae2d5f052014-05-06 13:59:50 -0300141{
Miquel Raynal2f28e4c2017-12-22 17:14:06 +0100142 u32 reg;
Ezequiel Garciae2d5f052014-05-06 13:59:50 -0300143
Miquel Raynal2f28e4c2017-12-22 17:14:06 +0100144 reg = readl(priv->control1);
Ezequiel Garciae2d5f052014-05-06 13:59:50 -0300145 reg &= ~(A375_UNIT_CONTROL_MASK << A375_UNIT_CONTROL_SHIFT);
146 reg &= ~A375_READOUT_INVERT;
147 reg &= ~A375_HW_RESETn;
148
Miquel Raynal2f28e4c2017-12-22 17:14:06 +0100149 writel(reg, priv->control1);
Baruch Siach7f3be012017-12-22 17:14:04 +0100150 msleep(20);
Ezequiel Garciae2d5f052014-05-06 13:59:50 -0300151
152 reg |= A375_HW_RESETn;
Miquel Raynal2f28e4c2017-12-22 17:14:06 +0100153 writel(reg, priv->control1);
Baruch Siach7f3be012017-12-22 17:14:04 +0100154 msleep(50);
Ezequiel Garciae2d5f052014-05-06 13:59:50 -0300155}
156
Miquel Raynal64163682017-12-22 17:14:12 +0100157static void armada_wait_sensor_validity(struct armada_thermal_priv *priv)
158{
159 u32 reg;
160
161 readl_relaxed_poll_timeout(priv->status, reg,
162 reg & priv->data->is_valid_bit,
163 STATUS_POLL_PERIOD_US,
164 STATUS_POLL_TIMEOUT_US);
165}
166
Miquel Raynal8b4c2712018-07-16 16:41:47 +0200167static void armada380_init(struct platform_device *pdev,
168 struct armada_thermal_priv *priv)
Ezequiel Garciae6e0a682014-05-06 13:59:51 -0300169{
Miquel Raynal2f28e4c2017-12-22 17:14:06 +0100170 u32 reg = readl_relaxed(priv->control1);
Ezequiel Garciae6e0a682014-05-06 13:59:51 -0300171
Baruch Siachccf8f522017-12-22 17:14:09 +0100172 /* Disable the HW/SW reset */
173 reg |= CONTROL1_EXT_TSEN_HW_RESETn;
174 reg &= ~CONTROL1_EXT_TSEN_SW_RESET;
175 writel(reg, priv->control1);
Miquel Raynal8c0b8882017-12-22 17:14:11 +0100176
177 /* Set Tsen Tc Trim to correct default value (errata #132698) */
178 if (priv->control0) {
179 reg = readl_relaxed(priv->control0);
180 reg &= ~CONTROL0_TSEN_TC_TRIM_MASK;
181 reg |= CONTROL0_TSEN_TC_TRIM_VAL;
182 writel(reg, priv->control0);
Miquel Raynal8c0b8882017-12-22 17:14:11 +0100183 }
Miquel Raynal64163682017-12-22 17:14:12 +0100184
185 /* Wait the sensors to be valid or the core will warn the user */
186 armada_wait_sensor_validity(priv);
Ezequiel Garciae6e0a682014-05-06 13:59:51 -0300187}
188
Miquel Raynal8b4c2712018-07-16 16:41:47 +0200189static void armada_ap806_init(struct platform_device *pdev,
190 struct armada_thermal_priv *priv)
Baruch Siach2ff12792017-12-22 17:14:08 +0100191{
192 u32 reg;
193
194 reg = readl_relaxed(priv->control0);
195 reg &= ~CONTROL0_TSEN_RESET;
196 reg |= CONTROL0_TSEN_START | CONTROL0_TSEN_ENABLE;
197 writel(reg, priv->control0);
Miquel Raynal64163682017-12-22 17:14:12 +0100198
199 /* Wait the sensors to be valid or the core will warn the user */
200 armada_wait_sensor_validity(priv);
Baruch Siach2ff12792017-12-22 17:14:08 +0100201}
202
Miquel Raynal5b5e17a2018-07-16 16:41:48 +0200203static void armada_cp110_init(struct platform_device *pdev,
204 struct armada_thermal_priv *priv)
205{
206 armada380_init(pdev, priv);
207}
208
Ezequiel Garciafa0d6542013-04-02 01:37:41 +0000209static bool armada_is_valid(struct armada_thermal_priv *priv)
210{
Miquel Raynal8371b8a2017-12-22 17:14:07 +0100211 u32 reg = readl_relaxed(priv->status);
Ezequiel Garciafa0d6542013-04-02 01:37:41 +0000212
Miquel Raynal27d92f22017-12-22 17:14:05 +0100213 return reg & priv->data->is_valid_bit;
Ezequiel Garciafa0d6542013-04-02 01:37:41 +0000214}
215
216static int armada_get_temp(struct thermal_zone_device *thermal,
Baruch Siach2ff12792017-12-22 17:14:08 +0100217 int *temp)
Ezequiel Garciafa0d6542013-04-02 01:37:41 +0000218{
219 struct armada_thermal_priv *priv = thermal->devdata;
Baruch Siach2ff12792017-12-22 17:14:08 +0100220 u32 reg, div;
221 s64 sample, b, m;
Ezequiel Garciafa0d6542013-04-02 01:37:41 +0000222
223 /* Valid check */
Ezequiel Garcia66fdb7b2014-05-06 13:59:45 -0300224 if (priv->data->is_valid && !priv->data->is_valid(priv)) {
Ezequiel Garciafa0d6542013-04-02 01:37:41 +0000225 dev_err(&thermal->device,
226 "Temperature sensor reading not valid\n");
227 return -EIO;
228 }
229
Miquel Raynal8371b8a2017-12-22 17:14:07 +0100230 reg = readl_relaxed(priv->status);
Ezequiel Garcia1fcacca2014-05-06 13:59:47 -0300231 reg = (reg >> priv->data->temp_shift) & priv->data->temp_mask;
Baruch Siach2ff12792017-12-22 17:14:08 +0100232 if (priv->data->signed_sample)
233 /* The most significant bit is the sign bit */
234 sample = sign_extend32(reg, fls(priv->data->temp_mask) - 1);
235 else
236 sample = reg;
Ezequiel Garcia9484bc62014-05-06 13:59:46 -0300237
238 /* Get formula coeficients */
239 b = priv->data->coef_b;
240 m = priv->data->coef_m;
241 div = priv->data->coef_div;
242
Ezequiel Garciafd2c94d2014-05-06 13:59:49 -0300243 if (priv->data->inverted)
Baruch Siach2ff12792017-12-22 17:14:08 +0100244 *temp = div_s64((m * sample) - b, div);
Ezequiel Garciafd2c94d2014-05-06 13:59:49 -0300245 else
Baruch Siach2ff12792017-12-22 17:14:08 +0100246 *temp = div_s64(b - (m * sample), div);
247
Ezequiel Garciafa0d6542013-04-02 01:37:41 +0000248 return 0;
249}
250
251static struct thermal_zone_device_ops ops = {
252 .get_temp = armada_get_temp,
253};
254
Ezequiel Garcia66fdb7b2014-05-06 13:59:45 -0300255static const struct armada_thermal_data armadaxp_data = {
Miquel Raynal8b4c2712018-07-16 16:41:47 +0200256 .init = armadaxp_init,
Ezequiel Garcia1fcacca2014-05-06 13:59:47 -0300257 .temp_shift = 10,
258 .temp_mask = 0x1ff,
Baruch Siach2ff12792017-12-22 17:14:08 +0100259 .coef_b = 3153000000ULL,
260 .coef_m = 10000000ULL,
Ezequiel Garcia9484bc62014-05-06 13:59:46 -0300261 .coef_div = 13825,
Ezequiel Garciafa0d6542013-04-02 01:37:41 +0000262};
263
Ezequiel Garcia66fdb7b2014-05-06 13:59:45 -0300264static const struct armada_thermal_data armada370_data = {
Ezequiel Garciafa0d6542013-04-02 01:37:41 +0000265 .is_valid = armada_is_valid,
Miquel Raynal8b4c2712018-07-16 16:41:47 +0200266 .init = armada370_init,
Miquel Raynal27d92f22017-12-22 17:14:05 +0100267 .is_valid_bit = BIT(9),
Ezequiel Garcia1fcacca2014-05-06 13:59:47 -0300268 .temp_shift = 10,
269 .temp_mask = 0x1ff,
Baruch Siach2ff12792017-12-22 17:14:08 +0100270 .coef_b = 3153000000ULL,
271 .coef_m = 10000000ULL,
Ezequiel Garcia9484bc62014-05-06 13:59:46 -0300272 .coef_div = 13825,
Ezequiel Garciafa0d6542013-04-02 01:37:41 +0000273};
274
Ezequiel Garciae2d5f052014-05-06 13:59:50 -0300275static const struct armada_thermal_data armada375_data = {
276 .is_valid = armada_is_valid,
Miquel Raynal8b4c2712018-07-16 16:41:47 +0200277 .init = armada375_init,
Miquel Raynal27d92f22017-12-22 17:14:05 +0100278 .is_valid_bit = BIT(10),
Ezequiel Garciae2d5f052014-05-06 13:59:50 -0300279 .temp_shift = 0,
280 .temp_mask = 0x1ff,
Baruch Siach2ff12792017-12-22 17:14:08 +0100281 .coef_b = 3171900000ULL,
282 .coef_m = 10000000ULL,
Ezequiel Garciae2d5f052014-05-06 13:59:50 -0300283 .coef_div = 13616,
Miquel Raynal2f28e4c2017-12-22 17:14:06 +0100284 .needs_control0 = true,
Ezequiel Garciae2d5f052014-05-06 13:59:50 -0300285};
286
Ezequiel Garciae6e0a682014-05-06 13:59:51 -0300287static const struct armada_thermal_data armada380_data = {
288 .is_valid = armada_is_valid,
Miquel Raynal8b4c2712018-07-16 16:41:47 +0200289 .init = armada380_init,
Miquel Raynal27d92f22017-12-22 17:14:05 +0100290 .is_valid_bit = BIT(10),
Ezequiel Garciae6e0a682014-05-06 13:59:51 -0300291 .temp_shift = 0,
292 .temp_mask = 0x3ff,
Baruch Siach2ff12792017-12-22 17:14:08 +0100293 .coef_b = 1172499100ULL,
294 .coef_m = 2000096ULL,
Nadav Haklaib56100d2015-08-06 18:03:49 +0200295 .coef_div = 4201,
Ezequiel Garciae6e0a682014-05-06 13:59:51 -0300296 .inverted = true,
297};
298
Baruch Siach2ff12792017-12-22 17:14:08 +0100299static const struct armada_thermal_data armada_ap806_data = {
300 .is_valid = armada_is_valid,
Miquel Raynal8b4c2712018-07-16 16:41:47 +0200301 .init = armada_ap806_init,
Baruch Siach2ff12792017-12-22 17:14:08 +0100302 .is_valid_bit = BIT(16),
303 .temp_shift = 0,
304 .temp_mask = 0x3ff,
305 .coef_b = -150000LL,
306 .coef_m = 423ULL,
307 .coef_div = 1,
308 .inverted = true,
309 .signed_sample = true,
310 .needs_control0 = true,
311};
312
Baruch Siachccf8f522017-12-22 17:14:09 +0100313static const struct armada_thermal_data armada_cp110_data = {
314 .is_valid = armada_is_valid,
Miquel Raynal5b5e17a2018-07-16 16:41:48 +0200315 .init = armada_cp110_init,
Baruch Siachccf8f522017-12-22 17:14:09 +0100316 .is_valid_bit = BIT(10),
317 .temp_shift = 0,
318 .temp_mask = 0x3ff,
319 .coef_b = 1172499100ULL,
320 .coef_m = 2000096ULL,
321 .coef_div = 4201,
322 .inverted = true,
323 .needs_control0 = true,
324};
325
Ezequiel Garciafa0d6542013-04-02 01:37:41 +0000326static const struct of_device_id armada_thermal_id_table[] = {
327 {
328 .compatible = "marvell,armadaxp-thermal",
Ezequiel Garcia66fdb7b2014-05-06 13:59:45 -0300329 .data = &armadaxp_data,
Ezequiel Garciafa0d6542013-04-02 01:37:41 +0000330 },
331 {
332 .compatible = "marvell,armada370-thermal",
Ezequiel Garcia66fdb7b2014-05-06 13:59:45 -0300333 .data = &armada370_data,
Ezequiel Garciafa0d6542013-04-02 01:37:41 +0000334 },
335 {
Ezequiel Garciae2d5f052014-05-06 13:59:50 -0300336 .compatible = "marvell,armada375-thermal",
337 .data = &armada375_data,
338 },
339 {
Ezequiel Garciae6e0a682014-05-06 13:59:51 -0300340 .compatible = "marvell,armada380-thermal",
341 .data = &armada380_data,
342 },
343 {
Baruch Siach2ff12792017-12-22 17:14:08 +0100344 .compatible = "marvell,armada-ap806-thermal",
345 .data = &armada_ap806_data,
346 },
347 {
Baruch Siachccf8f522017-12-22 17:14:09 +0100348 .compatible = "marvell,armada-cp110-thermal",
349 .data = &armada_cp110_data,
350 },
351 {
Ezequiel Garciafa0d6542013-04-02 01:37:41 +0000352 /* sentinel */
353 },
354};
355MODULE_DEVICE_TABLE(of, armada_thermal_id_table);
356
Miquel Raynal8d987612018-07-16 16:41:44 +0200357static void armada_set_sane_name(struct platform_device *pdev,
358 struct armada_thermal_priv *priv)
359{
360 const char *name = dev_name(&pdev->dev);
361 char *insane_char;
362
363 if (strlen(name) > THERMAL_NAME_LENGTH) {
364 /*
365 * When inside a system controller, the device name has the
366 * form: f06f8000.system-controller:ap-thermal so stripping
367 * after the ':' should give us a shorter but meaningful name.
368 */
369 name = strrchr(name, ':');
370 if (!name)
371 name = "armada_thermal";
372 else
373 name++;
374 }
375
376 /* Save the name locally */
377 strncpy(priv->zone_name, name, THERMAL_NAME_LENGTH - 1);
378 priv->zone_name[THERMAL_NAME_LENGTH - 1] = '\0';
379
380 /* Then check there are no '-' or hwmon core will complain */
381 do {
382 insane_char = strpbrk(priv->zone_name, "-");
383 if (insane_char)
384 *insane_char = '_';
385 } while (insane_char);
386}
387
Ezequiel Garciafa0d6542013-04-02 01:37:41 +0000388static int armada_thermal_probe(struct platform_device *pdev)
389{
Miquel Raynal2f28e4c2017-12-22 17:14:06 +0100390 void __iomem *control = NULL;
Ezequiel Garciafa0d6542013-04-02 01:37:41 +0000391 struct thermal_zone_device *thermal;
392 const struct of_device_id *match;
393 struct armada_thermal_priv *priv;
394 struct resource *res;
395
396 match = of_match_device(armada_thermal_id_table, &pdev->dev);
397 if (!match)
398 return -ENODEV;
399
400 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
401 if (!priv)
402 return -ENOMEM;
403
404 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Miquel Raynal8371b8a2017-12-22 17:14:07 +0100405 priv->status = devm_ioremap_resource(&pdev->dev, res);
406 if (IS_ERR(priv->status))
407 return PTR_ERR(priv->status);
Ezequiel Garciafa0d6542013-04-02 01:37:41 +0000408
409 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
Miquel Raynal2f28e4c2017-12-22 17:14:06 +0100410 control = devm_ioremap_resource(&pdev->dev, res);
411 if (IS_ERR(control))
412 return PTR_ERR(control);
Ezequiel Garciafa0d6542013-04-02 01:37:41 +0000413
Ezequiel Garcia66fdb7b2014-05-06 13:59:45 -0300414 priv->data = (struct armada_thermal_data *)match->data;
Miquel Raynal2f28e4c2017-12-22 17:14:06 +0100415
Miquel Raynal8d987612018-07-16 16:41:44 +0200416 /* Ensure device name is correct for the thermal core */
417 armada_set_sane_name(pdev, priv);
418
Miquel Raynal2f28e4c2017-12-22 17:14:06 +0100419 /*
420 * Legacy DT bindings only described "control1" register (also referred
421 * as "control MSB" on old documentation). New bindings cover
422 * "control0/control LSB" and "control1/control MSB" registers within
423 * the same resource, which is then of size 8 instead of 4.
424 */
425 if (resource_size(res) == LEGACY_CONTROL_MEM_LEN) {
426 /* ->control0 unavailable in this configuration */
427 if (priv->data->needs_control0) {
428 dev_err(&pdev->dev, "No access to control0 register\n");
429 return -EINVAL;
430 }
431
432 priv->control1 = control + LEGACY_CONTROL1_OFFSET;
433 } else {
434 priv->control0 = control + CONTROL0_OFFSET;
435 priv->control1 = control + CONTROL1_OFFSET;
436 }
437
Miquel Raynal8b4c2712018-07-16 16:41:47 +0200438 priv->data->init(pdev, priv);
Ezequiel Garciafa0d6542013-04-02 01:37:41 +0000439
Miquel Raynal8d987612018-07-16 16:41:44 +0200440 thermal = thermal_zone_device_register(priv->zone_name, 0, 0, priv,
Miquel Raynalf80ee032017-12-22 17:14:13 +0100441 &ops, NULL, 0, 0);
Ezequiel Garciafa0d6542013-04-02 01:37:41 +0000442 if (IS_ERR(thermal)) {
443 dev_err(&pdev->dev,
444 "Failed to register thermal zone device\n");
445 return PTR_ERR(thermal);
446 }
447
448 platform_set_drvdata(pdev, thermal);
449
450 return 0;
451}
452
453static int armada_thermal_exit(struct platform_device *pdev)
454{
455 struct thermal_zone_device *armada_thermal =
456 platform_get_drvdata(pdev);
457
458 thermal_zone_device_unregister(armada_thermal);
Ezequiel Garciafa0d6542013-04-02 01:37:41 +0000459
460 return 0;
461}
462
463static struct platform_driver armada_thermal_driver = {
464 .probe = armada_thermal_probe,
465 .remove = armada_thermal_exit,
466 .driver = {
467 .name = "armada_thermal",
Sachin Kamat1d089e02013-05-16 10:28:08 +0000468 .of_match_table = armada_thermal_id_table,
Ezequiel Garciafa0d6542013-04-02 01:37:41 +0000469 },
470};
471
472module_platform_driver(armada_thermal_driver);
473
474MODULE_AUTHOR("Ezequiel Garcia <ezequiel.garcia@free-electrons.com>");
Miquel Raynala9d58a12017-12-22 17:14:10 +0100475MODULE_DESCRIPTION("Marvell EBU Armada SoCs thermal driver");
Ezequiel Garciafa0d6542013-04-02 01:37:41 +0000476MODULE_LICENSE("GPL v2");