Larry Finger | 0c81733 | 2010-12-08 11:12:31 -0600 | [diff] [blame] | 1 | /****************************************************************************** |
| 2 | * |
| 3 | * Copyright(c) 2009-2010 Realtek Corporation. |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms of version 2 of the GNU General Public License as |
| 7 | * published by the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 12 | * more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License along with |
| 15 | * this program; if not, write to the Free Software Foundation, Inc., |
| 16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA |
| 17 | * |
| 18 | * The full GNU General Public License is included in this distribution in the |
| 19 | * file called LICENSE. |
| 20 | * |
| 21 | * Contact Information: |
| 22 | * wlanfae <wlanfae@realtek.com> |
| 23 | * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, |
| 24 | * Hsinchu 300, Taiwan. |
| 25 | * |
| 26 | * Larry Finger <Larry.Finger@lwfinger.net> |
| 27 | * |
| 28 | *****************************************************************************/ |
| 29 | |
Larry Finger | 4aea248 | 2010-12-15 22:55:34 -0600 | [diff] [blame] | 30 | #include <linux/vmalloc.h> |
| 31 | |
Larry Finger | 0c81733 | 2010-12-08 11:12:31 -0600 | [diff] [blame] | 32 | #include "../wifi.h" |
| 33 | #include "../core.h" |
| 34 | #include "../pci.h" |
John W. Linville | 5c405b5 | 2010-12-16 15:43:36 -0500 | [diff] [blame^] | 35 | #include "reg.h" |
| 36 | #include "def.h" |
| 37 | #include "phy.h" |
| 38 | #include "dm.h" |
| 39 | #include "hw.h" |
| 40 | #include "sw.h" |
| 41 | #include "trx.h" |
| 42 | #include "led.h" |
Larry Finger | 0c81733 | 2010-12-08 11:12:31 -0600 | [diff] [blame] | 43 | |
| 44 | int rtl92c_init_sw_vars(struct ieee80211_hw *hw) |
| 45 | { |
| 46 | struct rtl_priv *rtlpriv = rtl_priv(hw); |
| 47 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); |
| 48 | |
| 49 | rtlpriv->dm.b_dm_initialgain_enable = 1; |
| 50 | rtlpriv->dm.dm_flag = 0; |
| 51 | rtlpriv->dm.b_disable_framebursting = 0;; |
| 52 | rtlpriv->dm.thermalvalue = 0; |
| 53 | rtlpci->transmit_config = CFENDFORM | BIT(12) | BIT(13); |
| 54 | |
| 55 | rtlpci->receive_config = (RCR_APPFCS | |
| 56 | RCR_AMF | |
| 57 | RCR_ADF | |
| 58 | RCR_APP_MIC | |
| 59 | RCR_APP_ICV | |
| 60 | RCR_AICV | |
| 61 | RCR_ACRC32 | |
| 62 | RCR_AB | |
| 63 | RCR_AM | |
| 64 | RCR_APM | |
| 65 | RCR_APP_PHYST_RXFF | RCR_HTC_LOC_CTRL | 0); |
| 66 | |
| 67 | rtlpci->irq_mask[0] = |
| 68 | (u32) (IMR_ROK | |
| 69 | IMR_VODOK | |
| 70 | IMR_VIDOK | |
| 71 | IMR_BEDOK | |
| 72 | IMR_BKDOK | |
| 73 | IMR_MGNTDOK | |
| 74 | IMR_HIGHDOK | IMR_BDOK | IMR_RDU | IMR_RXFOVW | 0); |
| 75 | |
| 76 | rtlpci->irq_mask[1] = (u32) (IMR_CPWM | IMR_C2HCMD | 0); |
| 77 | |
| 78 | rtlpriv->rtlhal.pfirmware = (u8 *) vmalloc(0x4000); |
| 79 | if (!rtlpriv->rtlhal.pfirmware) { |
| 80 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, |
| 81 | ("Can't alloc buffer for fw.\n")); |
| 82 | return 1; |
| 83 | } |
| 84 | |
| 85 | return 0; |
| 86 | } |
| 87 | |
| 88 | void rtl92c_deinit_sw_vars(struct ieee80211_hw *hw) |
| 89 | { |
| 90 | struct rtl_priv *rtlpriv = rtl_priv(hw); |
| 91 | |
| 92 | if (rtlpriv->rtlhal.pfirmware) { |
| 93 | vfree(rtlpriv->rtlhal.pfirmware); |
| 94 | rtlpriv->rtlhal.pfirmware = NULL; |
| 95 | } |
| 96 | } |
| 97 | |
| 98 | static struct rtl_hal_ops rtl8192ce_hal_ops = { |
| 99 | .init_sw_vars = rtl92c_init_sw_vars, |
| 100 | .deinit_sw_vars = rtl92c_deinit_sw_vars, |
| 101 | .read_eeprom_info = rtl92ce_read_eeprom_info, |
| 102 | .interrupt_recognized = rtl92ce_interrupt_recognized, |
| 103 | .hw_init = rtl92ce_hw_init, |
| 104 | .hw_disable = rtl92ce_card_disable, |
| 105 | .enable_interrupt = rtl92ce_enable_interrupt, |
| 106 | .disable_interrupt = rtl92ce_disable_interrupt, |
| 107 | .set_network_type = rtl92ce_set_network_type, |
| 108 | .set_qos = rtl92ce_set_qos, |
| 109 | .set_bcn_reg = rtl92ce_set_beacon_related_registers, |
| 110 | .set_bcn_intv = rtl92ce_set_beacon_interval, |
| 111 | .update_interrupt_mask = rtl92ce_update_interrupt_mask, |
| 112 | .get_hw_reg = rtl92ce_get_hw_reg, |
| 113 | .set_hw_reg = rtl92ce_set_hw_reg, |
| 114 | .update_rate_table = rtl92ce_update_hal_rate_table, |
| 115 | .update_rate_mask = rtl92ce_update_hal_rate_mask, |
| 116 | .fill_tx_desc = rtl92ce_tx_fill_desc, |
| 117 | .fill_tx_cmddesc = rtl92ce_tx_fill_cmddesc, |
| 118 | .query_rx_desc = rtl92ce_rx_query_desc, |
| 119 | .set_channel_access = rtl92ce_update_channel_access_setting, |
| 120 | .radio_onoff_checking = rtl92ce_gpio_radio_on_off_checking, |
| 121 | .set_bw_mode = rtl92c_phy_set_bw_mode, |
| 122 | .switch_channel = rtl92c_phy_sw_chnl, |
| 123 | .dm_watchdog = rtl92c_dm_watchdog, |
| 124 | .scan_operation_backup = rtl92c_phy_scan_operation_backup, |
| 125 | .set_rf_power_state = rtl92c_phy_set_rf_power_state, |
| 126 | .led_control = rtl92ce_led_control, |
| 127 | .set_desc = rtl92ce_set_desc, |
| 128 | .get_desc = rtl92ce_get_desc, |
| 129 | .tx_polling = rtl92ce_tx_polling, |
| 130 | .enable_hw_sec = rtl92ce_enable_hw_security_config, |
| 131 | .set_key = rtl92ce_set_key, |
| 132 | .init_sw_leds = rtl92ce_init_sw_leds, |
| 133 | .deinit_sw_leds = rtl92ce_deinit_sw_leds, |
| 134 | .get_bbreg = rtl92c_phy_query_bb_reg, |
| 135 | .set_bbreg = rtl92c_phy_set_bb_reg, |
| 136 | .get_rfreg = rtl92c_phy_query_rf_reg, |
| 137 | .set_rfreg = rtl92c_phy_set_rf_reg, |
| 138 | }; |
| 139 | |
| 140 | static struct rtl_mod_params rtl92ce_mod_params = { |
| 141 | .sw_crypto = 0, |
| 142 | }; |
| 143 | |
| 144 | static struct rtl_hal_cfg rtl92ce_hal_cfg = { |
| 145 | .name = "rtl92c_pci", |
| 146 | .fw_name = "rtlwifi/rtl8192cfw.bin", |
| 147 | .ops = &rtl8192ce_hal_ops, |
| 148 | .mod_params = &rtl92ce_mod_params, |
| 149 | |
| 150 | .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL, |
| 151 | .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN, |
| 152 | .maps[SYS_CLK] = REG_SYS_CLKR, |
| 153 | .maps[MAC_RCR_AM] = AM, |
| 154 | .maps[MAC_RCR_AB] = AB, |
| 155 | .maps[MAC_RCR_ACRC32] = ACRC32, |
| 156 | .maps[MAC_RCR_ACF] = ACF, |
| 157 | .maps[MAC_RCR_AAP] = AAP, |
| 158 | |
| 159 | .maps[EFUSE_TEST] = REG_EFUSE_TEST, |
| 160 | .maps[EFUSE_CTRL] = REG_EFUSE_CTRL, |
| 161 | .maps[EFUSE_CLK] = 0, |
| 162 | .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL, |
| 163 | .maps[EFUSE_PWC_EV12V] = PWC_EV12V, |
| 164 | .maps[EFUSE_FEN_ELDR] = FEN_ELDR, |
| 165 | .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN, |
| 166 | .maps[EFUSE_ANA8M] = EFUSE_ANA8M, |
| 167 | .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE, |
| 168 | |
| 169 | .maps[RWCAM] = REG_CAMCMD, |
| 170 | .maps[WCAMI] = REG_CAMWRITE, |
| 171 | .maps[RCAMO] = REG_CAMREAD, |
| 172 | .maps[CAMDBG] = REG_CAMDBG, |
| 173 | .maps[SECR] = REG_SECCFG, |
| 174 | .maps[SEC_CAM_NONE] = CAM_NONE, |
| 175 | .maps[SEC_CAM_WEP40] = CAM_WEP40, |
| 176 | .maps[SEC_CAM_TKIP] = CAM_TKIP, |
| 177 | .maps[SEC_CAM_AES] = CAM_AES, |
| 178 | .maps[SEC_CAM_WEP104] = CAM_WEP104, |
| 179 | |
| 180 | .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6, |
| 181 | .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5, |
| 182 | .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4, |
| 183 | .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3, |
| 184 | .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2, |
| 185 | .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1, |
| 186 | .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8, |
| 187 | .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7, |
| 188 | .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6, |
| 189 | .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5, |
| 190 | .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4, |
| 191 | .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3, |
| 192 | .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2, |
| 193 | .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1, |
| 194 | .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2, |
| 195 | .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1, |
| 196 | |
| 197 | .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW, |
| 198 | .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT, |
| 199 | .maps[RTL_IMR_BcnInt] = IMR_BCNINT, |
| 200 | .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW, |
| 201 | .maps[RTL_IMR_RDU] = IMR_RDU, |
| 202 | .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND, |
| 203 | .maps[RTL_IMR_BDOK] = IMR_BDOK, |
| 204 | .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK, |
| 205 | .maps[RTL_IMR_TBDER] = IMR_TBDER, |
| 206 | .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK, |
| 207 | .maps[RTL_IMR_TBDOK] = IMR_TBDOK, |
| 208 | .maps[RTL_IMR_BKDOK] = IMR_BKDOK, |
| 209 | .maps[RTL_IMR_BEDOK] = IMR_BEDOK, |
| 210 | .maps[RTL_IMR_VIDOK] = IMR_VIDOK, |
| 211 | .maps[RTL_IMR_VODOK] = IMR_VODOK, |
| 212 | .maps[RTL_IMR_ROK] = IMR_ROK, |
| 213 | .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNINT | IMR_TBDOK | IMR_TBDER), |
| 214 | |
| 215 | .maps[RTL_RC_CCK_RATE1M] = DESC92C_RATE1M, |
| 216 | .maps[RTL_RC_CCK_RATE2M] = DESC92C_RATE2M, |
| 217 | .maps[RTL_RC_CCK_RATE5_5M] = DESC92C_RATE5_5M, |
| 218 | .maps[RTL_RC_CCK_RATE11M] = DESC92C_RATE11M, |
| 219 | .maps[RTL_RC_OFDM_RATE6M] = DESC92C_RATE6M, |
| 220 | .maps[RTL_RC_OFDM_RATE9M] = DESC92C_RATE9M, |
| 221 | .maps[RTL_RC_OFDM_RATE12M] = DESC92C_RATE12M, |
| 222 | .maps[RTL_RC_OFDM_RATE18M] = DESC92C_RATE18M, |
| 223 | .maps[RTL_RC_OFDM_RATE24M] = DESC92C_RATE24M, |
| 224 | .maps[RTL_RC_OFDM_RATE36M] = DESC92C_RATE36M, |
| 225 | .maps[RTL_RC_OFDM_RATE48M] = DESC92C_RATE48M, |
| 226 | .maps[RTL_RC_OFDM_RATE54M] = DESC92C_RATE54M, |
| 227 | |
| 228 | .maps[RTL_RC_HT_RATEMCS7] = DESC92C_RATEMCS7, |
| 229 | .maps[RTL_RC_HT_RATEMCS15] = DESC92C_RATEMCS15, |
| 230 | }; |
| 231 | |
| 232 | static struct pci_device_id rtl92ce_pci_ids[] __devinitdata = { |
| 233 | {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8191, rtl92ce_hal_cfg)}, |
| 234 | {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8178, rtl92ce_hal_cfg)}, |
| 235 | {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8177, rtl92ce_hal_cfg)}, |
| 236 | {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8176, rtl92ce_hal_cfg)}, |
| 237 | {}, |
| 238 | }; |
| 239 | |
| 240 | MODULE_DEVICE_TABLE(pci, rtl92ce_pci_ids); |
| 241 | |
| 242 | MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>"); |
| 243 | MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>"); |
| 244 | MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>"); |
| 245 | MODULE_LICENSE("GPL"); |
| 246 | MODULE_DESCRIPTION("Realtek 8192C/8188C 802.11n PCI wireless"); |
| 247 | MODULE_FIRMWARE("rtlwifi/rtl8192cfw.bin"); |
| 248 | |
| 249 | module_param_named(swenc, rtl92ce_mod_params.sw_crypto, bool, 0444); |
| 250 | MODULE_PARM_DESC(swenc, "using hardware crypto (default 0 [hardware])\n"); |
| 251 | |
| 252 | static struct pci_driver rtl92ce_driver = { |
| 253 | .name = KBUILD_MODNAME, |
| 254 | .id_table = rtl92ce_pci_ids, |
| 255 | .probe = rtl_pci_probe, |
| 256 | .remove = rtl_pci_disconnect, |
| 257 | |
| 258 | #ifdef CONFIG_PM |
| 259 | .suspend = rtl_pci_suspend, |
| 260 | .resume = rtl_pci_resume, |
| 261 | #endif |
| 262 | |
| 263 | }; |
| 264 | |
| 265 | static int __init rtl92ce_module_init(void) |
| 266 | { |
| 267 | int ret; |
| 268 | |
| 269 | ret = pci_register_driver(&rtl92ce_driver); |
| 270 | if (ret) |
| 271 | RT_ASSERT(false, (": No device found\n")); |
| 272 | |
| 273 | return ret; |
| 274 | } |
| 275 | |
| 276 | static void __exit rtl92ce_module_exit(void) |
| 277 | { |
| 278 | pci_unregister_driver(&rtl92ce_driver); |
| 279 | } |
| 280 | |
| 281 | module_init(rtl92ce_module_init); |
| 282 | module_exit(rtl92ce_module_exit); |