blob: 881b5d6708aa5ec3c89b8da08a510c8670d81254 [file] [log] [blame]
Chris Wilson42f55512016-06-24 14:00:26 +01001/*
2 * Copyright © 2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
Chris Wilsona09d0ba2016-06-24 14:00:27 +010025#include <linux/console.h>
Chris Wilson42f55512016-06-24 14:00:26 +010026#include <linux/vgaarb.h>
27#include <linux/vga_switcheroo.h>
28
29#include "i915_drv.h"
Chris Wilson953c7f82017-02-13 17:15:12 +000030#include "i915_selftest.h"
Chris Wilson42f55512016-06-24 14:00:26 +010031
32#define GEN_DEFAULT_PIPEOFFSETS \
33 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
34 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
35 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
36 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
37 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
38
39#define GEN_CHV_PIPEOFFSETS \
40 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
41 CHV_PIPE_C_OFFSET }, \
42 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
43 CHV_TRANSCODER_C_OFFSET, }, \
44 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
45 CHV_PALETTE_C_OFFSET }
46
47#define CURSOR_OFFSETS \
48 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
49
50#define IVB_CURSOR_OFFSETS \
51 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
52
53#define BDW_COLORS \
54 .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
55#define CHV_COLORS \
56 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
57
Jani Nikulaa5ce9292016-11-30 17:43:02 +020058/* Keep in gen based order, and chronological order within a gen */
Carlos Santa0eec8dc2016-08-17 12:30:51 -070059#define GEN2_FEATURES \
60 .gen = 2, .num_pipes = 1, \
61 .has_overlay = 1, .overlay_needs_physical = 1, \
Carlos Santa804b8712016-08-17 12:30:55 -070062 .has_gmch_display = 1, \
Carlos Santa31776592016-08-17 12:30:56 -070063 .hws_needs_physical = 1, \
Chris Wilsonf4ce7662017-03-25 11:32:43 +000064 .unfenced_needs_alignment = 1, \
Carlos Santa0eec8dc2016-08-17 12:30:51 -070065 .ring_mask = RENDER_RING, \
Chris Wilson5d95c242017-09-06 11:56:53 +010066 .has_snoop = true, \
Carlos Santa0eec8dc2016-08-17 12:30:51 -070067 GEN_DEFAULT_PIPEOFFSETS, \
68 CURSOR_OFFSETS
69
Lionel Landwerlin5b54edd2017-08-30 17:12:06 +010070static const struct intel_device_info intel_i830_info __initconst = {
Carlos Santa0eec8dc2016-08-17 12:30:51 -070071 GEN2_FEATURES,
Jani Nikula2e0d26f2016-12-01 14:49:55 +020072 .platform = INTEL_I830,
Carlos Santa0eec8dc2016-08-17 12:30:51 -070073 .is_mobile = 1, .cursor_needs_physical = 1,
74 .num_pipes = 2, /* legal, last one wins */
Chris Wilson42f55512016-06-24 14:00:26 +010075};
76
Lionel Landwerlin5b54edd2017-08-30 17:12:06 +010077static const struct intel_device_info intel_i845g_info __initconst = {
Carlos Santa0eec8dc2016-08-17 12:30:51 -070078 GEN2_FEATURES,
Jani Nikula2e0d26f2016-12-01 14:49:55 +020079 .platform = INTEL_I845G,
Chris Wilson42f55512016-06-24 14:00:26 +010080};
81
Lionel Landwerlin5b54edd2017-08-30 17:12:06 +010082static const struct intel_device_info intel_i85x_info __initconst = {
Carlos Santa0eec8dc2016-08-17 12:30:51 -070083 GEN2_FEATURES,
Jani Nikula2e0d26f2016-12-01 14:49:55 +020084 .platform = INTEL_I85X, .is_mobile = 1,
Carlos Santa0eec8dc2016-08-17 12:30:51 -070085 .num_pipes = 2, /* legal, last one wins */
Chris Wilson42f55512016-06-24 14:00:26 +010086 .cursor_needs_physical = 1,
Chris Wilson42f55512016-06-24 14:00:26 +010087 .has_fbc = 1,
Chris Wilson42f55512016-06-24 14:00:26 +010088};
89
Lionel Landwerlin5b54edd2017-08-30 17:12:06 +010090static const struct intel_device_info intel_i865g_info __initconst = {
Carlos Santa0eec8dc2016-08-17 12:30:51 -070091 GEN2_FEATURES,
Jani Nikula2e0d26f2016-12-01 14:49:55 +020092 .platform = INTEL_I865G,
Chris Wilson42f55512016-06-24 14:00:26 +010093};
94
Carlos Santa54d2a6a2016-08-17 12:30:50 -070095#define GEN3_FEATURES \
96 .gen = 3, .num_pipes = 2, \
Carlos Santa804b8712016-08-17 12:30:55 -070097 .has_gmch_display = 1, \
Carlos Santa54d2a6a2016-08-17 12:30:50 -070098 .ring_mask = RENDER_RING, \
Chris Wilson5d95c242017-09-06 11:56:53 +010099 .has_snoop = true, \
Carlos Santa54d2a6a2016-08-17 12:30:50 -0700100 GEN_DEFAULT_PIPEOFFSETS, \
101 CURSOR_OFFSETS
102
Lionel Landwerlin5b54edd2017-08-30 17:12:06 +0100103static const struct intel_device_info intel_i915g_info __initconst = {
Carlos Santa54d2a6a2016-08-17 12:30:50 -0700104 GEN3_FEATURES,
Jani Nikula2e0d26f2016-12-01 14:49:55 +0200105 .platform = INTEL_I915G, .cursor_needs_physical = 1,
Chris Wilson42f55512016-06-24 14:00:26 +0100106 .has_overlay = 1, .overlay_needs_physical = 1,
Carlos Santa31776592016-08-17 12:30:56 -0700107 .hws_needs_physical = 1,
Chris Wilsonf4ce7662017-03-25 11:32:43 +0000108 .unfenced_needs_alignment = 1,
Chris Wilson42f55512016-06-24 14:00:26 +0100109};
Jani Nikulaa5ce9292016-11-30 17:43:02 +0200110
Lionel Landwerlin5b54edd2017-08-30 17:12:06 +0100111static const struct intel_device_info intel_i915gm_info __initconst = {
Carlos Santa54d2a6a2016-08-17 12:30:50 -0700112 GEN3_FEATURES,
Jani Nikula2e0d26f2016-12-01 14:49:55 +0200113 .platform = INTEL_I915GM,
Carlos Santa54d2a6a2016-08-17 12:30:50 -0700114 .is_mobile = 1,
Chris Wilson42f55512016-06-24 14:00:26 +0100115 .cursor_needs_physical = 1,
116 .has_overlay = 1, .overlay_needs_physical = 1,
117 .supports_tv = 1,
118 .has_fbc = 1,
Carlos Santa31776592016-08-17 12:30:56 -0700119 .hws_needs_physical = 1,
Chris Wilsonf4ce7662017-03-25 11:32:43 +0000120 .unfenced_needs_alignment = 1,
Chris Wilson42f55512016-06-24 14:00:26 +0100121};
Jani Nikulaa5ce9292016-11-30 17:43:02 +0200122
Lionel Landwerlin5b54edd2017-08-30 17:12:06 +0100123static const struct intel_device_info intel_i945g_info __initconst = {
Carlos Santa54d2a6a2016-08-17 12:30:50 -0700124 GEN3_FEATURES,
Jani Nikula2e0d26f2016-12-01 14:49:55 +0200125 .platform = INTEL_I945G,
Carlos Santa54d2a6a2016-08-17 12:30:50 -0700126 .has_hotplug = 1, .cursor_needs_physical = 1,
Chris Wilson42f55512016-06-24 14:00:26 +0100127 .has_overlay = 1, .overlay_needs_physical = 1,
Carlos Santa31776592016-08-17 12:30:56 -0700128 .hws_needs_physical = 1,
Chris Wilsonf4ce7662017-03-25 11:32:43 +0000129 .unfenced_needs_alignment = 1,
Chris Wilson42f55512016-06-24 14:00:26 +0100130};
Jani Nikulaa5ce9292016-11-30 17:43:02 +0200131
Lionel Landwerlin5b54edd2017-08-30 17:12:06 +0100132static const struct intel_device_info intel_i945gm_info __initconst = {
Carlos Santa54d2a6a2016-08-17 12:30:50 -0700133 GEN3_FEATURES,
Jani Nikula2e0d26f2016-12-01 14:49:55 +0200134 .platform = INTEL_I945GM, .is_mobile = 1,
Chris Wilson42f55512016-06-24 14:00:26 +0100135 .has_hotplug = 1, .cursor_needs_physical = 1,
136 .has_overlay = 1, .overlay_needs_physical = 1,
137 .supports_tv = 1,
138 .has_fbc = 1,
Carlos Santa31776592016-08-17 12:30:56 -0700139 .hws_needs_physical = 1,
Chris Wilsonf4ce7662017-03-25 11:32:43 +0000140 .unfenced_needs_alignment = 1,
Chris Wilson42f55512016-06-24 14:00:26 +0100141};
142
Lionel Landwerlin5b54edd2017-08-30 17:12:06 +0100143static const struct intel_device_info intel_g33_info __initconst = {
Jani Nikulaa5ce9292016-11-30 17:43:02 +0200144 GEN3_FEATURES,
145 .platform = INTEL_G33,
146 .has_hotplug = 1,
147 .has_overlay = 1,
148};
149
Lionel Landwerlin5b54edd2017-08-30 17:12:06 +0100150static const struct intel_device_info intel_pineview_info __initconst = {
Jani Nikulaa5ce9292016-11-30 17:43:02 +0200151 GEN3_FEATURES,
Jani Nikula73f67aa2016-12-07 22:48:09 +0200152 .platform = INTEL_PINEVIEW, .is_mobile = 1,
Jani Nikulaa5ce9292016-11-30 17:43:02 +0200153 .has_hotplug = 1,
154 .has_overlay = 1,
155};
156
Carlos Santa4d495be2016-08-17 12:30:49 -0700157#define GEN4_FEATURES \
158 .gen = 4, .num_pipes = 2, \
159 .has_hotplug = 1, \
Carlos Santa804b8712016-08-17 12:30:55 -0700160 .has_gmch_display = 1, \
Carlos Santa4d495be2016-08-17 12:30:49 -0700161 .ring_mask = RENDER_RING, \
Chris Wilson5d95c242017-09-06 11:56:53 +0100162 .has_snoop = true, \
Carlos Santa4d495be2016-08-17 12:30:49 -0700163 GEN_DEFAULT_PIPEOFFSETS, \
164 CURSOR_OFFSETS
165
Lionel Landwerlin5b54edd2017-08-30 17:12:06 +0100166static const struct intel_device_info intel_i965g_info __initconst = {
Carlos Santa4d495be2016-08-17 12:30:49 -0700167 GEN4_FEATURES,
Jani Nikulac0f86832016-12-07 12:13:04 +0200168 .platform = INTEL_I965G,
Chris Wilson42f55512016-06-24 14:00:26 +0100169 .has_overlay = 1,
Carlos Santa31776592016-08-17 12:30:56 -0700170 .hws_needs_physical = 1,
Chris Wilson42f55512016-06-24 14:00:26 +0100171};
172
Lionel Landwerlin5b54edd2017-08-30 17:12:06 +0100173static const struct intel_device_info intel_i965gm_info __initconst = {
Carlos Santa4d495be2016-08-17 12:30:49 -0700174 GEN4_FEATURES,
Jani Nikulac0f86832016-12-07 12:13:04 +0200175 .platform = INTEL_I965GM,
Carlos Santa4d495be2016-08-17 12:30:49 -0700176 .is_mobile = 1, .has_fbc = 1,
Chris Wilson42f55512016-06-24 14:00:26 +0100177 .has_overlay = 1,
178 .supports_tv = 1,
Carlos Santa31776592016-08-17 12:30:56 -0700179 .hws_needs_physical = 1,
Chris Wilson42f55512016-06-24 14:00:26 +0100180};
181
Lionel Landwerlin5b54edd2017-08-30 17:12:06 +0100182static const struct intel_device_info intel_g45_info __initconst = {
Carlos Santa4d495be2016-08-17 12:30:49 -0700183 GEN4_FEATURES,
Jani Nikulaf69c11a2016-11-30 17:43:05 +0200184 .platform = INTEL_G45,
Carlos Santa4d495be2016-08-17 12:30:49 -0700185 .has_pipe_cxsr = 1,
Chris Wilson42f55512016-06-24 14:00:26 +0100186 .ring_mask = RENDER_RING | BSD_RING,
Chris Wilson42f55512016-06-24 14:00:26 +0100187};
188
Lionel Landwerlin5b54edd2017-08-30 17:12:06 +0100189static const struct intel_device_info intel_gm45_info __initconst = {
Carlos Santa4d495be2016-08-17 12:30:49 -0700190 GEN4_FEATURES,
Jani Nikulaf69c11a2016-11-30 17:43:05 +0200191 .platform = INTEL_GM45,
Carlos Santa31776592016-08-17 12:30:56 -0700192 .is_mobile = 1, .has_fbc = 1,
Carlos Santa4d495be2016-08-17 12:30:49 -0700193 .has_pipe_cxsr = 1,
Chris Wilson42f55512016-06-24 14:00:26 +0100194 .supports_tv = 1,
195 .ring_mask = RENDER_RING | BSD_RING,
Chris Wilson42f55512016-06-24 14:00:26 +0100196};
197
Carlos Santaa1323382016-08-17 12:30:47 -0700198#define GEN5_FEATURES \
199 .gen = 5, .num_pipes = 2, \
Carlos Santa31776592016-08-17 12:30:56 -0700200 .has_hotplug = 1, \
Carlos Santab355f102016-08-17 12:30:48 -0700201 .has_gmbus_irq = 1, \
Carlos Santaa1323382016-08-17 12:30:47 -0700202 .ring_mask = RENDER_RING | BSD_RING, \
Chris Wilson5d95c242017-09-06 11:56:53 +0100203 .has_snoop = true, \
Carlos Santaa1323382016-08-17 12:30:47 -0700204 GEN_DEFAULT_PIPEOFFSETS, \
205 CURSOR_OFFSETS
206
Lionel Landwerlin5b54edd2017-08-30 17:12:06 +0100207static const struct intel_device_info intel_ironlake_d_info __initconst = {
Carlos Santaa1323382016-08-17 12:30:47 -0700208 GEN5_FEATURES,
Jani Nikula2e0d26f2016-12-01 14:49:55 +0200209 .platform = INTEL_IRONLAKE,
Chris Wilson42f55512016-06-24 14:00:26 +0100210};
211
Lionel Landwerlin5b54edd2017-08-30 17:12:06 +0100212static const struct intel_device_info intel_ironlake_m_info __initconst = {
Carlos Santaa1323382016-08-17 12:30:47 -0700213 GEN5_FEATURES,
Jani Nikula2e0d26f2016-12-01 14:49:55 +0200214 .platform = INTEL_IRONLAKE,
Ville Syrjäläc2d1a0c2017-06-06 16:32:29 +0300215 .is_mobile = 1, .has_fbc = 1,
Chris Wilson42f55512016-06-24 14:00:26 +0100216};
217
Carlos Santa07db6be2016-08-17 12:30:38 -0700218#define GEN6_FEATURES \
219 .gen = 6, .num_pipes = 2, \
Carlos Santa31776592016-08-17 12:30:56 -0700220 .has_hotplug = 1, \
Carlos Santa07db6be2016-08-17 12:30:38 -0700221 .has_fbc = 1, \
222 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
223 .has_llc = 1, \
Carlos Santa86f36242016-08-17 12:30:44 -0700224 .has_rc6 = 1, \
Carlos Santa33b5bf82016-08-17 12:30:45 -0700225 .has_rc6p = 1, \
Carlos Santab355f102016-08-17 12:30:48 -0700226 .has_gmbus_irq = 1, \
Michel Thierry9e1d0e62016-12-05 17:57:03 -0800227 .has_aliasing_ppgtt = 1, \
Carlos Santa07db6be2016-08-17 12:30:38 -0700228 GEN_DEFAULT_PIPEOFFSETS, \
229 CURSOR_OFFSETS
230
Lionel Landwerlin08905402017-08-30 17:12:05 +0100231#define SNB_D_PLATFORM \
232 GEN6_FEATURES, \
233 .platform = INTEL_SANDYBRIDGE
234
Lionel Landwerlin5b54edd2017-08-30 17:12:06 +0100235static const struct intel_device_info intel_sandybridge_d_gt1_info __initconst = {
Lionel Landwerlin08905402017-08-30 17:12:05 +0100236 SNB_D_PLATFORM,
237 .gt = 1,
Chris Wilson42f55512016-06-24 14:00:26 +0100238};
239
Lionel Landwerlin5b54edd2017-08-30 17:12:06 +0100240static const struct intel_device_info intel_sandybridge_d_gt2_info __initconst = {
Lionel Landwerlin08905402017-08-30 17:12:05 +0100241 SNB_D_PLATFORM,
242 .gt = 2,
243};
244
245#define SNB_M_PLATFORM \
246 GEN6_FEATURES, \
247 .platform = INTEL_SANDYBRIDGE, \
248 .is_mobile = 1
249
250
Lionel Landwerlin5b54edd2017-08-30 17:12:06 +0100251static const struct intel_device_info intel_sandybridge_m_gt1_info __initconst = {
Lionel Landwerlin08905402017-08-30 17:12:05 +0100252 SNB_M_PLATFORM,
253 .gt = 1,
254};
255
Lionel Landwerlin5b54edd2017-08-30 17:12:06 +0100256static const struct intel_device_info intel_sandybridge_m_gt2_info __initconst = {
Lionel Landwerlin08905402017-08-30 17:12:05 +0100257 SNB_M_PLATFORM,
258 .gt = 2,
Chris Wilson42f55512016-06-24 14:00:26 +0100259};
260
261#define GEN7_FEATURES \
262 .gen = 7, .num_pipes = 3, \
Carlos Santa31776592016-08-17 12:30:56 -0700263 .has_hotplug = 1, \
Chris Wilson42f55512016-06-24 14:00:26 +0100264 .has_fbc = 1, \
265 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
266 .has_llc = 1, \
Carlos Santa86f36242016-08-17 12:30:44 -0700267 .has_rc6 = 1, \
Carlos Santa33b5bf82016-08-17 12:30:45 -0700268 .has_rc6p = 1, \
Carlos Santab355f102016-08-17 12:30:48 -0700269 .has_gmbus_irq = 1, \
Michel Thierry9e1d0e62016-12-05 17:57:03 -0800270 .has_aliasing_ppgtt = 1, \
271 .has_full_ppgtt = 1, \
Chris Wilson42f55512016-06-24 14:00:26 +0100272 GEN_DEFAULT_PIPEOFFSETS, \
273 IVB_CURSOR_OFFSETS
274
Lionel Landwerlin08905402017-08-30 17:12:05 +0100275#define IVB_D_PLATFORM \
276 GEN7_FEATURES, \
277 .platform = INTEL_IVYBRIDGE, \
278 .has_l3_dpf = 1
279
Lionel Landwerlin5b54edd2017-08-30 17:12:06 +0100280static const struct intel_device_info intel_ivybridge_d_gt1_info __initconst = {
Lionel Landwerlin08905402017-08-30 17:12:05 +0100281 IVB_D_PLATFORM,
282 .gt = 1,
Chris Wilson42f55512016-06-24 14:00:26 +0100283};
284
Lionel Landwerlin5b54edd2017-08-30 17:12:06 +0100285static const struct intel_device_info intel_ivybridge_d_gt2_info __initconst = {
Lionel Landwerlin08905402017-08-30 17:12:05 +0100286 IVB_D_PLATFORM,
287 .gt = 2,
288};
289
290#define IVB_M_PLATFORM \
291 GEN7_FEATURES, \
292 .platform = INTEL_IVYBRIDGE, \
293 .is_mobile = 1, \
294 .has_l3_dpf = 1
295
Lionel Landwerlin5b54edd2017-08-30 17:12:06 +0100296static const struct intel_device_info intel_ivybridge_m_gt1_info __initconst = {
Lionel Landwerlin08905402017-08-30 17:12:05 +0100297 IVB_M_PLATFORM,
298 .gt = 1,
299};
300
Lionel Landwerlin5b54edd2017-08-30 17:12:06 +0100301static const struct intel_device_info intel_ivybridge_m_gt2_info __initconst = {
Lionel Landwerlin08905402017-08-30 17:12:05 +0100302 IVB_M_PLATFORM,
303 .gt = 2,
Chris Wilson42f55512016-06-24 14:00:26 +0100304};
305
Lionel Landwerlin5b54edd2017-08-30 17:12:06 +0100306static const struct intel_device_info intel_ivybridge_q_info __initconst = {
Chris Wilson42f55512016-06-24 14:00:26 +0100307 GEN7_FEATURES,
Jani Nikula2e0d26f2016-12-01 14:49:55 +0200308 .platform = INTEL_IVYBRIDGE,
Lionel Landwerlin08905402017-08-30 17:12:05 +0100309 .gt = 2,
Chris Wilson42f55512016-06-24 14:00:26 +0100310 .num_pipes = 0, /* legal, last one wins */
Carlos Santaca9c4522016-08-17 12:30:54 -0700311 .has_l3_dpf = 1,
Chris Wilson42f55512016-06-24 14:00:26 +0100312};
313
Lionel Landwerlin5b54edd2017-08-30 17:12:06 +0100314static const struct intel_device_info intel_valleyview_info __initconst = {
Jani Nikula2e0d26f2016-12-01 14:49:55 +0200315 .platform = INTEL_VALLEYVIEW,
Rodrigo Vivieb6f7712016-12-19 13:55:08 -0800316 .gen = 7,
317 .is_lp = 1,
318 .num_pipes = 2,
319 .has_psr = 1,
320 .has_runtime_pm = 1,
321 .has_rc6 = 1,
322 .has_gmbus_irq = 1,
Rodrigo Vivieb6f7712016-12-19 13:55:08 -0800323 .has_gmch_display = 1,
324 .has_hotplug = 1,
325 .has_aliasing_ppgtt = 1,
326 .has_full_ppgtt = 1,
Chris Wilson5d95c242017-09-06 11:56:53 +0100327 .has_snoop = true,
Rodrigo Vivieb6f7712016-12-19 13:55:08 -0800328 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
329 .display_mmio_offset = VLV_DISPLAY_BASE,
330 GEN_DEFAULT_PIPEOFFSETS,
331 CURSOR_OFFSETS
Chris Wilson42f55512016-06-24 14:00:26 +0100332};
333
334#define HSW_FEATURES \
335 GEN7_FEATURES, \
336 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
337 .has_ddi = 1, \
Carlos Santa6e3b84d2016-08-17 12:30:36 -0700338 .has_fpga_dbg = 1, \
Carlos Santa4aa4c232016-08-17 12:30:39 -0700339 .has_psr = 1, \
Carlos Santa53233f02016-08-17 12:30:43 -0700340 .has_resource_streamer = 1, \
Carlos Santa1d3fe532016-08-17 12:30:46 -0700341 .has_dp_mst = 1, \
Carlos Santa33b5bf82016-08-17 12:30:45 -0700342 .has_rc6p = 0 /* RC6p removed-by HSW */, \
Carlos Santa4aa4c232016-08-17 12:30:39 -0700343 .has_runtime_pm = 1
Chris Wilson42f55512016-06-24 14:00:26 +0100344
Lionel Landwerlin08905402017-08-30 17:12:05 +0100345#define HSW_PLATFORM \
346 HSW_FEATURES, \
347 .platform = INTEL_HASWELL, \
348 .has_l3_dpf = 1
349
Lionel Landwerlin5b54edd2017-08-30 17:12:06 +0100350static const struct intel_device_info intel_haswell_gt1_info __initconst = {
Lionel Landwerlin08905402017-08-30 17:12:05 +0100351 HSW_PLATFORM,
352 .gt = 1,
353};
354
Lionel Landwerlin5b54edd2017-08-30 17:12:06 +0100355static const struct intel_device_info intel_haswell_gt2_info __initconst = {
Lionel Landwerlin08905402017-08-30 17:12:05 +0100356 HSW_PLATFORM,
357 .gt = 2,
358};
359
Lionel Landwerlin5b54edd2017-08-30 17:12:06 +0100360static const struct intel_device_info intel_haswell_gt3_info __initconst = {
Lionel Landwerlin08905402017-08-30 17:12:05 +0100361 HSW_PLATFORM,
362 .gt = 3,
Chris Wilson42f55512016-06-24 14:00:26 +0100363};
364
Chris Wilson42f55512016-06-24 14:00:26 +0100365#define BDW_FEATURES \
366 HSW_FEATURES, \
Carlos Santa4586f1d2016-08-17 12:30:53 -0700367 BDW_COLORS, \
Joonas Lahtinendfc51482016-11-03 10:39:46 +0200368 .has_logical_ring_contexts = 1, \
Michel Thierry9e1d0e62016-12-05 17:57:03 -0800369 .has_full_48bit_ppgtt = 1, \
Michel Thierry142bc7d2017-06-20 10:57:46 +0100370 .has_64bit_reloc = 1, \
371 .has_reset_engine = 1
Chris Wilson42f55512016-06-24 14:00:26 +0100372
Rodrigo Vivi94829de2017-06-06 09:06:06 -0700373#define BDW_PLATFORM \
374 BDW_FEATURES, \
375 .gen = 8, \
376 .platform = INTEL_BROADWELL
377
Lionel Landwerlin5b54edd2017-08-30 17:12:06 +0100378static const struct intel_device_info intel_broadwell_gt1_info __initconst = {
Rodrigo Vivi94829de2017-06-06 09:06:06 -0700379 BDW_PLATFORM,
Lionel Landwerlin08905402017-08-30 17:12:05 +0100380 .gt = 1,
381};
382
Lionel Landwerlin5b54edd2017-08-30 17:12:06 +0100383static const struct intel_device_info intel_broadwell_gt2_info __initconst = {
Lionel Landwerlin08905402017-08-30 17:12:05 +0100384 BDW_PLATFORM,
385 .gt = 2,
386};
387
Lionel Landwerlin5b54edd2017-08-30 17:12:06 +0100388static const struct intel_device_info intel_broadwell_rsvd_info __initconst = {
Lionel Landwerlin08905402017-08-30 17:12:05 +0100389 BDW_PLATFORM,
390 .gt = 3,
391 /* According to the device ID those devices are GT3, they were
392 * previously treated as not GT3, keep it like that.
393 */
Chris Wilson42f55512016-06-24 14:00:26 +0100394};
395
Lionel Landwerlin5b54edd2017-08-30 17:12:06 +0100396static const struct intel_device_info intel_broadwell_gt3_info __initconst = {
Rodrigo Vivi94829de2017-06-06 09:06:06 -0700397 BDW_PLATFORM,
Lionel Landwerlin08905402017-08-30 17:12:05 +0100398 .gt = 3,
Chris Wilson42f55512016-06-24 14:00:26 +0100399 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
400};
401
Lionel Landwerlin5b54edd2017-08-30 17:12:06 +0100402static const struct intel_device_info intel_cherryview_info __initconst = {
Chris Wilson42f55512016-06-24 14:00:26 +0100403 .gen = 8, .num_pipes = 3,
Carlos Santa31776592016-08-17 12:30:56 -0700404 .has_hotplug = 1,
Rodrigo Vivi8727dc02016-12-18 13:36:26 -0800405 .is_lp = 1,
Chris Wilson42f55512016-06-24 14:00:26 +0100406 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
Jani Nikula2e0d26f2016-12-01 14:49:55 +0200407 .platform = INTEL_CHERRYVIEW,
Joonas Lahtinendfc51482016-11-03 10:39:46 +0200408 .has_64bit_reloc = 1,
Carlos Santa6e3b84d2016-08-17 12:30:36 -0700409 .has_psr = 1,
Carlos Santa4aa4c232016-08-17 12:30:39 -0700410 .has_runtime_pm = 1,
Carlos Santa53233f02016-08-17 12:30:43 -0700411 .has_resource_streamer = 1,
Carlos Santa86f36242016-08-17 12:30:44 -0700412 .has_rc6 = 1,
Carlos Santab355f102016-08-17 12:30:48 -0700413 .has_gmbus_irq = 1,
Carlos Santa4586f1d2016-08-17 12:30:53 -0700414 .has_logical_ring_contexts = 1,
Carlos Santa804b8712016-08-17 12:30:55 -0700415 .has_gmch_display = 1,
Michel Thierry9e1d0e62016-12-05 17:57:03 -0800416 .has_aliasing_ppgtt = 1,
417 .has_full_ppgtt = 1,
Michel Thierry142bc7d2017-06-20 10:57:46 +0100418 .has_reset_engine = 1,
Chris Wilson5d95c242017-09-06 11:56:53 +0100419 .has_snoop = true,
Chris Wilson42f55512016-06-24 14:00:26 +0100420 .display_mmio_offset = VLV_DISPLAY_BASE,
421 GEN_CHV_PIPEOFFSETS,
422 CURSOR_OFFSETS,
423 CHV_COLORS,
424};
425
Rodrigo Vivi94829de2017-06-06 09:06:06 -0700426#define SKL_PLATFORM \
427 BDW_FEATURES, \
428 .gen = 9, \
429 .platform = INTEL_SKYLAKE, \
430 .has_csr = 1, \
431 .has_guc = 1, \
432 .ddb_size = 896
433
Lionel Landwerlin5b54edd2017-08-30 17:12:06 +0100434static const struct intel_device_info intel_skylake_gt1_info __initconst = {
Rodrigo Vivi94829de2017-06-06 09:06:06 -0700435 SKL_PLATFORM,
Lionel Landwerlin08905402017-08-30 17:12:05 +0100436 .gt = 1,
Chris Wilson42f55512016-06-24 14:00:26 +0100437};
438
Lionel Landwerlin5b54edd2017-08-30 17:12:06 +0100439static const struct intel_device_info intel_skylake_gt2_info __initconst = {
Rodrigo Vivi94829de2017-06-06 09:06:06 -0700440 SKL_PLATFORM,
Lionel Landwerlin08905402017-08-30 17:12:05 +0100441 .gt = 2,
442};
443
444#define SKL_GT3_PLUS_PLATFORM \
445 SKL_PLATFORM, \
446 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING
447
448
Lionel Landwerlin5b54edd2017-08-30 17:12:06 +0100449static const struct intel_device_info intel_skylake_gt3_info __initconst = {
Lionel Landwerlin08905402017-08-30 17:12:05 +0100450 SKL_GT3_PLUS_PLATFORM,
451 .gt = 3,
452};
453
Lionel Landwerlin5b54edd2017-08-30 17:12:06 +0100454static const struct intel_device_info intel_skylake_gt4_info __initconst = {
Lionel Landwerlin08905402017-08-30 17:12:05 +0100455 SKL_GT3_PLUS_PLATFORM,
456 .gt = 4,
Chris Wilson42f55512016-06-24 14:00:26 +0100457};
458
Rodrigo Vivi80fa66b2016-12-01 11:33:16 +0200459#define GEN9_LP_FEATURES \
460 .gen = 9, \
Ander Conselvan de Oliveira3e4274f2016-11-10 17:23:09 +0200461 .is_lp = 1, \
Rodrigo Vivi80fa66b2016-12-01 11:33:16 +0200462 .has_hotplug = 1, \
463 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
464 .num_pipes = 3, \
465 .has_64bit_reloc = 1, \
466 .has_ddi = 1, \
467 .has_fpga_dbg = 1, \
468 .has_fbc = 1, \
469 .has_runtime_pm = 1, \
470 .has_pooled_eu = 0, \
471 .has_csr = 1, \
472 .has_resource_streamer = 1, \
473 .has_rc6 = 1, \
474 .has_dp_mst = 1, \
475 .has_gmbus_irq = 1, \
Rodrigo Vivi80fa66b2016-12-01 11:33:16 +0200476 .has_logical_ring_contexts = 1, \
477 .has_guc = 1, \
Michel Thierry9e1d0e62016-12-05 17:57:03 -0800478 .has_aliasing_ppgtt = 1, \
479 .has_full_ppgtt = 1, \
480 .has_full_48bit_ppgtt = 1, \
Michel Thierry142bc7d2017-06-20 10:57:46 +0100481 .has_reset_engine = 1, \
Chris Wilson5d95c242017-09-06 11:56:53 +0100482 .has_snoop = true, \
Rodrigo Vivi80fa66b2016-12-01 11:33:16 +0200483 GEN_DEFAULT_PIPEOFFSETS, \
484 IVB_CURSOR_OFFSETS, \
485 BDW_COLORS
486
Lionel Landwerlin5b54edd2017-08-30 17:12:06 +0100487static const struct intel_device_info intel_broxton_info __initconst = {
Rodrigo Vivi80fa66b2016-12-01 11:33:16 +0200488 GEN9_LP_FEATURES,
Jani Nikula2e0d26f2016-12-01 14:49:55 +0200489 .platform = INTEL_BROXTON,
Deepak M6f3fff62016-09-15 15:01:10 +0530490 .ddb_size = 512,
Chris Wilson42f55512016-06-24 14:00:26 +0100491};
492
Lionel Landwerlin5b54edd2017-08-30 17:12:06 +0100493static const struct intel_device_info intel_geminilake_info __initconst = {
Ander Conselvan de Oliveirac22097f2016-11-14 16:25:26 +0200494 GEN9_LP_FEATURES,
Jani Nikula2e0d26f2016-12-01 14:49:55 +0200495 .platform = INTEL_GEMINILAKE,
Ander Conselvan de Oliveirac22097f2016-11-14 16:25:26 +0200496 .ddb_size = 1024,
Ander Conselvan de Oliveira9751baf2017-01-27 11:02:30 +0200497 .color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 }
Ander Conselvan de Oliveirac22097f2016-11-14 16:25:26 +0200498};
499
Rodrigo Vivi94829de2017-06-06 09:06:06 -0700500#define KBL_PLATFORM \
501 BDW_FEATURES, \
502 .gen = 9, \
503 .platform = INTEL_KABYLAKE, \
504 .has_csr = 1, \
505 .has_guc = 1, \
506 .ddb_size = 896
507
Lionel Landwerlin5b54edd2017-08-30 17:12:06 +0100508static const struct intel_device_info intel_kabylake_gt1_info __initconst = {
Rodrigo Vivi94829de2017-06-06 09:06:06 -0700509 KBL_PLATFORM,
Lionel Landwerlin08905402017-08-30 17:12:05 +0100510 .gt = 1,
511};
512
Lionel Landwerlin5b54edd2017-08-30 17:12:06 +0100513static const struct intel_device_info intel_kabylake_gt2_info __initconst = {
Lionel Landwerlin08905402017-08-30 17:12:05 +0100514 KBL_PLATFORM,
515 .gt = 2,
Chris Wilson42f55512016-06-24 14:00:26 +0100516};
517
Lionel Landwerlin5b54edd2017-08-30 17:12:06 +0100518static const struct intel_device_info intel_kabylake_gt3_info __initconst = {
Rodrigo Vivi94829de2017-06-06 09:06:06 -0700519 KBL_PLATFORM,
Lionel Landwerlin08905402017-08-30 17:12:05 +0100520 .gt = 3,
Chris Wilson42f55512016-06-24 14:00:26 +0100521 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
522};
523
Rodrigo Vivi71851fa2017-06-08 08:49:58 -0700524#define CFL_PLATFORM \
525 .is_alpha_support = 1, \
526 BDW_FEATURES, \
527 .gen = 9, \
528 .platform = INTEL_COFFEELAKE, \
Rodrigo Vivi84cd8432017-06-09 13:02:30 -0700529 .has_csr = 1, \
Anusha Srivatsac0f82962017-06-08 16:48:23 -0700530 .has_guc = 1, \
Rodrigo Vivi71851fa2017-06-08 08:49:58 -0700531 .ddb_size = 896
532
Lionel Landwerlin5b54edd2017-08-30 17:12:06 +0100533static const struct intel_device_info intel_coffeelake_gt1_info __initconst = {
Rodrigo Vivi71851fa2017-06-08 08:49:58 -0700534 CFL_PLATFORM,
Lionel Landwerlin08905402017-08-30 17:12:05 +0100535 .gt = 1,
536};
537
Lionel Landwerlin5b54edd2017-08-30 17:12:06 +0100538static const struct intel_device_info intel_coffeelake_gt2_info __initconst = {
Lionel Landwerlin08905402017-08-30 17:12:05 +0100539 CFL_PLATFORM,
540 .gt = 2,
Rodrigo Vivi71851fa2017-06-08 08:49:58 -0700541};
542
Lionel Landwerlin5b54edd2017-08-30 17:12:06 +0100543static const struct intel_device_info intel_coffeelake_gt3_info __initconst = {
Rodrigo Vivi71851fa2017-06-08 08:49:58 -0700544 CFL_PLATFORM,
Lionel Landwerlin08905402017-08-30 17:12:05 +0100545 .gt = 3,
Rodrigo Vivi71851fa2017-06-08 08:49:58 -0700546 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
547};
548
Lionel Landwerlin5b54edd2017-08-30 17:12:06 +0100549static const struct intel_device_info intel_cannonlake_gt2_info __initconst = {
Rodrigo Vivi413f3c12017-06-06 13:30:30 -0700550 BDW_FEATURES,
551 .is_alpha_support = 1,
552 .platform = INTEL_CANNONLAKE,
553 .gen = 10,
Lionel Landwerlin08905402017-08-30 17:12:05 +0100554 .gt = 2,
Rodrigo Vivi413f3c12017-06-06 13:30:30 -0700555 .ddb_size = 1024,
Anusha Srivatsacebfcea2017-06-09 15:26:10 -0700556 .has_csr = 1,
Rodrigo Vivi6602be02017-07-06 14:01:13 -0700557 .color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 }
Rodrigo Vivi413f3c12017-06-06 13:30:30 -0700558};
559
Chris Wilson42f55512016-06-24 14:00:26 +0100560/*
561 * Make sure any device matches here are from most specific to most
562 * general. For example, since the Quanta match is based on the subsystem
563 * and subvendor IDs, we need it to come before the more general IVB
564 * PCI ID matches, otherwise we'll use the wrong info struct above.
565 */
566static const struct pci_device_id pciidlist[] = {
567 INTEL_I830_IDS(&intel_i830_info),
Jani Nikula2a307c22016-11-30 17:43:04 +0200568 INTEL_I845G_IDS(&intel_i845g_info),
Chris Wilson42f55512016-06-24 14:00:26 +0100569 INTEL_I85X_IDS(&intel_i85x_info),
570 INTEL_I865G_IDS(&intel_i865g_info),
571 INTEL_I915G_IDS(&intel_i915g_info),
572 INTEL_I915GM_IDS(&intel_i915gm_info),
573 INTEL_I945G_IDS(&intel_i945g_info),
574 INTEL_I945GM_IDS(&intel_i945gm_info),
575 INTEL_I965G_IDS(&intel_i965g_info),
576 INTEL_G33_IDS(&intel_g33_info),
577 INTEL_I965GM_IDS(&intel_i965gm_info),
578 INTEL_GM45_IDS(&intel_gm45_info),
579 INTEL_G45_IDS(&intel_g45_info),
580 INTEL_PINEVIEW_IDS(&intel_pineview_info),
581 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
582 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
Lionel Landwerlin08905402017-08-30 17:12:05 +0100583 INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info),
584 INTEL_SNB_D_GT2_IDS(&intel_sandybridge_d_gt2_info),
585 INTEL_SNB_M_GT1_IDS(&intel_sandybridge_m_gt1_info),
586 INTEL_SNB_M_GT2_IDS(&intel_sandybridge_m_gt2_info),
Chris Wilson42f55512016-06-24 14:00:26 +0100587 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
Lionel Landwerlin08905402017-08-30 17:12:05 +0100588 INTEL_IVB_M_GT1_IDS(&intel_ivybridge_m_gt1_info),
589 INTEL_IVB_M_GT2_IDS(&intel_ivybridge_m_gt2_info),
590 INTEL_IVB_D_GT1_IDS(&intel_ivybridge_d_gt1_info),
591 INTEL_IVB_D_GT2_IDS(&intel_ivybridge_d_gt2_info),
592 INTEL_HSW_GT1_IDS(&intel_haswell_gt1_info),
593 INTEL_HSW_GT2_IDS(&intel_haswell_gt2_info),
594 INTEL_HSW_GT3_IDS(&intel_haswell_gt3_info),
Carlos Santa8d9c20e2016-08-17 12:30:37 -0700595 INTEL_VLV_IDS(&intel_valleyview_info),
Lionel Landwerlin08905402017-08-30 17:12:05 +0100596 INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info),
597 INTEL_BDW_GT2_IDS(&intel_broadwell_gt2_info),
Carlos Santa8d9c20e2016-08-17 12:30:37 -0700598 INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
Lionel Landwerlin08905402017-08-30 17:12:05 +0100599 INTEL_BDW_RSVD_IDS(&intel_broadwell_rsvd_info),
Chris Wilson42f55512016-06-24 14:00:26 +0100600 INTEL_CHV_IDS(&intel_cherryview_info),
Lionel Landwerlin08905402017-08-30 17:12:05 +0100601 INTEL_SKL_GT1_IDS(&intel_skylake_gt1_info),
602 INTEL_SKL_GT2_IDS(&intel_skylake_gt2_info),
Chris Wilson42f55512016-06-24 14:00:26 +0100603 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
Lionel Landwerlin08905402017-08-30 17:12:05 +0100604 INTEL_SKL_GT4_IDS(&intel_skylake_gt4_info),
Chris Wilson42f55512016-06-24 14:00:26 +0100605 INTEL_BXT_IDS(&intel_broxton_info),
Ander Conselvan de Oliveira8363e3c2016-11-10 17:23:08 +0200606 INTEL_GLK_IDS(&intel_geminilake_info),
Lionel Landwerlin08905402017-08-30 17:12:05 +0100607 INTEL_KBL_GT1_IDS(&intel_kabylake_gt1_info),
608 INTEL_KBL_GT2_IDS(&intel_kabylake_gt2_info),
Chris Wilson42f55512016-06-24 14:00:26 +0100609 INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
610 INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
Lionel Landwerlin08905402017-08-30 17:12:05 +0100611 INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info),
612 INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info),
613 INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info),
614 INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),
615 INTEL_CNL_U_GT2_IDS(&intel_cannonlake_gt2_info),
616 INTEL_CNL_Y_GT2_IDS(&intel_cannonlake_gt2_info),
Chris Wilson42f55512016-06-24 14:00:26 +0100617 {0, 0, 0}
618};
619MODULE_DEVICE_TABLE(pci, pciidlist);
620
Chris Wilson953c7f82017-02-13 17:15:12 +0000621static void i915_pci_remove(struct pci_dev *pdev)
622{
623 struct drm_device *dev = pci_get_drvdata(pdev);
624
625 i915_driver_unload(dev);
626 drm_dev_unref(dev);
627}
628
Chris Wilson42f55512016-06-24 14:00:26 +0100629static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
630{
631 struct intel_device_info *intel_info =
632 (struct intel_device_info *) ent->driver_data;
Chris Wilson953c7f82017-02-13 17:15:12 +0000633 int err;
Chris Wilson42f55512016-06-24 14:00:26 +0100634
Jani Nikulac007fb42016-10-31 12:18:28 +0200635 if (IS_ALPHA_SUPPORT(intel_info) && !i915.alpha_support) {
636 DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n"
637 "See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n"
638 "to enable support in this kernel version, or check for kernel updates.\n");
Chris Wilson42f55512016-06-24 14:00:26 +0100639 return -ENODEV;
640 }
641
642 /* Only bind to function 0 of the device. Early generations
643 * used function 1 as a placeholder for multi-head. This causes
644 * us confusion instead, especially on the systems where both
645 * functions have the same PCI-ID!
646 */
647 if (PCI_FUNC(pdev->devfn))
648 return -ENODEV;
649
650 /*
651 * apple-gmux is needed on dual GPU MacBook Pro
652 * to probe the panel if we're the inactive GPU.
653 */
654 if (vga_switcheroo_client_probe_defer(pdev))
655 return -EPROBE_DEFER;
656
Chris Wilson953c7f82017-02-13 17:15:12 +0000657 err = i915_driver_load(pdev, ent);
658 if (err)
659 return err;
Chris Wilson42f55512016-06-24 14:00:26 +0100660
Chris Wilson953c7f82017-02-13 17:15:12 +0000661 err = i915_live_selftests(pdev);
662 if (err) {
663 i915_pci_remove(pdev);
664 return err > 0 ? -ENOTTY : err;
665 }
Chris Wilson42f55512016-06-24 14:00:26 +0100666
Chris Wilson953c7f82017-02-13 17:15:12 +0000667 return 0;
Chris Wilson42f55512016-06-24 14:00:26 +0100668}
669
Chris Wilsona09d0ba2016-06-24 14:00:27 +0100670static struct pci_driver i915_pci_driver = {
Chris Wilson42f55512016-06-24 14:00:26 +0100671 .name = DRIVER_NAME,
672 .id_table = pciidlist,
673 .probe = i915_pci_probe,
674 .remove = i915_pci_remove,
675 .driver.pm = &i915_pm_ops,
676};
Chris Wilsona09d0ba2016-06-24 14:00:27 +0100677
678static int __init i915_init(void)
679{
680 bool use_kms = true;
Chris Wilson953c7f82017-02-13 17:15:12 +0000681 int err;
682
683 err = i915_mock_selftests();
684 if (err)
685 return err > 0 ? 0 : err;
Chris Wilsona09d0ba2016-06-24 14:00:27 +0100686
687 /*
688 * Enable KMS by default, unless explicitly overriden by
689 * either the i915.modeset prarameter or by the
690 * vga_text_mode_force boot option.
691 */
692
693 if (i915.modeset == 0)
694 use_kms = false;
695
696 if (vgacon_text_force() && i915.modeset == -1)
697 use_kms = false;
698
699 if (!use_kms) {
700 /* Silently fail loading to not upset userspace. */
701 DRM_DEBUG_DRIVER("KMS disabled.\n");
702 return 0;
703 }
704
705 return pci_register_driver(&i915_pci_driver);
706}
707
708static void __exit i915_exit(void)
709{
710 if (!i915_pci_driver.driver.owner)
711 return;
712
713 pci_unregister_driver(&i915_pci_driver);
714}
715
716module_init(i915_init);
717module_exit(i915_exit);
718
719MODULE_AUTHOR("Tungsten Graphics, Inc.");
720MODULE_AUTHOR("Intel Corporation");
721
722MODULE_DESCRIPTION(DRIVER_DESC);
723MODULE_LICENSE("GPL and additional rights");