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Hong Xucce783c2012-04-17 14:26:29 +08001/*
2 * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC
3 *
4 * Copyright (C) 2012 Atmel,
5 * 2012 Hong Xu <hong.xu@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9
Jean-Christophe PLAGNIOL-VILLARD6db64d22013-05-15 01:21:50 +080010#include "skeleton.dtsi"
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +080011#include <dt-bindings/pinctrl/at91.h>
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +080012#include <dt-bindings/interrupt-controller/irq.h>
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +080013#include <dt-bindings/gpio/gpio.h>
Hong Xucce783c2012-04-17 14:26:29 +080014
15/ {
16 model = "Atmel AT91SAM9N12 SoC";
17 compatible = "atmel,at91sam9n12";
18 interrupt-parent = <&aic>;
19
20 aliases {
21 serial0 = &dbgu;
22 serial1 = &usart0;
23 serial2 = &usart1;
24 serial3 = &usart2;
25 serial4 = &usart3;
26 gpio0 = &pioA;
27 gpio1 = &pioB;
28 gpio2 = &pioC;
29 gpio3 = &pioD;
30 tcb0 = &tcb0;
31 tcb1 = &tcb1;
Ludovic Desroches05dcd362012-09-12 08:42:16 +020032 i2c0 = &i2c0;
33 i2c1 = &i2c1;
Bo Shen544ae6b2013-01-11 15:08:30 +010034 ssc0 = &ssc0;
Hong Xucce783c2012-04-17 14:26:29 +080035 };
36 cpus {
37 cpu@0 {
38 compatible = "arm,arm926ejs";
39 };
40 };
41
42 memory {
43 reg = <0x20000000 0x10000000>;
44 };
45
46 ahb {
47 compatible = "simple-bus";
48 #address-cells = <1>;
49 #size-cells = <1>;
50 ranges;
51
52 apb {
53 compatible = "simple-bus";
54 #address-cells = <1>;
55 #size-cells = <1>;
56 ranges;
57
58 aic: interrupt-controller@fffff000 {
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +020059 #interrupt-cells = <3>;
Hong Xucce783c2012-04-17 14:26:29 +080060 compatible = "atmel,at91rm9200-aic";
61 interrupt-controller;
62 reg = <0xfffff000 0x200>;
63 };
64
65 ramc0: ramc@ffffe800 {
66 compatible = "atmel,at91sam9g45-ddramc";
67 reg = <0xffffe800 0x200>;
68 };
69
70 pmc: pmc@fffffc00 {
71 compatible = "atmel,at91rm9200-pmc";
72 reg = <0xfffffc00 0x100>;
73 };
74
75 rstc@fffffe00 {
76 compatible = "atmel,at91sam9g45-rstc";
77 reg = <0xfffffe00 0x10>;
78 };
79
80 pit: timer@fffffe30 {
81 compatible = "atmel,at91sam9260-pit";
82 reg = <0xfffffe30 0xf>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +080083 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
Hong Xucce783c2012-04-17 14:26:29 +080084 };
85
86 shdwc@fffffe10 {
87 compatible = "atmel,at91sam9x5-shdwc";
88 reg = <0xfffffe10 0x10>;
89 };
90
Ludovic Desroches98731372012-11-19 12:23:36 +010091 mmc0: mmc@f0008000 {
92 compatible = "atmel,hsmci";
93 reg = <0xf0008000 0x600>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +080094 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
Ludovic Desroches05c1bc92013-04-16 15:03:10 +020095 dmas = <&dma 1 0>;
96 dma-names = "rxtx";
Ludovic Desroches98731372012-11-19 12:23:36 +010097 #address-cells = <1>;
98 #size-cells = <0>;
99 status = "disabled";
100 };
101
Hong Xucce783c2012-04-17 14:26:29 +0800102 tcb0: timer@f8008000 {
103 compatible = "atmel,at91sam9x5-tcb";
104 reg = <0xf8008000 0x100>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800105 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
Hong Xucce783c2012-04-17 14:26:29 +0800106 };
107
108 tcb1: timer@f800c000 {
109 compatible = "atmel,at91sam9x5-tcb";
110 reg = <0xf800c000 0x100>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800111 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
Hong Xucce783c2012-04-17 14:26:29 +0800112 };
113
114 dma: dma-controller@ffffec00 {
115 compatible = "atmel,at91sam9g45-dma";
116 reg = <0xffffec00 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800117 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
Ludovic Desroches980ce7d2013-04-16 15:03:06 +0200118 #dma-cells = <2>;
Hong Xucce783c2012-04-17 14:26:29 +0800119 };
120
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800121 pinctrl@fffff400 {
122 #address-cells = <1>;
123 #size-cells = <1>;
Jean-Christophe PLAGNIOL-VILLARD5314ec82012-07-05 16:56:09 +0800124 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800125 ranges = <0xfffff400 0xfffff400 0x800>;
Hong Xucce783c2012-04-17 14:26:29 +0800126
Jean-Christophe PLAGNIOL-VILLARD5314ec82012-07-05 16:56:09 +0800127 atmel,mux-mask = <
128 /* A B C */
129 0xffffffff 0xffe07983 0x00000000 /* pioA */
130 0x00040000 0x00047e0f 0x00000000 /* pioB */
131 0xfdffffff 0x07c00000 0xb83fffff /* pioC */
132 0x003fffff 0x003f8000 0x00000000 /* pioD */
133 >;
134
135 /* shared pinctrl settings */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800136 dbgu {
137 pinctrl_dbgu: dbgu-0 {
138 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800139 <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */
140 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA10 periph with pullup */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800141 };
142 };
143
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800144 usart0 {
145 pinctrl_usart0: usart0-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800146 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800147 <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */
148 AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA0 periph A */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800149 };
150
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800151 pinctrl_usart0_rts: usart0_rts-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800152 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800153 <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A */
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800154 };
155
156 pinctrl_usart0_cts: usart0_cts-0 {
157 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800158 <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA3 periph A */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800159 };
160 };
161
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800162 usart1 {
163 pinctrl_usart1: usart1-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800164 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800165 <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA6 periph A with pullup */
166 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA5 periph A */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800167 };
168 };
169
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800170 usart2 {
171 pinctrl_usart2: usart2-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800172 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800173 <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA8 periph A with pullup */
174 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA7 periph A */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800175 };
176
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800177 pinctrl_usart2_rts: usart2_rts-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800178 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800179 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800180 };
181
182 pinctrl_usart2_cts: usart2_cts-0 {
183 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800184 <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800185 };
186 };
187
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800188 usart3 {
189 pinctrl_usart3: usart3-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800190 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800191 <AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PC23 periph B with pullup */
192 AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC22 periph B */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800193 };
194
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800195 pinctrl_usart3_rts: usart3_rts-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800196 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800197 <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800198 };
199
200 pinctrl_usart3_cts: usart3_cts-0 {
201 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800202 <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800203 };
204 };
205
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800206 uart0 {
207 pinctrl_uart0: uart0-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800208 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800209 <AT91_PIOC 9 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* PC9 periph C with pullup */
210 AT91_PIOC 8 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC8 periph C */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800211 };
212 };
213
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800214 uart1 {
215 pinctrl_uart1: uart1-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800216 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800217 <AT91_PIOC 16 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* PC17 periph C with pullup */
218 AT91_PIOC 17 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC16 periph C */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800219 };
220 };
Jean-Christophe PLAGNIOL-VILLARD5314ec82012-07-05 16:56:09 +0800221
Jean-Christophe PLAGNIOL-VILLARD7a38d452012-07-12 23:36:52 +0800222 nand {
223 pinctrl_nand: nand-0 {
224 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800225 <AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD5 gpio RDY pin pull_up*/
226 AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PD4 gpio enable pin pull_up */
Jean-Christophe PLAGNIOL-VILLARD7a38d452012-07-12 23:36:52 +0800227 };
228 };
229
Jean-Christophe PLAGNIOL-VILLARDd4fe9ac2012-11-16 08:24:17 +0800230 mmc0 {
231 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
232 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800233 <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */
234 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */
235 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA15 periph A with pullup */
Jean-Christophe PLAGNIOL-VILLARDd4fe9ac2012-11-16 08:24:17 +0800236 };
237
238 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
239 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800240 <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */
241 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */
242 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */
Jean-Christophe PLAGNIOL-VILLARDd4fe9ac2012-11-16 08:24:17 +0800243 };
244
245 pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
246 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800247 <AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA11 periph B with pullup */
248 AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA12 periph B with pullup */
249 AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA13 periph B with pullup */
250 AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA14 periph B with pullup */
Jean-Christophe PLAGNIOL-VILLARDd4fe9ac2012-11-16 08:24:17 +0800251 };
252 };
253
Bo Shen544ae6b2013-01-11 15:08:30 +0100254 ssc0 {
255 pinctrl_ssc0_tx: ssc0_tx-0 {
256 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800257 <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */
258 AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */
259 AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA26 periph B */
Bo Shen544ae6b2013-01-11 15:08:30 +0100260 };
261
262 pinctrl_ssc0_rx: ssc0_rx-0 {
263 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800264 <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */
265 AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */
266 AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */
Bo Shen544ae6b2013-01-11 15:08:30 +0100267 };
268 };
269
Wenyou Yanga68b7282013-04-03 14:03:52 +0800270 spi0 {
271 pinctrl_spi0: spi0-0 {
272 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800273 <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A SPI0_MISO pin */
274 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A SPI0_MOSI pin */
275 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA13 periph A SPI0_SPCK pin */
Wenyou Yanga68b7282013-04-03 14:03:52 +0800276 };
277 };
278
279 spi1 {
280 pinctrl_spi1: spi1-0 {
281 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800282 <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA21 periph B SPI1_MISO pin */
283 AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B SPI1_MOSI pin */
284 AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B SPI1_SPCK pin */
Wenyou Yanga68b7282013-04-03 14:03:52 +0800285 };
286 };
287
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800288 pioA: gpio@fffff400 {
289 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
290 reg = <0xfffff400 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800291 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800292 #gpio-cells = <2>;
293 gpio-controller;
294 interrupt-controller;
295 #interrupt-cells = <2>;
296 };
Hong Xucce783c2012-04-17 14:26:29 +0800297
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800298 pioB: gpio@fffff600 {
299 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
300 reg = <0xfffff600 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800301 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800302 #gpio-cells = <2>;
303 gpio-controller;
304 interrupt-controller;
305 #interrupt-cells = <2>;
306 };
Hong Xucce783c2012-04-17 14:26:29 +0800307
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800308 pioC: gpio@fffff800 {
309 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
310 reg = <0xfffff800 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800311 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800312 #gpio-cells = <2>;
313 gpio-controller;
314 interrupt-controller;
315 #interrupt-cells = <2>;
316 };
317
318 pioD: gpio@fffffa00 {
319 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
320 reg = <0xfffffa00 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800321 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800322 #gpio-cells = <2>;
323 gpio-controller;
324 interrupt-controller;
325 #interrupt-cells = <2>;
326 };
Hong Xucce783c2012-04-17 14:26:29 +0800327 };
328
329 dbgu: serial@fffff200 {
330 compatible = "atmel,at91sam9260-usart";
331 reg = <0xfffff200 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800332 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800333 pinctrl-names = "default";
334 pinctrl-0 = <&pinctrl_dbgu>;
Hong Xucce783c2012-04-17 14:26:29 +0800335 status = "disabled";
336 };
337
Bo Shen544ae6b2013-01-11 15:08:30 +0100338 ssc0: ssc@f0010000 {
339 compatible = "atmel,at91sam9g45-ssc";
340 reg = <0xf0010000 0x4000>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800341 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
Bo Shen544ae6b2013-01-11 15:08:30 +0100342 pinctrl-names = "default";
343 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
344 status = "disabled";
345 };
346
Hong Xucce783c2012-04-17 14:26:29 +0800347 usart0: serial@f801c000 {
348 compatible = "atmel,at91sam9260-usart";
349 reg = <0xf801c000 0x4000>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800350 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800351 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800352 pinctrl-0 = <&pinctrl_usart0>;
Hong Xucce783c2012-04-17 14:26:29 +0800353 status = "disabled";
354 };
355
356 usart1: serial@f8020000 {
357 compatible = "atmel,at91sam9260-usart";
358 reg = <0xf8020000 0x4000>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800359 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800360 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800361 pinctrl-0 = <&pinctrl_usart1>;
Hong Xucce783c2012-04-17 14:26:29 +0800362 status = "disabled";
363 };
364
365 usart2: serial@f8024000 {
366 compatible = "atmel,at91sam9260-usart";
367 reg = <0xf8024000 0x4000>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800368 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800369 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800370 pinctrl-0 = <&pinctrl_usart2>;
Hong Xucce783c2012-04-17 14:26:29 +0800371 status = "disabled";
372 };
373
374 usart3: serial@f8028000 {
375 compatible = "atmel,at91sam9260-usart";
376 reg = <0xf8028000 0x4000>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800377 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800378 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800379 pinctrl-0 = <&pinctrl_usart3>;
Hong Xucce783c2012-04-17 14:26:29 +0800380 status = "disabled";
381 };
Ludovic Desroches05dcd362012-09-12 08:42:16 +0200382
383 i2c0: i2c@f8010000 {
384 compatible = "atmel,at91sam9x5-i2c";
385 reg = <0xf8010000 0x100>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800386 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>;
Ludovic Desrochesd9a63a42013-04-16 15:03:08 +0200387 dmas = <&dma 1 13>,
388 <&dma 1 14>;
389 dma-names = "tx", "rx";
Ludovic Desroches05dcd362012-09-12 08:42:16 +0200390 #address-cells = <1>;
391 #size-cells = <0>;
392 status = "disabled";
393 };
394
395 i2c1: i2c@f8014000 {
396 compatible = "atmel,at91sam9x5-i2c";
397 reg = <0xf8014000 0x100>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800398 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>;
Ludovic Desrochesd9a63a42013-04-16 15:03:08 +0200399 dmas = <&dma 1 15>,
400 <&dma 1 16>;
401 dma-names = "tx", "rx";
Ludovic Desroches05dcd362012-09-12 08:42:16 +0200402 #address-cells = <1>;
403 #size-cells = <0>;
404 status = "disabled";
405 };
Richard Genoudd50f88a2013-04-03 14:02:18 +0800406
407 spi0: spi@f0000000 {
408 #address-cells = <1>;
409 #size-cells = <0>;
410 compatible = "atmel,at91rm9200-spi";
411 reg = <0xf0000000 0x100>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800412 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
Wenyou Yanga68b7282013-04-03 14:03:52 +0800413 pinctrl-names = "default";
414 pinctrl-0 = <&pinctrl_spi0>;
Richard Genoudd50f88a2013-04-03 14:02:18 +0800415 status = "disabled";
416 };
417
418 spi1: spi@f0004000 {
419 #address-cells = <1>;
420 #size-cells = <0>;
421 compatible = "atmel,at91rm9200-spi";
422 reg = <0xf0004000 0x100>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800423 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
Wenyou Yanga68b7282013-04-03 14:03:52 +0800424 pinctrl-names = "default";
425 pinctrl-0 = <&pinctrl_spi1>;
Richard Genoudd50f88a2013-04-03 14:02:18 +0800426 status = "disabled";
427 };
Hong Xucce783c2012-04-17 14:26:29 +0800428 };
429
430 nand0: nand@40000000 {
431 compatible = "atmel,at91rm9200-nand";
432 #address-cells = <1>;
433 #size-cells = <1>;
434 reg = < 0x40000000 0x10000000
435 0xffffe000 0x00000600
436 0xffffe600 0x00000200
Josh Wuc18c6b22013-01-23 20:47:10 +0800437 0x00108000 0x00018000
Hong Xucce783c2012-04-17 14:26:29 +0800438 >;
Josh Wuc18c6b22013-01-23 20:47:10 +0800439 atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
Hong Xucce783c2012-04-17 14:26:29 +0800440 atmel,nand-addr-offset = <21>;
441 atmel,nand-cmd-offset = <22>;
Jean-Christophe PLAGNIOL-VILLARD7a38d452012-07-12 23:36:52 +0800442 pinctrl-names = "default";
443 pinctrl-0 = <&pinctrl_nand>;
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800444 gpios = <&pioD 5 GPIO_ACTIVE_HIGH
445 &pioD 4 GPIO_ACTIVE_HIGH
Hong Xucce783c2012-04-17 14:26:29 +0800446 0
447 >;
448 status = "disabled";
449 };
450
451 usb0: ohci@00500000 {
452 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
453 reg = <0x00500000 0x00100000>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800454 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
Hong Xucce783c2012-04-17 14:26:29 +0800455 status = "disabled";
456 };
457 };
458
459 i2c@0 {
460 compatible = "i2c-gpio";
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800461 gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */
462 &pioA 31 GPIO_ACTIVE_HIGH /* scl */
Hong Xucce783c2012-04-17 14:26:29 +0800463 >;
464 i2c-gpio,sda-open-drain;
465 i2c-gpio,scl-open-drain;
466 i2c-gpio,delay-us = <2>; /* ~100 kHz */
467 #address-cells = <1>;
468 #size-cells = <0>;
469 status = "disabled";
470 };
471};