Greg Kroah-Hartman | b244131 | 2017-11-01 15:07:57 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
Waiman Long | d73a339 | 2015-04-24 14:56:31 -0400 | [diff] [blame] | 2 | #ifndef _ASM_X86_QSPINLOCK_H |
| 3 | #define _ASM_X86_QSPINLOCK_H |
| 4 | |
Juergen Gross | 9043442 | 2017-09-06 19:36:24 +0200 | [diff] [blame] | 5 | #include <linux/jump_label.h> |
Peter Zijlstra (Intel) | 2aa79af | 2015-04-24 14:56:36 -0400 | [diff] [blame] | 6 | #include <asm/cpufeature.h> |
Waiman Long | d73a339 | 2015-04-24 14:56:31 -0400 | [diff] [blame] | 7 | #include <asm-generic/qspinlock_types.h> |
Peter Zijlstra (Intel) | f233f7f | 2015-04-24 14:56:38 -0400 | [diff] [blame] | 8 | #include <asm/paravirt.h> |
Waiman Long | d73a339 | 2015-04-24 14:56:31 -0400 | [diff] [blame] | 9 | |
| 10 | #define queued_spin_unlock queued_spin_unlock |
| 11 | /** |
| 12 | * queued_spin_unlock - release a queued spinlock |
| 13 | * @lock : Pointer to queued spinlock structure |
| 14 | * |
| 15 | * A smp_store_release() on the least-significant byte. |
| 16 | */ |
Peter Zijlstra (Intel) | f233f7f | 2015-04-24 14:56:38 -0400 | [diff] [blame] | 17 | static inline void native_queued_spin_unlock(struct qspinlock *lock) |
Waiman Long | d73a339 | 2015-04-24 14:56:31 -0400 | [diff] [blame] | 18 | { |
Will Deacon | 625e88b | 2018-04-26 11:34:16 +0100 | [diff] [blame^] | 19 | smp_store_release(&lock->locked, 0); |
Waiman Long | d73a339 | 2015-04-24 14:56:31 -0400 | [diff] [blame] | 20 | } |
| 21 | |
Peter Zijlstra (Intel) | f233f7f | 2015-04-24 14:56:38 -0400 | [diff] [blame] | 22 | #ifdef CONFIG_PARAVIRT_SPINLOCKS |
| 23 | extern void native_queued_spin_lock_slowpath(struct qspinlock *lock, u32 val); |
| 24 | extern void __pv_init_lock_hash(void); |
| 25 | extern void __pv_queued_spin_lock_slowpath(struct qspinlock *lock, u32 val); |
| 26 | extern void __raw_callee_save___pv_queued_spin_unlock(struct qspinlock *lock); |
| 27 | |
| 28 | static inline void queued_spin_lock_slowpath(struct qspinlock *lock, u32 val) |
| 29 | { |
| 30 | pv_queued_spin_lock_slowpath(lock, val); |
| 31 | } |
| 32 | |
| 33 | static inline void queued_spin_unlock(struct qspinlock *lock) |
| 34 | { |
| 35 | pv_queued_spin_unlock(lock); |
| 36 | } |
Peter Zijlstra | 3cded41 | 2016-11-15 16:47:06 +0100 | [diff] [blame] | 37 | |
| 38 | #define vcpu_is_preempted vcpu_is_preempted |
Waiman Long | 6c62985 | 2017-02-20 13:36:03 -0500 | [diff] [blame] | 39 | static inline bool vcpu_is_preempted(long cpu) |
Peter Zijlstra | 3cded41 | 2016-11-15 16:47:06 +0100 | [diff] [blame] | 40 | { |
| 41 | return pv_vcpu_is_preempted(cpu); |
| 42 | } |
Peter Zijlstra (Intel) | f233f7f | 2015-04-24 14:56:38 -0400 | [diff] [blame] | 43 | #else |
| 44 | static inline void queued_spin_unlock(struct qspinlock *lock) |
| 45 | { |
| 46 | native_queued_spin_unlock(lock); |
| 47 | } |
| 48 | #endif |
| 49 | |
Peter Zijlstra | a6b2778 | 2015-09-05 16:55:05 +0200 | [diff] [blame] | 50 | #ifdef CONFIG_PARAVIRT |
Juergen Gross | 9043442 | 2017-09-06 19:36:24 +0200 | [diff] [blame] | 51 | DECLARE_STATIC_KEY_TRUE(virt_spin_lock_key); |
| 52 | |
| 53 | void native_pv_lock_init(void) __init; |
| 54 | |
Peter Zijlstra | 43b3f02 | 2015-09-04 17:25:23 +0200 | [diff] [blame] | 55 | #define virt_spin_lock virt_spin_lock |
Peter Zijlstra | 43b3f02 | 2015-09-04 17:25:23 +0200 | [diff] [blame] | 56 | static inline bool virt_spin_lock(struct qspinlock *lock) |
Peter Zijlstra (Intel) | 2aa79af | 2015-04-24 14:56:36 -0400 | [diff] [blame] | 57 | { |
Juergen Gross | 9043442 | 2017-09-06 19:36:24 +0200 | [diff] [blame] | 58 | if (!static_branch_likely(&virt_spin_lock_key)) |
Peter Zijlstra (Intel) | 2aa79af | 2015-04-24 14:56:36 -0400 | [diff] [blame] | 59 | return false; |
| 60 | |
Peter Zijlstra | 43b3f02 | 2015-09-04 17:25:23 +0200 | [diff] [blame] | 61 | /* |
| 62 | * On hypervisors without PARAVIRT_SPINLOCKS support we fall |
| 63 | * back to a Test-and-Set spinlock, because fair locks have |
| 64 | * horrible lock 'holder' preemption issues. |
| 65 | */ |
| 66 | |
| 67 | do { |
| 68 | while (atomic_read(&lock->val) != 0) |
| 69 | cpu_relax(); |
| 70 | } while (atomic_cmpxchg(&lock->val, 0, _Q_LOCKED_VAL) != 0); |
Peter Zijlstra (Intel) | 2aa79af | 2015-04-24 14:56:36 -0400 | [diff] [blame] | 71 | |
| 72 | return true; |
| 73 | } |
Juergen Gross | 9043442 | 2017-09-06 19:36:24 +0200 | [diff] [blame] | 74 | #else |
| 75 | static inline void native_pv_lock_init(void) |
| 76 | { |
| 77 | } |
Peter Zijlstra | a6b2778 | 2015-09-05 16:55:05 +0200 | [diff] [blame] | 78 | #endif /* CONFIG_PARAVIRT */ |
Peter Zijlstra (Intel) | 2aa79af | 2015-04-24 14:56:36 -0400 | [diff] [blame] | 79 | |
Waiman Long | d73a339 | 2015-04-24 14:56:31 -0400 | [diff] [blame] | 80 | #include <asm-generic/qspinlock.h> |
| 81 | |
| 82 | #endif /* _ASM_X86_QSPINLOCK_H */ |