R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 1 | /* |
Sricharan R | fa63d03 | 2013-06-07 18:52:47 +0530 | [diff] [blame] | 2 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | */ |
| 8 | /dts-v1/; |
| 9 | |
Florian Vaussard | 98ef7957 | 2013-05-31 14:32:55 +0200 | [diff] [blame] | 10 | #include "omap5.dtsi" |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 11 | |
| 12 | / { |
Sricharan R | fa63d03 | 2013-06-07 18:52:47 +0530 | [diff] [blame] | 13 | model = "TI OMAP5 uEVM board"; |
| 14 | compatible = "ti,omap5-uevm", "ti,omap5"; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 15 | |
| 16 | memory { |
| 17 | device_type = "memory"; |
Santosh Shilimkar | 03178c6 | 2013-01-18 11:43:16 +0530 | [diff] [blame] | 18 | reg = <0x80000000 0x7F000000>; /* 2032 MB */ |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 19 | }; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 20 | |
| 21 | vmmcsd_fixed: fixedregulator-mmcsd { |
| 22 | compatible = "regulator-fixed"; |
| 23 | regulator-name = "vmmcsd_fixed"; |
| 24 | regulator-min-microvolt = <3000000>; |
| 25 | regulator-max-microvolt = <3000000>; |
| 26 | }; |
Sourav Poddar | 5449fbc | 2012-07-25 11:03:27 +0530 | [diff] [blame] | 27 | |
Roger Quadros | ed7f8e8 | 2013-06-07 18:52:48 +0530 | [diff] [blame] | 28 | /* HS USB Port 2 RESET */ |
| 29 | hsusb2_reset: hsusb2_reset_reg { |
| 30 | compatible = "regulator-fixed"; |
| 31 | regulator-name = "hsusb2_reset"; |
| 32 | regulator-min-microvolt = <3300000>; |
| 33 | regulator-max-microvolt = <3300000>; |
| 34 | gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; /* gpio3_80 HUB_NRESET */ |
| 35 | startup-delay-us = <70000>; |
| 36 | enable-active-high; |
| 37 | }; |
| 38 | |
| 39 | /* HS USB Host PHY on PORT 2 */ |
| 40 | hsusb2_phy: hsusb2_phy { |
| 41 | compatible = "usb-nop-xceiv"; |
| 42 | reset-supply = <&hsusb2_reset>; |
| 43 | }; |
| 44 | |
| 45 | /* HS USB Port 3 RESET */ |
| 46 | hsusb3_reset: hsusb3_reset_reg { |
| 47 | compatible = "regulator-fixed"; |
| 48 | regulator-name = "hsusb3_reset"; |
| 49 | regulator-min-microvolt = <3300000>; |
| 50 | regulator-max-microvolt = <3300000>; |
| 51 | gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>; /* gpio3_79 ETH_NRESET */ |
| 52 | startup-delay-us = <70000>; |
| 53 | enable-active-high; |
| 54 | }; |
| 55 | |
| 56 | /* HS USB Host PHY on PORT 3 */ |
| 57 | hsusb3_phy: hsusb3_phy { |
| 58 | compatible = "usb-nop-xceiv"; |
| 59 | reset-supply = <&hsusb3_reset>; |
| 60 | }; |
| 61 | |
Dan Murphy | 6615530 | 2013-06-07 18:52:49 +0530 | [diff] [blame^] | 62 | leds { |
| 63 | compatible = "gpio-leds"; |
| 64 | led@1 { |
| 65 | label = "omap5:blue:usr1"; |
| 66 | gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; /* gpio5_153 D1 LED */ |
| 67 | linux,default-trigger = "heartbeat"; |
| 68 | default-state = "off"; |
| 69 | }; |
| 70 | }; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 71 | }; |
| 72 | |
Peter Ujfalusi | 8bbacc5 | 2012-10-04 14:57:28 +0300 | [diff] [blame] | 73 | &omap5_pmx_core { |
| 74 | pinctrl-names = "default"; |
| 75 | pinctrl-0 = < |
| 76 | &twl6040_pins |
| 77 | &mcpdm_pins |
| 78 | &dmic_pins |
| 79 | &mcbsp1_pins |
| 80 | &mcbsp2_pins |
Roger Quadros | ed7f8e8 | 2013-06-07 18:52:48 +0530 | [diff] [blame] | 81 | &usbhost_pins |
Dan Murphy | 6615530 | 2013-06-07 18:52:49 +0530 | [diff] [blame^] | 82 | &led_gpio_pins |
Peter Ujfalusi | 8bbacc5 | 2012-10-04 14:57:28 +0300 | [diff] [blame] | 83 | >; |
| 84 | |
| 85 | twl6040_pins: pinmux_twl6040_pins { |
| 86 | pinctrl-single,pins = < |
Florian Vaussard | bcd3cca | 2013-05-31 14:32:59 +0200 | [diff] [blame] | 87 | 0x18a (PIN_OUTPUT | MUX_MODE6) /* perslimbus2_clock.gpio5_145 */ |
Peter Ujfalusi | 8bbacc5 | 2012-10-04 14:57:28 +0300 | [diff] [blame] | 88 | >; |
| 89 | }; |
| 90 | |
| 91 | mcpdm_pins: pinmux_mcpdm_pins { |
| 92 | pinctrl-single,pins = < |
Florian Vaussard | bcd3cca | 2013-05-31 14:32:59 +0200 | [diff] [blame] | 93 | 0x142 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_clks.abe_clks */ |
| 94 | 0x15c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_ul_data.abemcpdm_ul_data */ |
| 95 | 0x15e (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_dl_data.abemcpdm_dl_data */ |
| 96 | 0x160 (PIN_INPUT_PULLUP | MUX_MODE0) /* abemcpdm_frame.abemcpdm_frame */ |
| 97 | 0x162 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_lb_clk.abemcpdm_lb_clk */ |
Peter Ujfalusi | 8bbacc5 | 2012-10-04 14:57:28 +0300 | [diff] [blame] | 98 | >; |
| 99 | }; |
| 100 | |
| 101 | dmic_pins: pinmux_dmic_pins { |
| 102 | pinctrl-single,pins = < |
Florian Vaussard | bcd3cca | 2013-05-31 14:32:59 +0200 | [diff] [blame] | 103 | 0x144 (PIN_INPUT | MUX_MODE0) /* abedmic_din1.abedmic_din1 */ |
| 104 | 0x146 (PIN_INPUT | MUX_MODE0) /* abedmic_din2.abedmic_din2 */ |
| 105 | 0x148 (PIN_INPUT | MUX_MODE0) /* abedmic_din3.abedmic_din3 */ |
| 106 | 0x14a (PIN_OUTPUT | MUX_MODE0) /* abedmic_clk1.abedmic_clk1 */ |
Peter Ujfalusi | 8bbacc5 | 2012-10-04 14:57:28 +0300 | [diff] [blame] | 107 | >; |
| 108 | }; |
| 109 | |
| 110 | mcbsp1_pins: pinmux_mcbsp1_pins { |
| 111 | pinctrl-single,pins = < |
Florian Vaussard | bcd3cca | 2013-05-31 14:32:59 +0200 | [diff] [blame] | 112 | 0x14c (PIN_INPUT | MUX_MODE1) /* abedmic_clk2.abemcbsp1_fsx */ |
| 113 | 0x14e (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* abedmic_clk3.abemcbsp1_dx */ |
| 114 | 0x150 (PIN_INPUT | MUX_MODE1) /* abeslimbus1_clock.abemcbsp1_clkx */ |
| 115 | 0x152 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* abeslimbus1_data.abemcbsp1_dr */ |
Peter Ujfalusi | 8bbacc5 | 2012-10-04 14:57:28 +0300 | [diff] [blame] | 116 | >; |
| 117 | }; |
| 118 | |
| 119 | mcbsp2_pins: pinmux_mcbsp2_pins { |
| 120 | pinctrl-single,pins = < |
Florian Vaussard | bcd3cca | 2013-05-31 14:32:59 +0200 | [diff] [blame] | 121 | 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcbsp2_dr.abemcbsp2_dr */ |
| 122 | 0x156 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abemcbsp2_dx.abemcbsp2_dx */ |
| 123 | 0x158 (PIN_INPUT | MUX_MODE0) /* abemcbsp2_fsx.abemcbsp2_fsx */ |
| 124 | 0x15a (PIN_INPUT | MUX_MODE0) /* abemcbsp2_clkx.abemcbsp2_clkx */ |
Peter Ujfalusi | 8bbacc5 | 2012-10-04 14:57:28 +0300 | [diff] [blame] | 125 | >; |
| 126 | }; |
Sourav Poddar | 9be495c | 2013-02-13 14:58:22 +0530 | [diff] [blame] | 127 | |
Florian Vaussard | bcd3cca | 2013-05-31 14:32:59 +0200 | [diff] [blame] | 128 | i2c1_pins: pinmux_i2c1_pins { |
| 129 | pinctrl-single,pins = < |
| 130 | 0x1b2 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ |
| 131 | 0x1b4 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ |
| 132 | >; |
| 133 | }; |
Sourav Poddar | 9be495c | 2013-02-13 14:58:22 +0530 | [diff] [blame] | 134 | |
Sourav Poddar | 9be495c | 2013-02-13 14:58:22 +0530 | [diff] [blame] | 135 | i2c5_pins: pinmux_i2c5_pins { |
| 136 | pinctrl-single,pins = < |
Florian Vaussard | bcd3cca | 2013-05-31 14:32:59 +0200 | [diff] [blame] | 137 | 0x184 (PIN_INPUT | MUX_MODE0) /* i2c5_scl */ |
| 138 | 0x186 (PIN_INPUT | MUX_MODE0) /* i2c5_sda */ |
Sourav Poddar | 9be495c | 2013-02-13 14:58:22 +0530 | [diff] [blame] | 139 | >; |
| 140 | }; |
Sourav Poddar | 392adaf | 2013-02-13 14:58:44 +0530 | [diff] [blame] | 141 | |
| 142 | mcspi2_pins: pinmux_mcspi2_pins { |
| 143 | pinctrl-single,pins = < |
Florian Vaussard | bcd3cca | 2013-05-31 14:32:59 +0200 | [diff] [blame] | 144 | 0xbc (PIN_INPUT | MUX_MODE0) /* mcspi2_clk */ |
| 145 | 0xbe (PIN_INPUT | MUX_MODE0) /* mcspi2_simo */ |
| 146 | 0xc0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi2_somi */ |
| 147 | 0xc2 (PIN_OUTPUT | MUX_MODE0) /* mcspi2_cs */ |
Sourav Poddar | 392adaf | 2013-02-13 14:58:44 +0530 | [diff] [blame] | 148 | >; |
| 149 | }; |
| 150 | |
| 151 | mcspi3_pins: pinmux_mcspi3_pins { |
| 152 | pinctrl-single,pins = < |
Florian Vaussard | bcd3cca | 2013-05-31 14:32:59 +0200 | [diff] [blame] | 153 | 0x78 (PIN_INPUT | MUX_MODE1) /* mcspi2_somi */ |
| 154 | 0x7a (PIN_INPUT | MUX_MODE1) /* mcspi2_cs */ |
| 155 | 0x7c (PIN_INPUT | MUX_MODE1) /* mcspi2_simo */ |
| 156 | 0x7e (PIN_INPUT | MUX_MODE1) /* mcspi2_clk */ |
Sourav Poddar | 392adaf | 2013-02-13 14:58:44 +0530 | [diff] [blame] | 157 | >; |
| 158 | }; |
| 159 | |
| 160 | mcspi4_pins: pinmux_mcspi4_pins { |
| 161 | pinctrl-single,pins = < |
Florian Vaussard | bcd3cca | 2013-05-31 14:32:59 +0200 | [diff] [blame] | 162 | 0x164 (PIN_INPUT | MUX_MODE1) /* mcspi2_clk */ |
| 163 | 0x168 (PIN_INPUT | MUX_MODE1) /* mcspi2_simo */ |
| 164 | 0x16a (PIN_INPUT | MUX_MODE1) /* mcspi2_somi */ |
| 165 | 0x16c (PIN_INPUT | MUX_MODE1) /* mcspi2_cs */ |
Sourav Poddar | 392adaf | 2013-02-13 14:58:44 +0530 | [diff] [blame] | 166 | >; |
| 167 | }; |
Roger Quadros | ed7f8e8 | 2013-06-07 18:52:48 +0530 | [diff] [blame] | 168 | |
| 169 | usbhost_pins: pinmux_usbhost_pins { |
| 170 | pinctrl-single,pins = < |
| 171 | 0x84 (PIN_INPUT | MUX_MODE0) /* usbb2_hsic_strobe */ |
| 172 | 0x86 (PIN_INPUT | MUX_MODE0) /* usbb2_hsic_data */ |
| 173 | |
| 174 | 0x19e (PIN_INPUT | MUX_MODE0) /* usbb3_hsic_strobe */ |
| 175 | 0x1a0 (PIN_INPUT | MUX_MODE0) /* usbb3_hsic_data */ |
| 176 | |
| 177 | 0x70 (PIN_OUTPUT | MUX_MODE6) /* gpio3_80 HUB_NRESET */ |
| 178 | 0x6e (PIN_OUTPUT | MUX_MODE6) /* gpio3_79 ETH_NRESET */ |
| 179 | >; |
| 180 | }; |
Dan Murphy | 6615530 | 2013-06-07 18:52:49 +0530 | [diff] [blame^] | 181 | |
| 182 | led_gpio_pins: pinmux_led_gpio_pins { |
| 183 | pinctrl-single,pins = < |
| 184 | 0x196 (PIN_OUTPUT | MUX_MODE6) /* uart3_cts_rctx.gpio5_153 */ |
| 185 | >; |
| 186 | }; |
Roger Quadros | ed7f8e8 | 2013-06-07 18:52:48 +0530 | [diff] [blame] | 187 | }; |
| 188 | |
| 189 | &omap5_pmx_wkup { |
| 190 | pinctrl-names = "default"; |
| 191 | pinctrl-0 = < |
| 192 | &usbhost_wkup_pins |
| 193 | >; |
| 194 | |
| 195 | usbhost_wkup_pins: pinmux_usbhost_wkup_pins { |
| 196 | pinctrl-single,pins = < |
| 197 | 0x1A (PIN_OUTPUT | MUX_MODE0) /* fref_clk1_out, USB hub clk */ |
| 198 | >; |
| 199 | }; |
Peter Ujfalusi | 8bbacc5 | 2012-10-04 14:57:28 +0300 | [diff] [blame] | 200 | }; |
| 201 | |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 202 | &mmc1 { |
| 203 | vmmc-supply = <&vmmcsd_fixed>; |
| 204 | bus-width = <4>; |
| 205 | }; |
| 206 | |
| 207 | &mmc2 { |
| 208 | vmmc-supply = <&vmmcsd_fixed>; |
| 209 | bus-width = <8>; |
| 210 | ti,non-removable; |
| 211 | }; |
| 212 | |
| 213 | &mmc3 { |
| 214 | bus-width = <4>; |
| 215 | ti,non-removable; |
| 216 | }; |
| 217 | |
| 218 | &mmc4 { |
| 219 | status = "disabled"; |
| 220 | }; |
| 221 | |
| 222 | &mmc5 { |
| 223 | status = "disabled"; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 224 | }; |
Sourav Poddar | 08f3e21 | 2012-07-25 11:02:43 +0530 | [diff] [blame] | 225 | |
Sourav Poddar | 9be495c | 2013-02-13 14:58:22 +0530 | [diff] [blame] | 226 | &i2c1 { |
| 227 | pinctrl-names = "default"; |
| 228 | pinctrl-0 = <&i2c1_pins>; |
| 229 | |
| 230 | clock-frequency = <400000>; |
| 231 | }; |
| 232 | |
Sourav Poddar | 9be495c | 2013-02-13 14:58:22 +0530 | [diff] [blame] | 233 | &i2c5 { |
| 234 | pinctrl-names = "default"; |
| 235 | pinctrl-0 = <&i2c5_pins>; |
| 236 | |
| 237 | clock-frequency = <400000>; |
| 238 | }; |
| 239 | |
Peter Ujfalusi | 42601d5 | 2012-10-04 14:57:24 +0300 | [diff] [blame] | 240 | &mcbsp3 { |
| 241 | status = "disabled"; |
| 242 | }; |
Lokesh Vutla | 4d2750f | 2012-11-05 18:22:52 +0530 | [diff] [blame] | 243 | |
Roger Quadros | ed7f8e8 | 2013-06-07 18:52:48 +0530 | [diff] [blame] | 244 | &usbhshost { |
| 245 | port2-mode = "ehci-hsic"; |
| 246 | port3-mode = "ehci-hsic"; |
| 247 | }; |
| 248 | |
| 249 | &usbhsehci { |
| 250 | phys = <0 &hsusb2_phy &hsusb3_phy>; |
| 251 | }; |
| 252 | |
Sourav Poddar | 392adaf | 2013-02-13 14:58:44 +0530 | [diff] [blame] | 253 | &mcspi1 { |
| 254 | |
| 255 | }; |
| 256 | |
| 257 | &mcspi2 { |
| 258 | pinctrl-names = "default"; |
| 259 | pinctrl-0 = <&mcspi2_pins>; |
| 260 | }; |
| 261 | |
| 262 | &mcspi3 { |
| 263 | pinctrl-names = "default"; |
| 264 | pinctrl-0 = <&mcspi3_pins>; |
| 265 | }; |
| 266 | |
| 267 | &mcspi4 { |
| 268 | pinctrl-names = "default"; |
| 269 | pinctrl-0 = <&mcspi4_pins>; |
| 270 | }; |