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gerrit-public.fairphone.software / kernel / msm-5.4 / 678bc9a2eabb7f444ef8ad1cfc5ef394e2bd8bf2 / . / arch / arm / mach-omap2 / clock34xx_data.c
blob: 4dd5926ad980ca72da5e1d2f0de6058c29f57386 [file] [log] [blame]
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]1/*
2 * OMAP3 clock data
3 *
4 * Copyright (C) 2007-2009 Texas Instruments, Inc.
5 * Copyright (C) 2007-2009 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 * With many device clock fixes by Kevin Hilman and Jouni Högander
9 * DPLL bypass clock support added by Roman Tereshonkov
10 *
11 */
12
13/*
14 * Virtual clocks are introduced as convenient tools.
15 * They are sources for other clocks and not supposed
16 * to be requested from drivers directly.
17 */
18
19#include <linux/module.h>
20#include <linux/kernel.h>
21#include <linux/clk.h>
22
23#include <plat/control.h>
24#include <plat/clkdev_omap.h>
25
26#include "clock.h"
27#include "clock34xx.h"
28#include "cm.h"
29#include "cm-regbits-34xx.h"
30#include "prm.h"
31#include "prm-regbits-34xx.h"
32
33/*
34 * clocks
35 */
36
37#define OMAP_CM_REGADDR OMAP34XX_CM_REGADDR
38
39/* Maximum DPLL multiplier, divider values for OMAP3 */
40#define OMAP3_MAX_DPLL_MULT 2048
Richard Woodruff358965d2010-02-22 22:09:08 -0700[diff] [blame]41#define OMAP3630_MAX_JTYPE_DPLL_MULT 4095
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]42#define OMAP3_MAX_DPLL_DIV 128
43
44/*
45 * DPLL1 supplies clock to the MPU.
46 * DPLL2 supplies clock to the IVA2.
47 * DPLL3 supplies CORE domain clocks.
48 * DPLL4 supplies peripheral clocks.
49 * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
50 */
51
52/* Forward declarations for DPLL bypass clocks */
53static struct clk dpll1_fck;
54static struct clk dpll2_fck;
55
56/* PRM CLOCKS */
57
58/* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
59static struct clk omap_32k_fck = {
60 .name = "omap_32k_fck",
61 .ops = &clkops_null,
62 .rate = 32768,
63 .flags = RATE_FIXED,
64};
65
66static struct clk secure_32k_fck = {
67 .name = "secure_32k_fck",
68 .ops = &clkops_null,
69 .rate = 32768,
70 .flags = RATE_FIXED,
71};
72
73/* Virtual source clocks for osc_sys_ck */
74static struct clk virt_12m_ck = {
75 .name = "virt_12m_ck",
76 .ops = &clkops_null,
77 .rate = 12000000,
78 .flags = RATE_FIXED,
79};
80
81static struct clk virt_13m_ck = {
82 .name = "virt_13m_ck",
83 .ops = &clkops_null,
84 .rate = 13000000,
85 .flags = RATE_FIXED,
86};
87
88static struct clk virt_16_8m_ck = {
89 .name = "virt_16_8m_ck",
90 .ops = &clkops_null,
91 .rate = 16800000,
92 .flags = RATE_FIXED,
93};
94
95static struct clk virt_19_2m_ck = {
96 .name = "virt_19_2m_ck",
97 .ops = &clkops_null,
98 .rate = 19200000,
99 .flags = RATE_FIXED,
100};
101
102static struct clk virt_26m_ck = {
103 .name = "virt_26m_ck",
104 .ops = &clkops_null,
105 .rate = 26000000,
106 .flags = RATE_FIXED,
107};
108
109static struct clk virt_38_4m_ck = {
110 .name = "virt_38_4m_ck",
111 .ops = &clkops_null,
112 .rate = 38400000,
113 .flags = RATE_FIXED,
114};
115
116static const struct clksel_rate osc_sys_12m_rates[] = {
117 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
118 { .div = 0 }
119};
120
121static const struct clksel_rate osc_sys_13m_rates[] = {
122 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
123 { .div = 0 }
124};
125
126static const struct clksel_rate osc_sys_16_8m_rates[] = {
127 { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
128 { .div = 0 }
129};
130
131static const struct clksel_rate osc_sys_19_2m_rates[] = {
132 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
133 { .div = 0 }
134};
135
136static const struct clksel_rate osc_sys_26m_rates[] = {
137 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
138 { .div = 0 }
139};
140
141static const struct clksel_rate osc_sys_38_4m_rates[] = {
142 { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
143 { .div = 0 }
144};
145
146static const struct clksel osc_sys_clksel[] = {
147 { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates },
148 { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates },
149 { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
150 { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
151 { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates },
152 { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
153 { .parent = NULL },
154};
155
156/* Oscillator clock */
157/* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
158static struct clk osc_sys_ck = {
159 .name = "osc_sys_ck",
160 .ops = &clkops_null,
161 .init = &omap2_init_clksel_parent,
162 .clksel_reg = OMAP3430_PRM_CLKSEL,
163 .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK,
164 .clksel = osc_sys_clksel,
165 /* REVISIT: deal with autoextclkmode? */
166 .flags = RATE_FIXED,
167 .recalc = &omap2_clksel_recalc,
168};
169
170static const struct clksel_rate div2_rates[] = {
171 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
172 { .div = 2, .val = 2, .flags = RATE_IN_343X },
173 { .div = 0 }
174};
175
176static const struct clksel sys_clksel[] = {
177 { .parent = &osc_sys_ck, .rates = div2_rates },
178 { .parent = NULL }
179};
180
181/* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
182/* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
183static struct clk sys_ck = {
184 .name = "sys_ck",
185 .ops = &clkops_null,
186 .parent = &osc_sys_ck,
187 .init = &omap2_init_clksel_parent,
188 .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL,
189 .clksel_mask = OMAP_SYSCLKDIV_MASK,
190 .clksel = sys_clksel,
191 .recalc = &omap2_clksel_recalc,
192};
193
194static struct clk sys_altclk = {
195 .name = "sys_altclk",
196 .ops = &clkops_null,
197};
198
199/* Optional external clock input for some McBSPs */
200static struct clk mcbsp_clks = {
201 .name = "mcbsp_clks",
202 .ops = &clkops_null,
203};
204
205/* PRM EXTERNAL CLOCK OUTPUT */
206
207static struct clk sys_clkout1 = {
208 .name = "sys_clkout1",
209 .ops = &clkops_omap2_dflt,
210 .parent = &osc_sys_ck,
211 .enable_reg = OMAP3430_PRM_CLKOUT_CTRL,
212 .enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
213 .recalc = &followparent_recalc,
214};
215
216/* DPLLS */
217
218/* CM CLOCKS */
219
220static const struct clksel_rate div16_dpll_rates[] = {
221 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
222 { .div = 2, .val = 2, .flags = RATE_IN_343X },
223 { .div = 3, .val = 3, .flags = RATE_IN_343X },
224 { .div = 4, .val = 4, .flags = RATE_IN_343X },
225 { .div = 5, .val = 5, .flags = RATE_IN_343X },
226 { .div = 6, .val = 6, .flags = RATE_IN_343X },
227 { .div = 7, .val = 7, .flags = RATE_IN_343X },
228 { .div = 8, .val = 8, .flags = RATE_IN_343X },
229 { .div = 9, .val = 9, .flags = RATE_IN_343X },
230 { .div = 10, .val = 10, .flags = RATE_IN_343X },
231 { .div = 11, .val = 11, .flags = RATE_IN_343X },
232 { .div = 12, .val = 12, .flags = RATE_IN_343X },
233 { .div = 13, .val = 13, .flags = RATE_IN_343X },
234 { .div = 14, .val = 14, .flags = RATE_IN_343X },
235 { .div = 15, .val = 15, .flags = RATE_IN_343X },
236 { .div = 16, .val = 16, .flags = RATE_IN_343X },
237 { .div = 0 }
238};
239
Vishwanath BS678bc9a2010-02-22 22:09:09 -0700[diff] [blame^]240static const struct clksel_rate div32_dpll4_rates_3630[] = {
241 { .div = 1, .val = 1, .flags = RATE_IN_36XX | DEFAULT_RATE },
242 { .div = 2, .val = 2, .flags = RATE_IN_36XX },
243 { .div = 3, .val = 3, .flags = RATE_IN_36XX },
244 { .div = 4, .val = 4, .flags = RATE_IN_36XX },
245 { .div = 5, .val = 5, .flags = RATE_IN_36XX },
246 { .div = 6, .val = 6, .flags = RATE_IN_36XX },
247 { .div = 7, .val = 7, .flags = RATE_IN_36XX },
248 { .div = 8, .val = 8, .flags = RATE_IN_36XX },
249 { .div = 9, .val = 9, .flags = RATE_IN_36XX },
250 { .div = 10, .val = 10, .flags = RATE_IN_36XX },
251 { .div = 11, .val = 11, .flags = RATE_IN_36XX },
252 { .div = 12, .val = 12, .flags = RATE_IN_36XX },
253 { .div = 13, .val = 13, .flags = RATE_IN_36XX },
254 { .div = 14, .val = 14, .flags = RATE_IN_36XX },
255 { .div = 15, .val = 15, .flags = RATE_IN_36XX },
256 { .div = 16, .val = 16, .flags = RATE_IN_36XX },
257 { .div = 17, .val = 17, .flags = RATE_IN_36XX },
258 { .div = 18, .val = 18, .flags = RATE_IN_36XX },
259 { .div = 19, .val = 19, .flags = RATE_IN_36XX },
260 { .div = 20, .val = 20, .flags = RATE_IN_36XX },
261 { .div = 21, .val = 21, .flags = RATE_IN_36XX },
262 { .div = 22, .val = 22, .flags = RATE_IN_36XX },
263 { .div = 23, .val = 23, .flags = RATE_IN_36XX },
264 { .div = 24, .val = 24, .flags = RATE_IN_36XX },
265 { .div = 25, .val = 25, .flags = RATE_IN_36XX },
266 { .div = 26, .val = 26, .flags = RATE_IN_36XX },
267 { .div = 27, .val = 27, .flags = RATE_IN_36XX },
268 { .div = 28, .val = 28, .flags = RATE_IN_36XX },
269 { .div = 29, .val = 29, .flags = RATE_IN_36XX },
270 { .div = 30, .val = 30, .flags = RATE_IN_36XX },
271 { .div = 31, .val = 31, .flags = RATE_IN_36XX },
272 { .div = 32, .val = 32, .flags = RATE_IN_36XX },
273 { .div = 0 }
274};
275
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]276/* DPLL1 */
277/* MPU clock source */
278/* Type: DPLL */
279static struct dpll_data dpll1_dd = {
280 .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
281 .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK,
282 .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
283 .clk_bypass = &dpll1_fck,
284 .clk_ref = &sys_ck,
285 .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK,
286 .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
287 .enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
288 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
289 .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
290 .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
291 .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT,
292 .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
293 .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK,
294 .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
295 .idlest_mask = OMAP3430_ST_MPU_CLK_MASK,
296 .max_multiplier = OMAP3_MAX_DPLL_MULT,
297 .min_divider = 1,
298 .max_divider = OMAP3_MAX_DPLL_DIV,
299 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
300};
301
302static struct clk dpll1_ck = {
303 .name = "dpll1_ck",
304 .ops = &clkops_null,
305 .parent = &sys_ck,
306 .dpll_data = &dpll1_dd,
307 .round_rate = &omap2_dpll_round_rate,
308 .set_rate = &omap3_noncore_dpll_set_rate,
309 .clkdm_name = "dpll1_clkdm",
310 .recalc = &omap3_dpll_recalc,
311};
312
313/*
314 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
315 * DPLL isn't bypassed.
316 */
317static struct clk dpll1_x2_ck = {
318 .name = "dpll1_x2_ck",
319 .ops = &clkops_null,
320 .parent = &dpll1_ck,
321 .clkdm_name = "dpll1_clkdm",
322 .recalc = &omap3_clkoutx2_recalc,
323};
324
325/* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
326static const struct clksel div16_dpll1_x2m2_clksel[] = {
327 { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
328 { .parent = NULL }
329};
330
331/*
332 * Does not exist in the TRM - needed to separate the M2 divider from
333 * bypass selection in mpu_ck
334 */
335static struct clk dpll1_x2m2_ck = {
336 .name = "dpll1_x2m2_ck",
337 .ops = &clkops_null,
338 .parent = &dpll1_x2_ck,
339 .init = &omap2_init_clksel_parent,
340 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
341 .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
342 .clksel = div16_dpll1_x2m2_clksel,
343 .clkdm_name = "dpll1_clkdm",
344 .recalc = &omap2_clksel_recalc,
345};
346
347/* DPLL2 */
348/* IVA2 clock source */
349/* Type: DPLL */
350
351static struct dpll_data dpll2_dd = {
352 .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
353 .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK,
354 .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
355 .clk_bypass = &dpll2_fck,
356 .clk_ref = &sys_ck,
357 .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
358 .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
359 .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
360 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
361 (1 << DPLL_LOW_POWER_BYPASS),
362 .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
363 .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
364 .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
365 .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
366 .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK,
367 .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
368 .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK,
369 .max_multiplier = OMAP3_MAX_DPLL_MULT,
370 .min_divider = 1,
371 .max_divider = OMAP3_MAX_DPLL_DIV,
372 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
373};
374
375static struct clk dpll2_ck = {
376 .name = "dpll2_ck",
Tony Lindgren47512272010-02-15 09:27:25 -0800[diff] [blame]377 .ops = &omap3_clkops_noncore_dpll_ops,
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]378 .parent = &sys_ck,
379 .dpll_data = &dpll2_dd,
380 .round_rate = &omap2_dpll_round_rate,
381 .set_rate = &omap3_noncore_dpll_set_rate,
382 .clkdm_name = "dpll2_clkdm",
383 .recalc = &omap3_dpll_recalc,
384};
385
386static const struct clksel div16_dpll2_m2x2_clksel[] = {
387 { .parent = &dpll2_ck, .rates = div16_dpll_rates },
388 { .parent = NULL }
389};
390
391/*
392 * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
393 * or CLKOUTX2. CLKOUT seems most plausible.
394 */
395static struct clk dpll2_m2_ck = {
396 .name = "dpll2_m2_ck",
397 .ops = &clkops_null,
398 .parent = &dpll2_ck,
399 .init = &omap2_init_clksel_parent,
400 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
401 OMAP3430_CM_CLKSEL2_PLL),
402 .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
403 .clksel = div16_dpll2_m2x2_clksel,
404 .clkdm_name = "dpll2_clkdm",
405 .recalc = &omap2_clksel_recalc,
406};
407
408/*
409 * DPLL3
410 * Source clock for all interfaces and for some device fclks
411 * REVISIT: Also supports fast relock bypass - not included below
412 */
413static struct dpll_data dpll3_dd = {
414 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
415 .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
416 .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK,
417 .clk_bypass = &sys_ck,
418 .clk_ref = &sys_ck,
419 .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK,
420 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
421 .enable_mask = OMAP3430_EN_CORE_DPLL_MASK,
422 .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
423 .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
424 .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
425 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
426 .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK,
427 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
428 .idlest_mask = OMAP3430_ST_CORE_CLK_MASK,
429 .max_multiplier = OMAP3_MAX_DPLL_MULT,
430 .min_divider = 1,
431 .max_divider = OMAP3_MAX_DPLL_DIV,
432 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
433};
434
435static struct clk dpll3_ck = {
436 .name = "dpll3_ck",
437 .ops = &clkops_null,
438 .parent = &sys_ck,
439 .dpll_data = &dpll3_dd,
440 .round_rate = &omap2_dpll_round_rate,
441 .clkdm_name = "dpll3_clkdm",
442 .recalc = &omap3_dpll_recalc,
443};
444
445/*
446 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
447 * DPLL isn't bypassed
448 */
449static struct clk dpll3_x2_ck = {
450 .name = "dpll3_x2_ck",
451 .ops = &clkops_null,
452 .parent = &dpll3_ck,
453 .clkdm_name = "dpll3_clkdm",
454 .recalc = &omap3_clkoutx2_recalc,
455};
456
457static const struct clksel_rate div31_dpll3_rates[] = {
458 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
459 { .div = 2, .val = 2, .flags = RATE_IN_343X },
460 { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
461 { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
462 { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
463 { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
464 { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
465 { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
466 { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
467 { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
468 { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
469 { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
470 { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
471 { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
472 { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
473 { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
474 { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
475 { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
476 { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
477 { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
478 { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
479 { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
480 { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
481 { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
482 { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
483 { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
484 { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
485 { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
486 { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
487 { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
488 { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
489 { .div = 0 },
490};
491
492static const struct clksel div31_dpll3m2_clksel[] = {
493 { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
494 { .parent = NULL }
495};
496
497/* DPLL3 output M2 - primary control point for CORE speed */
498static struct clk dpll3_m2_ck = {
499 .name = "dpll3_m2_ck",
500 .ops = &clkops_null,
501 .parent = &dpll3_ck,
502 .init = &omap2_init_clksel_parent,
503 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
504 .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
505 .clksel = div31_dpll3m2_clksel,
506 .clkdm_name = "dpll3_clkdm",
507 .round_rate = &omap2_clksel_round_rate,
508 .set_rate = &omap3_core_dpll_m2_set_rate,
509 .recalc = &omap2_clksel_recalc,
510};
511
512static struct clk core_ck = {
513 .name = "core_ck",
514 .ops = &clkops_null,
515 .parent = &dpll3_m2_ck,
516 .recalc = &followparent_recalc,
517};
518
519static struct clk dpll3_m2x2_ck = {
520 .name = "dpll3_m2x2_ck",
521 .ops = &clkops_null,
522 .parent = &dpll3_m2_ck,
523 .clkdm_name = "dpll3_clkdm",
524 .recalc = &omap3_clkoutx2_recalc,
525};
526
527/* The PWRDN bit is apparently only available on 3430ES2 and above */
528static const struct clksel div16_dpll3_clksel[] = {
529 { .parent = &dpll3_ck, .rates = div16_dpll_rates },
530 { .parent = NULL }
531};
532
533/* This virtual clock is the source for dpll3_m3x2_ck */
534static struct clk dpll3_m3_ck = {
535 .name = "dpll3_m3_ck",
536 .ops = &clkops_null,
537 .parent = &dpll3_ck,
538 .init = &omap2_init_clksel_parent,
539 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
540 .clksel_mask = OMAP3430_DIV_DPLL3_MASK,
541 .clksel = div16_dpll3_clksel,
542 .clkdm_name = "dpll3_clkdm",
543 .recalc = &omap2_clksel_recalc,
544};
545
546/* The PWRDN bit is apparently only available on 3430ES2 and above */
547static struct clk dpll3_m3x2_ck = {
548 .name = "dpll3_m3x2_ck",
549 .ops = &clkops_omap2_dflt_wait,
550 .parent = &dpll3_m3_ck,
551 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
552 .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
553 .flags = INVERT_ENABLE,
554 .clkdm_name = "dpll3_clkdm",
555 .recalc = &omap3_clkoutx2_recalc,
556};
557
558static struct clk emu_core_alwon_ck = {
559 .name = "emu_core_alwon_ck",
560 .ops = &clkops_null,
561 .parent = &dpll3_m3x2_ck,
562 .clkdm_name = "dpll3_clkdm",
563 .recalc = &followparent_recalc,
564};
565
566/* DPLL4 */
567/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
568/* Type: DPLL */
Richard Woodruff358965d2010-02-22 22:09:08 -0700[diff] [blame]569static struct dpll_data dpll4_dd;
570static struct dpll_data dpll4_dd_34xx __initdata = {
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]571 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
572 .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
573 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
574 .clk_bypass = &sys_ck,
575 .clk_ref = &sys_ck,
576 .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
577 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
578 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
579 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
580 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
581 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
582 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
583 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
584 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
585 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
586 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
587 .max_multiplier = OMAP3_MAX_DPLL_MULT,
588 .min_divider = 1,
589 .max_divider = OMAP3_MAX_DPLL_DIV,
590 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
591};
592
Richard Woodruff358965d2010-02-22 22:09:08 -0700[diff] [blame]593static struct dpll_data dpll4_dd_3630 __initdata = {
594 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
595 .mult_mask = OMAP3630_PERIPH_DPLL_MULT_MASK,
596 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
597 .clk_bypass = &sys_ck,
598 .clk_ref = &sys_ck,
599 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
600 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
601 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
602 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
603 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
604 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
605 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
606 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
607 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
608 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
609 .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT,
610 .min_divider = 1,
611 .max_divider = OMAP3_MAX_DPLL_DIV,
612 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE,
613 .flags = DPLL_J_TYPE
614};
615
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]616static struct clk dpll4_ck = {
617 .name = "dpll4_ck",
Tony Lindgren47512272010-02-15 09:27:25 -0800[diff] [blame]618 .ops = &omap3_clkops_noncore_dpll_ops,
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]619 .parent = &sys_ck,
620 .dpll_data = &dpll4_dd,
621 .round_rate = &omap2_dpll_round_rate,
622 .set_rate = &omap3_dpll4_set_rate,
623 .clkdm_name = "dpll4_clkdm",
624 .recalc = &omap3_dpll_recalc,
625};
626
627/*
628 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
629 * DPLL isn't bypassed --
630 * XXX does this serve any downstream clocks?
631 */
632static struct clk dpll4_x2_ck = {
633 .name = "dpll4_x2_ck",
634 .ops = &clkops_null,
635 .parent = &dpll4_ck,
636 .clkdm_name = "dpll4_clkdm",
637 .recalc = &omap3_clkoutx2_recalc,
638};
639
640static const struct clksel div16_dpll4_clksel[] = {
641 { .parent = &dpll4_ck, .rates = div16_dpll_rates },
642 { .parent = NULL }
643};
644
Vishwanath BS678bc9a2010-02-22 22:09:09 -0700[diff] [blame^]645static const struct clksel div32_dpll4_clksel[] = {
646 { .parent = &dpll4_ck, .rates = div32_dpll4_rates_3630 },
647 { .parent = NULL }
648};
649
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]650/* This virtual clock is the source for dpll4_m2x2_ck */
Vishwanath BS678bc9a2010-02-22 22:09:09 -0700[diff] [blame^]651static struct clk dpll4_m2_ck;
652
653static struct clk dpll4_m2_ck_34xx __initdata = {
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]654 .name = "dpll4_m2_ck",
655 .ops = &clkops_null,
656 .parent = &dpll4_ck,
657 .init = &omap2_init_clksel_parent,
658 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
659 .clksel_mask = OMAP3430_DIV_96M_MASK,
660 .clksel = div16_dpll4_clksel,
661 .clkdm_name = "dpll4_clkdm",
662 .recalc = &omap2_clksel_recalc,
663};
664
Vishwanath BS678bc9a2010-02-22 22:09:09 -0700[diff] [blame^]665static struct clk dpll4_m2_ck_3630 __initdata = {
666 .name = "dpll4_m2_ck",
667 .ops = &clkops_null,
668 .parent = &dpll4_ck,
669 .init = &omap2_init_clksel_parent,
670 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
671 .clksel_mask = OMAP3630_DIV_96M_MASK,
672 .clksel = div32_dpll4_clksel,
673 .clkdm_name = "dpll4_clkdm",
674 .recalc = &omap2_clksel_recalc,
675};
676
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]677/* The PWRDN bit is apparently only available on 3430ES2 and above */
678static struct clk dpll4_m2x2_ck = {
679 .name = "dpll4_m2x2_ck",
680 .ops = &clkops_omap2_dflt_wait,
681 .parent = &dpll4_m2_ck,
682 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
683 .enable_bit = OMAP3430_PWRDN_96M_SHIFT,
684 .flags = INVERT_ENABLE,
685 .clkdm_name = "dpll4_clkdm",
686 .recalc = &omap3_clkoutx2_recalc,
687};
688
689/*
690 * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
691 * PRM_96M_ALWON_(F)CLK. Two clocks then emerge from the PRM:
692 * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
693 * CM_96K_(F)CLK.
694 */
695static struct clk omap_96m_alwon_fck = {
696 .name = "omap_96m_alwon_fck",
697 .ops = &clkops_null,
698 .parent = &dpll4_m2x2_ck,
699 .recalc = &followparent_recalc,
700};
701
702static struct clk cm_96m_fck = {
703 .name = "cm_96m_fck",
704 .ops = &clkops_null,
705 .parent = &omap_96m_alwon_fck,
706 .recalc = &followparent_recalc,
707};
708
709static const struct clksel_rate omap_96m_dpll_rates[] = {
710 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
711 { .div = 0 }
712};
713
714static const struct clksel_rate omap_96m_sys_rates[] = {
715 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
716 { .div = 0 }
717};
718
719static const struct clksel omap_96m_fck_clksel[] = {
720 { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
721 { .parent = &sys_ck, .rates = omap_96m_sys_rates },
722 { .parent = NULL }
723};
724
725static struct clk omap_96m_fck = {
726 .name = "omap_96m_fck",
727 .ops = &clkops_null,
728 .parent = &sys_ck,
729 .init = &omap2_init_clksel_parent,
730 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
731 .clksel_mask = OMAP3430_SOURCE_96M_MASK,
732 .clksel = omap_96m_fck_clksel,
733 .recalc = &omap2_clksel_recalc,
734};
735
736/* This virtual clock is the source for dpll4_m3x2_ck */
Vishwanath BS678bc9a2010-02-22 22:09:09 -0700[diff] [blame^]737static struct clk dpll4_m3_ck;
738
739static struct clk dpll4_m3_ck_34xx __initdata = {
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]740 .name = "dpll4_m3_ck",
741 .ops = &clkops_null,
742 .parent = &dpll4_ck,
743 .init = &omap2_init_clksel_parent,
744 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
745 .clksel_mask = OMAP3430_CLKSEL_TV_MASK,
746 .clksel = div16_dpll4_clksel,
747 .clkdm_name = "dpll4_clkdm",
748 .recalc = &omap2_clksel_recalc,
749};
750
Vishwanath BS678bc9a2010-02-22 22:09:09 -0700[diff] [blame^]751static struct clk dpll4_m3_ck_3630 __initdata = {
752 .name = "dpll4_m3_ck",
753 .ops = &clkops_null,
754 .parent = &dpll4_ck,
755 .init = &omap2_init_clksel_parent,
756 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
757 .clksel_mask = OMAP3630_CLKSEL_TV_MASK,
758 .clksel = div32_dpll4_clksel,
759 .clkdm_name = "dpll4_clkdm",
760 .recalc = &omap2_clksel_recalc,
761};
762
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]763/* The PWRDN bit is apparently only available on 3430ES2 and above */
764static struct clk dpll4_m3x2_ck = {
765 .name = "dpll4_m3x2_ck",
766 .ops = &clkops_omap2_dflt_wait,
767 .parent = &dpll4_m3_ck,
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]768 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
769 .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
770 .flags = INVERT_ENABLE,
771 .clkdm_name = "dpll4_clkdm",
772 .recalc = &omap3_clkoutx2_recalc,
773};
774
775static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
776 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
777 { .div = 0 }
778};
779
780static const struct clksel_rate omap_54m_alt_rates[] = {
781 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
782 { .div = 0 }
783};
784
785static const struct clksel omap_54m_clksel[] = {
786 { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
787 { .parent = &sys_altclk, .rates = omap_54m_alt_rates },
788 { .parent = NULL }
789};
790
791static struct clk omap_54m_fck = {
792 .name = "omap_54m_fck",
793 .ops = &clkops_null,
794 .init = &omap2_init_clksel_parent,
795 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
796 .clksel_mask = OMAP3430_SOURCE_54M_MASK,
797 .clksel = omap_54m_clksel,
798 .recalc = &omap2_clksel_recalc,
799};
800
801static const struct clksel_rate omap_48m_cm96m_rates[] = {
802 { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
803 { .div = 0 }
804};
805
806static const struct clksel_rate omap_48m_alt_rates[] = {
807 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
808 { .div = 0 }
809};
810
811static const struct clksel omap_48m_clksel[] = {
812 { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
813 { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
814 { .parent = NULL }
815};
816
817static struct clk omap_48m_fck = {
818 .name = "omap_48m_fck",
819 .ops = &clkops_null,
820 .init = &omap2_init_clksel_parent,
821 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
822 .clksel_mask = OMAP3430_SOURCE_48M_MASK,
823 .clksel = omap_48m_clksel,
824 .recalc = &omap2_clksel_recalc,
825};
826
827static struct clk omap_12m_fck = {
828 .name = "omap_12m_fck",
829 .ops = &clkops_null,
830 .parent = &omap_48m_fck,
831 .fixed_div = 4,
Paul Walmsleye9b98f62010-01-26 20:12:57 -0700[diff] [blame]832 .recalc = &omap_fixed_divisor_recalc,
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]833};
834
835/* This virstual clock is the source for dpll4_m4x2_ck */
Vishwanath BS678bc9a2010-02-22 22:09:09 -0700[diff] [blame^]836static struct clk dpll4_m4_ck;
837
838static struct clk dpll4_m4_ck_34xx __initdata = {
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]839 .name = "dpll4_m4_ck",
840 .ops = &clkops_null,
841 .parent = &dpll4_ck,
842 .init = &omap2_init_clksel_parent,
843 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
844 .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK,
845 .clksel = div16_dpll4_clksel,
846 .clkdm_name = "dpll4_clkdm",
847 .recalc = &omap2_clksel_recalc,
848 .set_rate = &omap2_clksel_set_rate,
849 .round_rate = &omap2_clksel_round_rate,
850};
851
Vishwanath BS678bc9a2010-02-22 22:09:09 -0700[diff] [blame^]852static struct clk dpll4_m4_ck_3630 __initdata = {
853 .name = "dpll4_m4_ck",
854 .ops = &clkops_null,
855 .parent = &dpll4_ck,
856 .init = &omap2_init_clksel_parent,
857 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
858 .clksel_mask = OMAP3630_CLKSEL_DSS1_MASK,
859 .clksel = div32_dpll4_clksel,
860 .clkdm_name = "dpll4_clkdm",
861 .recalc = &omap2_clksel_recalc,
862 .set_rate = &omap2_clksel_set_rate,
863 .round_rate = &omap2_clksel_round_rate,
864};
865
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]866/* The PWRDN bit is apparently only available on 3430ES2 and above */
867static struct clk dpll4_m4x2_ck = {
868 .name = "dpll4_m4x2_ck",
869 .ops = &clkops_omap2_dflt_wait,
870 .parent = &dpll4_m4_ck,
871 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
872 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
873 .flags = INVERT_ENABLE,
874 .clkdm_name = "dpll4_clkdm",
875 .recalc = &omap3_clkoutx2_recalc,
876};
877
878/* This virtual clock is the source for dpll4_m5x2_ck */
Vishwanath BS678bc9a2010-02-22 22:09:09 -0700[diff] [blame^]879static struct clk dpll4_m5_ck;
880
881static struct clk dpll4_m5_ck_34xx __initdata = {
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]882 .name = "dpll4_m5_ck",
883 .ops = &clkops_null,
884 .parent = &dpll4_ck,
885 .init = &omap2_init_clksel_parent,
886 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
887 .clksel_mask = OMAP3430_CLKSEL_CAM_MASK,
888 .clksel = div16_dpll4_clksel,
889 .clkdm_name = "dpll4_clkdm",
Tuukka Toivonen3e3ee152010-01-08 15:23:08 -0700[diff] [blame]890 .set_rate = &omap2_clksel_set_rate,
891 .round_rate = &omap2_clksel_round_rate,
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]892 .recalc = &omap2_clksel_recalc,
893};
894
Vishwanath BS678bc9a2010-02-22 22:09:09 -0700[diff] [blame^]895static struct clk dpll4_m5_ck_3630 __initdata = {
896 .name = "dpll4_m5_ck",
897 .ops = &clkops_null,
898 .parent = &dpll4_ck,
899 .init = &omap2_init_clksel_parent,
900 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
901 .clksel_mask = OMAP3630_CLKSEL_CAM_MASK,
902 .clksel = div32_dpll4_clksel,
903 .clkdm_name = "dpll4_clkdm",
904 .recalc = &omap2_clksel_recalc,
905};
906
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]907/* The PWRDN bit is apparently only available on 3430ES2 and above */
908static struct clk dpll4_m5x2_ck = {
909 .name = "dpll4_m5x2_ck",
910 .ops = &clkops_omap2_dflt_wait,
911 .parent = &dpll4_m5_ck,
912 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
913 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
914 .flags = INVERT_ENABLE,
915 .clkdm_name = "dpll4_clkdm",
916 .recalc = &omap3_clkoutx2_recalc,
917};
918
919/* This virtual clock is the source for dpll4_m6x2_ck */
Vishwanath BS678bc9a2010-02-22 22:09:09 -0700[diff] [blame^]920static struct clk dpll4_m6_ck;
921
922static struct clk dpll4_m6_ck_34xx __initdata = {
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]923 .name = "dpll4_m6_ck",
924 .ops = &clkops_null,
925 .parent = &dpll4_ck,
926 .init = &omap2_init_clksel_parent,
927 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
928 .clksel_mask = OMAP3430_DIV_DPLL4_MASK,
929 .clksel = div16_dpll4_clksel,
930 .clkdm_name = "dpll4_clkdm",
931 .recalc = &omap2_clksel_recalc,
932};
933
Vishwanath BS678bc9a2010-02-22 22:09:09 -0700[diff] [blame^]934static struct clk dpll4_m6_ck_3630 __initdata = {
935 .name = "dpll4_m6_ck",
936 .ops = &clkops_null,
937 .parent = &dpll4_ck,
938 .init = &omap2_init_clksel_parent,
939 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
940 .clksel_mask = OMAP3630_DIV_DPLL4_MASK,
941 .clksel = div32_dpll4_clksel,
942 .clkdm_name = "dpll4_clkdm",
943 .recalc = &omap2_clksel_recalc,
944};
945
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]946/* The PWRDN bit is apparently only available on 3430ES2 and above */
947static struct clk dpll4_m6x2_ck = {
948 .name = "dpll4_m6x2_ck",
949 .ops = &clkops_omap2_dflt_wait,
950 .parent = &dpll4_m6_ck,
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]951 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
952 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
953 .flags = INVERT_ENABLE,
954 .clkdm_name = "dpll4_clkdm",
955 .recalc = &omap3_clkoutx2_recalc,
956};
957
958static struct clk emu_per_alwon_ck = {
959 .name = "emu_per_alwon_ck",
960 .ops = &clkops_null,
961 .parent = &dpll4_m6x2_ck,
962 .clkdm_name = "dpll4_clkdm",
963 .recalc = &followparent_recalc,
964};
965
966/* DPLL5 */
967/* Supplies 120MHz clock, USIM source clock */
968/* Type: DPLL */
969/* 3430ES2 only */
970static struct dpll_data dpll5_dd = {
971 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
972 .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
973 .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
974 .clk_bypass = &sys_ck,
975 .clk_ref = &sys_ck,
976 .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
977 .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
978 .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
979 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
980 .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
981 .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
982 .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
983 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
984 .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
985 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
986 .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
987 .max_multiplier = OMAP3_MAX_DPLL_MULT,
988 .min_divider = 1,
989 .max_divider = OMAP3_MAX_DPLL_DIV,
990 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
991};
992
993static struct clk dpll5_ck = {
994 .name = "dpll5_ck",
Tony Lindgren47512272010-02-15 09:27:25 -0800[diff] [blame]995 .ops = &omap3_clkops_noncore_dpll_ops,
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]996 .parent = &sys_ck,
997 .dpll_data = &dpll5_dd,
998 .round_rate = &omap2_dpll_round_rate,
999 .set_rate = &omap3_noncore_dpll_set_rate,
1000 .clkdm_name = "dpll5_clkdm",
1001 .recalc = &omap3_dpll_recalc,
1002};
1003
1004static const struct clksel div16_dpll5_clksel[] = {
1005 { .parent = &dpll5_ck, .rates = div16_dpll_rates },
1006 { .parent = NULL }
1007};
1008
1009static struct clk dpll5_m2_ck = {
1010 .name = "dpll5_m2_ck",
1011 .ops = &clkops_null,
1012 .parent = &dpll5_ck,
1013 .init = &omap2_init_clksel_parent,
1014 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
1015 .clksel_mask = OMAP3430ES2_DIV_120M_MASK,
1016 .clksel = div16_dpll5_clksel,
1017 .clkdm_name = "dpll5_clkdm",
1018 .recalc = &omap2_clksel_recalc,
1019};
1020
1021/* CM EXTERNAL CLOCK OUTPUTS */
1022
1023static const struct clksel_rate clkout2_src_core_rates[] = {
1024 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1025 { .div = 0 }
1026};
1027
1028static const struct clksel_rate clkout2_src_sys_rates[] = {
1029 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1030 { .div = 0 }
1031};
1032
1033static const struct clksel_rate clkout2_src_96m_rates[] = {
1034 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
1035 { .div = 0 }
1036};
1037
1038static const struct clksel_rate clkout2_src_54m_rates[] = {
1039 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1040 { .div = 0 }
1041};
1042
1043static const struct clksel clkout2_src_clksel[] = {
1044 { .parent = &core_ck, .rates = clkout2_src_core_rates },
1045 { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
1046 { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates },
1047 { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
1048 { .parent = NULL }
1049};
1050
1051static struct clk clkout2_src_ck = {
1052 .name = "clkout2_src_ck",
1053 .ops = &clkops_omap2_dflt,
1054 .init = &omap2_init_clksel_parent,
1055 .enable_reg = OMAP3430_CM_CLKOUT_CTRL,
1056 .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT,
1057 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
1058 .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK,
1059 .clksel = clkout2_src_clksel,
1060 .clkdm_name = "core_clkdm",
1061 .recalc = &omap2_clksel_recalc,
1062};
1063
1064static const struct clksel_rate sys_clkout2_rates[] = {
1065 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1066 { .div = 2, .val = 1, .flags = RATE_IN_343X },
1067 { .div = 4, .val = 2, .flags = RATE_IN_343X },
1068 { .div = 8, .val = 3, .flags = RATE_IN_343X },
1069 { .div = 16, .val = 4, .flags = RATE_IN_343X },
1070 { .div = 0 },
1071};
1072
1073static const struct clksel sys_clkout2_clksel[] = {
1074 { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
1075 { .parent = NULL },
1076};
1077
1078static struct clk sys_clkout2 = {
1079 .name = "sys_clkout2",
1080 .ops = &clkops_null,
1081 .init = &omap2_init_clksel_parent,
1082 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
1083 .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK,
1084 .clksel = sys_clkout2_clksel,
1085 .recalc = &omap2_clksel_recalc,
1086};
1087
1088/* CM OUTPUT CLOCKS */
1089
1090static struct clk corex2_fck = {
1091 .name = "corex2_fck",
1092 .ops = &clkops_null,
1093 .parent = &dpll3_m2x2_ck,
1094 .recalc = &followparent_recalc,
1095};
1096
1097/* DPLL power domain clock controls */
1098
1099static const struct clksel_rate div4_rates[] = {
1100 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1101 { .div = 2, .val = 2, .flags = RATE_IN_343X },
1102 { .div = 4, .val = 4, .flags = RATE_IN_343X },
1103 { .div = 0 }
1104};
1105
1106static const struct clksel div4_core_clksel[] = {
1107 { .parent = &core_ck, .rates = div4_rates },
1108 { .parent = NULL }
1109};
1110
1111/*
1112 * REVISIT: Are these in DPLL power domain or CM power domain? docs
1113 * may be inconsistent here?
1114 */
1115static struct clk dpll1_fck = {
1116 .name = "dpll1_fck",
1117 .ops = &clkops_null,
1118 .parent = &core_ck,
1119 .init = &omap2_init_clksel_parent,
1120 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1121 .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK,
1122 .clksel = div4_core_clksel,
1123 .recalc = &omap2_clksel_recalc,
1124};
1125
1126static struct clk mpu_ck = {
1127 .name = "mpu_ck",
1128 .ops = &clkops_null,
1129 .parent = &dpll1_x2m2_ck,
1130 .clkdm_name = "mpu_clkdm",
1131 .recalc = &followparent_recalc,
1132};
1133
1134/* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1135static const struct clksel_rate arm_fck_rates[] = {
1136 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1137 { .div = 2, .val = 1, .flags = RATE_IN_343X },
1138 { .div = 0 },
1139};
1140
1141static const struct clksel arm_fck_clksel[] = {
1142 { .parent = &mpu_ck, .rates = arm_fck_rates },
1143 { .parent = NULL }
1144};
1145
1146static struct clk arm_fck = {
1147 .name = "arm_fck",
1148 .ops = &clkops_null,
1149 .parent = &mpu_ck,
1150 .init = &omap2_init_clksel_parent,
1151 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1152 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
1153 .clksel = arm_fck_clksel,
1154 .clkdm_name = "mpu_clkdm",
1155 .recalc = &omap2_clksel_recalc,
1156};
1157
1158/* XXX What about neon_clkdm ? */
1159
1160/*
1161 * REVISIT: This clock is never specifically defined in the 3430 TRM,
1162 * although it is referenced - so this is a guess
1163 */
1164static struct clk emu_mpu_alwon_ck = {
1165 .name = "emu_mpu_alwon_ck",
1166 .ops = &clkops_null,
1167 .parent = &mpu_ck,
1168 .recalc = &followparent_recalc,
1169};
1170
1171static struct clk dpll2_fck = {
1172 .name = "dpll2_fck",
1173 .ops = &clkops_null,
1174 .parent = &core_ck,
1175 .init = &omap2_init_clksel_parent,
1176 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1177 .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK,
1178 .clksel = div4_core_clksel,
1179 .recalc = &omap2_clksel_recalc,
1180};
1181
1182static struct clk iva2_ck = {
1183 .name = "iva2_ck",
1184 .ops = &clkops_omap2_dflt_wait,
1185 .parent = &dpll2_m2_ck,
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]1186 .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1187 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1188 .clkdm_name = "iva2_clkdm",
1189 .recalc = &followparent_recalc,
1190};
1191
1192/* Common interface clocks */
1193
1194static const struct clksel div2_core_clksel[] = {
1195 { .parent = &core_ck, .rates = div2_rates },
1196 { .parent = NULL }
1197};
1198
1199static struct clk l3_ick = {
1200 .name = "l3_ick",
1201 .ops = &clkops_null,
1202 .parent = &core_ck,
1203 .init = &omap2_init_clksel_parent,
1204 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1205 .clksel_mask = OMAP3430_CLKSEL_L3_MASK,
1206 .clksel = div2_core_clksel,
1207 .clkdm_name = "core_l3_clkdm",
1208 .recalc = &omap2_clksel_recalc,
1209};
1210
1211static const struct clksel div2_l3_clksel[] = {
1212 { .parent = &l3_ick, .rates = div2_rates },
1213 { .parent = NULL }
1214};
1215
1216static struct clk l4_ick = {
1217 .name = "l4_ick",
1218 .ops = &clkops_null,
1219 .parent = &l3_ick,
1220 .init = &omap2_init_clksel_parent,
1221 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1222 .clksel_mask = OMAP3430_CLKSEL_L4_MASK,
1223 .clksel = div2_l3_clksel,
1224 .clkdm_name = "core_l4_clkdm",
1225 .recalc = &omap2_clksel_recalc,
1226
1227};
1228
1229static const struct clksel div2_l4_clksel[] = {
1230 { .parent = &l4_ick, .rates = div2_rates },
1231 { .parent = NULL }
1232};
1233
1234static struct clk rm_ick = {
1235 .name = "rm_ick",
1236 .ops = &clkops_null,
1237 .parent = &l4_ick,
1238 .init = &omap2_init_clksel_parent,
1239 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1240 .clksel_mask = OMAP3430_CLKSEL_RM_MASK,
1241 .clksel = div2_l4_clksel,
1242 .recalc = &omap2_clksel_recalc,
1243};
1244
1245/* GFX power domain */
1246
1247/* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1248
1249static const struct clksel gfx_l3_clksel[] = {
1250 { .parent = &l3_ick, .rates = gfx_l3_rates },
1251 { .parent = NULL }
1252};
1253
1254/* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1255static struct clk gfx_l3_ck = {
1256 .name = "gfx_l3_ck",
1257 .ops = &clkops_omap2_dflt_wait,
1258 .parent = &l3_ick,
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]1259 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1260 .enable_bit = OMAP_EN_GFX_SHIFT,
1261 .recalc = &followparent_recalc,
1262};
1263
1264static struct clk gfx_l3_fck = {
1265 .name = "gfx_l3_fck",
1266 .ops = &clkops_null,
1267 .parent = &gfx_l3_ck,
1268 .init = &omap2_init_clksel_parent,
1269 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1270 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1271 .clksel = gfx_l3_clksel,
1272 .clkdm_name = "gfx_3430es1_clkdm",
1273 .recalc = &omap2_clksel_recalc,
1274};
1275
1276static struct clk gfx_l3_ick = {
1277 .name = "gfx_l3_ick",
1278 .ops = &clkops_null,
1279 .parent = &gfx_l3_ck,
1280 .clkdm_name = "gfx_3430es1_clkdm",
1281 .recalc = &followparent_recalc,
1282};
1283
1284static struct clk gfx_cg1_ck = {
1285 .name = "gfx_cg1_ck",
1286 .ops = &clkops_omap2_dflt_wait,
1287 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1288 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1289 .enable_bit = OMAP3430ES1_EN_2D_SHIFT,
1290 .clkdm_name = "gfx_3430es1_clkdm",
1291 .recalc = &followparent_recalc,
1292};
1293
1294static struct clk gfx_cg2_ck = {
1295 .name = "gfx_cg2_ck",
1296 .ops = &clkops_omap2_dflt_wait,
1297 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1298 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1299 .enable_bit = OMAP3430ES1_EN_3D_SHIFT,
1300 .clkdm_name = "gfx_3430es1_clkdm",
1301 .recalc = &followparent_recalc,
1302};
1303
1304/* SGX power domain - 3430ES2 only */
1305
1306static const struct clksel_rate sgx_core_rates[] = {
1307 { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1308 { .div = 4, .val = 1, .flags = RATE_IN_343X },
1309 { .div = 6, .val = 2, .flags = RATE_IN_343X },
1310 { .div = 0 },
1311};
1312
1313static const struct clksel_rate sgx_96m_rates[] = {
1314 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1315 { .div = 0 },
1316};
1317
1318static const struct clksel sgx_clksel[] = {
1319 { .parent = &core_ck, .rates = sgx_core_rates },
1320 { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1321 { .parent = NULL },
1322};
1323
1324static struct clk sgx_fck = {
1325 .name = "sgx_fck",
1326 .ops = &clkops_omap2_dflt_wait,
1327 .init = &omap2_init_clksel_parent,
1328 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1329 .enable_bit = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
1330 .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1331 .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK,
1332 .clksel = sgx_clksel,
1333 .clkdm_name = "sgx_clkdm",
1334 .recalc = &omap2_clksel_recalc,
1335};
1336
1337static struct clk sgx_ick = {
1338 .name = "sgx_ick",
1339 .ops = &clkops_omap2_dflt_wait,
1340 .parent = &l3_ick,
1341 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1342 .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
1343 .clkdm_name = "sgx_clkdm",
1344 .recalc = &followparent_recalc,
1345};
1346
1347/* CORE power domain */
1348
1349static struct clk d2d_26m_fck = {
1350 .name = "d2d_26m_fck",
1351 .ops = &clkops_omap2_dflt_wait,
1352 .parent = &sys_ck,
1353 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1354 .enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
1355 .clkdm_name = "d2d_clkdm",
1356 .recalc = &followparent_recalc,
1357};
1358
1359static struct clk modem_fck = {
1360 .name = "modem_fck",
1361 .ops = &clkops_omap2_dflt_wait,
1362 .parent = &sys_ck,
1363 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1364 .enable_bit = OMAP3430_EN_MODEM_SHIFT,
1365 .clkdm_name = "d2d_clkdm",
1366 .recalc = &followparent_recalc,
1367};
1368
1369static struct clk sad2d_ick = {
1370 .name = "sad2d_ick",
1371 .ops = &clkops_omap2_dflt_wait,
1372 .parent = &l3_ick,
1373 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1374 .enable_bit = OMAP3430_EN_SAD2D_SHIFT,
1375 .clkdm_name = "d2d_clkdm",
1376 .recalc = &followparent_recalc,
1377};
1378
1379static struct clk mad2d_ick = {
1380 .name = "mad2d_ick",
1381 .ops = &clkops_omap2_dflt_wait,
1382 .parent = &l3_ick,
1383 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1384 .enable_bit = OMAP3430_EN_MAD2D_SHIFT,
1385 .clkdm_name = "d2d_clkdm",
1386 .recalc = &followparent_recalc,
1387};
1388
1389static const struct clksel omap343x_gpt_clksel[] = {
1390 { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1391 { .parent = &sys_ck, .rates = gpt_sys_rates },
1392 { .parent = NULL}
1393};
1394
1395static struct clk gpt10_fck = {
1396 .name = "gpt10_fck",
1397 .ops = &clkops_omap2_dflt_wait,
1398 .parent = &sys_ck,
1399 .init = &omap2_init_clksel_parent,
1400 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1401 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1402 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1403 .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK,
1404 .clksel = omap343x_gpt_clksel,
1405 .clkdm_name = "core_l4_clkdm",
1406 .recalc = &omap2_clksel_recalc,
1407};
1408
1409static struct clk gpt11_fck = {
1410 .name = "gpt11_fck",
1411 .ops = &clkops_omap2_dflt_wait,
1412 .parent = &sys_ck,
1413 .init = &omap2_init_clksel_parent,
1414 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1415 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1416 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1417 .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK,
1418 .clksel = omap343x_gpt_clksel,
1419 .clkdm_name = "core_l4_clkdm",
1420 .recalc = &omap2_clksel_recalc,
1421};
1422
1423static struct clk cpefuse_fck = {
1424 .name = "cpefuse_fck",
1425 .ops = &clkops_omap2_dflt,
1426 .parent = &sys_ck,
1427 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1428 .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1429 .recalc = &followparent_recalc,
1430};
1431
1432static struct clk ts_fck = {
1433 .name = "ts_fck",
1434 .ops = &clkops_omap2_dflt,
1435 .parent = &omap_32k_fck,
1436 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1437 .enable_bit = OMAP3430ES2_EN_TS_SHIFT,
1438 .recalc = &followparent_recalc,
1439};
1440
1441static struct clk usbtll_fck = {
1442 .name = "usbtll_fck",
1443 .ops = &clkops_omap2_dflt,
1444 .parent = &dpll5_m2_ck,
1445 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1446 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1447 .recalc = &followparent_recalc,
1448};
1449
1450/* CORE 96M FCLK-derived clocks */
1451
1452static struct clk core_96m_fck = {
1453 .name = "core_96m_fck",
1454 .ops = &clkops_null,
1455 .parent = &omap_96m_fck,
1456 .clkdm_name = "core_l4_clkdm",
1457 .recalc = &followparent_recalc,
1458};
1459
1460static struct clk mmchs3_fck = {
1461 .name = "mmchs_fck",
1462 .ops = &clkops_omap2_dflt_wait,
1463 .id = 2,
1464 .parent = &core_96m_fck,
1465 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1466 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1467 .clkdm_name = "core_l4_clkdm",
1468 .recalc = &followparent_recalc,
1469};
1470
1471static struct clk mmchs2_fck = {
1472 .name = "mmchs_fck",
1473 .ops = &clkops_omap2_dflt_wait,
1474 .id = 1,
1475 .parent = &core_96m_fck,
1476 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1477 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1478 .clkdm_name = "core_l4_clkdm",
1479 .recalc = &followparent_recalc,
1480};
1481
1482static struct clk mspro_fck = {
1483 .name = "mspro_fck",
1484 .ops = &clkops_omap2_dflt_wait,
1485 .parent = &core_96m_fck,
1486 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1487 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1488 .clkdm_name = "core_l4_clkdm",
1489 .recalc = &followparent_recalc,
1490};
1491
1492static struct clk mmchs1_fck = {
1493 .name = "mmchs_fck",
1494 .ops = &clkops_omap2_dflt_wait,
1495 .parent = &core_96m_fck,
1496 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1497 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1498 .clkdm_name = "core_l4_clkdm",
1499 .recalc = &followparent_recalc,
1500};
1501
1502static struct clk i2c3_fck = {
1503 .name = "i2c_fck",
1504 .ops = &clkops_omap2_dflt_wait,
1505 .id = 3,
1506 .parent = &core_96m_fck,
1507 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1508 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1509 .clkdm_name = "core_l4_clkdm",
1510 .recalc = &followparent_recalc,
1511};
1512
1513static struct clk i2c2_fck = {
1514 .name = "i2c_fck",
1515 .ops = &clkops_omap2_dflt_wait,
1516 .id = 2,
1517 .parent = &core_96m_fck,
1518 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1519 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1520 .clkdm_name = "core_l4_clkdm",
1521 .recalc = &followparent_recalc,
1522};
1523
1524static struct clk i2c1_fck = {
1525 .name = "i2c_fck",
1526 .ops = &clkops_omap2_dflt_wait,
1527 .id = 1,
1528 .parent = &core_96m_fck,
1529 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1530 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1531 .clkdm_name = "core_l4_clkdm",
1532 .recalc = &followparent_recalc,
1533};
1534
1535/*
1536 * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1537 * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1538 */
1539static const struct clksel_rate common_mcbsp_96m_rates[] = {
1540 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1541 { .div = 0 }
1542};
1543
1544static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1545 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1546 { .div = 0 }
1547};
1548
1549static const struct clksel mcbsp_15_clksel[] = {
1550 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1551 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1552 { .parent = NULL }
1553};
1554
1555static struct clk mcbsp5_fck = {
1556 .name = "mcbsp_fck",
1557 .ops = &clkops_omap2_dflt_wait,
1558 .id = 5,
1559 .init = &omap2_init_clksel_parent,
1560 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1561 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
1562 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1563 .clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
1564 .clksel = mcbsp_15_clksel,
1565 .clkdm_name = "core_l4_clkdm",
1566 .recalc = &omap2_clksel_recalc,
1567};
1568
1569static struct clk mcbsp1_fck = {
1570 .name = "mcbsp_fck",
1571 .ops = &clkops_omap2_dflt_wait,
1572 .id = 1,
1573 .init = &omap2_init_clksel_parent,
1574 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1575 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
1576 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1577 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
1578 .clksel = mcbsp_15_clksel,
1579 .clkdm_name = "core_l4_clkdm",
1580 .recalc = &omap2_clksel_recalc,
1581};
1582
1583/* CORE_48M_FCK-derived clocks */
1584
1585static struct clk core_48m_fck = {
1586 .name = "core_48m_fck",
1587 .ops = &clkops_null,
1588 .parent = &omap_48m_fck,
1589 .clkdm_name = "core_l4_clkdm",
1590 .recalc = &followparent_recalc,
1591};
1592
1593static struct clk mcspi4_fck = {
1594 .name = "mcspi_fck",
1595 .ops = &clkops_omap2_dflt_wait,
1596 .id = 4,
1597 .parent = &core_48m_fck,
1598 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1599 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1600 .recalc = &followparent_recalc,
1601};
1602
1603static struct clk mcspi3_fck = {
1604 .name = "mcspi_fck",
1605 .ops = &clkops_omap2_dflt_wait,
1606 .id = 3,
1607 .parent = &core_48m_fck,
1608 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1609 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1610 .recalc = &followparent_recalc,
1611};
1612
1613static struct clk mcspi2_fck = {
1614 .name = "mcspi_fck",
1615 .ops = &clkops_omap2_dflt_wait,
1616 .id = 2,
1617 .parent = &core_48m_fck,
1618 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1619 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1620 .recalc = &followparent_recalc,
1621};
1622
1623static struct clk mcspi1_fck = {
1624 .name = "mcspi_fck",
1625 .ops = &clkops_omap2_dflt_wait,
1626 .id = 1,
1627 .parent = &core_48m_fck,
1628 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1629 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1630 .recalc = &followparent_recalc,
1631};
1632
1633static struct clk uart2_fck = {
1634 .name = "uart2_fck",
1635 .ops = &clkops_omap2_dflt_wait,
1636 .parent = &core_48m_fck,
1637 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1638 .enable_bit = OMAP3430_EN_UART2_SHIFT,
Kevin Hilman9b5bc5f2010-01-08 15:23:06 -0700[diff] [blame]1639 .clkdm_name = "core_l4_clkdm",
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]1640 .recalc = &followparent_recalc,
1641};
1642
1643static struct clk uart1_fck = {
1644 .name = "uart1_fck",
1645 .ops = &clkops_omap2_dflt_wait,
1646 .parent = &core_48m_fck,
1647 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1648 .enable_bit = OMAP3430_EN_UART1_SHIFT,
Kevin Hilman9b5bc5f2010-01-08 15:23:06 -0700[diff] [blame]1649 .clkdm_name = "core_l4_clkdm",
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]1650 .recalc = &followparent_recalc,
1651};
1652
1653static struct clk fshostusb_fck = {
1654 .name = "fshostusb_fck",
1655 .ops = &clkops_omap2_dflt_wait,
1656 .parent = &core_48m_fck,
1657 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1658 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1659 .recalc = &followparent_recalc,
1660};
1661
1662/* CORE_12M_FCK based clocks */
1663
1664static struct clk core_12m_fck = {
1665 .name = "core_12m_fck",
1666 .ops = &clkops_null,
1667 .parent = &omap_12m_fck,
1668 .clkdm_name = "core_l4_clkdm",
1669 .recalc = &followparent_recalc,
1670};
1671
1672static struct clk hdq_fck = {
1673 .name = "hdq_fck",
1674 .ops = &clkops_omap2_dflt_wait,
1675 .parent = &core_12m_fck,
1676 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1677 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1678 .recalc = &followparent_recalc,
1679};
1680
1681/* DPLL3-derived clock */
1682
1683static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1684 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1685 { .div = 2, .val = 2, .flags = RATE_IN_343X },
1686 { .div = 3, .val = 3, .flags = RATE_IN_343X },
1687 { .div = 4, .val = 4, .flags = RATE_IN_343X },
1688 { .div = 6, .val = 6, .flags = RATE_IN_343X },
1689 { .div = 8, .val = 8, .flags = RATE_IN_343X },
1690 { .div = 0 }
1691};
1692
1693static const struct clksel ssi_ssr_clksel[] = {
1694 { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1695 { .parent = NULL }
1696};
1697
1698static struct clk ssi_ssr_fck_3430es1 = {
1699 .name = "ssi_ssr_fck",
1700 .ops = &clkops_omap2_dflt,
1701 .init = &omap2_init_clksel_parent,
1702 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1703 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1704 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1705 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1706 .clksel = ssi_ssr_clksel,
1707 .clkdm_name = "core_l4_clkdm",
1708 .recalc = &omap2_clksel_recalc,
1709};
1710
1711static struct clk ssi_ssr_fck_3430es2 = {
1712 .name = "ssi_ssr_fck",
1713 .ops = &clkops_omap3430es2_ssi_wait,
1714 .init = &omap2_init_clksel_parent,
1715 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1716 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1717 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1718 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1719 .clksel = ssi_ssr_clksel,
1720 .clkdm_name = "core_l4_clkdm",
1721 .recalc = &omap2_clksel_recalc,
1722};
1723
1724static struct clk ssi_sst_fck_3430es1 = {
1725 .name = "ssi_sst_fck",
1726 .ops = &clkops_null,
1727 .parent = &ssi_ssr_fck_3430es1,
1728 .fixed_div = 2,
Paul Walmsleye9b98f62010-01-26 20:12:57 -0700[diff] [blame]1729 .recalc = &omap_fixed_divisor_recalc,
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]1730};
1731
1732static struct clk ssi_sst_fck_3430es2 = {
1733 .name = "ssi_sst_fck",
1734 .ops = &clkops_null,
1735 .parent = &ssi_ssr_fck_3430es2,
1736 .fixed_div = 2,
Paul Walmsleye9b98f62010-01-26 20:12:57 -0700[diff] [blame]1737 .recalc = &omap_fixed_divisor_recalc,
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]1738};
1739
1740
1741
1742/* CORE_L3_ICK based clocks */
1743
1744/*
1745 * XXX must add clk_enable/clk_disable for these if standard code won't
1746 * handle it
1747 */
1748static struct clk core_l3_ick = {
1749 .name = "core_l3_ick",
1750 .ops = &clkops_null,
1751 .parent = &l3_ick,
1752 .clkdm_name = "core_l3_clkdm",
1753 .recalc = &followparent_recalc,
1754};
1755
1756static struct clk hsotgusb_ick_3430es1 = {
1757 .name = "hsotgusb_ick",
1758 .ops = &clkops_omap2_dflt,
1759 .parent = &core_l3_ick,
1760 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1761 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1762 .clkdm_name = "core_l3_clkdm",
1763 .recalc = &followparent_recalc,
1764};
1765
1766static struct clk hsotgusb_ick_3430es2 = {
1767 .name = "hsotgusb_ick",
1768 .ops = &clkops_omap3430es2_hsotgusb_wait,
1769 .parent = &core_l3_ick,
1770 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1771 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1772 .clkdm_name = "core_l3_clkdm",
1773 .recalc = &followparent_recalc,
1774};
1775
1776static struct clk sdrc_ick = {
1777 .name = "sdrc_ick",
1778 .ops = &clkops_omap2_dflt_wait,
1779 .parent = &core_l3_ick,
1780 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1781 .enable_bit = OMAP3430_EN_SDRC_SHIFT,
1782 .flags = ENABLE_ON_INIT,
1783 .clkdm_name = "core_l3_clkdm",
1784 .recalc = &followparent_recalc,
1785};
1786
1787static struct clk gpmc_fck = {
1788 .name = "gpmc_fck",
1789 .ops = &clkops_null,
1790 .parent = &core_l3_ick,
1791 .flags = ENABLE_ON_INIT, /* huh? */
1792 .clkdm_name = "core_l3_clkdm",
1793 .recalc = &followparent_recalc,
1794};
1795
1796/* SECURITY_L3_ICK based clocks */
1797
1798static struct clk security_l3_ick = {
1799 .name = "security_l3_ick",
1800 .ops = &clkops_null,
1801 .parent = &l3_ick,
1802 .recalc = &followparent_recalc,
1803};
1804
1805static struct clk pka_ick = {
1806 .name = "pka_ick",
1807 .ops = &clkops_omap2_dflt_wait,
1808 .parent = &security_l3_ick,
1809 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1810 .enable_bit = OMAP3430_EN_PKA_SHIFT,
1811 .recalc = &followparent_recalc,
1812};
1813
1814/* CORE_L4_ICK based clocks */
1815
1816static struct clk core_l4_ick = {
1817 .name = "core_l4_ick",
1818 .ops = &clkops_null,
1819 .parent = &l4_ick,
1820 .clkdm_name = "core_l4_clkdm",
1821 .recalc = &followparent_recalc,
1822};
1823
1824static struct clk usbtll_ick = {
1825 .name = "usbtll_ick",
1826 .ops = &clkops_omap2_dflt_wait,
1827 .parent = &core_l4_ick,
1828 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1829 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1830 .clkdm_name = "core_l4_clkdm",
1831 .recalc = &followparent_recalc,
1832};
1833
1834static struct clk mmchs3_ick = {
1835 .name = "mmchs_ick",
1836 .ops = &clkops_omap2_dflt_wait,
1837 .id = 2,
1838 .parent = &core_l4_ick,
1839 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1840 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1841 .clkdm_name = "core_l4_clkdm",
1842 .recalc = &followparent_recalc,
1843};
1844
1845/* Intersystem Communication Registers - chassis mode only */
1846static struct clk icr_ick = {
1847 .name = "icr_ick",
1848 .ops = &clkops_omap2_dflt_wait,
1849 .parent = &core_l4_ick,
1850 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1851 .enable_bit = OMAP3430_EN_ICR_SHIFT,
1852 .clkdm_name = "core_l4_clkdm",
1853 .recalc = &followparent_recalc,
1854};
1855
1856static struct clk aes2_ick = {
1857 .name = "aes2_ick",
1858 .ops = &clkops_omap2_dflt_wait,
1859 .parent = &core_l4_ick,
1860 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1861 .enable_bit = OMAP3430_EN_AES2_SHIFT,
1862 .clkdm_name = "core_l4_clkdm",
1863 .recalc = &followparent_recalc,
1864};
1865
1866static struct clk sha12_ick = {
1867 .name = "sha12_ick",
1868 .ops = &clkops_omap2_dflt_wait,
1869 .parent = &core_l4_ick,
1870 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1871 .enable_bit = OMAP3430_EN_SHA12_SHIFT,
1872 .clkdm_name = "core_l4_clkdm",
1873 .recalc = &followparent_recalc,
1874};
1875
1876static struct clk des2_ick = {
1877 .name = "des2_ick",
1878 .ops = &clkops_omap2_dflt_wait,
1879 .parent = &core_l4_ick,
1880 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1881 .enable_bit = OMAP3430_EN_DES2_SHIFT,
1882 .clkdm_name = "core_l4_clkdm",
1883 .recalc = &followparent_recalc,
1884};
1885
1886static struct clk mmchs2_ick = {
1887 .name = "mmchs_ick",
1888 .ops = &clkops_omap2_dflt_wait,
1889 .id = 1,
1890 .parent = &core_l4_ick,
1891 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1892 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1893 .clkdm_name = "core_l4_clkdm",
1894 .recalc = &followparent_recalc,
1895};
1896
1897static struct clk mmchs1_ick = {
1898 .name = "mmchs_ick",
1899 .ops = &clkops_omap2_dflt_wait,
1900 .parent = &core_l4_ick,
1901 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1902 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1903 .clkdm_name = "core_l4_clkdm",
1904 .recalc = &followparent_recalc,
1905};
1906
1907static struct clk mspro_ick = {
1908 .name = "mspro_ick",
1909 .ops = &clkops_omap2_dflt_wait,
1910 .parent = &core_l4_ick,
1911 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1912 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1913 .clkdm_name = "core_l4_clkdm",
1914 .recalc = &followparent_recalc,
1915};
1916
1917static struct clk hdq_ick = {
1918 .name = "hdq_ick",
1919 .ops = &clkops_omap2_dflt_wait,
1920 .parent = &core_l4_ick,
1921 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1922 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1923 .clkdm_name = "core_l4_clkdm",
1924 .recalc = &followparent_recalc,
1925};
1926
1927static struct clk mcspi4_ick = {
1928 .name = "mcspi_ick",
1929 .ops = &clkops_omap2_dflt_wait,
1930 .id = 4,
1931 .parent = &core_l4_ick,
1932 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1933 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1934 .clkdm_name = "core_l4_clkdm",
1935 .recalc = &followparent_recalc,
1936};
1937
1938static struct clk mcspi3_ick = {
1939 .name = "mcspi_ick",
1940 .ops = &clkops_omap2_dflt_wait,
1941 .id = 3,
1942 .parent = &core_l4_ick,
1943 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1944 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1945 .clkdm_name = "core_l4_clkdm",
1946 .recalc = &followparent_recalc,
1947};
1948
1949static struct clk mcspi2_ick = {
1950 .name = "mcspi_ick",
1951 .ops = &clkops_omap2_dflt_wait,
1952 .id = 2,
1953 .parent = &core_l4_ick,
1954 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1955 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1956 .clkdm_name = "core_l4_clkdm",
1957 .recalc = &followparent_recalc,
1958};
1959
1960static struct clk mcspi1_ick = {
1961 .name = "mcspi_ick",
1962 .ops = &clkops_omap2_dflt_wait,
1963 .id = 1,
1964 .parent = &core_l4_ick,
1965 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1966 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1967 .clkdm_name = "core_l4_clkdm",
1968 .recalc = &followparent_recalc,
1969};
1970
1971static struct clk i2c3_ick = {
1972 .name = "i2c_ick",
1973 .ops = &clkops_omap2_dflt_wait,
1974 .id = 3,
1975 .parent = &core_l4_ick,
1976 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1977 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1978 .clkdm_name = "core_l4_clkdm",
1979 .recalc = &followparent_recalc,
1980};
1981
1982static struct clk i2c2_ick = {
1983 .name = "i2c_ick",
1984 .ops = &clkops_omap2_dflt_wait,
1985 .id = 2,
1986 .parent = &core_l4_ick,
1987 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1988 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1989 .clkdm_name = "core_l4_clkdm",
1990 .recalc = &followparent_recalc,
1991};
1992
1993static struct clk i2c1_ick = {
1994 .name = "i2c_ick",
1995 .ops = &clkops_omap2_dflt_wait,
1996 .id = 1,
1997 .parent = &core_l4_ick,
1998 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1999 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
2000 .clkdm_name = "core_l4_clkdm",
2001 .recalc = &followparent_recalc,
2002};
2003
2004static struct clk uart2_ick = {
2005 .name = "uart2_ick",
2006 .ops = &clkops_omap2_dflt_wait,
2007 .parent = &core_l4_ick,
2008 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2009 .enable_bit = OMAP3430_EN_UART2_SHIFT,
2010 .clkdm_name = "core_l4_clkdm",
2011 .recalc = &followparent_recalc,
2012};
2013
2014static struct clk uart1_ick = {
2015 .name = "uart1_ick",
2016 .ops = &clkops_omap2_dflt_wait,
2017 .parent = &core_l4_ick,
2018 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2019 .enable_bit = OMAP3430_EN_UART1_SHIFT,
2020 .clkdm_name = "core_l4_clkdm",
2021 .recalc = &followparent_recalc,
2022};
2023
2024static struct clk gpt11_ick = {
2025 .name = "gpt11_ick",
2026 .ops = &clkops_omap2_dflt_wait,
2027 .parent = &core_l4_ick,
2028 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2029 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
2030 .clkdm_name = "core_l4_clkdm",
2031 .recalc = &followparent_recalc,
2032};
2033
2034static struct clk gpt10_ick = {
2035 .name = "gpt10_ick",
2036 .ops = &clkops_omap2_dflt_wait,
2037 .parent = &core_l4_ick,
2038 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2039 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
2040 .clkdm_name = "core_l4_clkdm",
2041 .recalc = &followparent_recalc,
2042};
2043
2044static struct clk mcbsp5_ick = {
2045 .name = "mcbsp_ick",
2046 .ops = &clkops_omap2_dflt_wait,
2047 .id = 5,
2048 .parent = &core_l4_ick,
2049 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2050 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
2051 .clkdm_name = "core_l4_clkdm",
2052 .recalc = &followparent_recalc,
2053};
2054
2055static struct clk mcbsp1_ick = {
2056 .name = "mcbsp_ick",
2057 .ops = &clkops_omap2_dflt_wait,
2058 .id = 1,
2059 .parent = &core_l4_ick,
2060 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2061 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
2062 .clkdm_name = "core_l4_clkdm",
2063 .recalc = &followparent_recalc,
2064};
2065
2066static struct clk fac_ick = {
2067 .name = "fac_ick",
2068 .ops = &clkops_omap2_dflt_wait,
2069 .parent = &core_l4_ick,
2070 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2071 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
2072 .clkdm_name = "core_l4_clkdm",
2073 .recalc = &followparent_recalc,
2074};
2075
2076static struct clk mailboxes_ick = {
2077 .name = "mailboxes_ick",
2078 .ops = &clkops_omap2_dflt_wait,
2079 .parent = &core_l4_ick,
2080 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2081 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2082 .clkdm_name = "core_l4_clkdm",
2083 .recalc = &followparent_recalc,
2084};
2085
2086static struct clk omapctrl_ick = {
2087 .name = "omapctrl_ick",
2088 .ops = &clkops_omap2_dflt_wait,
2089 .parent = &core_l4_ick,
2090 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2091 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
2092 .flags = ENABLE_ON_INIT,
2093 .recalc = &followparent_recalc,
2094};
2095
2096/* SSI_L4_ICK based clocks */
2097
2098static struct clk ssi_l4_ick = {
2099 .name = "ssi_l4_ick",
2100 .ops = &clkops_null,
2101 .parent = &l4_ick,
2102 .clkdm_name = "core_l4_clkdm",
2103 .recalc = &followparent_recalc,
2104};
2105
2106static struct clk ssi_ick_3430es1 = {
2107 .name = "ssi_ick",
2108 .ops = &clkops_omap2_dflt,
2109 .parent = &ssi_l4_ick,
2110 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2111 .enable_bit = OMAP3430_EN_SSI_SHIFT,
2112 .clkdm_name = "core_l4_clkdm",
2113 .recalc = &followparent_recalc,
2114};
2115
2116static struct clk ssi_ick_3430es2 = {
2117 .name = "ssi_ick",
2118 .ops = &clkops_omap3430es2_ssi_wait,
2119 .parent = &ssi_l4_ick,
2120 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2121 .enable_bit = OMAP3430_EN_SSI_SHIFT,
2122 .clkdm_name = "core_l4_clkdm",
2123 .recalc = &followparent_recalc,
2124};
2125
2126/* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2127 * but l4_ick makes more sense to me */
2128
2129static const struct clksel usb_l4_clksel[] = {
2130 { .parent = &l4_ick, .rates = div2_rates },
2131 { .parent = NULL },
2132};
2133
2134static struct clk usb_l4_ick = {
2135 .name = "usb_l4_ick",
2136 .ops = &clkops_omap2_dflt_wait,
2137 .parent = &l4_ick,
2138 .init = &omap2_init_clksel_parent,
2139 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2140 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2141 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2142 .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2143 .clksel = usb_l4_clksel,
2144 .recalc = &omap2_clksel_recalc,
2145};
2146
2147/* SECURITY_L4_ICK2 based clocks */
2148
2149static struct clk security_l4_ick2 = {
2150 .name = "security_l4_ick2",
2151 .ops = &clkops_null,
2152 .parent = &l4_ick,
2153 .recalc = &followparent_recalc,
2154};
2155
2156static struct clk aes1_ick = {
2157 .name = "aes1_ick",
2158 .ops = &clkops_omap2_dflt_wait,
2159 .parent = &security_l4_ick2,
2160 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2161 .enable_bit = OMAP3430_EN_AES1_SHIFT,
2162 .recalc = &followparent_recalc,
2163};
2164
2165static struct clk rng_ick = {
2166 .name = "rng_ick",
2167 .ops = &clkops_omap2_dflt_wait,
2168 .parent = &security_l4_ick2,
2169 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2170 .enable_bit = OMAP3430_EN_RNG_SHIFT,
2171 .recalc = &followparent_recalc,
2172};
2173
2174static struct clk sha11_ick = {
2175 .name = "sha11_ick",
2176 .ops = &clkops_omap2_dflt_wait,
2177 .parent = &security_l4_ick2,
2178 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2179 .enable_bit = OMAP3430_EN_SHA11_SHIFT,
2180 .recalc = &followparent_recalc,
2181};
2182
2183static struct clk des1_ick = {
2184 .name = "des1_ick",
2185 .ops = &clkops_omap2_dflt_wait,
2186 .parent = &security_l4_ick2,
2187 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2188 .enable_bit = OMAP3430_EN_DES1_SHIFT,
2189 .recalc = &followparent_recalc,
2190};
2191
2192/* DSS */
2193static struct clk dss1_alwon_fck_3430es1 = {
2194 .name = "dss1_alwon_fck",
2195 .ops = &clkops_omap2_dflt,
2196 .parent = &dpll4_m4x2_ck,
2197 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2198 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
2199 .clkdm_name = "dss_clkdm",
2200 .recalc = &followparent_recalc,
2201};
2202
2203static struct clk dss1_alwon_fck_3430es2 = {
2204 .name = "dss1_alwon_fck",
2205 .ops = &clkops_omap3430es2_dss_usbhost_wait,
2206 .parent = &dpll4_m4x2_ck,
2207 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2208 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
2209 .clkdm_name = "dss_clkdm",
2210 .recalc = &followparent_recalc,
2211};
2212
2213static struct clk dss_tv_fck = {
2214 .name = "dss_tv_fck",
2215 .ops = &clkops_omap2_dflt,
2216 .parent = &omap_54m_fck,
2217 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2218 .enable_bit = OMAP3430_EN_TV_SHIFT,
2219 .clkdm_name = "dss_clkdm",
2220 .recalc = &followparent_recalc,
2221};
2222
2223static struct clk dss_96m_fck = {
2224 .name = "dss_96m_fck",
2225 .ops = &clkops_omap2_dflt,
2226 .parent = &omap_96m_fck,
2227 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2228 .enable_bit = OMAP3430_EN_TV_SHIFT,
2229 .clkdm_name = "dss_clkdm",
2230 .recalc = &followparent_recalc,
2231};
2232
2233static struct clk dss2_alwon_fck = {
2234 .name = "dss2_alwon_fck",
2235 .ops = &clkops_omap2_dflt,
2236 .parent = &sys_ck,
2237 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2238 .enable_bit = OMAP3430_EN_DSS2_SHIFT,
2239 .clkdm_name = "dss_clkdm",
2240 .recalc = &followparent_recalc,
2241};
2242
2243static struct clk dss_ick_3430es1 = {
2244 /* Handles both L3 and L4 clocks */
2245 .name = "dss_ick",
2246 .ops = &clkops_omap2_dflt,
2247 .parent = &l4_ick,
2248 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2249 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2250 .clkdm_name = "dss_clkdm",
2251 .recalc = &followparent_recalc,
2252};
2253
2254static struct clk dss_ick_3430es2 = {
2255 /* Handles both L3 and L4 clocks */
2256 .name = "dss_ick",
2257 .ops = &clkops_omap3430es2_dss_usbhost_wait,
2258 .parent = &l4_ick,
2259 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2260 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2261 .clkdm_name = "dss_clkdm",
2262 .recalc = &followparent_recalc,
2263};
2264
2265/* CAM */
2266
2267static struct clk cam_mclk = {
2268 .name = "cam_mclk",
2269 .ops = &clkops_omap2_dflt,
2270 .parent = &dpll4_m5x2_ck,
2271 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2272 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2273 .clkdm_name = "cam_clkdm",
2274 .recalc = &followparent_recalc,
2275};
2276
2277static struct clk cam_ick = {
2278 /* Handles both L3 and L4 clocks */
2279 .name = "cam_ick",
2280 .ops = &clkops_omap2_dflt,
2281 .parent = &l4_ick,
2282 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2283 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2284 .clkdm_name = "cam_clkdm",
2285 .recalc = &followparent_recalc,
2286};
2287
2288static struct clk csi2_96m_fck = {
2289 .name = "csi2_96m_fck",
2290 .ops = &clkops_omap2_dflt,
2291 .parent = &core_96m_fck,
2292 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2293 .enable_bit = OMAP3430_EN_CSI2_SHIFT,
2294 .clkdm_name = "cam_clkdm",
2295 .recalc = &followparent_recalc,
2296};
2297
2298/* USBHOST - 3430ES2 only */
2299
2300static struct clk usbhost_120m_fck = {
2301 .name = "usbhost_120m_fck",
2302 .ops = &clkops_omap2_dflt,
2303 .parent = &dpll5_m2_ck,
2304 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2305 .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
2306 .clkdm_name = "usbhost_clkdm",
2307 .recalc = &followparent_recalc,
2308};
2309
2310static struct clk usbhost_48m_fck = {
2311 .name = "usbhost_48m_fck",
2312 .ops = &clkops_omap3430es2_dss_usbhost_wait,
2313 .parent = &omap_48m_fck,
2314 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2315 .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
2316 .clkdm_name = "usbhost_clkdm",
2317 .recalc = &followparent_recalc,
2318};
2319
2320static struct clk usbhost_ick = {
2321 /* Handles both L3 and L4 clocks */
2322 .name = "usbhost_ick",
2323 .ops = &clkops_omap3430es2_dss_usbhost_wait,
2324 .parent = &l4_ick,
2325 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2326 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
2327 .clkdm_name = "usbhost_clkdm",
2328 .recalc = &followparent_recalc,
2329};
2330
2331/* WKUP */
2332
2333static const struct clksel_rate usim_96m_rates[] = {
2334 { .div = 2, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2335 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2336 { .div = 8, .val = 5, .flags = RATE_IN_343X },
2337 { .div = 10, .val = 6, .flags = RATE_IN_343X },
2338 { .div = 0 },
2339};
2340
2341static const struct clksel_rate usim_120m_rates[] = {
2342 { .div = 4, .val = 7, .flags = RATE_IN_343X | DEFAULT_RATE },
2343 { .div = 8, .val = 8, .flags = RATE_IN_343X },
2344 { .div = 16, .val = 9, .flags = RATE_IN_343X },
2345 { .div = 20, .val = 10, .flags = RATE_IN_343X },
2346 { .div = 0 },
2347};
2348
2349static const struct clksel usim_clksel[] = {
2350 { .parent = &omap_96m_fck, .rates = usim_96m_rates },
2351 { .parent = &dpll5_m2_ck, .rates = usim_120m_rates },
2352 { .parent = &sys_ck, .rates = div2_rates },
2353 { .parent = NULL },
2354};
2355
2356/* 3430ES2 only */
2357static struct clk usim_fck = {
2358 .name = "usim_fck",
2359 .ops = &clkops_omap2_dflt_wait,
2360 .init = &omap2_init_clksel_parent,
2361 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2362 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2363 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2364 .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2365 .clksel = usim_clksel,
2366 .recalc = &omap2_clksel_recalc,
2367};
2368
2369/* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2370static struct clk gpt1_fck = {
2371 .name = "gpt1_fck",
2372 .ops = &clkops_omap2_dflt_wait,
2373 .init = &omap2_init_clksel_parent,
2374 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2375 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2376 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2377 .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK,
2378 .clksel = omap343x_gpt_clksel,
2379 .clkdm_name = "wkup_clkdm",
2380 .recalc = &omap2_clksel_recalc,
2381};
2382
2383static struct clk wkup_32k_fck = {
2384 .name = "wkup_32k_fck",
2385 .ops = &clkops_null,
2386 .parent = &omap_32k_fck,
2387 .clkdm_name = "wkup_clkdm",
2388 .recalc = &followparent_recalc,
2389};
2390
2391static struct clk gpio1_dbck = {
2392 .name = "gpio1_dbck",
2393 .ops = &clkops_omap2_dflt,
2394 .parent = &wkup_32k_fck,
2395 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2396 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2397 .clkdm_name = "wkup_clkdm",
2398 .recalc = &followparent_recalc,
2399};
2400
2401static struct clk wdt2_fck = {
2402 .name = "wdt2_fck",
2403 .ops = &clkops_omap2_dflt_wait,
2404 .parent = &wkup_32k_fck,
2405 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2406 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2407 .clkdm_name = "wkup_clkdm",
2408 .recalc = &followparent_recalc,
2409};
2410
2411static struct clk wkup_l4_ick = {
2412 .name = "wkup_l4_ick",
2413 .ops = &clkops_null,
2414 .parent = &sys_ck,
2415 .clkdm_name = "wkup_clkdm",
2416 .recalc = &followparent_recalc,
2417};
2418
2419/* 3430ES2 only */
2420/* Never specifically named in the TRM, so we have to infer a likely name */
2421static struct clk usim_ick = {
2422 .name = "usim_ick",
2423 .ops = &clkops_omap2_dflt_wait,
2424 .parent = &wkup_l4_ick,
2425 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2426 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2427 .clkdm_name = "wkup_clkdm",
2428 .recalc = &followparent_recalc,
2429};
2430
2431static struct clk wdt2_ick = {
2432 .name = "wdt2_ick",
2433 .ops = &clkops_omap2_dflt_wait,
2434 .parent = &wkup_l4_ick,
2435 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2436 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2437 .clkdm_name = "wkup_clkdm",
2438 .recalc = &followparent_recalc,
2439};
2440
2441static struct clk wdt1_ick = {
2442 .name = "wdt1_ick",
2443 .ops = &clkops_omap2_dflt_wait,
2444 .parent = &wkup_l4_ick,
2445 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2446 .enable_bit = OMAP3430_EN_WDT1_SHIFT,
2447 .clkdm_name = "wkup_clkdm",
2448 .recalc = &followparent_recalc,
2449};
2450
2451static struct clk gpio1_ick = {
2452 .name = "gpio1_ick",
2453 .ops = &clkops_omap2_dflt_wait,
2454 .parent = &wkup_l4_ick,
2455 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2456 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2457 .clkdm_name = "wkup_clkdm",
2458 .recalc = &followparent_recalc,
2459};
2460
2461static struct clk omap_32ksync_ick = {
2462 .name = "omap_32ksync_ick",
2463 .ops = &clkops_omap2_dflt_wait,
2464 .parent = &wkup_l4_ick,
2465 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2466 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
2467 .clkdm_name = "wkup_clkdm",
2468 .recalc = &followparent_recalc,
2469};
2470
2471/* XXX This clock no longer exists in 3430 TRM rev F */
2472static struct clk gpt12_ick = {
2473 .name = "gpt12_ick",
2474 .ops = &clkops_omap2_dflt_wait,
2475 .parent = &wkup_l4_ick,
2476 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2477 .enable_bit = OMAP3430_EN_GPT12_SHIFT,
2478 .clkdm_name = "wkup_clkdm",
2479 .recalc = &followparent_recalc,
2480};
2481
2482static struct clk gpt1_ick = {
2483 .name = "gpt1_ick",
2484 .ops = &clkops_omap2_dflt_wait,
2485 .parent = &wkup_l4_ick,
2486 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2487 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2488 .clkdm_name = "wkup_clkdm",
2489 .recalc = &followparent_recalc,
2490};
2491
2492
2493
2494/* PER clock domain */
2495
2496static struct clk per_96m_fck = {
2497 .name = "per_96m_fck",
2498 .ops = &clkops_null,
2499 .parent = &omap_96m_alwon_fck,
2500 .clkdm_name = "per_clkdm",
2501 .recalc = &followparent_recalc,
2502};
2503
2504static struct clk per_48m_fck = {
2505 .name = "per_48m_fck",
2506 .ops = &clkops_null,
2507 .parent = &omap_48m_fck,
2508 .clkdm_name = "per_clkdm",
2509 .recalc = &followparent_recalc,
2510};
2511
2512static struct clk uart3_fck = {
2513 .name = "uart3_fck",
2514 .ops = &clkops_omap2_dflt_wait,
2515 .parent = &per_48m_fck,
2516 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2517 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2518 .clkdm_name = "per_clkdm",
2519 .recalc = &followparent_recalc,
2520};
2521
2522static struct clk gpt2_fck = {
2523 .name = "gpt2_fck",
2524 .ops = &clkops_omap2_dflt_wait,
2525 .init = &omap2_init_clksel_parent,
2526 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2527 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2528 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2529 .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK,
2530 .clksel = omap343x_gpt_clksel,
2531 .clkdm_name = "per_clkdm",
2532 .recalc = &omap2_clksel_recalc,
2533};
2534
2535static struct clk gpt3_fck = {
2536 .name = "gpt3_fck",
2537 .ops = &clkops_omap2_dflt_wait,
2538 .init = &omap2_init_clksel_parent,
2539 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2540 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2541 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2542 .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK,
2543 .clksel = omap343x_gpt_clksel,
2544 .clkdm_name = "per_clkdm",
2545 .recalc = &omap2_clksel_recalc,
2546};
2547
2548static struct clk gpt4_fck = {
2549 .name = "gpt4_fck",
2550 .ops = &clkops_omap2_dflt_wait,
2551 .init = &omap2_init_clksel_parent,
2552 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2553 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2554 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2555 .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK,
2556 .clksel = omap343x_gpt_clksel,
2557 .clkdm_name = "per_clkdm",
2558 .recalc = &omap2_clksel_recalc,
2559};
2560
2561static struct clk gpt5_fck = {
2562 .name = "gpt5_fck",
2563 .ops = &clkops_omap2_dflt_wait,
2564 .init = &omap2_init_clksel_parent,
2565 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2566 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2567 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2568 .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK,
2569 .clksel = omap343x_gpt_clksel,
2570 .clkdm_name = "per_clkdm",
2571 .recalc = &omap2_clksel_recalc,
2572};
2573
2574static struct clk gpt6_fck = {
2575 .name = "gpt6_fck",
2576 .ops = &clkops_omap2_dflt_wait,
2577 .init = &omap2_init_clksel_parent,
2578 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2579 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2580 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2581 .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK,
2582 .clksel = omap343x_gpt_clksel,
2583 .clkdm_name = "per_clkdm",
2584 .recalc = &omap2_clksel_recalc,
2585};
2586
2587static struct clk gpt7_fck = {
2588 .name = "gpt7_fck",
2589 .ops = &clkops_omap2_dflt_wait,
2590 .init = &omap2_init_clksel_parent,
2591 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2592 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2593 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2594 .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK,
2595 .clksel = omap343x_gpt_clksel,
2596 .clkdm_name = "per_clkdm",
2597 .recalc = &omap2_clksel_recalc,
2598};
2599
2600static struct clk gpt8_fck = {
2601 .name = "gpt8_fck",
2602 .ops = &clkops_omap2_dflt_wait,
2603 .init = &omap2_init_clksel_parent,
2604 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2605 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2606 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2607 .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK,
2608 .clksel = omap343x_gpt_clksel,
2609 .clkdm_name = "per_clkdm",
2610 .recalc = &omap2_clksel_recalc,
2611};
2612
2613static struct clk gpt9_fck = {
2614 .name = "gpt9_fck",
2615 .ops = &clkops_omap2_dflt_wait,
2616 .init = &omap2_init_clksel_parent,
2617 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2618 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2619 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2620 .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK,
2621 .clksel = omap343x_gpt_clksel,
2622 .clkdm_name = "per_clkdm",
2623 .recalc = &omap2_clksel_recalc,
2624};
2625
2626static struct clk per_32k_alwon_fck = {
2627 .name = "per_32k_alwon_fck",
2628 .ops = &clkops_null,
2629 .parent = &omap_32k_fck,
2630 .clkdm_name = "per_clkdm",
2631 .recalc = &followparent_recalc,
2632};
2633
2634static struct clk gpio6_dbck = {
2635 .name = "gpio6_dbck",
2636 .ops = &clkops_omap2_dflt,
2637 .parent = &per_32k_alwon_fck,
2638 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2639 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2640 .clkdm_name = "per_clkdm",
2641 .recalc = &followparent_recalc,
2642};
2643
2644static struct clk gpio5_dbck = {
2645 .name = "gpio5_dbck",
2646 .ops = &clkops_omap2_dflt,
2647 .parent = &per_32k_alwon_fck,
2648 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2649 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2650 .clkdm_name = "per_clkdm",
2651 .recalc = &followparent_recalc,
2652};
2653
2654static struct clk gpio4_dbck = {
2655 .name = "gpio4_dbck",
2656 .ops = &clkops_omap2_dflt,
2657 .parent = &per_32k_alwon_fck,
2658 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2659 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2660 .clkdm_name = "per_clkdm",
2661 .recalc = &followparent_recalc,
2662};
2663
2664static struct clk gpio3_dbck = {
2665 .name = "gpio3_dbck",
2666 .ops = &clkops_omap2_dflt,
2667 .parent = &per_32k_alwon_fck,
2668 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2669 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2670 .clkdm_name = "per_clkdm",
2671 .recalc = &followparent_recalc,
2672};
2673
2674static struct clk gpio2_dbck = {
2675 .name = "gpio2_dbck",
2676 .ops = &clkops_omap2_dflt,
2677 .parent = &per_32k_alwon_fck,
2678 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2679 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2680 .clkdm_name = "per_clkdm",
2681 .recalc = &followparent_recalc,
2682};
2683
2684static struct clk wdt3_fck = {
2685 .name = "wdt3_fck",
2686 .ops = &clkops_omap2_dflt_wait,
2687 .parent = &per_32k_alwon_fck,
2688 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2689 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2690 .clkdm_name = "per_clkdm",
2691 .recalc = &followparent_recalc,
2692};
2693
2694static struct clk per_l4_ick = {
2695 .name = "per_l4_ick",
2696 .ops = &clkops_null,
2697 .parent = &l4_ick,
2698 .clkdm_name = "per_clkdm",
2699 .recalc = &followparent_recalc,
2700};
2701
2702static struct clk gpio6_ick = {
2703 .name = "gpio6_ick",
2704 .ops = &clkops_omap2_dflt_wait,
2705 .parent = &per_l4_ick,
2706 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2707 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2708 .clkdm_name = "per_clkdm",
2709 .recalc = &followparent_recalc,
2710};
2711
2712static struct clk gpio5_ick = {
2713 .name = "gpio5_ick",
2714 .ops = &clkops_omap2_dflt_wait,
2715 .parent = &per_l4_ick,
2716 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2717 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2718 .clkdm_name = "per_clkdm",
2719 .recalc = &followparent_recalc,
2720};
2721
2722static struct clk gpio4_ick = {
2723 .name = "gpio4_ick",
2724 .ops = &clkops_omap2_dflt_wait,
2725 .parent = &per_l4_ick,
2726 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2727 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2728 .clkdm_name = "per_clkdm",
2729 .recalc = &followparent_recalc,
2730};
2731
2732static struct clk gpio3_ick = {
2733 .name = "gpio3_ick",
2734 .ops = &clkops_omap2_dflt_wait,
2735 .parent = &per_l4_ick,
2736 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2737 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2738 .clkdm_name = "per_clkdm",
2739 .recalc = &followparent_recalc,
2740};
2741
2742static struct clk gpio2_ick = {
2743 .name = "gpio2_ick",
2744 .ops = &clkops_omap2_dflt_wait,
2745 .parent = &per_l4_ick,
2746 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2747 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2748 .clkdm_name = "per_clkdm",
2749 .recalc = &followparent_recalc,
2750};
2751
2752static struct clk wdt3_ick = {
2753 .name = "wdt3_ick",
2754 .ops = &clkops_omap2_dflt_wait,
2755 .parent = &per_l4_ick,
2756 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2757 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2758 .clkdm_name = "per_clkdm",
2759 .recalc = &followparent_recalc,
2760};
2761
2762static struct clk uart3_ick = {
2763 .name = "uart3_ick",
2764 .ops = &clkops_omap2_dflt_wait,
2765 .parent = &per_l4_ick,
2766 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2767 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2768 .clkdm_name = "per_clkdm",
2769 .recalc = &followparent_recalc,
2770};
2771
2772static struct clk gpt9_ick = {
2773 .name = "gpt9_ick",
2774 .ops = &clkops_omap2_dflt_wait,
2775 .parent = &per_l4_ick,
2776 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2777 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2778 .clkdm_name = "per_clkdm",
2779 .recalc = &followparent_recalc,
2780};
2781
2782static struct clk gpt8_ick = {
2783 .name = "gpt8_ick",
2784 .ops = &clkops_omap2_dflt_wait,
2785 .parent = &per_l4_ick,
2786 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2787 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2788 .clkdm_name = "per_clkdm",
2789 .recalc = &followparent_recalc,
2790};
2791
2792static struct clk gpt7_ick = {
2793 .name = "gpt7_ick",
2794 .ops = &clkops_omap2_dflt_wait,
2795 .parent = &per_l4_ick,
2796 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2797 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2798 .clkdm_name = "per_clkdm",
2799 .recalc = &followparent_recalc,
2800};
2801
2802static struct clk gpt6_ick = {
2803 .name = "gpt6_ick",
2804 .ops = &clkops_omap2_dflt_wait,
2805 .parent = &per_l4_ick,
2806 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2807 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2808 .clkdm_name = "per_clkdm",
2809 .recalc = &followparent_recalc,
2810};
2811
2812static struct clk gpt5_ick = {
2813 .name = "gpt5_ick",
2814 .ops = &clkops_omap2_dflt_wait,
2815 .parent = &per_l4_ick,
2816 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2817 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2818 .clkdm_name = "per_clkdm",
2819 .recalc = &followparent_recalc,
2820};
2821
2822static struct clk gpt4_ick = {
2823 .name = "gpt4_ick",
2824 .ops = &clkops_omap2_dflt_wait,
2825 .parent = &per_l4_ick,
2826 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2827 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2828 .clkdm_name = "per_clkdm",
2829 .recalc = &followparent_recalc,
2830};
2831
2832static struct clk gpt3_ick = {
2833 .name = "gpt3_ick",
2834 .ops = &clkops_omap2_dflt_wait,
2835 .parent = &per_l4_ick,
2836 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2837 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2838 .clkdm_name = "per_clkdm",
2839 .recalc = &followparent_recalc,
2840};
2841
2842static struct clk gpt2_ick = {
2843 .name = "gpt2_ick",
2844 .ops = &clkops_omap2_dflt_wait,
2845 .parent = &per_l4_ick,
2846 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2847 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2848 .clkdm_name = "per_clkdm",
2849 .recalc = &followparent_recalc,
2850};
2851
2852static struct clk mcbsp2_ick = {
2853 .name = "mcbsp_ick",
2854 .ops = &clkops_omap2_dflt_wait,
2855 .id = 2,
2856 .parent = &per_l4_ick,
2857 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2858 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2859 .clkdm_name = "per_clkdm",
2860 .recalc = &followparent_recalc,
2861};
2862
2863static struct clk mcbsp3_ick = {
2864 .name = "mcbsp_ick",
2865 .ops = &clkops_omap2_dflt_wait,
2866 .id = 3,
2867 .parent = &per_l4_ick,
2868 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2869 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2870 .clkdm_name = "per_clkdm",
2871 .recalc = &followparent_recalc,
2872};
2873
2874static struct clk mcbsp4_ick = {
2875 .name = "mcbsp_ick",
2876 .ops = &clkops_omap2_dflt_wait,
2877 .id = 4,
2878 .parent = &per_l4_ick,
2879 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2880 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2881 .clkdm_name = "per_clkdm",
2882 .recalc = &followparent_recalc,
2883};
2884
2885static const struct clksel mcbsp_234_clksel[] = {
Paul Walmsley073463c2010-01-08 15:23:07 -0700[diff] [blame]2886 { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]2887 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
2888 { .parent = NULL }
2889};
2890
2891static struct clk mcbsp2_fck = {
2892 .name = "mcbsp_fck",
2893 .ops = &clkops_omap2_dflt_wait,
2894 .id = 2,
2895 .init = &omap2_init_clksel_parent,
2896 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2897 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2898 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2899 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
2900 .clksel = mcbsp_234_clksel,
2901 .clkdm_name = "per_clkdm",
2902 .recalc = &omap2_clksel_recalc,
2903};
2904
2905static struct clk mcbsp3_fck = {
2906 .name = "mcbsp_fck",
2907 .ops = &clkops_omap2_dflt_wait,
2908 .id = 3,
2909 .init = &omap2_init_clksel_parent,
2910 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2911 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2912 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2913 .clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
2914 .clksel = mcbsp_234_clksel,
2915 .clkdm_name = "per_clkdm",
2916 .recalc = &omap2_clksel_recalc,
2917};
2918
2919static struct clk mcbsp4_fck = {
2920 .name = "mcbsp_fck",
2921 .ops = &clkops_omap2_dflt_wait,
2922 .id = 4,
2923 .init = &omap2_init_clksel_parent,
2924 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2925 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2926 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2927 .clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
2928 .clksel = mcbsp_234_clksel,
2929 .clkdm_name = "per_clkdm",
2930 .recalc = &omap2_clksel_recalc,
2931};
2932
2933/* EMU clocks */
2934
2935/* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2936
2937static const struct clksel_rate emu_src_sys_rates[] = {
2938 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2939 { .div = 0 },
2940};
2941
2942static const struct clksel_rate emu_src_core_rates[] = {
2943 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2944 { .div = 0 },
2945};
2946
2947static const struct clksel_rate emu_src_per_rates[] = {
2948 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2949 { .div = 0 },
2950};
2951
2952static const struct clksel_rate emu_src_mpu_rates[] = {
2953 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2954 { .div = 0 },
2955};
2956
2957static const struct clksel emu_src_clksel[] = {
2958 { .parent = &sys_ck, .rates = emu_src_sys_rates },
2959 { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2960 { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates },
2961 { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates },
2962 { .parent = NULL },
2963};
2964
2965/*
2966 * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2967 * to switch the source of some of the EMU clocks.
2968 * XXX Are there CLKEN bits for these EMU clks?
2969 */
2970static struct clk emu_src_ck = {
2971 .name = "emu_src_ck",
2972 .ops = &clkops_null,
2973 .init = &omap2_init_clksel_parent,
2974 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2975 .clksel_mask = OMAP3430_MUX_CTRL_MASK,
2976 .clksel = emu_src_clksel,
2977 .clkdm_name = "emu_clkdm",
2978 .recalc = &omap2_clksel_recalc,
2979};
2980
2981static const struct clksel_rate pclk_emu_rates[] = {
2982 { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2983 { .div = 3, .val = 3, .flags = RATE_IN_343X },
2984 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2985 { .div = 6, .val = 6, .flags = RATE_IN_343X },
2986 { .div = 0 },
2987};
2988
2989static const struct clksel pclk_emu_clksel[] = {
2990 { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2991 { .parent = NULL },
2992};
2993
2994static struct clk pclk_fck = {
2995 .name = "pclk_fck",
2996 .ops = &clkops_null,
2997 .init = &omap2_init_clksel_parent,
2998 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2999 .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK,
3000 .clksel = pclk_emu_clksel,
3001 .clkdm_name = "emu_clkdm",
3002 .recalc = &omap2_clksel_recalc,
3003};
3004
3005static const struct clksel_rate pclkx2_emu_rates[] = {
3006 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3007 { .div = 2, .val = 2, .flags = RATE_IN_343X },
3008 { .div = 3, .val = 3, .flags = RATE_IN_343X },
3009 { .div = 0 },
3010};
3011
3012static const struct clksel pclkx2_emu_clksel[] = {
3013 { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
3014 { .parent = NULL },
3015};
3016
3017static struct clk pclkx2_fck = {
3018 .name = "pclkx2_fck",
3019 .ops = &clkops_null,
3020 .init = &omap2_init_clksel_parent,
3021 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3022 .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK,
3023 .clksel = pclkx2_emu_clksel,
3024 .clkdm_name = "emu_clkdm",
3025 .recalc = &omap2_clksel_recalc,
3026};
3027
3028static const struct clksel atclk_emu_clksel[] = {
3029 { .parent = &emu_src_ck, .rates = div2_rates },
3030 { .parent = NULL },
3031};
3032
3033static struct clk atclk_fck = {
3034 .name = "atclk_fck",
3035 .ops = &clkops_null,
3036 .init = &omap2_init_clksel_parent,
3037 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3038 .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK,
3039 .clksel = atclk_emu_clksel,
3040 .clkdm_name = "emu_clkdm",
3041 .recalc = &omap2_clksel_recalc,
3042};
3043
3044static struct clk traceclk_src_fck = {
3045 .name = "traceclk_src_fck",
3046 .ops = &clkops_null,
3047 .init = &omap2_init_clksel_parent,
3048 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3049 .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK,
3050 .clksel = emu_src_clksel,
3051 .clkdm_name = "emu_clkdm",
3052 .recalc = &omap2_clksel_recalc,
3053};
3054
3055static const struct clksel_rate traceclk_rates[] = {
3056 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3057 { .div = 2, .val = 2, .flags = RATE_IN_343X },
3058 { .div = 4, .val = 4, .flags = RATE_IN_343X },
3059 { .div = 0 },
3060};
3061
3062static const struct clksel traceclk_clksel[] = {
3063 { .parent = &traceclk_src_fck, .rates = traceclk_rates },
3064 { .parent = NULL },
3065};
3066
3067static struct clk traceclk_fck = {
3068 .name = "traceclk_fck",
3069 .ops = &clkops_null,
3070 .init = &omap2_init_clksel_parent,
3071 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3072 .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK,
3073 .clksel = traceclk_clksel,
3074 .clkdm_name = "emu_clkdm",
3075 .recalc = &omap2_clksel_recalc,
3076};
3077
3078/* SR clocks */
3079
3080/* SmartReflex fclk (VDD1) */
3081static struct clk sr1_fck = {
3082 .name = "sr1_fck",
3083 .ops = &clkops_omap2_dflt_wait,
3084 .parent = &sys_ck,
3085 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3086 .enable_bit = OMAP3430_EN_SR1_SHIFT,
3087 .recalc = &followparent_recalc,
3088};
3089
3090/* SmartReflex fclk (VDD2) */
3091static struct clk sr2_fck = {
3092 .name = "sr2_fck",
3093 .ops = &clkops_omap2_dflt_wait,
3094 .parent = &sys_ck,
3095 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3096 .enable_bit = OMAP3430_EN_SR2_SHIFT,
3097 .recalc = &followparent_recalc,
3098};
3099
3100static struct clk sr_l4_ick = {
3101 .name = "sr_l4_ick",
3102 .ops = &clkops_null, /* RMK: missing? */
3103 .parent = &l4_ick,
3104 .clkdm_name = "core_l4_clkdm",
3105 .recalc = &followparent_recalc,
3106};
3107
3108/* SECURE_32K_FCK clocks */
3109
3110static struct clk gpt12_fck = {
3111 .name = "gpt12_fck",
3112 .ops = &clkops_null,
3113 .parent = &secure_32k_fck,
3114 .recalc = &followparent_recalc,
3115};
3116
3117static struct clk wdt1_fck = {
3118 .name = "wdt1_fck",
3119 .ops = &clkops_null,
3120 .parent = &secure_32k_fck,
3121 .recalc = &followparent_recalc,
3122};
3123
Ranjith Lohithakshan3cc4a2f2010-02-24 12:05:55 -0700[diff] [blame]3124/* Clocks for AM35XX */
3125static struct clk ipss_ick = {
3126 .name = "ipss_ick",
3127 .ops = &clkops_am35xx_ipss_wait,
3128 .parent = &core_l3_ick,
3129 .clkdm_name = "core_l3_clkdm",
3130 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
3131 .enable_bit = AM35XX_EN_IPSS_SHIFT,
3132 .recalc = &followparent_recalc,
3133};
3134
3135static struct clk emac_ick = {
3136 .name = "emac_ick",
3137 .ops = &clkops_am35xx_ipss_module_wait,
3138 .parent = &ipss_ick,
3139 .clkdm_name = "core_l3_clkdm",
3140 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3141 .enable_bit = AM35XX_CPGMAC_VBUSP_CLK_SHIFT,
3142 .recalc = &followparent_recalc,
3143};
3144
3145static struct clk rmii_ck = {
3146 .name = "rmii_ck",
3147 .ops = &clkops_null,
3148 .flags = RATE_FIXED,
3149 .rate = 50000000,
3150};
3151
3152static struct clk emac_fck = {
3153 .name = "emac_fck",
3154 .ops = &clkops_omap2_dflt,
3155 .parent = &rmii_ck,
3156 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3157 .enable_bit = AM35XX_CPGMAC_FCLK_SHIFT,
3158 .recalc = &followparent_recalc,
3159};
3160
3161static struct clk hsotgusb_ick_am35xx = {
3162 .name = "hsotgusb_ick",
3163 .ops = &clkops_am35xx_ipss_module_wait,
3164 .parent = &ipss_ick,
3165 .clkdm_name = "core_l3_clkdm",
3166 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3167 .enable_bit = AM35XX_USBOTG_VBUSP_CLK_SHIFT,
3168 .recalc = &followparent_recalc,
3169};
3170
3171static struct clk hsotgusb_fck_am35xx = {
3172 .name = "hsotgusb_fck",
3173 .ops = &clkops_omap2_dflt,
3174 .parent = &sys_ck,
3175 .clkdm_name = "core_l3_clkdm",
3176 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3177 .enable_bit = AM35XX_USBOTG_FCLK_SHIFT,
3178 .recalc = &followparent_recalc,
3179};
3180
3181static struct clk hecc_ck = {
3182 .name = "hecc_ck",
3183 .ops = &clkops_am35xx_ipss_module_wait,
3184 .parent = &sys_ck,
3185 .clkdm_name = "core_l3_clkdm",
3186 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3187 .enable_bit = AM35XX_HECC_VBUSP_CLK_SHIFT,
3188 .recalc = &followparent_recalc,
3189};
3190
3191static struct clk vpfe_ick = {
3192 .name = "vpfe_ick",
3193 .ops = &clkops_am35xx_ipss_module_wait,
3194 .parent = &ipss_ick,
3195 .clkdm_name = "core_l3_clkdm",
3196 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3197 .enable_bit = AM35XX_VPFE_VBUSP_CLK_SHIFT,
3198 .recalc = &followparent_recalc,
3199};
3200
3201static struct clk pclk_ck = {
3202 .name = "pclk_ck",
3203 .ops = &clkops_null,
3204 .flags = RATE_FIXED,
3205 .rate = 27000000,
3206};
3207
3208static struct clk vpfe_fck = {
3209 .name = "vpfe_fck",
3210 .ops = &clkops_omap2_dflt,
3211 .parent = &pclk_ck,
3212 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3213 .enable_bit = AM35XX_VPFE_FCLK_SHIFT,
3214 .recalc = &followparent_recalc,
3215};
3216
3217/*
3218 * The UART1/2 functional clock acts as the functional
3219 * clock for UART4. No separate fclk control available.
3220 */
3221static struct clk uart4_ick_am35xx = {
3222 .name = "uart4_ick",
3223 .ops = &clkops_omap2_dflt_wait,
3224 .parent = &core_l4_ick,
3225 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
3226 .enable_bit = AM35XX_EN_UART4_SHIFT,
3227 .clkdm_name = "core_l4_clkdm",
3228 .recalc = &followparent_recalc,
3229};
3230
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3231
3232/*
3233 * clkdev
3234 */
3235
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3236/* XXX At some point we should rename this file to clock3xxx_data.c */
3237static struct omap_clk omap3xxx_clks[] = {
3238 CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_3XXX),
3239 CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_3XXX),
3240 CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_3XXX),
3241 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2 | CK_AM35XX),
3242 CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_3XXX),
3243 CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_3XXX),
3244 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX),
3245 CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_3XXX),
3246 CLK(NULL, "sys_ck", &sys_ck, CK_3XXX),
3247 CLK(NULL, "sys_altclk", &sys_altclk, CK_3XXX),
3248 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_3XXX),
3249 CLK(NULL, "sys_clkout1", &sys_clkout1, CK_3XXX),
3250 CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX),
3251 CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_3XXX),
3252 CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3253 CLK(NULL, "dpll2_ck", &dpll2_ck, CK_343X),
3254 CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_343X),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3255 CLK(NULL, "dpll3_ck", &dpll3_ck, CK_3XXX),
3256 CLK(NULL, "core_ck", &core_ck, CK_3XXX),
3257 CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_3XXX),
3258 CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_3XXX),
3259 CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX),
3260 CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_3XXX),
3261 CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX),
3262 CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
3263 CLK(NULL, "dpll4_ck", &dpll4_ck, CK_3XXX),
3264 CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_3XXX),
3265 CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX),
3266 CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_3XXX),
3267 CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_3XXX),
3268 CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_3XXX),
3269 CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_3XXX),
3270 CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_3XXX),
3271 CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_3XXX),
3272 CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_3XXX),
3273 CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_3XXX),
3274 CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_3XXX),
3275 CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_3XXX),
3276 CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_3XXX),
3277 CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_3XXX),
3278 CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX),
3279 CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_3XXX),
3280 CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
3281 CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
3282 CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2 | CK_AM35XX),
3283 CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2 | CK_AM35XX),
3284 CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_3XXX),
3285 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_3XXX),
3286 CLK(NULL, "corex2_fck", &corex2_fck, CK_3XXX),
3287 CLK(NULL, "dpll1_fck", &dpll1_fck, CK_3XXX),
3288 CLK(NULL, "mpu_ck", &mpu_ck, CK_3XXX),
3289 CLK(NULL, "arm_fck", &arm_fck, CK_3XXX),
3290 CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3291 CLK(NULL, "dpll2_fck", &dpll2_fck, CK_343X),
3292 CLK(NULL, "iva2_ck", &iva2_ck, CK_343X),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3293 CLK(NULL, "l3_ick", &l3_ick, CK_3XXX),
3294 CLK(NULL, "l4_ick", &l4_ick, CK_3XXX),
3295 CLK(NULL, "rm_ick", &rm_ick, CK_3XXX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3296 CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1),
3297 CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1),
3298 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1),
3299 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1),
3300 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3301 CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2 | CK_3517),
3302 CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2 | CK_3517),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3303 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1),
3304 CLK(NULL, "modem_fck", &modem_fck, CK_343X),
3305 CLK(NULL, "sad2d_ick", &sad2d_ick, CK_343X),
3306 CLK(NULL, "mad2d_ick", &mad2d_ick, CK_343X),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3307 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_3XXX),
3308 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_3XXX),
3309 CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2 | CK_AM35XX),
3310 CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2 | CK_AM35XX),
3311 CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2 | CK_AM35XX),
3312 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX),
3313 CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2 | CK_AM35XX),
3314 CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_3XXX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3315 CLK(NULL, "mspro_fck", &mspro_fck, CK_343X),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3316 CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_3XXX),
3317 CLK("i2c_omap.3", "fck", &i2c3_fck, CK_3XXX),
3318 CLK("i2c_omap.2", "fck", &i2c2_fck, CK_3XXX),
3319 CLK("i2c_omap.1", "fck", &i2c1_fck, CK_3XXX),
3320 CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_3XXX),
3321 CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_3XXX),
3322 CLK(NULL, "core_48m_fck", &core_48m_fck, CK_3XXX),
3323 CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_3XXX),
3324 CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_3XXX),
3325 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_3XXX),
3326 CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_3XXX),
3327 CLK(NULL, "uart2_fck", &uart2_fck, CK_3XXX),
3328 CLK(NULL, "uart1_fck", &uart1_fck, CK_3XXX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3329 CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3330 CLK(NULL, "core_12m_fck", &core_12m_fck, CK_3XXX),
3331 CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3332 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1),
3333 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2),
3334 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1),
3335 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3336 CLK(NULL, "core_l3_ick", &core_l3_ick, CK_3XXX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3337 CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es1, CK_3430ES1),
3338 CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es2, CK_3430ES2),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3339 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_3XXX),
3340 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_3XXX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3341 CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X),
3342 CLK(NULL, "pka_ick", &pka_ick, CK_343X),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3343 CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX),
3344 CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2 | CK_AM35XX),
3345 CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2 | CK_AM35XX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3346 CLK(NULL, "icr_ick", &icr_ick, CK_343X),
3347 CLK(NULL, "aes2_ick", &aes2_ick, CK_343X),
3348 CLK(NULL, "sha12_ick", &sha12_ick, CK_343X),
3349 CLK(NULL, "des2_ick", &des2_ick, CK_343X),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3350 CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_3XXX),
3351 CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_3XXX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3352 CLK(NULL, "mspro_ick", &mspro_ick, CK_343X),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3353 CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX),
3354 CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX),
3355 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_3XXX),
3356 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_3XXX),
3357 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_3XXX),
3358 CLK("i2c_omap.3", "ick", &i2c3_ick, CK_3XXX),
3359 CLK("i2c_omap.2", "ick", &i2c2_ick, CK_3XXX),
3360 CLK("i2c_omap.1", "ick", &i2c1_ick, CK_3XXX),
3361 CLK(NULL, "uart2_ick", &uart2_ick, CK_3XXX),
3362 CLK(NULL, "uart1_ick", &uart1_ick, CK_3XXX),
3363 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_3XXX),
3364 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_3XXX),
3365 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_3XXX),
3366 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_3XXX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3367 CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1),
3368 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_343X),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3369 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_3XXX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3370 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_343X),
3371 CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1),
3372 CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2),
3373 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1),
3374 CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_343X),
3375 CLK(NULL, "aes1_ick", &aes1_ick, CK_343X),
3376 CLK("omap_rng", "ick", &rng_ick, CK_343X),
3377 CLK(NULL, "sha11_ick", &sha11_ick, CK_343X),
3378 CLK(NULL, "des1_ick", &des1_ick, CK_343X),
3379 CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es1, CK_3430ES1),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3380 CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2 | CK_AM35XX),
3381 CLK("omapdss", "tv_fck", &dss_tv_fck, CK_3XXX),
3382 CLK("omapdss", "video_fck", &dss_96m_fck, CK_3XXX),
3383 CLK("omapdss", "dss2_fck", &dss2_alwon_fck, CK_3XXX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3384 CLK("omapdss", "ick", &dss_ick_3430es1, CK_3430ES1),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3385 CLK("omapdss", "ick", &dss_ick_3430es2, CK_3430ES2 | CK_AM35XX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3386 CLK(NULL, "cam_mclk", &cam_mclk, CK_343X),
3387 CLK(NULL, "cam_ick", &cam_ick, CK_343X),
3388 CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3389 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2 | CK_AM35XX),
3390 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2 | CK_AM35XX),
3391 CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2 | CK_AM35XX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3392 CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3393 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX),
3394 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_3XXX),
3395 CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_3XXX),
3396 CLK("omap_wdt", "fck", &wdt2_fck, CK_3XXX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3397 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_343X),
3398 CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3399 CLK("omap_wdt", "ick", &wdt2_ick, CK_3XXX),
3400 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_3XXX),
3401 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_3XXX),
3402 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
3403 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_3XXX),
3404 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_3XXX),
3405 CLK(NULL, "per_96m_fck", &per_96m_fck, CK_3XXX),
3406 CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX),
3407 CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX),
3408 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_3XXX),
3409 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_3XXX),
3410 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_3XXX),
3411 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_3XXX),
3412 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_3XXX),
3413 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_3XXX),
3414 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_3XXX),
3415 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_3XXX),
3416 CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_3XXX),
3417 CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_3XXX),
3418 CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_3XXX),
3419 CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_3XXX),
3420 CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_3XXX),
3421 CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_3XXX),
3422 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_3XXX),
3423 CLK(NULL, "per_l4_ick", &per_l4_ick, CK_3XXX),
3424 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_3XXX),
3425 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_3XXX),
3426 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_3XXX),
3427 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_3XXX),
3428 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_3XXX),
3429 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_3XXX),
3430 CLK(NULL, "uart3_ick", &uart3_ick, CK_3XXX),
3431 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_3XXX),
3432 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_3XXX),
3433 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_3XXX),
3434 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_3XXX),
3435 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_3XXX),
3436 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_3XXX),
3437 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_3XXX),
3438 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_3XXX),
3439 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_3XXX),
3440 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_3XXX),
3441 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_3XXX),
3442 CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_3XXX),
3443 CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_3XXX),
3444 CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_3XXX),
3445 CLK("etb", "emu_src_ck", &emu_src_ck, CK_3XXX),
3446 CLK(NULL, "pclk_fck", &pclk_fck, CK_3XXX),
3447 CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_3XXX),
3448 CLK(NULL, "atclk_fck", &atclk_fck, CK_3XXX),
3449 CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_3XXX),
3450 CLK(NULL, "traceclk_fck", &traceclk_fck, CK_3XXX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3451 CLK(NULL, "sr1_fck", &sr1_fck, CK_343X),
3452 CLK(NULL, "sr2_fck", &sr2_fck, CK_343X),
3453 CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_343X),
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3454 CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_3XXX),
3455 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_3XXX),
3456 CLK(NULL, "wdt1_fck", &wdt1_fck, CK_3XXX),
Ranjith Lohithakshan3cc4a2f2010-02-24 12:05:55 -0700[diff] [blame]3457 CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX),
3458 CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX),
3459 CLK(NULL, "pclk_ck", &pclk_ck, CK_AM35XX),
3460 CLK("davinci_emac", "ick", &emac_ick, CK_AM35XX),
3461 CLK("davinci_emac", "fck", &emac_fck, CK_AM35XX),
3462 CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX),
3463 CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX),
3464 CLK("musb_hdrc", "ick", &hsotgusb_ick_am35xx, CK_AM35XX),
3465 CLK("musb_hdrc", "fck", &hsotgusb_fck_am35xx, CK_AM35XX),
3466 CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX),
3467 CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX),
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3468};
3469
3470
Paul Walmsleye80a9722010-01-26 20:13:12 -0700[diff] [blame]3471int __init omap3xxx_clk_init(void)
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3472{
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3473 struct omap_clk *c;
Paul Walmsley2c8a1772010-01-26 20:12:56 -0700[diff] [blame]3474 u32 cpu_clkflg = CK_3XXX;
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3475
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3476 if (cpu_is_omap3517()) {
3477 cpu_mask = RATE_IN_343X | RATE_IN_3430ES2;
3478 cpu_clkflg |= CK_3517;
3479 } else if (cpu_is_omap3505()) {
3480 cpu_mask = RATE_IN_343X | RATE_IN_3430ES2;
3481 cpu_clkflg |= CK_3505;
3482 } else if (cpu_is_omap34xx()) {
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3483 cpu_mask = RATE_IN_343X;
Paul Walmsley2c8a1772010-01-26 20:12:56 -0700[diff] [blame]3484 cpu_clkflg |= CK_343X;
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3485
3486 /*
3487 * Update this if there are further clock changes between ES2
3488 * and production parts
3489 */
3490 if (omap_rev() == OMAP3430_REV_ES1_0) {
3491 /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
3492 cpu_clkflg |= CK_3430ES1;
3493 } else {
3494 cpu_mask |= RATE_IN_3430ES2;
3495 cpu_clkflg |= CK_3430ES2;
3496 }
3497 }
3498
Mike Turquettea7e069f2010-02-24 12:06:00 -0700[diff] [blame]3499 if (cpu_is_omap3630()) {
Vishwanath BS678bc9a2010-02-22 22:09:09 -0700[diff] [blame^]3500 cpu_mask |= RATE_IN_36XX;
3501 cpu_clkflg |= CK_36XX;
3502
3503 /*
3504 * XXX This type of dynamic rewriting of the clock tree is
3505 * deprecated and should be revised soon.
3506 */
3507 dpll4_m2_ck = dpll4_m2_ck_3630;
3508 dpll4_m3_ck = dpll4_m3_ck_3630;
3509 dpll4_m4_ck = dpll4_m4_ck_3630;
3510 dpll4_m5_ck = dpll4_m5_ck_3630;
3511 dpll4_m6_ck = dpll4_m6_ck_3630;
3512
Mike Turquettea7e069f2010-02-24 12:06:00 -0700[diff] [blame]3513 /*
3514 * For 3630: override clkops_omap2_dflt_wait for the
3515 * clocks affected from PWRDN reset Limitation
3516 */
3517 dpll3_m3x2_ck.ops =
3518 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3519 dpll4_m2x2_ck.ops =
3520 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3521 dpll4_m3x2_ck.ops =
3522 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3523 dpll4_m4x2_ck.ops =
3524 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3525 dpll4_m5x2_ck.ops =
3526 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3527 dpll4_m6x2_ck.ops =
3528 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
Vishwanath BS678bc9a2010-02-22 22:09:09 -0700[diff] [blame^]3529 } else {
3530 /*
3531 * XXX This type of dynamic rewriting of the clock tree is
3532 * deprecated and should be revised soon.
3533 */
3534 dpll4_m2_ck = dpll4_m2_ck_34xx;
3535 dpll4_m3_ck = dpll4_m3_ck_34xx;
3536 dpll4_m4_ck = dpll4_m4_ck_34xx;
3537 dpll4_m5_ck = dpll4_m5_ck_34xx;
3538 dpll4_m6_ck = dpll4_m6_ck_34xx;
Mike Turquettea7e069f2010-02-24 12:06:00 -0700[diff] [blame]3539 }
3540
Richard Woodruff358965d2010-02-22 22:09:08 -0700[diff] [blame]3541 if (cpu_is_omap3630())
3542 dpll4_dd = dpll4_dd_3630;
3543 else
3544 dpll4_dd = dpll4_dd_34xx;
3545
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3546 clk_init(&omap2_clk_functions);
3547
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3548 for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks); c++)
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3549 clk_preinit(c->lk.clk);
3550
Ranjith Lohithakshanced82522010-01-26 20:12:57 -0700[diff] [blame]3551 for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks); c++)
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3552 if (c->cpu & cpu_clkflg) {
3553 clkdev_add(&c->lk);
3554 clk_register(c->lk.clk);
3555 omap2_init_clk_clkdm(c->lk.clk);
3556 }
3557
Paul Walmsley82e9bd52009-12-08 16:18:47 -0700[diff] [blame]3558 recalculate_root_clocks();
3559
3560 printk(KERN_INFO "Clocking rate (Crystal/Core/MPU): "
3561 "%ld.%01ld/%ld/%ld MHz\n",
3562 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
3563 (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
3564
3565 /*
3566 * Only enable those clocks we will need, let the drivers
3567 * enable other clocks as necessary
3568 */
3569 clk_enable_init_clocks();
3570
3571 /*
3572 * Lock DPLL5 and put it in autoidle.
3573 */
3574 if (omap_rev() >= OMAP3430_REV_ES2_0)
3575 omap3_clk_lock_dpll5();
3576
3577 /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
3578 sdrc_ick_p = clk_get(NULL, "sdrc_ick");
3579 arm_fck_p = clk_get(NULL, "arm_fck");
3580
3581 return 0;
3582}