blob: 092d067f93e16534aca712779ce2aa5705069395 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/**
2 * \file radeon_drv.c
3 * ATI Radeon driver
4 *
5 * \author Gareth Hughes <gareth@valinux.com>
6 */
7
8/*
9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
10 * All Rights Reserved.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a
13 * copy of this software and associated documentation files (the "Software"),
14 * to deal in the Software without restriction, including without limitation
15 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
16 * and/or sell copies of the Software, and to permit persons to whom the
17 * Software is furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice (including the next
20 * paragraph) shall be included in all copies or substantial portions of the
21 * Software.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29 * OTHER DEALINGS IN THE SOFTWARE.
30 */
31
David Howells760285e2012-10-02 18:01:07 +010032#include <drm/drmP.h>
33#include <drm/radeon_drm.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070034#include "radeon_drv.h"
35
David Howells760285e2012-10-02 18:01:07 +010036#include <drm/drm_pciids.h>
Jerome Glisse771fe6b2009-06-05 14:42:42 +020037#include <linux/console.h>
Paul Gortmakere0cd3602011-08-30 11:04:30 -040038#include <linux/module.h>
Dave Airlie10ebc0b2012-09-17 14:40:31 +100039#include <linux/pm_runtime.h>
40#include <linux/vga_switcheroo.h>
41#include "drm_crtc_helper.h"
Jerome Glisse771fe6b2009-06-05 14:42:42 +020042/*
43 * KMS wrapper.
Dave Airlie0de1a572010-03-01 16:32:15 +100044 * - 2.0.0 - initial interface
45 * - 2.1.0 - add square tiling interface
Alex Deucherfdb43522010-03-26 15:24:14 -040046 * - 2.2.0 - add r6xx/r7xx const buffer support
Marek Olšákcae94b02010-02-21 21:24:15 +010047 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs
Jerome Glissebc35afd2010-05-12 18:01:13 +020048 * - 2.4.0 - add crtc id query
Alex Deucher148a03b2010-06-03 19:00:03 -040049 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen
Dave Airlieab9e1f52010-07-13 11:11:11 +100050 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500)
Alex Deucher71901cc2010-10-21 13:45:30 -040051 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs
Alex Deucher58bbf012011-01-24 17:14:26 -050052 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query
Dave Airlie486af182011-03-01 14:32:27 +100053 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query
Alex Deucherb8709892011-07-27 04:17:25 +000054 * 2.10.0 - fusion 2D tiling
55 * 2.11.0 - backend map, initial compute support for the CS checker
Marek Olšáke70f2242011-10-25 01:38:45 +020056 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS
Marek Olšákdd220a02012-01-27 12:17:59 -050057 * 2.13.0 - virtual memory support, streamout
Jerome Glisse285484e2011-12-16 17:03:42 -050058 * 2.14.0 - add evergreen tiling informations
Tom Stellard609c1e12012-03-20 17:17:55 -040059 * 2.15.0 - add max_pipes query
Jerome Glissed2609872012-06-09 10:57:41 -040060 * 2.16.0 - fix evergreen 2D tiled surface calculation
Alex Deucher7c77bf22012-06-14 22:06:37 +020061 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx
Marek Olšák0f457e42012-07-29 16:24:57 +020062 * 2.18.0 - r600-eg: allow "invalid" DB formats
Marek Olšákb51ad122012-08-09 16:34:16 +020063 * 2.19.0 - r600-eg: MSAA textures
Marek Olšák6759a0a2012-08-09 16:34:17 +020064 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query
Marek Olšákc116cc92012-08-19 02:22:09 +020065 * 2.21.0 - r600-r700: FMASK and CMASK
Marek Olšák523885d2012-08-24 14:27:36 +020066 * 2.22.0 - r600 only: RESOLVE_BOX allowed
Marek Olšák46fc8782012-09-25 01:45:33 +020067 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880
Marek Olšák61051af2012-09-25 03:34:01 +020068 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures
Alex Deucher71bfe912012-12-07 20:00:30 -050069 * 2.25.0 - eg+: new info request for num SE and num SH
Jerome Glisse4ac05332012-12-13 12:08:11 -050070 * 2.26.0 - r600-eg: fix htile size computation
Alex Deucher8696e332012-12-13 18:57:07 -050071 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA
Jerome Glisse4613ca12012-12-19 12:26:45 -050072 * 2.28.0 - r600-eg: Add MEM_WRITE packet support
Marek Olšákc18b1172013-01-12 04:19:37 +010073 * 2.29.0 - R500 FP16 color clear registers
Marek Olšák774c3892013-03-01 13:40:31 +010074 * 2.30.0 - fix for FMASK texturing
Samuel Lia0a53aa2013-04-08 17:25:47 -040075 * 2.31.0 - Add fastfb support for rs690
Christian König902aaef2013-04-09 10:35:42 -040076 * 2.32.0 - new info request for rings working
Jerome Glisse64d7b8b2013-04-09 11:17:08 -040077 * 2.33.0 - Add SI tiling mode array query
Alex Deucher39aee492013-04-10 13:41:25 -040078 * 2.34.0 - Add CIK tiling mode array query
Michel Dänzer32f79a82013-11-18 18:26:00 +090079 * 2.35.0 - Add CIK macrotile mode array query
Alex Deucher9482d0d2013-12-23 11:31:44 -050080 * 2.36.0 - Fix CIK DCE tiling setup
Dave Airlie7c4c62a2014-01-30 14:11:12 +100081 * 2.37.0 - allow GS ring setup on r6xx/r7xx
Marek Olšák020ff542014-03-22 16:20:43 +010082 * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN),
83 * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG
Alex Deucher65fcf662014-06-02 16:13:21 -040084 * 2.39.0 - Add INFO query for number of active CUs
Michel Dänzer72a99872014-07-31 18:43:49 +090085 * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting
86 * CS to GPU
Jerome Glisse771fe6b2009-06-05 14:42:42 +020087 */
88#define KMS_DRIVER_MAJOR 2
Michel Dänzer72a99872014-07-31 18:43:49 +090089#define KMS_DRIVER_MINOR 40
Jerome Glisse771fe6b2009-06-05 14:42:42 +020090#define KMS_DRIVER_PATCHLEVEL 0
91int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
92int radeon_driver_unload_kms(struct drm_device *dev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +020093void radeon_driver_lastclose_kms(struct drm_device *dev);
94int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
95void radeon_driver_postclose_kms(struct drm_device *dev,
96 struct drm_file *file_priv);
97void radeon_driver_preclose_kms(struct drm_device *dev,
98 struct drm_file *file_priv);
Dave Airlie10ebc0b2012-09-17 14:40:31 +100099int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
100int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200101u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc);
102int radeon_enable_vblank_kms(struct drm_device *dev, int crtc);
103void radeon_disable_vblank_kms(struct drm_device *dev, int crtc);
Mario Kleinerf5a80202010-10-23 04:42:17 +0200104int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
105 int *max_error,
106 struct timeval *vblank_time,
107 unsigned flags);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200108void radeon_driver_irq_preinstall_kms(struct drm_device *dev);
109int radeon_driver_irq_postinstall_kms(struct drm_device *dev);
110void radeon_driver_irq_uninstall_kms(struct drm_device *dev);
Daniel Vettere9f0d762013-12-11 11:34:42 +0100111irqreturn_t radeon_driver_irq_handler_kms(int irq, void *arg);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200112void radeon_gem_object_free(struct drm_gem_object *obj);
Jerome Glisse721604a2012-01-05 22:11:05 -0500113int radeon_gem_object_open(struct drm_gem_object *obj,
114 struct drm_file *file_priv);
115void radeon_gem_object_close(struct drm_gem_object *obj,
116 struct drm_file *file_priv);
Mario Kleinerf5a80202010-10-23 04:42:17 +0200117extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc,
Ville Syrjäläabca9e42013-10-28 20:50:48 +0200118 unsigned int flags,
Mario Kleinerd47abc52013-10-30 05:13:07 +0100119 int *vpos, int *hpos, ktime_t *stime,
120 ktime_t *etime);
Alex Deucher90c4cde2014-04-10 22:29:01 -0400121extern bool radeon_is_px(struct drm_device *dev);
Rob Clarkbaa70942013-08-02 13:27:49 -0400122extern const struct drm_ioctl_desc radeon_ioctls_kms[];
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200123extern int radeon_max_kms_ioctl;
124int radeon_mmap(struct file *filp, struct vm_area_struct *vma);
Dave Airlieff72145b2011-02-07 12:16:14 +1000125int radeon_mode_dumb_mmap(struct drm_file *filp,
126 struct drm_device *dev,
127 uint32_t handle, uint64_t *offset_p);
128int radeon_mode_dumb_create(struct drm_file *file_priv,
129 struct drm_device *dev,
130 struct drm_mode_create_dumb *args);
Aaron Plattner1e6d17a2013-01-15 20:47:44 +0000131struct sg_table *radeon_gem_prime_get_sg_table(struct drm_gem_object *obj);
132struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev,
133 size_t size,
134 struct sg_table *sg);
135int radeon_gem_prime_pin(struct drm_gem_object *obj);
Maarten Lankhorst280cf212013-06-27 13:38:18 +0200136void radeon_gem_prime_unpin(struct drm_gem_object *obj);
Maarten Lankhorst3aac4502014-07-01 12:57:26 +0200137struct reservation_object *radeon_gem_prime_res_obj(struct drm_gem_object *);
Aaron Plattner1e6d17a2013-01-15 20:47:44 +0000138void *radeon_gem_prime_vmap(struct drm_gem_object *obj);
139void radeon_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
Christian König14adc892013-01-21 13:58:46 +0100140extern long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd,
141 unsigned long arg);
Dave Airlieff72145b2011-02-07 12:16:14 +1000142
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200143#if defined(CONFIG_DEBUG_FS)
144int radeon_debugfs_init(struct drm_minor *minor);
145void radeon_debugfs_cleanup(struct drm_minor *minor);
146#endif
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200147
Christian König14adc892013-01-21 13:58:46 +0100148/* atpx handler */
149#if defined(CONFIG_VGA_SWITCHEROO)
150void radeon_register_atpx_handler(void);
151void radeon_unregister_atpx_handler(void);
152#else
153static inline void radeon_register_atpx_handler(void) {}
154static inline void radeon_unregister_atpx_handler(void) {}
155#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700156
Dave Airlie689b9d72005-09-30 17:09:07 +1000157int radeon_no_wb;
Dave Airliee9ced8e2013-05-15 01:23:36 +0000158int radeon_modeset = -1;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200159int radeon_dynclks = -1;
160int radeon_r4xx_atom = 0;
161int radeon_agpmode = 0;
162int radeon_vram_limit = 0;
Alex Deucheredcd26e2013-07-05 17:16:51 -0400163int radeon_gart_size = -1; /* auto */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200164int radeon_benchmarking = 0;
Michel Dänzerecc0b322009-07-21 11:23:57 +0200165int radeon_testing = 0;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200166int radeon_connector_table = 0;
Dave Airlie4ce001a2009-08-13 16:32:14 +1000167int radeon_tv = 1;
Alex Deucher108dc8e2013-10-14 13:17:50 -0400168int radeon_audio = -1;
Alex Deucherf46c0122010-03-31 00:33:27 -0400169int radeon_disp_priority = 0;
Alex Deuchere2b0a8e2010-03-17 02:07:37 -0400170int radeon_hw_i2c = 0;
Dave Airlie197bbb32012-06-27 08:35:54 +0100171int radeon_pcie_gen2 = -1;
Alex Deuchera18cee12011-11-01 14:20:30 -0400172int radeon_msi = -1;
Christian König3368ff02012-05-02 15:11:21 +0200173int radeon_lockup_timeout = 10000;
Samuel Lia0a53aa2013-04-08 17:25:47 -0400174int radeon_fastfb = 0;
Alex Deucherda321c82013-04-12 13:55:22 -0400175int radeon_dpm = -1;
Alex Deucher1294d4a2013-07-16 15:58:50 -0400176int radeon_aspm = -1;
Dave Airlie10ebc0b2012-09-17 14:40:31 +1000177int radeon_runtime_pm = -1;
Alex Deucher363eb0b2014-01-08 17:55:08 -0500178int radeon_hard_reset = 0;
Christian Königdfc230f2014-07-19 13:55:58 +0200179int radeon_vm_size = 8;
180int radeon_vm_block_size = -1;
Alex Deuchera624f422014-07-01 11:23:03 -0400181int radeon_deep_color = 0;
Mario Kleiner39dc5452014-07-29 06:21:44 +0200182int radeon_use_pflipirq = 2;
Dave Airlie689b9d72005-09-30 17:09:07 +1000183
Niels de Vos61a2d072008-07-31 00:07:23 -0700184MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
Dave Airlie689b9d72005-09-30 17:09:07 +1000185module_param_named(no_wb, radeon_no_wb, int, 0444);
186
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200187MODULE_PARM_DESC(modeset, "Disable/Enable modesetting");
188module_param_named(modeset, radeon_modeset, int, 0400);
189
190MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks");
191module_param_named(dynclks, radeon_dynclks, int, 0444);
192
193MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx");
194module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444);
195
Lauri Kasanen8902e6f2014-04-08 13:39:36 +0300196MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200197module_param_named(vramlimit, radeon_vram_limit, int, 0600);
198
199MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)");
200module_param_named(agpmode, radeon_agpmode, int, 0444);
201
Alex Deucheredcd26e2013-07-05 17:16:51 -0400202MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200203module_param_named(gartsize, radeon_gart_size, int, 0600);
204
205MODULE_PARM_DESC(benchmark, "Run benchmark");
206module_param_named(benchmark, radeon_benchmarking, int, 0444);
207
Michel Dänzerecc0b322009-07-21 11:23:57 +0200208MODULE_PARM_DESC(test, "Run tests");
209module_param_named(test, radeon_testing, int, 0444);
210
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200211MODULE_PARM_DESC(connector_table, "Force connector table");
212module_param_named(connector_table, radeon_connector_table, int, 0444);
Dave Airlie4ce001a2009-08-13 16:32:14 +1000213
214MODULE_PARM_DESC(tv, "TV enable (0 = disable)");
215module_param_named(tv, radeon_tv, int, 0444);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200216
Alex Deucher108dc8e2013-10-14 13:17:50 -0400217MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
Christian Koenigdafc3bd2009-10-11 23:49:13 +0200218module_param_named(audio, radeon_audio, int, 0444);
219
Alex Deucherf46c0122010-03-31 00:33:27 -0400220MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
221module_param_named(disp_priority, radeon_disp_priority, int, 0444);
222
Alex Deuchere2b0a8e2010-03-17 02:07:37 -0400223MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
224module_param_named(hw_i2c, radeon_hw_i2c, int, 0444);
225
Dave Airlie197bbb32012-06-27 08:35:54 +0100226MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
Alex Deucherd42dd572011-01-12 20:05:11 -0500227module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444);
228
Alex Deuchera18cee12011-11-01 14:20:30 -0400229MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
230module_param_named(msi, radeon_msi, int, 0444);
231
Christian König3368ff02012-05-02 15:11:21 +0200232MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (defaul 10000 = 10 seconds, 0 = disable)");
233module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444);
234
Samuel Lia0a53aa2013-04-08 17:25:47 -0400235MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)");
236module_param_named(fastfb, radeon_fastfb, int, 0444);
237
Alex Deucherda321c82013-04-12 13:55:22 -0400238MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
239module_param_named(dpm, radeon_dpm, int, 0444);
240
Alex Deucher1294d4a2013-07-16 15:58:50 -0400241MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
242module_param_named(aspm, radeon_aspm, int, 0444);
243
Dave Airlie10ebc0b2012-09-17 14:40:31 +1000244MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
245module_param_named(runpm, radeon_runtime_pm, int, 0444);
246
Alex Deucher363eb0b2014-01-08 17:55:08 -0500247MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))");
248module_param_named(hard_reset, radeon_hard_reset, int, 0444);
249
Christian König20b26562014-07-18 13:56:56 +0200250MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)");
Christian Königc1c44132014-06-05 23:47:32 -0400251module_param_named(vm_size, radeon_vm_size, int, 0444);
252
Christian Königdfc230f2014-07-19 13:55:58 +0200253MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
Christian König4510fb92014-06-05 23:56:50 -0400254module_param_named(vm_block_size, radeon_vm_block_size, int, 0444);
255
Alex Deuchera624f422014-07-01 11:23:03 -0400256MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
257module_param_named(deep_color, radeon_deep_color, int, 0444);
258
Mario Kleiner39dc5452014-07-29 06:21:44 +0200259MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))");
260module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444);
261
Christian König14adc892013-01-21 13:58:46 +0100262static struct pci_device_id pciidlist[] = {
263 radeon_PCI_IDS
264};
265
266MODULE_DEVICE_TABLE(pci, pciidlist);
267
268#ifdef CONFIG_DRM_RADEON_UMS
269
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700270static int radeon_suspend(struct drm_device *dev, pm_message_t state)
271{
272 drm_radeon_private_t *dev_priv = dev->dev_private;
273
Dave Airlie03efb882009-03-10 18:36:38 +1000274 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
275 return 0;
276
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700277 /* Disable *all* interrupts */
Alex Deucher800b6992009-03-06 11:47:54 -0500278 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700279 RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
280 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
281 return 0;
282}
283
284static int radeon_resume(struct drm_device *dev)
285{
286 drm_radeon_private_t *dev_priv = dev->dev_private;
287
Dave Airlie03efb882009-03-10 18:36:38 +1000288 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
289 return 0;
290
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700291 /* Restore interrupt registers */
Alex Deucher800b6992009-03-06 11:47:54 -0500292 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700293 RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg);
294 RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
295 return 0;
296}
297
Dave Airlie10ebc0b2012-09-17 14:40:31 +1000298
Arjan van de Vene08e96d2011-10-31 07:28:57 -0700299static const struct file_operations radeon_driver_old_fops = {
300 .owner = THIS_MODULE,
301 .open = drm_open,
302 .release = drm_release,
303 .unlocked_ioctl = drm_ioctl,
304 .mmap = drm_mmap,
305 .poll = drm_poll,
Arjan van de Vene08e96d2011-10-31 07:28:57 -0700306 .read = drm_read,
307#ifdef CONFIG_COMPAT
308 .compat_ioctl = radeon_compat_ioctl,
309#endif
310 .llseek = noop_llseek,
311};
312
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200313static struct drm_driver driver_old = {
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000314 .driver_features =
Daniel Vetter28185642013-08-08 15:41:27 +0200315 DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_SG |
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700316 DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700317 .dev_priv_size = sizeof(drm_radeon_buf_priv_t),
Dave Airlie22eae942005-11-10 22:16:34 +1100318 .load = radeon_driver_load,
319 .firstopen = radeon_driver_firstopen,
320 .open = radeon_driver_open,
321 .preclose = radeon_driver_preclose,
322 .postclose = radeon_driver_postclose,
323 .lastclose = radeon_driver_lastclose,
324 .unload = radeon_driver_unload,
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700325 .suspend = radeon_suspend,
326 .resume = radeon_resume,
327 .get_vblank_counter = radeon_get_vblank_counter,
328 .enable_vblank = radeon_enable_vblank,
329 .disable_vblank = radeon_disable_vblank,
Dave Airlie60f2ee02008-12-19 10:22:02 +1100330 .master_create = radeon_master_create,
331 .master_destroy = radeon_master_destroy,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700332 .irq_preinstall = radeon_driver_irq_preinstall,
333 .irq_postinstall = radeon_driver_irq_postinstall,
334 .irq_uninstall = radeon_driver_irq_uninstall,
335 .irq_handler = radeon_driver_irq_handler,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700336 .ioctls = radeon_ioctls,
337 .dma_ioctl = radeon_cp_buffers,
Arjan van de Vene08e96d2011-10-31 07:28:57 -0700338 .fops = &radeon_driver_old_fops,
Dave Airlie22eae942005-11-10 22:16:34 +1100339 .name = DRIVER_NAME,
340 .desc = DRIVER_DESC,
341 .date = DRIVER_DATE,
342 .major = DRIVER_MAJOR,
343 .minor = DRIVER_MINOR,
344 .patchlevel = DRIVER_PATCHLEVEL,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700345};
346
Christian König14adc892013-01-21 13:58:46 +0100347#endif
348
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200349static struct drm_driver kms_driver;
350
Tommi Rantala30238152012-11-09 09:19:39 +0000351static int radeon_kick_out_firmware_fb(struct pci_dev *pdev)
Benjamin Herrenschmidta56f7422010-10-06 16:39:07 +0000352{
353 struct apertures_struct *ap;
354 bool primary = false;
355
356 ap = alloc_apertures(1);
Tommi Rantala30238152012-11-09 09:19:39 +0000357 if (!ap)
358 return -ENOMEM;
359
Benjamin Herrenschmidta56f7422010-10-06 16:39:07 +0000360 ap->ranges[0].base = pci_resource_start(pdev, 0);
361 ap->ranges[0].size = pci_resource_len(pdev, 0);
362
363#ifdef CONFIG_X86
364 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
365#endif
366 remove_conflicting_framebuffers(ap, "radeondrmfb", primary);
367 kfree(ap);
Tommi Rantala30238152012-11-09 09:19:39 +0000368
369 return 0;
Benjamin Herrenschmidta56f7422010-10-06 16:39:07 +0000370}
371
Greg Kroah-Hartman56550d92012-12-21 15:09:25 -0800372static int radeon_pci_probe(struct pci_dev *pdev,
373 const struct pci_device_id *ent)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200374{
Tommi Rantala30238152012-11-09 09:19:39 +0000375 int ret;
376
Benjamin Herrenschmidta56f7422010-10-06 16:39:07 +0000377 /* Get rid of things like offb */
Tommi Rantala30238152012-11-09 09:19:39 +0000378 ret = radeon_kick_out_firmware_fb(pdev);
379 if (ret)
380 return ret;
Benjamin Herrenschmidta56f7422010-10-06 16:39:07 +0000381
Jordan Crousedcdb1672010-05-27 13:40:25 -0600382 return drm_get_pci_dev(pdev, ent, &kms_driver);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200383}
384
385static void
386radeon_pci_remove(struct pci_dev *pdev)
387{
388 struct drm_device *dev = pci_get_drvdata(pdev);
389
390 drm_put_dev(dev);
391}
392
Dave Airlie7473e832012-09-13 12:02:30 +1000393static int radeon_pmops_suspend(struct device *dev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200394{
Dave Airlie7473e832012-09-13 12:02:30 +1000395 struct pci_dev *pdev = to_pci_dev(dev);
396 struct drm_device *drm_dev = pci_get_drvdata(pdev);
Dave Airlie10ebc0b2012-09-17 14:40:31 +1000397 return radeon_suspend_kms(drm_dev, true, true);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200398}
399
Dave Airlie7473e832012-09-13 12:02:30 +1000400static int radeon_pmops_resume(struct device *dev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200401{
Dave Airlie7473e832012-09-13 12:02:30 +1000402 struct pci_dev *pdev = to_pci_dev(dev);
403 struct drm_device *drm_dev = pci_get_drvdata(pdev);
Dave Airlie10ebc0b2012-09-17 14:40:31 +1000404 return radeon_resume_kms(drm_dev, true, true);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200405}
406
Dave Airlie7473e832012-09-13 12:02:30 +1000407static int radeon_pmops_freeze(struct device *dev)
408{
409 struct pci_dev *pdev = to_pci_dev(dev);
410 struct drm_device *drm_dev = pci_get_drvdata(pdev);
Dave Airlie10ebc0b2012-09-17 14:40:31 +1000411 return radeon_suspend_kms(drm_dev, false, true);
Dave Airlie7473e832012-09-13 12:02:30 +1000412}
413
414static int radeon_pmops_thaw(struct device *dev)
415{
416 struct pci_dev *pdev = to_pci_dev(dev);
417 struct drm_device *drm_dev = pci_get_drvdata(pdev);
Dave Airlie10ebc0b2012-09-17 14:40:31 +1000418 return radeon_resume_kms(drm_dev, false, true);
419}
420
421static int radeon_pmops_runtime_suspend(struct device *dev)
422{
423 struct pci_dev *pdev = to_pci_dev(dev);
424 struct drm_device *drm_dev = pci_get_drvdata(pdev);
425 int ret;
426
Alex Deucher90c4cde2014-04-10 22:29:01 -0400427 if (!radeon_is_px(drm_dev)) {
Dave Airlie1d8eec82014-03-27 14:09:18 +1000428 pm_runtime_forbid(dev);
429 return -EBUSY;
430 }
Alex Deucher9babd352014-01-24 14:59:42 -0500431
Dave Airlie10ebc0b2012-09-17 14:40:31 +1000432 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
433 drm_kms_helper_poll_disable(drm_dev);
434 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
435
436 ret = radeon_suspend_kms(drm_dev, false, false);
437 pci_save_state(pdev);
438 pci_disable_device(pdev);
439 pci_set_power_state(pdev, PCI_D3cold);
440 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
441
442 return 0;
443}
444
445static int radeon_pmops_runtime_resume(struct device *dev)
446{
447 struct pci_dev *pdev = to_pci_dev(dev);
448 struct drm_device *drm_dev = pci_get_drvdata(pdev);
449 int ret;
450
Alex Deucher90c4cde2014-04-10 22:29:01 -0400451 if (!radeon_is_px(drm_dev))
Alex Deucher9babd352014-01-24 14:59:42 -0500452 return -EINVAL;
453
Dave Airlie10ebc0b2012-09-17 14:40:31 +1000454 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
455
456 pci_set_power_state(pdev, PCI_D0);
457 pci_restore_state(pdev);
458 ret = pci_enable_device(pdev);
459 if (ret)
460 return ret;
461 pci_set_master(pdev);
462
463 ret = radeon_resume_kms(drm_dev, false, false);
464 drm_kms_helper_poll_enable(drm_dev);
465 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON);
466 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
467 return 0;
468}
469
470static int radeon_pmops_runtime_idle(struct device *dev)
471{
472 struct pci_dev *pdev = to_pci_dev(dev);
473 struct drm_device *drm_dev = pci_get_drvdata(pdev);
474 struct drm_crtc *crtc;
475
Alex Deucher90c4cde2014-04-10 22:29:01 -0400476 if (!radeon_is_px(drm_dev)) {
Dave Airlie1d8eec82014-03-27 14:09:18 +1000477 pm_runtime_forbid(dev);
Dave Airlie10ebc0b2012-09-17 14:40:31 +1000478 return -EBUSY;
479 }
480
481 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
482 if (crtc->enabled) {
483 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
484 return -EBUSY;
485 }
486 }
487
488 pm_runtime_mark_last_busy(dev);
489 pm_runtime_autosuspend(dev);
490 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
491 return 1;
492}
493
494long radeon_drm_ioctl(struct file *filp,
495 unsigned int cmd, unsigned long arg)
496{
497 struct drm_file *file_priv = filp->private_data;
498 struct drm_device *dev;
499 long ret;
500 dev = file_priv->minor->dev;
501 ret = pm_runtime_get_sync(dev->dev);
502 if (ret < 0)
503 return ret;
504
505 ret = drm_ioctl(filp, cmd, arg);
506
507 pm_runtime_mark_last_busy(dev->dev);
508 pm_runtime_put_autosuspend(dev->dev);
509 return ret;
Dave Airlie7473e832012-09-13 12:02:30 +1000510}
511
512static const struct dev_pm_ops radeon_pm_ops = {
513 .suspend = radeon_pmops_suspend,
514 .resume = radeon_pmops_resume,
515 .freeze = radeon_pmops_freeze,
516 .thaw = radeon_pmops_thaw,
517 .poweroff = radeon_pmops_freeze,
518 .restore = radeon_pmops_resume,
Dave Airlie10ebc0b2012-09-17 14:40:31 +1000519 .runtime_suspend = radeon_pmops_runtime_suspend,
520 .runtime_resume = radeon_pmops_runtime_resume,
521 .runtime_idle = radeon_pmops_runtime_idle,
Dave Airlie7473e832012-09-13 12:02:30 +1000522};
523
Arjan van de Vene08e96d2011-10-31 07:28:57 -0700524static const struct file_operations radeon_driver_kms_fops = {
525 .owner = THIS_MODULE,
526 .open = drm_open,
527 .release = drm_release,
Dave Airlie10ebc0b2012-09-17 14:40:31 +1000528 .unlocked_ioctl = radeon_drm_ioctl,
Arjan van de Vene08e96d2011-10-31 07:28:57 -0700529 .mmap = radeon_mmap,
530 .poll = drm_poll,
Arjan van de Vene08e96d2011-10-31 07:28:57 -0700531 .read = drm_read,
532#ifdef CONFIG_COMPAT
533 .compat_ioctl = radeon_kms_compat_ioctl,
534#endif
535};
536
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200537static struct drm_driver kms_driver = {
538 .driver_features =
Daniel Vetter28185642013-08-08 15:41:27 +0200539 DRIVER_USE_AGP |
Daniel Vetter81e95692013-07-10 14:11:49 +0200540 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
Christian Königf33bcab2013-08-25 18:29:03 +0200541 DRIVER_PRIME | DRIVER_RENDER,
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200542 .load = radeon_driver_load_kms,
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200543 .open = radeon_driver_open_kms,
544 .preclose = radeon_driver_preclose_kms,
545 .postclose = radeon_driver_postclose_kms,
546 .lastclose = radeon_driver_lastclose_kms,
547 .unload = radeon_driver_unload_kms,
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200548 .get_vblank_counter = radeon_get_vblank_counter_kms,
549 .enable_vblank = radeon_enable_vblank_kms,
550 .disable_vblank = radeon_disable_vblank_kms,
Mario Kleinerf5a80202010-10-23 04:42:17 +0200551 .get_vblank_timestamp = radeon_get_vblank_timestamp_kms,
552 .get_scanout_position = radeon_get_crtc_scanoutpos,
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200553#if defined(CONFIG_DEBUG_FS)
554 .debugfs_init = radeon_debugfs_init,
555 .debugfs_cleanup = radeon_debugfs_cleanup,
556#endif
557 .irq_preinstall = radeon_driver_irq_preinstall_kms,
558 .irq_postinstall = radeon_driver_irq_postinstall_kms,
559 .irq_uninstall = radeon_driver_irq_uninstall_kms,
560 .irq_handler = radeon_driver_irq_handler_kms,
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200561 .ioctls = radeon_ioctls_kms,
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200562 .gem_free_object = radeon_gem_object_free,
Jerome Glisse721604a2012-01-05 22:11:05 -0500563 .gem_open_object = radeon_gem_object_open,
564 .gem_close_object = radeon_gem_object_close,
Dave Airlieff72145b2011-02-07 12:16:14 +1000565 .dumb_create = radeon_mode_dumb_create,
566 .dumb_map_offset = radeon_mode_dumb_mmap,
Daniel Vetter43387b32013-07-16 09:12:04 +0200567 .dumb_destroy = drm_gem_dumb_destroy,
Arjan van de Vene08e96d2011-10-31 07:28:57 -0700568 .fops = &radeon_driver_kms_fops,
Alex Deucher40f5cf92012-05-10 18:33:13 -0400569
570 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
571 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
Aaron Plattner1e6d17a2013-01-15 20:47:44 +0000572 .gem_prime_export = drm_gem_prime_export,
573 .gem_prime_import = drm_gem_prime_import,
574 .gem_prime_pin = radeon_gem_prime_pin,
Maarten Lankhorst280cf212013-06-27 13:38:18 +0200575 .gem_prime_unpin = radeon_gem_prime_unpin,
Maarten Lankhorst3aac4502014-07-01 12:57:26 +0200576 .gem_prime_res_obj = radeon_gem_prime_res_obj,
Aaron Plattner1e6d17a2013-01-15 20:47:44 +0000577 .gem_prime_get_sg_table = radeon_gem_prime_get_sg_table,
578 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table,
579 .gem_prime_vmap = radeon_gem_prime_vmap,
580 .gem_prime_vunmap = radeon_gem_prime_vunmap,
Alex Deucher40f5cf92012-05-10 18:33:13 -0400581
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200582 .name = DRIVER_NAME,
583 .desc = DRIVER_DESC,
584 .date = DRIVER_DATE,
585 .major = KMS_DRIVER_MAJOR,
586 .minor = KMS_DRIVER_MINOR,
587 .patchlevel = KMS_DRIVER_PATCHLEVEL,
588};
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200589
590static struct drm_driver *driver;
Dave Airlie8410ea32010-12-15 03:16:38 +1000591static struct pci_driver *pdriver;
592
Christian König14adc892013-01-21 13:58:46 +0100593#ifdef CONFIG_DRM_RADEON_UMS
Dave Airlie8410ea32010-12-15 03:16:38 +1000594static struct pci_driver radeon_pci_driver = {
595 .name = DRIVER_NAME,
596 .id_table = pciidlist,
597};
Christian König14adc892013-01-21 13:58:46 +0100598#endif
Dave Airlie8410ea32010-12-15 03:16:38 +1000599
600static struct pci_driver radeon_kms_pci_driver = {
601 .name = DRIVER_NAME,
602 .id_table = pciidlist,
603 .probe = radeon_pci_probe,
604 .remove = radeon_pci_remove,
Dave Airlie7473e832012-09-13 12:02:30 +1000605 .driver.pm = &radeon_pm_ops,
Dave Airlie8410ea32010-12-15 03:16:38 +1000606};
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200607
Linus Torvalds1da177e2005-04-16 15:20:36 -0700608static int __init radeon_init(void)
609{
Dave Airliee9ced8e2013-05-15 01:23:36 +0000610#ifdef CONFIG_VGA_CONSOLE
611 if (vgacon_text_force() && radeon_modeset == -1) {
612 DRM_INFO("VGACON disable radeon kernel modesetting.\n");
613 radeon_modeset = 0;
614 }
615#endif
616 /* set to modesetting by default if not nomodeset */
617 if (radeon_modeset == -1)
618 radeon_modeset = 1;
619
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200620 if (radeon_modeset == 1) {
621 DRM_INFO("radeon kernel modesetting enabled.\n");
622 driver = &kms_driver;
Dave Airlie8410ea32010-12-15 03:16:38 +1000623 pdriver = &radeon_kms_pci_driver;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200624 driver->driver_features |= DRIVER_MODESET;
625 driver->num_ioctls = radeon_max_kms_ioctl;
Dave Airlie6a9ee8a2010-02-01 15:38:10 +1000626 radeon_register_atpx_handler();
Christian König14adc892013-01-21 13:58:46 +0100627
628 } else {
629#ifdef CONFIG_DRM_RADEON_UMS
630 DRM_INFO("radeon userspace modesetting enabled.\n");
631 driver = &driver_old;
632 pdriver = &radeon_pci_driver;
633 driver->driver_features &= ~DRIVER_MODESET;
634 driver->num_ioctls = radeon_max_ioctl;
635#else
636 DRM_ERROR("No UMS support in radeon module!\n");
637 return -EINVAL;
638#endif
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200639 }
Christian König14adc892013-01-21 13:58:46 +0100640
641 /* let modprobe override vga console setting */
Dave Airlie8410ea32010-12-15 03:16:38 +1000642 return drm_pci_init(driver, pdriver);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700643}
644
645static void __exit radeon_exit(void)
646{
Dave Airlie8410ea32010-12-15 03:16:38 +1000647 drm_pci_exit(driver, pdriver);
Dave Airlie6a9ee8a2010-02-01 15:38:10 +1000648 radeon_unregister_atpx_handler();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700649}
650
Jerome Glisse176f6132009-06-22 18:16:13 +0200651module_init(radeon_init);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700652module_exit(radeon_exit);
653
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000654MODULE_AUTHOR(DRIVER_AUTHOR);
655MODULE_DESCRIPTION(DRIVER_DESC);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700656MODULE_LICENSE("GPL and additional rights");