blob: 6b6cc8434d3c8bfb0b077dd06039b57d9d54df78 [file] [log] [blame]
Dave Airlief26c4732006-01-02 17:18:39 +11001/* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
2/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07003 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
Alex Deucher45e51902008-05-28 13:28:59 +10005 * Copyright 2007 Advanced Micro Devices, Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07006 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Kevin E. Martin <martin@valinux.com>
29 * Gareth Hughes <gareth@valinux.com>
30 */
31
32#include "drmP.h"
33#include "drm.h"
Dave Airlie7c1c2872008-11-28 14:22:24 +100034#include "drm_sarea.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070035#include "radeon_drm.h"
36#include "radeon_drv.h"
Dave Airlie414ed532005-08-16 20:43:16 +100037#include "r300_reg.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070038
39#define RADEON_FIFO_DEBUG 0
40
Ben Hutchings70967ab2009-08-29 14:53:51 +010041/* Firmware Names */
42#define FIRMWARE_R100 "radeon/R100_cp.bin"
43#define FIRMWARE_R200 "radeon/R200_cp.bin"
44#define FIRMWARE_R300 "radeon/R300_cp.bin"
45#define FIRMWARE_R420 "radeon/R420_cp.bin"
46#define FIRMWARE_RS690 "radeon/RS690_cp.bin"
47#define FIRMWARE_RS600 "radeon/RS600_cp.bin"
48#define FIRMWARE_R520 "radeon/R520_cp.bin"
49
50MODULE_FIRMWARE(FIRMWARE_R100);
51MODULE_FIRMWARE(FIRMWARE_R200);
52MODULE_FIRMWARE(FIRMWARE_R300);
53MODULE_FIRMWARE(FIRMWARE_R420);
54MODULE_FIRMWARE(FIRMWARE_RS690);
55MODULE_FIRMWARE(FIRMWARE_RS600);
56MODULE_FIRMWARE(FIRMWARE_R520);
57
Dave Airlie84b1fd12007-07-11 15:53:27 +100058static int radeon_do_cleanup_cp(struct drm_device * dev);
Jerome Glisse54f961a2008-08-13 09:46:31 +100059static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -070060
Alex Deucherc05ce082009-02-24 16:22:29 -050061u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off)
David Millerb07fa022009-02-12 02:15:37 -080062{
63 u32 val;
64
65 if (dev_priv->flags & RADEON_IS_AGP) {
66 val = DRM_READ32(dev_priv->ring_rptr, off);
67 } else {
68 val = *(((volatile u32 *)
69 dev_priv->ring_rptr->handle) +
70 (off / sizeof(u32)));
71 val = le32_to_cpu(val);
72 }
73 return val;
74}
75
76u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv)
77{
78 if (dev_priv->writeback_works)
79 return radeon_read_ring_rptr(dev_priv, 0);
Alex Deucherc05ce082009-02-24 16:22:29 -050080 else {
81 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
82 return RADEON_READ(R600_CP_RB_RPTR);
83 else
84 return RADEON_READ(RADEON_CP_RB_RPTR);
85 }
David Millerb07fa022009-02-12 02:15:37 -080086}
87
Alex Deucherc05ce082009-02-24 16:22:29 -050088void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val)
David Millerb07fa022009-02-12 02:15:37 -080089{
90 if (dev_priv->flags & RADEON_IS_AGP)
91 DRM_WRITE32(dev_priv->ring_rptr, off, val);
92 else
93 *(((volatile u32 *) dev_priv->ring_rptr->handle) +
94 (off / sizeof(u32))) = cpu_to_le32(val);
95}
96
97void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val)
98{
99 radeon_write_ring_rptr(dev_priv, 0, val);
100}
101
102u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index)
103{
Alex Deucherc05ce082009-02-24 16:22:29 -0500104 if (dev_priv->writeback_works) {
105 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
106 return radeon_read_ring_rptr(dev_priv,
107 R600_SCRATCHOFF(index));
108 else
109 return radeon_read_ring_rptr(dev_priv,
110 RADEON_SCRATCHOFF(index));
111 } else {
112 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
113 return RADEON_READ(R600_SCRATCH_REG0 + 4*index);
114 else
115 return RADEON_READ(RADEON_SCRATCH_REG0 + 4*index);
116 }
David Millerb07fa022009-02-12 02:15:37 -0800117}
118
Alex Deucherbefb73c2009-02-24 14:02:13 -0500119u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr)
120{
121 u32 ret;
122
123 if (addr < 0x10000)
124 ret = DRM_READ32(dev_priv->mmio, addr);
125 else {
126 DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, addr);
127 ret = DRM_READ32(dev_priv->mmio, RADEON_MM_DATA);
128 }
129
130 return ret;
131}
132
Alex Deucher45e51902008-05-28 13:28:59 +1000133static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000134{
135 u32 ret;
136 RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
137 ret = RADEON_READ(R520_MC_IND_DATA);
138 RADEON_WRITE(R520_MC_IND_INDEX, 0);
139 return ret;
140}
141
Alex Deucher45e51902008-05-28 13:28:59 +1000142static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
143{
144 u32 ret;
145 RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
146 ret = RADEON_READ(RS480_NB_MC_DATA);
147 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
148 return ret;
149}
150
Maciej Cencora60f92682008-02-19 21:32:45 +1000151static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
152{
Alex Deucher45e51902008-05-28 13:28:59 +1000153 u32 ret;
Maciej Cencora60f92682008-02-19 21:32:45 +1000154 RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
Alex Deucher45e51902008-05-28 13:28:59 +1000155 ret = RADEON_READ(RS690_MC_DATA);
156 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
157 return ret;
158}
159
Alex Deucherc1556f72009-02-25 16:57:49 -0500160static u32 RS600_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
161{
162 u32 ret;
163 RADEON_WRITE(RS600_MC_INDEX, ((addr & RS600_MC_ADDR_MASK) |
164 RS600_MC_IND_CITF_ARB0));
165 ret = RADEON_READ(RS600_MC_DATA);
166 return ret;
167}
168
Alex Deucher45e51902008-05-28 13:28:59 +1000169static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
170{
Alex Deucherf0738e92008-10-16 17:12:02 +1000171 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
172 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
Alex Deucher45e51902008-05-28 13:28:59 +1000173 return RS690_READ_MCIND(dev_priv, addr);
Alex Deucherc1556f72009-02-25 16:57:49 -0500174 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
175 return RS600_READ_MCIND(dev_priv, addr);
Alex Deucher45e51902008-05-28 13:28:59 +1000176 else
177 return RS480_READ_MCIND(dev_priv, addr);
Maciej Cencora60f92682008-02-19 21:32:45 +1000178}
179
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000180u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
181{
182
Alex Deucherc05ce082009-02-24 16:22:29 -0500183 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
184 return RADEON_READ(R700_MC_VM_FB_LOCATION);
185 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
186 return RADEON_READ(R600_MC_VM_FB_LOCATION);
187 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
Alex Deucher45e51902008-05-28 13:28:59 +1000188 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
Alex Deucherf0738e92008-10-16 17:12:02 +1000189 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
190 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
Maciej Cencora60f92682008-02-19 21:32:45 +1000191 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
Alex Deucherc1556f72009-02-25 16:57:49 -0500192 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
193 return RS600_READ_MCIND(dev_priv, RS600_MC_FB_LOCATION);
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000194 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
Alex Deucher45e51902008-05-28 13:28:59 +1000195 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000196 else
197 return RADEON_READ(RADEON_MC_FB_LOCATION);
198}
199
200static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
201{
Alex Deucherc05ce082009-02-24 16:22:29 -0500202 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
203 RADEON_WRITE(R700_MC_VM_FB_LOCATION, fb_loc);
204 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
205 RADEON_WRITE(R600_MC_VM_FB_LOCATION, fb_loc);
206 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
Alex Deucher45e51902008-05-28 13:28:59 +1000207 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
Alex Deucherf0738e92008-10-16 17:12:02 +1000208 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
209 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
Maciej Cencora60f92682008-02-19 21:32:45 +1000210 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
Alex Deucherc1556f72009-02-25 16:57:49 -0500211 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
212 RS600_WRITE_MCIND(RS600_MC_FB_LOCATION, fb_loc);
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000213 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
Alex Deucher45e51902008-05-28 13:28:59 +1000214 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000215 else
216 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
217}
218
Alex Deucherc05ce082009-02-24 16:22:29 -0500219void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000220{
Alex Deucherc05ce082009-02-24 16:22:29 -0500221 /*R6xx/R7xx: AGP_TOP and BOT are actually 18 bits each */
222 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
223 RADEON_WRITE(R700_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
224 RADEON_WRITE(R700_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
225 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
226 RADEON_WRITE(R600_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
227 RADEON_WRITE(R600_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
228 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
Alex Deucher45e51902008-05-28 13:28:59 +1000229 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
Alex Deucherf0738e92008-10-16 17:12:02 +1000230 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
231 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
Maciej Cencora60f92682008-02-19 21:32:45 +1000232 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
Alex Deucherc1556f72009-02-25 16:57:49 -0500233 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
234 RS600_WRITE_MCIND(RS600_MC_AGP_LOCATION, agp_loc);
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000235 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
Alex Deucher45e51902008-05-28 13:28:59 +1000236 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000237 else
238 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
239}
240
Alex Deucherc05ce082009-02-24 16:22:29 -0500241void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
Dave Airlie70b13d52008-06-19 11:40:44 +1000242{
243 u32 agp_base_hi = upper_32_bits(agp_base);
244 u32 agp_base_lo = agp_base & 0xffffffff;
Alex Deucherc05ce082009-02-24 16:22:29 -0500245 u32 r6xx_agp_base = (agp_base >> 22) & 0x3ffff;
Dave Airlie70b13d52008-06-19 11:40:44 +1000246
Alex Deucherc05ce082009-02-24 16:22:29 -0500247 /* R6xx/R7xx must be aligned to a 4MB boundry */
248 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
249 RADEON_WRITE(R700_MC_VM_AGP_BASE, r6xx_agp_base);
250 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
251 RADEON_WRITE(R600_MC_VM_AGP_BASE, r6xx_agp_base);
252 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
Dave Airlie70b13d52008-06-19 11:40:44 +1000253 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
254 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
Alex Deucherf0738e92008-10-16 17:12:02 +1000255 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
256 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
Dave Airlie70b13d52008-06-19 11:40:44 +1000257 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
258 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
Alex Deucherc1556f72009-02-25 16:57:49 -0500259 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
260 RS600_WRITE_MCIND(RS600_AGP_BASE, agp_base_lo);
261 RS600_WRITE_MCIND(RS600_AGP_BASE_2, agp_base_hi);
Dave Airlie70b13d52008-06-19 11:40:44 +1000262 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
263 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
264 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
Alex Deucherb2ceddf2008-10-17 09:19:33 +1000265 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
266 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
Alex Deucher5cfb6952008-06-19 12:38:29 +1000267 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
Alex Deucherb2ceddf2008-10-17 09:19:33 +1000268 RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi);
Dave Airlie70b13d52008-06-19 11:40:44 +1000269 } else {
270 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
271 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
272 RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
273 }
274}
275
Alex Deucherc05ce082009-02-24 16:22:29 -0500276void radeon_enable_bm(struct drm_radeon_private *dev_priv)
Dave Airliedd8d7cb2009-02-20 13:28:59 +1000277{
278 u32 tmp;
279 /* Turn on bus mastering */
280 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
281 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
282 /* rs600/rs690/rs740 */
283 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
284 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
285 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) ||
286 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
287 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
288 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
289 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
290 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
291 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
292 } /* PCIE cards appears to not need this */
293}
294
Dave Airlie84b1fd12007-07-11 15:53:27 +1000295static int RADEON_READ_PLL(struct drm_device * dev, int addr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700296{
297 drm_radeon_private_t *dev_priv = dev->dev_private;
298
299 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
300 return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
301}
302
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000303static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700304{
Dave Airlieea98a922005-09-11 20:28:11 +1000305 RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
306 return RADEON_READ(RADEON_PCIE_DATA);
307}
308
Linus Torvalds1da177e2005-04-16 15:20:36 -0700309#if RADEON_FIFO_DEBUG
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000310static void radeon_status(drm_radeon_private_t * dev_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700311{
Harvey Harrisonbf9d8922008-04-30 00:55:10 -0700312 printk("%s:\n", __func__);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000313 printk("RBBM_STATUS = 0x%08x\n",
314 (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
315 printk("CP_RB_RTPR = 0x%08x\n",
316 (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
317 printk("CP_RB_WTPR = 0x%08x\n",
318 (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
319 printk("AIC_CNTL = 0x%08x\n",
320 (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
321 printk("AIC_STAT = 0x%08x\n",
322 (unsigned int)RADEON_READ(RADEON_AIC_STAT));
323 printk("AIC_PT_BASE = 0x%08x\n",
324 (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
325 printk("TLB_ADDR = 0x%08x\n",
326 (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
327 printk("TLB_DATA = 0x%08x\n",
328 (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700329}
330#endif
331
Linus Torvalds1da177e2005-04-16 15:20:36 -0700332/* ================================================================
333 * Engine, FIFO control
334 */
335
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000336static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700337{
338 u32 tmp;
339 int i;
340
341 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
342
Alex Deucher259434a2008-05-28 11:51:12 +1000343 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
344 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
345 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
346 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700347
Alex Deucher259434a2008-05-28 11:51:12 +1000348 for (i = 0; i < dev_priv->usec_timeout; i++) {
349 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
350 & RADEON_RB3D_DC_BUSY)) {
351 return 0;
352 }
353 DRM_UDELAY(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700354 }
Alex Deucher259434a2008-05-28 11:51:12 +1000355 } else {
Jerome Glisse54f961a2008-08-13 09:46:31 +1000356 /* don't flush or purge cache here or lockup */
357 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700358 }
359
360#if RADEON_FIFO_DEBUG
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000361 DRM_ERROR("failed!\n");
362 radeon_status(dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700363#endif
Eric Anholt20caafa2007-08-25 19:22:43 +1000364 return -EBUSY;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700365}
366
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000367static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700368{
369 int i;
370
371 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
372
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000373 for (i = 0; i < dev_priv->usec_timeout; i++) {
374 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
375 & RADEON_RBBM_FIFOCNT_MASK);
376 if (slots >= entries)
377 return 0;
378 DRM_UDELAY(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700379 }
Dave Airlie6c7be292008-09-01 08:51:52 +1000380 DRM_DEBUG("wait for fifo failed status : 0x%08X 0x%08X\n",
Jerome Glisse54f961a2008-08-13 09:46:31 +1000381 RADEON_READ(RADEON_RBBM_STATUS),
382 RADEON_READ(R300_VAP_CNTL_STATUS));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700383
384#if RADEON_FIFO_DEBUG
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000385 DRM_ERROR("failed!\n");
386 radeon_status(dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700387#endif
Eric Anholt20caafa2007-08-25 19:22:43 +1000388 return -EBUSY;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700389}
390
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000391static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700392{
393 int i, ret;
394
395 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
396
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000397 ret = radeon_do_wait_for_fifo(dev_priv, 64);
398 if (ret)
399 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700400
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000401 for (i = 0; i < dev_priv->usec_timeout; i++) {
402 if (!(RADEON_READ(RADEON_RBBM_STATUS)
403 & RADEON_RBBM_ACTIVE)) {
404 radeon_do_pixcache_flush(dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700405 return 0;
406 }
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000407 DRM_UDELAY(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700408 }
Dave Airlie6c7be292008-09-01 08:51:52 +1000409 DRM_DEBUG("wait idle failed status : 0x%08X 0x%08X\n",
Jerome Glisse54f961a2008-08-13 09:46:31 +1000410 RADEON_READ(RADEON_RBBM_STATUS),
411 RADEON_READ(R300_VAP_CNTL_STATUS));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700412
413#if RADEON_FIFO_DEBUG
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000414 DRM_ERROR("failed!\n");
415 radeon_status(dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700416#endif
Eric Anholt20caafa2007-08-25 19:22:43 +1000417 return -EBUSY;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700418}
419
Alex Deucher5b92c402008-05-28 11:57:40 +1000420static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
421{
422 uint32_t gb_tile_config, gb_pipe_sel = 0;
423
424 /* RS4xx/RS6xx/R4xx/R5xx */
425 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
426 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
427 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
428 } else {
429 /* R3xx */
430 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
431 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
432 dev_priv->num_gb_pipes = 2;
433 } else {
434 /* R3Vxx */
435 dev_priv->num_gb_pipes = 1;
436 }
437 }
438 DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
439
440 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
441
442 switch (dev_priv->num_gb_pipes) {
443 case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
444 case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
445 case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
446 default:
447 case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
448 }
449
450 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
451 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
Maciej Cencoraaf7ae352009-03-24 01:48:50 +0100452 RADEON_WRITE(R300_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
Alex Deucher5b92c402008-05-28 11:57:40 +1000453 }
454 RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
455 radeon_do_wait_for_idle(dev_priv);
456 RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
457 RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
458 R300_DC_AUTOFLUSH_ENABLE |
459 R300_DC_DC_DISABLE_IGNORE_PE));
460
461
462}
463
Linus Torvalds1da177e2005-04-16 15:20:36 -0700464/* ================================================================
465 * CP control, initialization
466 */
467
468/* Load the microcode for the CP */
Ben Hutchings70967ab2009-08-29 14:53:51 +0100469static int radeon_cp_init_microcode(drm_radeon_private_t *dev_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700470{
Ben Hutchings70967ab2009-08-29 14:53:51 +0100471 struct platform_device *pdev;
472 const char *fw_name = NULL;
473 int err;
474
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000475 DRM_DEBUG("\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700476
Ben Hutchings70967ab2009-08-29 14:53:51 +0100477 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
478 err = IS_ERR(pdev);
479 if (err) {
480 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
481 return -EINVAL;
482 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700483
Alex Deucher9f184092008-05-28 11:21:25 +1000484 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
485 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
486 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
487 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
488 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
489 DRM_INFO("Loading R100 Microcode\n");
Ben Hutchings70967ab2009-08-29 14:53:51 +0100490 fw_name = FIRMWARE_R100;
Alex Deucher9f184092008-05-28 11:21:25 +1000491 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
492 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
493 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
494 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700495 DRM_INFO("Loading R200 Microcode\n");
Ben Hutchings70967ab2009-08-29 14:53:51 +0100496 fw_name = FIRMWARE_R200;
Alex Deucher9f184092008-05-28 11:21:25 +1000497 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
498 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
499 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
500 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
Alex Deucherb2ceddf2008-10-17 09:19:33 +1000501 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
Alex Deucher45e51902008-05-28 13:28:59 +1000502 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700503 DRM_INFO("Loading R300 Microcode\n");
Ben Hutchings70967ab2009-08-29 14:53:51 +0100504 fw_name = FIRMWARE_R300;
Alex Deucher9f184092008-05-28 11:21:25 +1000505 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
Alex Deucheredc6f382008-10-17 09:21:45 +1000506 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) ||
Alex Deucher9f184092008-05-28 11:21:25 +1000507 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
508 DRM_INFO("Loading R400 Microcode\n");
Ben Hutchings70967ab2009-08-29 14:53:51 +0100509 fw_name = FIRMWARE_R420;
Alex Deucherf0738e92008-10-16 17:12:02 +1000510 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
511 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
512 DRM_INFO("Loading RS690/RS740 Microcode\n");
Ben Hutchings70967ab2009-08-29 14:53:51 +0100513 fw_name = FIRMWARE_RS690;
Alex Deucherc1556f72009-02-25 16:57:49 -0500514 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
515 DRM_INFO("Loading RS600 Microcode\n");
Ben Hutchings70967ab2009-08-29 14:53:51 +0100516 fw_name = FIRMWARE_RS600;
Alex Deucher9f184092008-05-28 11:21:25 +1000517 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
518 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
519 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
520 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
521 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
522 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
523 DRM_INFO("Loading R500 Microcode\n");
Ben Hutchings70967ab2009-08-29 14:53:51 +0100524 fw_name = FIRMWARE_R520;
525 }
526
527 err = request_firmware(&dev_priv->me_fw, fw_name, &pdev->dev);
528 platform_device_unregister(pdev);
529 if (err) {
530 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
531 fw_name);
532 } else if (dev_priv->me_fw->size % 8) {
533 printk(KERN_ERR
534 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
535 dev_priv->me_fw->size, fw_name);
536 err = -EINVAL;
537 release_firmware(dev_priv->me_fw);
538 dev_priv->me_fw = NULL;
539 }
540 return err;
541}
542
543static void radeon_cp_load_microcode(drm_radeon_private_t *dev_priv)
544{
545 const __be32 *fw_data;
546 int i, size;
547
548 radeon_do_wait_for_idle(dev_priv);
549
550 if (dev_priv->me_fw) {
551 size = dev_priv->me_fw->size / 4;
552 fw_data = (const __be32 *)&dev_priv->me_fw->data[0];
553 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
554 for (i = 0; i < size; i += 2) {
Alex Deucher9f184092008-05-28 11:21:25 +1000555 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
Ben Hutchings70967ab2009-08-29 14:53:51 +0100556 be32_to_cpup(&fw_data[i]));
Alex Deucher9f184092008-05-28 11:21:25 +1000557 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
Ben Hutchings70967ab2009-08-29 14:53:51 +0100558 be32_to_cpup(&fw_data[i + 1]));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700559 }
560 }
561}
562
563/* Flush any pending commands to the CP. This should only be used just
564 * prior to a wait for idle, as it informs the engine that the command
565 * stream is ending.
566 */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000567static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700568{
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000569 DRM_DEBUG("\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700570#if 0
571 u32 tmp;
572
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000573 tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
574 RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700575#endif
576}
577
578/* Wait for the CP to go idle.
579 */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000580int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700581{
582 RING_LOCALS;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000583 DRM_DEBUG("\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700584
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000585 BEGIN_RING(6);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700586
587 RADEON_PURGE_CACHE();
588 RADEON_PURGE_ZCACHE();
589 RADEON_WAIT_UNTIL_IDLE();
590
591 ADVANCE_RING();
592 COMMIT_RING();
593
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000594 return radeon_do_wait_for_idle(dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700595}
596
597/* Start the Command Processor.
598 */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000599static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700600{
601 RING_LOCALS;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000602 DRM_DEBUG("\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700603
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000604 radeon_do_wait_for_idle(dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700605
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000606 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700607
608 dev_priv->cp_running = 1;
609
Jerome Glisse54f961a2008-08-13 09:46:31 +1000610 BEGIN_RING(8);
611 /* isync can only be written through cp on r5xx write it here */
612 OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
613 OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
614 RADEON_ISYNC_ANY3D_IDLE2D |
615 RADEON_ISYNC_WAIT_IDLEGUI |
616 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700617 RADEON_PURGE_CACHE();
618 RADEON_PURGE_ZCACHE();
619 RADEON_WAIT_UNTIL_IDLE();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700620 ADVANCE_RING();
621 COMMIT_RING();
Jerome Glisse54f961a2008-08-13 09:46:31 +1000622
623 dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700624}
625
626/* Reset the Command Processor. This will not flush any pending
627 * commands, so you must wait for the CP command stream to complete
628 * before calling this routine.
629 */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000630static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700631{
632 u32 cur_read_ptr;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000633 DRM_DEBUG("\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700634
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000635 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
636 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
637 SET_RING_HEAD(dev_priv, cur_read_ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700638 dev_priv->ring.tail = cur_read_ptr;
639}
640
641/* Stop the Command Processor. This will not flush any pending
642 * commands, so you must flush the command stream and wait for the CP
643 * to go idle before calling this routine.
644 */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000645static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700646{
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000647 DRM_DEBUG("\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700648
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000649 RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700650
651 dev_priv->cp_running = 0;
652}
653
654/* Reset the engine. This will stop the CP if it is running.
655 */
Dave Airlie84b1fd12007-07-11 15:53:27 +1000656static int radeon_do_engine_reset(struct drm_device * dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700657{
658 drm_radeon_private_t *dev_priv = dev->dev_private;
Alex Deucherd396db32008-05-28 11:54:06 +1000659 u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000660 DRM_DEBUG("\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700661
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000662 radeon_do_pixcache_flush(dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700663
Alex Deucherd396db32008-05-28 11:54:06 +1000664 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
665 /* may need something similar for newer chips */
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000666 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
667 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700668
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000669 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
670 RADEON_FORCEON_MCLKA |
671 RADEON_FORCEON_MCLKB |
672 RADEON_FORCEON_YCLKA |
673 RADEON_FORCEON_YCLKB |
674 RADEON_FORCEON_MC |
675 RADEON_FORCEON_AIC));
Alex Deucherd396db32008-05-28 11:54:06 +1000676 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700677
Alex Deucherd396db32008-05-28 11:54:06 +1000678 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700679
Alex Deucherd396db32008-05-28 11:54:06 +1000680 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
681 RADEON_SOFT_RESET_CP |
682 RADEON_SOFT_RESET_HI |
683 RADEON_SOFT_RESET_SE |
684 RADEON_SOFT_RESET_RE |
685 RADEON_SOFT_RESET_PP |
686 RADEON_SOFT_RESET_E2 |
687 RADEON_SOFT_RESET_RB));
688 RADEON_READ(RADEON_RBBM_SOFT_RESET);
689 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
690 ~(RADEON_SOFT_RESET_CP |
691 RADEON_SOFT_RESET_HI |
692 RADEON_SOFT_RESET_SE |
693 RADEON_SOFT_RESET_RE |
694 RADEON_SOFT_RESET_PP |
695 RADEON_SOFT_RESET_E2 |
696 RADEON_SOFT_RESET_RB)));
697 RADEON_READ(RADEON_RBBM_SOFT_RESET);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700698
Alex Deucherd396db32008-05-28 11:54:06 +1000699 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000700 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
701 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
702 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
703 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700704
Alex Deucher5b92c402008-05-28 11:57:40 +1000705 /* setup the raster pipes */
706 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
707 radeon_init_pipes(dev_priv);
708
Linus Torvalds1da177e2005-04-16 15:20:36 -0700709 /* Reset the CP ring */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000710 radeon_do_cp_reset(dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700711
712 /* The CP is no longer running after an engine reset */
713 dev_priv->cp_running = 0;
714
715 /* Reset any pending vertex, indirect buffers */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000716 radeon_freelist_reset(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700717
718 return 0;
719}
720
Dave Airlie84b1fd12007-07-11 15:53:27 +1000721static void radeon_cp_init_ring_buffer(struct drm_device * dev,
etienne3d161182009-02-20 09:44:45 +1000722 drm_radeon_private_t *dev_priv,
723 struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700724{
etienne3d161182009-02-20 09:44:45 +1000725 struct drm_radeon_master_private *master_priv;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700726 u32 ring_start, cur_read_ptr;
Dave Airliebc5f4522007-11-05 12:50:58 +1000727
Dave Airlied5ea7022006-03-19 19:37:55 +1100728 /* Initialize the memory controller. With new memory map, the fb location
729 * is not changed, it should have been properly initialized already. Part
730 * of the problem is that the code below is bogus, assuming the GART is
731 * always appended to the fb which is not necessarily the case
732 */
733 if (!dev_priv->new_memmap)
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000734 radeon_write_fb_location(dev_priv,
Dave Airlied5ea7022006-03-19 19:37:55 +1100735 ((dev_priv->gart_vm_start - 1) & 0xffff0000)
736 | (dev_priv->fb_location >> 16));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700737
738#if __OS_HAS_AGP
Dave Airlie54a56ac2006-09-22 04:25:09 +1000739 if (dev_priv->flags & RADEON_IS_AGP) {
Dave Airlie70b13d52008-06-19 11:40:44 +1000740 radeon_write_agp_base(dev_priv, dev->agp->base);
741
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000742 radeon_write_agp_location(dev_priv,
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000743 (((dev_priv->gart_vm_start - 1 +
744 dev_priv->gart_size) & 0xffff0000) |
745 (dev_priv->gart_vm_start >> 16)));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700746
747 ring_start = (dev_priv->cp_ring->offset
748 - dev->agp->base
749 + dev_priv->gart_vm_start);
Ivan Kokshayskyb0917bd2005-10-26 11:05:25 +0100750 } else
Linus Torvalds1da177e2005-04-16 15:20:36 -0700751#endif
752 ring_start = (dev_priv->cp_ring->offset
Ivan Kokshayskyb0917bd2005-10-26 11:05:25 +0100753 - (unsigned long)dev->sg->virtual
Linus Torvalds1da177e2005-04-16 15:20:36 -0700754 + dev_priv->gart_vm_start);
755
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000756 RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700757
758 /* Set the write pointer delay */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000759 RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700760
761 /* Initialize the ring buffer's read and write pointers */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000762 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
763 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
764 SET_RING_HEAD(dev_priv, cur_read_ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700765 dev_priv->ring.tail = cur_read_ptr;
766
767#if __OS_HAS_AGP
Dave Airlie54a56ac2006-09-22 04:25:09 +1000768 if (dev_priv->flags & RADEON_IS_AGP) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000769 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
770 dev_priv->ring_rptr->offset
771 - dev->agp->base + dev_priv->gart_vm_start);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700772 } else
773#endif
774 {
David Millere8a89432009-02-12 02:15:44 -0800775 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
776 dev_priv->ring_rptr->offset
777 - ((unsigned long) dev->sg->virtual)
778 + dev_priv->gart_vm_start);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700779 }
780
Dave Airlied5ea7022006-03-19 19:37:55 +1100781 /* Set ring buffer size */
782#ifdef __BIG_ENDIAN
783 RADEON_WRITE(RADEON_CP_RB_CNTL,
Roland Scheidegger576cc452008-02-07 14:59:24 +1000784 RADEON_BUF_SWAP_32BIT |
785 (dev_priv->ring.fetch_size_l2ow << 18) |
786 (dev_priv->ring.rptr_update_l2qw << 8) |
787 dev_priv->ring.size_l2qw);
Dave Airlied5ea7022006-03-19 19:37:55 +1100788#else
Roland Scheidegger576cc452008-02-07 14:59:24 +1000789 RADEON_WRITE(RADEON_CP_RB_CNTL,
790 (dev_priv->ring.fetch_size_l2ow << 18) |
791 (dev_priv->ring.rptr_update_l2qw << 8) |
792 dev_priv->ring.size_l2qw);
Dave Airlied5ea7022006-03-19 19:37:55 +1100793#endif
794
Dave Airlied5ea7022006-03-19 19:37:55 +1100795
Linus Torvalds1da177e2005-04-16 15:20:36 -0700796 /* Initialize the scratch register pointer. This will cause
797 * the scratch register values to be written out to memory
798 * whenever they are updated.
799 *
800 * We simply put this behind the ring read pointer, this works
801 * with PCI GART as well as (whatever kind of) AGP GART
802 */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000803 RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
804 + RADEON_SCRATCH_REG_OFFSET);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700805
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000806 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700807
Dave Airliedd8d7cb2009-02-20 13:28:59 +1000808 radeon_enable_bm(dev_priv);
Dave Airlied5ea7022006-03-19 19:37:55 +1100809
David Millerb07fa022009-02-12 02:15:37 -0800810 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(0), 0);
Dave Airlie7c1c2872008-11-28 14:22:24 +1000811 RADEON_WRITE(RADEON_LAST_FRAME_REG, 0);
Dave Airlied5ea7022006-03-19 19:37:55 +1100812
David Millerb07fa022009-02-12 02:15:37 -0800813 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
Dave Airlie7c1c2872008-11-28 14:22:24 +1000814 RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);
Dave Airlied5ea7022006-03-19 19:37:55 +1100815
David Millerb07fa022009-02-12 02:15:37 -0800816 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(2), 0);
Dave Airlie7c1c2872008-11-28 14:22:24 +1000817 RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
Dave Airlied5ea7022006-03-19 19:37:55 +1100818
etienne3d161182009-02-20 09:44:45 +1000819 /* reset sarea copies of these */
820 master_priv = file_priv->master->driver_priv;
821 if (master_priv->sarea_priv) {
822 master_priv->sarea_priv->last_frame = 0;
823 master_priv->sarea_priv->last_dispatch = 0;
824 master_priv->sarea_priv->last_clear = 0;
825 }
826
Dave Airlied5ea7022006-03-19 19:37:55 +1100827 radeon_do_wait_for_idle(dev_priv);
828
829 /* Sync everything up */
830 RADEON_WRITE(RADEON_ISYNC_CNTL,
831 (RADEON_ISYNC_ANY2D_IDLE3D |
832 RADEON_ISYNC_ANY3D_IDLE2D |
833 RADEON_ISYNC_WAIT_IDLEGUI |
834 RADEON_ISYNC_CPSCRATCH_IDLEGUI));
835
836}
837
838static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
839{
840 u32 tmp;
841
Dave Airlie6b79d522008-09-02 10:10:16 +1000842 /* Start with assuming that writeback doesn't work */
843 dev_priv->writeback_works = 0;
844
Dave Airlied5ea7022006-03-19 19:37:55 +1100845 /* Writeback doesn't seem to work everywhere, test it here and possibly
846 * enable it if it appears to work
847 */
David Millerb07fa022009-02-12 02:15:37 -0800848 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
849
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000850 RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700851
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000852 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
David Millerb07fa022009-02-12 02:15:37 -0800853 u32 val;
854
855 val = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
856 if (val == 0xdeadbeef)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700857 break;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000858 DRM_UDELAY(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700859 }
860
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000861 if (tmp < dev_priv->usec_timeout) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700862 dev_priv->writeback_works = 1;
Dave Airlied5ea7022006-03-19 19:37:55 +1100863 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700864 } else {
865 dev_priv->writeback_works = 0;
Dave Airlied5ea7022006-03-19 19:37:55 +1100866 DRM_INFO("writeback test failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700867 }
Dave Airlie689b9d72005-09-30 17:09:07 +1000868 if (radeon_no_wb == 1) {
869 dev_priv->writeback_works = 0;
Dave Airlied5ea7022006-03-19 19:37:55 +1100870 DRM_INFO("writeback forced off\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700871 }
Michel Dänzerae1b1a482006-08-07 20:37:46 +1000872
873 if (!dev_priv->writeback_works) {
874 /* Disable writeback to avoid unnecessary bus master transfer */
875 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
876 RADEON_RB_NO_UPDATE);
877 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
878 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700879}
880
Dave Airlief2b04cd2007-05-08 15:19:23 +1000881/* Enable or disable IGP GART on the chip */
882static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
883{
Maciej Cencora60f92682008-02-19 21:32:45 +1000884 u32 temp;
885
886 if (on) {
Alex Deucher45e51902008-05-28 13:28:59 +1000887 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
Maciej Cencora60f92682008-02-19 21:32:45 +1000888 dev_priv->gart_vm_start,
889 (long)dev_priv->gart_info.bus_addr,
890 dev_priv->gart_size);
891
Alex Deucher45e51902008-05-28 13:28:59 +1000892 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
Alex Deucherf0738e92008-10-16 17:12:02 +1000893 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
894 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
Alex Deucher45e51902008-05-28 13:28:59 +1000895 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
896 RS690_BLOCK_GFX_D3_EN));
897 else
898 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
Maciej Cencora60f92682008-02-19 21:32:45 +1000899
Alex Deucher45e51902008-05-28 13:28:59 +1000900 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
901 RS480_VA_SIZE_32MB));
Maciej Cencora60f92682008-02-19 21:32:45 +1000902
Alex Deucher45e51902008-05-28 13:28:59 +1000903 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
904 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
905 RS480_TLB_ENABLE |
906 RS480_GTW_LAC_EN |
907 RS480_1LEVEL_GART));
Maciej Cencora60f92682008-02-19 21:32:45 +1000908
Dave Airliefa0d71b2008-05-28 11:27:01 +1000909 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
910 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
Alex Deucher45e51902008-05-28 13:28:59 +1000911 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
Maciej Cencora60f92682008-02-19 21:32:45 +1000912
Alex Deucher45e51902008-05-28 13:28:59 +1000913 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
914 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
915 RS480_REQ_TYPE_SNOOP_DIS));
Maciej Cencora60f92682008-02-19 21:32:45 +1000916
Alex Deucher5cfb6952008-06-19 12:38:29 +1000917 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
Dave Airlie3722bfc2008-05-28 11:28:27 +1000918
Maciej Cencora60f92682008-02-19 21:32:45 +1000919 dev_priv->gart_size = 32*1024*1024;
920 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
921 0xffff0000) | (dev_priv->gart_vm_start >> 16));
922
Alex Deucher45e51902008-05-28 13:28:59 +1000923 radeon_write_agp_location(dev_priv, temp);
Maciej Cencora60f92682008-02-19 21:32:45 +1000924
Alex Deucher45e51902008-05-28 13:28:59 +1000925 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
926 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
927 RS480_VA_SIZE_32MB));
Maciej Cencora60f92682008-02-19 21:32:45 +1000928
929 do {
Alex Deucher45e51902008-05-28 13:28:59 +1000930 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
931 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
Maciej Cencora60f92682008-02-19 21:32:45 +1000932 break;
933 DRM_UDELAY(1);
934 } while (1);
935
Alex Deucher45e51902008-05-28 13:28:59 +1000936 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
937 RS480_GART_CACHE_INVALIDATE);
Alex Deucher27359772008-05-28 12:54:16 +1000938
Maciej Cencora60f92682008-02-19 21:32:45 +1000939 do {
Alex Deucher45e51902008-05-28 13:28:59 +1000940 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
941 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
Maciej Cencora60f92682008-02-19 21:32:45 +1000942 break;
943 DRM_UDELAY(1);
944 } while (1);
945
Alex Deucher45e51902008-05-28 13:28:59 +1000946 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
Maciej Cencora60f92682008-02-19 21:32:45 +1000947 } else {
Alex Deucher45e51902008-05-28 13:28:59 +1000948 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
Maciej Cencora60f92682008-02-19 21:32:45 +1000949 }
950}
951
Alex Deucherc1556f72009-02-25 16:57:49 -0500952/* Enable or disable IGP GART on the chip */
953static void rs600_set_igpgart(drm_radeon_private_t *dev_priv, int on)
954{
955 u32 temp;
956 int i;
957
958 if (on) {
959 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
960 dev_priv->gart_vm_start,
961 (long)dev_priv->gart_info.bus_addr,
962 dev_priv->gart_size);
963
964 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (RS600_EFFECTIVE_L2_CACHE_SIZE(6) |
965 RS600_EFFECTIVE_L2_QUEUE_SIZE(6)));
966
967 for (i = 0; i < 19; i++)
968 IGP_WRITE_MCIND(RS600_MC_PT0_CLIENT0_CNTL + i,
969 (RS600_ENABLE_TRANSLATION_MODE_OVERRIDE |
970 RS600_SYSTEM_ACCESS_MODE_IN_SYS |
971 RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH |
972 RS600_EFFECTIVE_L1_CACHE_SIZE(3) |
973 RS600_ENABLE_FRAGMENT_PROCESSING |
974 RS600_EFFECTIVE_L1_QUEUE_SIZE(3)));
975
976 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL, (RS600_ENABLE_PAGE_TABLE |
977 RS600_PAGE_TABLE_TYPE_FLAT));
978
979 /* disable all other contexts */
980 for (i = 1; i < 8; i++)
981 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL + i, 0);
982
983 /* setup the page table aperture */
984 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
985 dev_priv->gart_info.bus_addr);
986 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR,
987 dev_priv->gart_vm_start);
988 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR,
989 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
990 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
991
992 /* setup the system aperture */
993 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR,
994 dev_priv->gart_vm_start);
995 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR,
996 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
997
998 /* enable page tables */
999 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1000 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (temp | RS600_ENABLE_PT));
1001
1002 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
1003 IGP_WRITE_MCIND(RS600_MC_CNTL1, (temp | RS600_ENABLE_PAGE_TABLES));
1004
1005 /* invalidate the cache */
1006 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1007
1008 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
1009 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
1010 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1011
1012 temp |= RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE;
1013 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
1014 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1015
1016 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
1017 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
1018 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1019
1020 } else {
1021 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, 0);
1022 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
1023 temp &= ~RS600_ENABLE_PAGE_TABLES;
1024 IGP_WRITE_MCIND(RS600_MC_CNTL1, temp);
1025 }
1026}
1027
Dave Airlieea98a922005-09-11 20:28:11 +10001028static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001029{
Dave Airlieea98a922005-09-11 20:28:11 +10001030 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
1031 if (on) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001032
Dave Airlieea98a922005-09-11 20:28:11 +10001033 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001034 dev_priv->gart_vm_start,
1035 (long)dev_priv->gart_info.bus_addr,
Dave Airlieea98a922005-09-11 20:28:11 +10001036 dev_priv->gart_size);
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001037 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
1038 dev_priv->gart_vm_start);
1039 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
1040 dev_priv->gart_info.bus_addr);
1041 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
1042 dev_priv->gart_vm_start);
1043 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
1044 dev_priv->gart_vm_start +
1045 dev_priv->gart_size - 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001046
Dave Airlie3d5e2c12008-02-07 15:01:05 +10001047 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001048
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001049 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1050 RADEON_PCIE_TX_GART_EN);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001051 } else {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001052 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1053 tmp & ~RADEON_PCIE_TX_GART_EN);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001054 }
1055}
1056
Linus Torvalds1da177e2005-04-16 15:20:36 -07001057/* Enable or disable PCI GART on the chip */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001058static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001059{
Dave Airlied985c102006-01-02 21:32:48 +11001060 u32 tmp;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001061
Alex Deucher45e51902008-05-28 13:28:59 +10001062 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
Alex Deucherf0738e92008-10-16 17:12:02 +10001063 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) ||
Alex Deucher45e51902008-05-28 13:28:59 +10001064 (dev_priv->flags & RADEON_IS_IGPGART)) {
Dave Airlief2b04cd2007-05-08 15:19:23 +10001065 radeon_set_igpgart(dev_priv, on);
1066 return;
1067 }
1068
Alex Deucherc1556f72009-02-25 16:57:49 -05001069 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
1070 rs600_set_igpgart(dev_priv, on);
1071 return;
1072 }
1073
Dave Airlie54a56ac2006-09-22 04:25:09 +10001074 if (dev_priv->flags & RADEON_IS_PCIE) {
Dave Airlieea98a922005-09-11 20:28:11 +10001075 radeon_set_pciegart(dev_priv, on);
1076 return;
1077 }
1078
Dave Airliebc5f4522007-11-05 12:50:58 +10001079 tmp = RADEON_READ(RADEON_AIC_CNTL);
Dave Airlied985c102006-01-02 21:32:48 +11001080
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001081 if (on) {
1082 RADEON_WRITE(RADEON_AIC_CNTL,
1083 tmp | RADEON_PCIGART_TRANSLATE_EN);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001084
1085 /* set PCI GART page-table base address
1086 */
Dave Airlieea98a922005-09-11 20:28:11 +10001087 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001088
1089 /* set address range for PCI address translate
1090 */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001091 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
1092 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
1093 + dev_priv->gart_size - 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001094
1095 /* Turn off AGP aperture -- is this required for PCI GART?
1096 */
Dave Airlie3d5e2c12008-02-07 15:01:05 +10001097 radeon_write_agp_location(dev_priv, 0xffffffc0);
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001098 RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001099 } else {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001100 RADEON_WRITE(RADEON_AIC_CNTL,
1101 tmp & ~RADEON_PCIGART_TRANSLATE_EN);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001102 }
1103}
1104
David Miller6abf6bb2009-02-14 01:51:07 -08001105static int radeon_setup_pcigart_surface(drm_radeon_private_t *dev_priv)
1106{
1107 struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
1108 struct radeon_virt_surface *vp;
1109 int i;
1110
1111 for (i = 0; i < RADEON_MAX_SURFACES * 2; i++) {
1112 if (!dev_priv->virt_surfaces[i].file_priv ||
1113 dev_priv->virt_surfaces[i].file_priv == PCIGART_FILE_PRIV)
1114 break;
1115 }
1116 if (i >= 2 * RADEON_MAX_SURFACES)
1117 return -ENOMEM;
1118 vp = &dev_priv->virt_surfaces[i];
1119
1120 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1121 struct radeon_surface *sp = &dev_priv->surfaces[i];
1122 if (sp->refcount)
1123 continue;
1124
1125 vp->surface_index = i;
1126 vp->lower = gart_info->bus_addr;
1127 vp->upper = vp->lower + gart_info->table_size;
1128 vp->flags = 0;
1129 vp->file_priv = PCIGART_FILE_PRIV;
1130
1131 sp->refcount = 1;
1132 sp->lower = vp->lower;
1133 sp->upper = vp->upper;
1134 sp->flags = 0;
1135
1136 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, sp->flags);
1137 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * i, sp->lower);
1138 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * i, sp->upper);
1139 return 0;
1140 }
1141
1142 return -ENOMEM;
1143}
1144
Dave Airlie7c1c2872008-11-28 14:22:24 +10001145static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
1146 struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001147{
Dave Airlied985c102006-01-02 21:32:48 +11001148 drm_radeon_private_t *dev_priv = dev->dev_private;
Dave Airlie7c1c2872008-11-28 14:22:24 +10001149 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
Dave Airlied985c102006-01-02 21:32:48 +11001150
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001151 DRM_DEBUG("\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001152
Dave Airlief3dd5c32006-03-25 18:09:46 +11001153 /* if we require new memory map but we don't have it fail */
Dave Airlie54a56ac2006-09-22 04:25:09 +10001154 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
Dave Airlieb15ec362006-08-19 17:43:52 +10001155 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
Dave Airlief3dd5c32006-03-25 18:09:46 +11001156 radeon_do_cleanup_cp(dev);
Eric Anholt20caafa2007-08-25 19:22:43 +10001157 return -EINVAL;
Dave Airlief3dd5c32006-03-25 18:09:46 +11001158 }
1159
Dave Airlie54a56ac2006-09-22 04:25:09 +10001160 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
Dave Airlied985c102006-01-02 21:32:48 +11001161 DRM_DEBUG("Forcing AGP card to PCI mode\n");
Dave Airlie54a56ac2006-09-22 04:25:09 +10001162 dev_priv->flags &= ~RADEON_IS_AGP;
1163 } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
Dave Airlieb15ec362006-08-19 17:43:52 +10001164 && !init->is_pci) {
1165 DRM_DEBUG("Restoring AGP flag\n");
Dave Airlie54a56ac2006-09-22 04:25:09 +10001166 dev_priv->flags |= RADEON_IS_AGP;
Dave Airlied985c102006-01-02 21:32:48 +11001167 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001168
Dave Airlie54a56ac2006-09-22 04:25:09 +10001169 if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001170 DRM_ERROR("PCI GART memory not allocated!\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001171 radeon_do_cleanup_cp(dev);
Eric Anholt20caafa2007-08-25 19:22:43 +10001172 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001173 }
1174
1175 dev_priv->usec_timeout = init->usec_timeout;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001176 if (dev_priv->usec_timeout < 1 ||
1177 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1178 DRM_DEBUG("TIMEOUT problem!\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001179 radeon_do_cleanup_cp(dev);
Eric Anholt20caafa2007-08-25 19:22:43 +10001180 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001181 }
1182
Dave Airlieddbee332007-07-11 12:16:01 +10001183 /* Enable vblank on CRTC1 for older X servers
1184 */
1185 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1186
Dave Airlied985c102006-01-02 21:32:48 +11001187 switch(init->func) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001188 case RADEON_INIT_R200_CP:
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001189 dev_priv->microcode_version = UCODE_R200;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001190 break;
1191 case RADEON_INIT_R300_CP:
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001192 dev_priv->microcode_version = UCODE_R300;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001193 break;
1194 default:
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001195 dev_priv->microcode_version = UCODE_R100;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001196 }
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001197
Linus Torvalds1da177e2005-04-16 15:20:36 -07001198 dev_priv->do_boxes = 0;
1199 dev_priv->cp_mode = init->cp_mode;
1200
1201 /* We don't support anything other than bus-mastering ring mode,
1202 * but the ring can be in either AGP or PCI space for the ring
1203 * read pointer.
1204 */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001205 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1206 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1207 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001208 radeon_do_cleanup_cp(dev);
Eric Anholt20caafa2007-08-25 19:22:43 +10001209 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001210 }
1211
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001212 switch (init->fb_bpp) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001213 case 16:
1214 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1215 break;
1216 case 32:
1217 default:
1218 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1219 break;
1220 }
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001221 dev_priv->front_offset = init->front_offset;
1222 dev_priv->front_pitch = init->front_pitch;
1223 dev_priv->back_offset = init->back_offset;
1224 dev_priv->back_pitch = init->back_pitch;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001225
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001226 switch (init->depth_bpp) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001227 case 16:
1228 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1229 break;
1230 case 32:
1231 default:
1232 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1233 break;
1234 }
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001235 dev_priv->depth_offset = init->depth_offset;
1236 dev_priv->depth_pitch = init->depth_pitch;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001237
1238 /* Hardware state for depth clears. Remove this if/when we no
1239 * longer clear the depth buffer with a 3D rectangle. Hard-code
1240 * all values to prevent unwanted 3D state from slipping through
1241 * and screwing with the clear operation.
1242 */
1243 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1244 (dev_priv->color_fmt << 10) |
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001245 (dev_priv->microcode_version ==
1246 UCODE_R100 ? RADEON_ZBLOCK16 : 0));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001247
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001248 dev_priv->depth_clear.rb3d_zstencilcntl =
1249 (dev_priv->depth_fmt |
1250 RADEON_Z_TEST_ALWAYS |
1251 RADEON_STENCIL_TEST_ALWAYS |
1252 RADEON_STENCIL_S_FAIL_REPLACE |
1253 RADEON_STENCIL_ZPASS_REPLACE |
1254 RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001255
1256 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1257 RADEON_BFACE_SOLID |
1258 RADEON_FFACE_SOLID |
1259 RADEON_FLAT_SHADE_VTX_LAST |
1260 RADEON_DIFFUSE_SHADE_FLAT |
1261 RADEON_ALPHA_SHADE_FLAT |
1262 RADEON_SPECULAR_SHADE_FLAT |
1263 RADEON_FOG_SHADE_FLAT |
1264 RADEON_VTX_PIX_CENTER_OGL |
1265 RADEON_ROUND_MODE_TRUNC |
1266 RADEON_ROUND_PREC_8TH_PIX);
1267
Linus Torvalds1da177e2005-04-16 15:20:36 -07001268
Linus Torvalds1da177e2005-04-16 15:20:36 -07001269 dev_priv->ring_offset = init->ring_offset;
1270 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1271 dev_priv->buffers_offset = init->buffers_offset;
1272 dev_priv->gart_textures_offset = init->gart_textures_offset;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001273
Dave Airlie7c1c2872008-11-28 14:22:24 +10001274 master_priv->sarea = drm_getsarea(dev);
1275 if (!master_priv->sarea) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001276 DRM_ERROR("could not find sarea!\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001277 radeon_do_cleanup_cp(dev);
Eric Anholt20caafa2007-08-25 19:22:43 +10001278 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001279 }
1280
Linus Torvalds1da177e2005-04-16 15:20:36 -07001281 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001282 if (!dev_priv->cp_ring) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001283 DRM_ERROR("could not find cp ring region!\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001284 radeon_do_cleanup_cp(dev);
Eric Anholt20caafa2007-08-25 19:22:43 +10001285 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001286 }
1287 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001288 if (!dev_priv->ring_rptr) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001289 DRM_ERROR("could not find ring read pointer!\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001290 radeon_do_cleanup_cp(dev);
Eric Anholt20caafa2007-08-25 19:22:43 +10001291 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001292 }
Dave Airlied1f2b552005-08-05 22:11:22 +10001293 dev->agp_buffer_token = init->buffers_offset;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001294 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001295 if (!dev->agp_buffer_map) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001296 DRM_ERROR("could not find dma buffer region!\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001297 radeon_do_cleanup_cp(dev);
Eric Anholt20caafa2007-08-25 19:22:43 +10001298 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001299 }
1300
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001301 if (init->gart_textures_offset) {
1302 dev_priv->gart_textures =
1303 drm_core_findmap(dev, init->gart_textures_offset);
1304 if (!dev_priv->gart_textures) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001305 DRM_ERROR("could not find GART texture region!\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001306 radeon_do_cleanup_cp(dev);
Eric Anholt20caafa2007-08-25 19:22:43 +10001307 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001308 }
1309 }
1310
Linus Torvalds1da177e2005-04-16 15:20:36 -07001311#if __OS_HAS_AGP
Dave Airlie54a56ac2006-09-22 04:25:09 +10001312 if (dev_priv->flags & RADEON_IS_AGP) {
Dave Airlie9b8d5a12009-02-07 11:15:41 +10001313 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
1314 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
1315 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001316 if (!dev_priv->cp_ring->handle ||
1317 !dev_priv->ring_rptr->handle ||
1318 !dev->agp_buffer_map->handle) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001319 DRM_ERROR("could not find ioremap agp regions!\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001320 radeon_do_cleanup_cp(dev);
Eric Anholt20caafa2007-08-25 19:22:43 +10001321 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001322 }
1323 } else
1324#endif
1325 {
Benjamin Herrenschmidt41c2e752009-02-02 16:55:47 +11001326 dev_priv->cp_ring->handle =
1327 (void *)(unsigned long)dev_priv->cp_ring->offset;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001328 dev_priv->ring_rptr->handle =
Benjamin Herrenschmidt41c2e752009-02-02 16:55:47 +11001329 (void *)(unsigned long)dev_priv->ring_rptr->offset;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001330 dev->agp_buffer_map->handle =
Benjamin Herrenschmidt41c2e752009-02-02 16:55:47 +11001331 (void *)(unsigned long)dev->agp_buffer_map->offset;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001332
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001333 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1334 dev_priv->cp_ring->handle);
1335 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1336 dev_priv->ring_rptr->handle);
1337 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1338 dev->agp_buffer_map->handle);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001339 }
1340
Dave Airlie3d5e2c12008-02-07 15:01:05 +10001341 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
Dave Airliebc5f4522007-11-05 12:50:58 +10001342 dev_priv->fb_size =
Dave Airlie3d5e2c12008-02-07 15:01:05 +10001343 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
Dave Airlied5ea7022006-03-19 19:37:55 +11001344 - dev_priv->fb_location;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001345
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001346 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1347 ((dev_priv->front_offset
1348 + dev_priv->fb_location) >> 10));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001349
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001350 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1351 ((dev_priv->back_offset
1352 + dev_priv->fb_location) >> 10));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001353
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001354 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1355 ((dev_priv->depth_offset
1356 + dev_priv->fb_location) >> 10));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001357
1358 dev_priv->gart_size = init->gart_size;
Dave Airlied5ea7022006-03-19 19:37:55 +11001359
1360 /* New let's set the memory map ... */
1361 if (dev_priv->new_memmap) {
1362 u32 base = 0;
1363
1364 DRM_INFO("Setting GART location based on new memory map\n");
1365
1366 /* If using AGP, try to locate the AGP aperture at the same
1367 * location in the card and on the bus, though we have to
1368 * align it down.
1369 */
1370#if __OS_HAS_AGP
Dave Airlie54a56ac2006-09-22 04:25:09 +10001371 if (dev_priv->flags & RADEON_IS_AGP) {
Dave Airlied5ea7022006-03-19 19:37:55 +11001372 base = dev->agp->base;
1373 /* Check if valid */
Michel Dänzer80b2c382007-02-18 18:03:21 +11001374 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1375 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
Dave Airlied5ea7022006-03-19 19:37:55 +11001376 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1377 dev->agp->base);
1378 base = 0;
1379 }
1380 }
1381#endif
1382 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1383 if (base == 0) {
1384 base = dev_priv->fb_location + dev_priv->fb_size;
Michel Dänzer80b2c382007-02-18 18:03:21 +11001385 if (base < dev_priv->fb_location ||
1386 ((base + dev_priv->gart_size) & 0xfffffffful) < base)
Dave Airlied5ea7022006-03-19 19:37:55 +11001387 base = dev_priv->fb_location
1388 - dev_priv->gart_size;
Dave Airliebc5f4522007-11-05 12:50:58 +10001389 }
Dave Airlied5ea7022006-03-19 19:37:55 +11001390 dev_priv->gart_vm_start = base & 0xffc00000u;
1391 if (dev_priv->gart_vm_start != base)
1392 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1393 base, dev_priv->gart_vm_start);
1394 } else {
1395 DRM_INFO("Setting GART location based on old memory map\n");
1396 dev_priv->gart_vm_start = dev_priv->fb_location +
1397 RADEON_READ(RADEON_CONFIG_APER_SIZE);
1398 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001399
1400#if __OS_HAS_AGP
Dave Airlie54a56ac2006-09-22 04:25:09 +10001401 if (dev_priv->flags & RADEON_IS_AGP)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001402 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001403 - dev->agp->base
1404 + dev_priv->gart_vm_start);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001405 else
1406#endif
1407 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
Ivan Kokshayskyb0917bd2005-10-26 11:05:25 +01001408 - (unsigned long)dev->sg->virtual
1409 + dev_priv->gart_vm_start);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001410
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001411 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1412 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1413 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1414 dev_priv->gart_buffers_offset);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001415
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001416 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1417 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
Linus Torvalds1da177e2005-04-16 15:20:36 -07001418 + init->ring_size / sizeof(u32));
1419 dev_priv->ring.size = init->ring_size;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001420 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001421
Roland Scheidegger576cc452008-02-07 14:59:24 +10001422 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1423 dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1424
1425 dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1426 dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001427 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001428
1429 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1430
1431#if __OS_HAS_AGP
Dave Airlie54a56ac2006-09-22 04:25:09 +10001432 if (dev_priv->flags & RADEON_IS_AGP) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001433 /* Turn off PCI GART */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001434 radeon_set_pcigart(dev_priv, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001435 } else
1436#endif
1437 {
David Miller6abf6bb2009-02-14 01:51:07 -08001438 u32 sctrl;
1439 int ret;
1440
Dave Airlieb05c2382008-03-17 10:24:24 +10001441 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
Dave Airlieea98a922005-09-11 20:28:11 +10001442 /* if we have an offset set from userspace */
Dave Airlief2b04cd2007-05-08 15:19:23 +10001443 if (dev_priv->pcigart_offset_set) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001444 dev_priv->gart_info.bus_addr =
Benjamin Herrenschmidt41c2e752009-02-02 16:55:47 +11001445 (resource_size_t)dev_priv->pcigart_offset + dev_priv->fb_location;
Dave Airlief26c4732006-01-02 17:18:39 +11001446 dev_priv->gart_info.mapping.offset =
Dave Airlie7fc86862007-11-05 10:45:27 +10001447 dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
Dave Airlief26c4732006-01-02 17:18:39 +11001448 dev_priv->gart_info.mapping.size =
Dave Airlief2b04cd2007-05-08 15:19:23 +10001449 dev_priv->gart_info.table_size;
Dave Airlief26c4732006-01-02 17:18:39 +11001450
Dave Airlie242e3df2008-07-15 15:48:05 +10001451 drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001452 dev_priv->gart_info.addr =
Dave Airlief26c4732006-01-02 17:18:39 +11001453 dev_priv->gart_info.mapping.handle;
Dave Airlieea98a922005-09-11 20:28:11 +10001454
Dave Airlief2b04cd2007-05-08 15:19:23 +10001455 if (dev_priv->flags & RADEON_IS_PCIE)
1456 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1457 else
1458 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001459 dev_priv->gart_info.gart_table_location =
1460 DRM_ATI_GART_FB;
1461
Dave Airlief26c4732006-01-02 17:18:39 +11001462 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001463 dev_priv->gart_info.addr,
1464 dev_priv->pcigart_offset);
1465 } else {
Dave Airlief2b04cd2007-05-08 15:19:23 +10001466 if (dev_priv->flags & RADEON_IS_IGPGART)
1467 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1468 else
1469 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001470 dev_priv->gart_info.gart_table_location =
1471 DRM_ATI_GART_MAIN;
Dave Airlief26c4732006-01-02 17:18:39 +11001472 dev_priv->gart_info.addr = NULL;
1473 dev_priv->gart_info.bus_addr = 0;
Dave Airlie54a56ac2006-09-22 04:25:09 +10001474 if (dev_priv->flags & RADEON_IS_PCIE) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001475 DRM_ERROR
1476 ("Cannot use PCI Express without GART in FB memory\n");
Dave Airlieea98a922005-09-11 20:28:11 +10001477 radeon_do_cleanup_cp(dev);
Eric Anholt20caafa2007-08-25 19:22:43 +10001478 return -EINVAL;
Dave Airlieea98a922005-09-11 20:28:11 +10001479 }
1480 }
1481
David Miller6abf6bb2009-02-14 01:51:07 -08001482 sctrl = RADEON_READ(RADEON_SURFACE_CNTL);
1483 RADEON_WRITE(RADEON_SURFACE_CNTL, 0);
Alex Deucherc1556f72009-02-25 16:57:49 -05001484 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1485 ret = r600_page_table_init(dev);
1486 else
1487 ret = drm_ati_pcigart_init(dev, &dev_priv->gart_info);
David Miller6abf6bb2009-02-14 01:51:07 -08001488 RADEON_WRITE(RADEON_SURFACE_CNTL, sctrl);
1489
1490 if (!ret) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001491 DRM_ERROR("failed to init PCI GART!\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001492 radeon_do_cleanup_cp(dev);
Eric Anholt20caafa2007-08-25 19:22:43 +10001493 return -ENOMEM;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001494 }
1495
David Miller6abf6bb2009-02-14 01:51:07 -08001496 ret = radeon_setup_pcigart_surface(dev_priv);
1497 if (ret) {
1498 DRM_ERROR("failed to setup GART surface!\n");
Alex Deucherc1556f72009-02-25 16:57:49 -05001499 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1500 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1501 else
1502 drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info);
David Miller6abf6bb2009-02-14 01:51:07 -08001503 radeon_do_cleanup_cp(dev);
1504 return ret;
1505 }
1506
Linus Torvalds1da177e2005-04-16 15:20:36 -07001507 /* Turn on PCI GART */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001508 radeon_set_pcigart(dev_priv, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001509 }
1510
Ben Hutchings70967ab2009-08-29 14:53:51 +01001511 if (!dev_priv->me_fw) {
1512 int err = radeon_cp_init_microcode(dev_priv);
1513 if (err) {
1514 DRM_ERROR("Failed to load firmware!\n");
1515 radeon_do_cleanup_cp(dev);
1516 return err;
1517 }
1518 }
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001519 radeon_cp_load_microcode(dev_priv);
etienne3d161182009-02-20 09:44:45 +10001520 radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001521
1522 dev_priv->last_buf = 0;
1523
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001524 radeon_do_engine_reset(dev);
Dave Airlied5ea7022006-03-19 19:37:55 +11001525 radeon_test_writeback(dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001526
1527 return 0;
1528}
1529
Dave Airlie84b1fd12007-07-11 15:53:27 +10001530static int radeon_do_cleanup_cp(struct drm_device * dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001531{
1532 drm_radeon_private_t *dev_priv = dev->dev_private;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001533 DRM_DEBUG("\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001534
1535 /* Make sure interrupts are disabled here because the uninstall ioctl
1536 * may not have been called from userspace and after dev_private
1537 * is freed, it's too late.
1538 */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001539 if (dev->irq_enabled)
1540 drm_irq_uninstall(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001541
1542#if __OS_HAS_AGP
Dave Airlie54a56ac2006-09-22 04:25:09 +10001543 if (dev_priv->flags & RADEON_IS_AGP) {
Dave Airlied985c102006-01-02 21:32:48 +11001544 if (dev_priv->cp_ring != NULL) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001545 drm_core_ioremapfree(dev_priv->cp_ring, dev);
Dave Airlied985c102006-01-02 21:32:48 +11001546 dev_priv->cp_ring = NULL;
1547 }
1548 if (dev_priv->ring_rptr != NULL) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001549 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
Dave Airlied985c102006-01-02 21:32:48 +11001550 dev_priv->ring_rptr = NULL;
1551 }
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001552 if (dev->agp_buffer_map != NULL) {
1553 drm_core_ioremapfree(dev->agp_buffer_map, dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001554 dev->agp_buffer_map = NULL;
1555 }
1556 } else
1557#endif
1558 {
Dave Airlied985c102006-01-02 21:32:48 +11001559
1560 if (dev_priv->gart_info.bus_addr) {
1561 /* Turn off PCI GART */
1562 radeon_set_pcigart(dev_priv, 0);
Alex Deucherc1556f72009-02-25 16:57:49 -05001563 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1564 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1565 else {
1566 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1567 DRM_ERROR("failed to cleanup PCI GART!\n");
1568 }
Dave Airlied985c102006-01-02 21:32:48 +11001569 }
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001570
Dave Airlied985c102006-01-02 21:32:48 +11001571 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1572 {
Dave Airlief26c4732006-01-02 17:18:39 +11001573 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
Hannes Eder8f497aa2009-03-05 20:14:18 +01001574 dev_priv->gart_info.addr = NULL;
Dave Airlieea98a922005-09-11 20:28:11 +10001575 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001576 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001577 /* only clear to the start of flags */
1578 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1579
1580 return 0;
1581}
1582
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001583/* This code will reinit the Radeon CP hardware after a resume from disc.
1584 * AFAIK, it would be very difficult to pickle the state at suspend time, so
Linus Torvalds1da177e2005-04-16 15:20:36 -07001585 * here we make sure that all Radeon hardware initialisation is re-done without
1586 * affecting running applications.
1587 *
1588 * Charl P. Botha <http://cpbotha.net>
1589 */
etienne3d161182009-02-20 09:44:45 +10001590static int radeon_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001591{
1592 drm_radeon_private_t *dev_priv = dev->dev_private;
1593
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001594 if (!dev_priv) {
1595 DRM_ERROR("Called with no initialization\n");
Eric Anholt20caafa2007-08-25 19:22:43 +10001596 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001597 }
1598
1599 DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1600
1601#if __OS_HAS_AGP
Dave Airlie54a56ac2006-09-22 04:25:09 +10001602 if (dev_priv->flags & RADEON_IS_AGP) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001603 /* Turn off PCI GART */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001604 radeon_set_pcigart(dev_priv, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001605 } else
1606#endif
1607 {
1608 /* Turn on PCI GART */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001609 radeon_set_pcigart(dev_priv, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001610 }
1611
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001612 radeon_cp_load_microcode(dev_priv);
etienne3d161182009-02-20 09:44:45 +10001613 radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001614
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001615 radeon_do_engine_reset(dev);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001616 radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001617
1618 DRM_DEBUG("radeon_do_resume_cp() complete\n");
1619
1620 return 0;
1621}
1622
Eric Anholtc153f452007-09-03 12:06:45 +10001623int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001624{
Alex Deucherc05ce082009-02-24 16:22:29 -05001625 drm_radeon_private_t *dev_priv = dev->dev_private;
Eric Anholtc153f452007-09-03 12:06:45 +10001626 drm_radeon_init_t *init = data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001627
Eric Anholt6c340ea2007-08-25 20:23:09 +10001628 LOCK_TEST_WITH_RETURN(dev, file_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001629
Eric Anholtc153f452007-09-03 12:06:45 +10001630 if (init->func == RADEON_INIT_R300_CP)
Dave Airlie3d5e2c12008-02-07 15:01:05 +10001631 r300_init_reg_flags(dev);
Dave Airlie414ed532005-08-16 20:43:16 +10001632
Eric Anholtc153f452007-09-03 12:06:45 +10001633 switch (init->func) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001634 case RADEON_INIT_CP:
1635 case RADEON_INIT_R200_CP:
1636 case RADEON_INIT_R300_CP:
Dave Airlie7c1c2872008-11-28 14:22:24 +10001637 return radeon_do_init_cp(dev, init, file_priv);
Alex Deucherc05ce082009-02-24 16:22:29 -05001638 case RADEON_INIT_R600_CP:
1639 return r600_do_init_cp(dev, init, file_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001640 case RADEON_CLEANUP_CP:
Alex Deucherc05ce082009-02-24 16:22:29 -05001641 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1642 return r600_do_cleanup_cp(dev);
1643 else
1644 return radeon_do_cleanup_cp(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001645 }
1646
Eric Anholt20caafa2007-08-25 19:22:43 +10001647 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001648}
1649
Eric Anholtc153f452007-09-03 12:06:45 +10001650int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001651{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001652 drm_radeon_private_t *dev_priv = dev->dev_private;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001653 DRM_DEBUG("\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001654
Eric Anholt6c340ea2007-08-25 20:23:09 +10001655 LOCK_TEST_WITH_RETURN(dev, file_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001656
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001657 if (dev_priv->cp_running) {
Márton Németh3e684ea2008-01-24 15:58:57 +10001658 DRM_DEBUG("while CP running\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001659 return 0;
1660 }
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001661 if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
Márton Németh3e684ea2008-01-24 15:58:57 +10001662 DRM_DEBUG("called with bogus CP mode (%d)\n",
1663 dev_priv->cp_mode);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001664 return 0;
1665 }
1666
Alex Deucherc05ce082009-02-24 16:22:29 -05001667 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1668 r600_do_cp_start(dev_priv);
1669 else
1670 radeon_do_cp_start(dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001671
1672 return 0;
1673}
1674
1675/* Stop the CP. The engine must have been idled before calling this
1676 * routine.
1677 */
Eric Anholtc153f452007-09-03 12:06:45 +10001678int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001679{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001680 drm_radeon_private_t *dev_priv = dev->dev_private;
Eric Anholtc153f452007-09-03 12:06:45 +10001681 drm_radeon_cp_stop_t *stop = data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001682 int ret;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001683 DRM_DEBUG("\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001684
Eric Anholt6c340ea2007-08-25 20:23:09 +10001685 LOCK_TEST_WITH_RETURN(dev, file_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001686
Linus Torvalds1da177e2005-04-16 15:20:36 -07001687 if (!dev_priv->cp_running)
1688 return 0;
1689
1690 /* Flush any pending CP commands. This ensures any outstanding
1691 * commands are exectuted by the engine before we turn it off.
1692 */
Eric Anholtc153f452007-09-03 12:06:45 +10001693 if (stop->flush) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001694 radeon_do_cp_flush(dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001695 }
1696
1697 /* If we fail to make the engine go idle, we return an error
1698 * code so that the DRM ioctl wrapper can try again.
1699 */
Eric Anholtc153f452007-09-03 12:06:45 +10001700 if (stop->idle) {
Alex Deucherc05ce082009-02-24 16:22:29 -05001701 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1702 ret = r600_do_cp_idle(dev_priv);
1703 else
1704 ret = radeon_do_cp_idle(dev_priv);
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001705 if (ret)
1706 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001707 }
1708
1709 /* Finally, we can turn off the CP. If the engine isn't idle,
1710 * we will get some dropped triangles as they won't be fully
1711 * rendered before the CP is shut down.
1712 */
Alex Deucherc05ce082009-02-24 16:22:29 -05001713 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1714 r600_do_cp_stop(dev_priv);
1715 else
1716 radeon_do_cp_stop(dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001717
1718 /* Reset the engine */
Alex Deucherc05ce082009-02-24 16:22:29 -05001719 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1720 r600_do_engine_reset(dev);
1721 else
1722 radeon_do_engine_reset(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001723
1724 return 0;
1725}
1726
Dave Airlie84b1fd12007-07-11 15:53:27 +10001727void radeon_do_release(struct drm_device * dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001728{
1729 drm_radeon_private_t *dev_priv = dev->dev_private;
1730 int i, ret;
1731
1732 if (dev_priv) {
1733 if (dev_priv->cp_running) {
1734 /* Stop the cp */
Dave Airlie53c379e2009-03-09 12:12:28 +10001735 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
Alex Deucherc05ce082009-02-24 16:22:29 -05001736 while ((ret = r600_do_cp_idle(dev_priv)) != 0) {
1737 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001738#ifdef __linux__
Alex Deucherc05ce082009-02-24 16:22:29 -05001739 schedule();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001740#else
Alex Deucherc05ce082009-02-24 16:22:29 -05001741 tsleep(&ret, PZERO, "rdnrel", 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001742#endif
Alex Deucherc05ce082009-02-24 16:22:29 -05001743 }
1744 } else {
1745 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1746 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1747#ifdef __linux__
1748 schedule();
1749#else
1750 tsleep(&ret, PZERO, "rdnrel", 1);
1751#endif
1752 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001753 }
Alex Deucherc05ce082009-02-24 16:22:29 -05001754 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1755 r600_do_cp_stop(dev_priv);
1756 r600_do_engine_reset(dev);
1757 } else {
1758 radeon_do_cp_stop(dev_priv);
1759 radeon_do_engine_reset(dev);
1760 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001761 }
1762
Alex Deucherc05ce082009-02-24 16:22:29 -05001763 if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_R600) {
1764 /* Disable *all* interrupts */
1765 if (dev_priv->mmio) /* remove this after permanent addmaps */
1766 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001767
Alex Deucherc05ce082009-02-24 16:22:29 -05001768 if (dev_priv->mmio) { /* remove all surfaces */
1769 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1770 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1771 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1772 16 * i, 0);
1773 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1774 16 * i, 0);
1775 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001776 }
1777 }
1778
1779 /* Free memory heap structures */
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001780 radeon_mem_takedown(&(dev_priv->gart_heap));
1781 radeon_mem_takedown(&(dev_priv->fb_heap));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001782
1783 /* deallocate kernel resources */
Alex Deucherc05ce082009-02-24 16:22:29 -05001784 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1785 r600_do_cleanup_cp(dev);
1786 else
1787 radeon_do_cleanup_cp(dev);
Ben Hutchings70967ab2009-08-29 14:53:51 +01001788 if (dev_priv->me_fw) {
1789 release_firmware(dev_priv->me_fw);
1790 dev_priv->me_fw = NULL;
1791 }
1792 if (dev_priv->pfp_fw) {
1793 release_firmware(dev_priv->pfp_fw);
1794 dev_priv->pfp_fw = NULL;
1795 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001796 }
1797}
1798
1799/* Just reset the CP ring. Called as part of an X Server engine reset.
1800 */
Eric Anholtc153f452007-09-03 12:06:45 +10001801int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001802{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001803 drm_radeon_private_t *dev_priv = dev->dev_private;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001804 DRM_DEBUG("\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001805
Eric Anholt6c340ea2007-08-25 20:23:09 +10001806 LOCK_TEST_WITH_RETURN(dev, file_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001807
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001808 if (!dev_priv) {
Márton Németh3e684ea2008-01-24 15:58:57 +10001809 DRM_DEBUG("called before init done\n");
Eric Anholt20caafa2007-08-25 19:22:43 +10001810 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001811 }
1812
Alex Deucherc05ce082009-02-24 16:22:29 -05001813 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1814 r600_do_cp_reset(dev_priv);
1815 else
1816 radeon_do_cp_reset(dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001817
1818 /* The CP is no longer running after an engine reset */
1819 dev_priv->cp_running = 0;
1820
1821 return 0;
1822}
1823
Eric Anholtc153f452007-09-03 12:06:45 +10001824int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001825{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001826 drm_radeon_private_t *dev_priv = dev->dev_private;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001827 DRM_DEBUG("\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001828
Eric Anholt6c340ea2007-08-25 20:23:09 +10001829 LOCK_TEST_WITH_RETURN(dev, file_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001830
Alex Deucherc05ce082009-02-24 16:22:29 -05001831 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1832 return r600_do_cp_idle(dev_priv);
1833 else
1834 return radeon_do_cp_idle(dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001835}
1836
1837/* Added by Charl P. Botha to call radeon_do_resume_cp().
1838 */
Eric Anholtc153f452007-09-03 12:06:45 +10001839int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001840{
Alex Deucherc05ce082009-02-24 16:22:29 -05001841 drm_radeon_private_t *dev_priv = dev->dev_private;
1842 DRM_DEBUG("\n");
1843
1844 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1845 return r600_do_resume_cp(dev, file_priv);
1846 else
1847 return radeon_do_resume_cp(dev, file_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001848}
1849
Eric Anholtc153f452007-09-03 12:06:45 +10001850int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001851{
Alex Deucherc05ce082009-02-24 16:22:29 -05001852 drm_radeon_private_t *dev_priv = dev->dev_private;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001853 DRM_DEBUG("\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001854
Eric Anholt6c340ea2007-08-25 20:23:09 +10001855 LOCK_TEST_WITH_RETURN(dev, file_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001856
Alex Deucherc05ce082009-02-24 16:22:29 -05001857 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1858 return r600_do_engine_reset(dev);
1859 else
1860 return radeon_do_engine_reset(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001861}
1862
Linus Torvalds1da177e2005-04-16 15:20:36 -07001863/* ================================================================
1864 * Fullscreen mode
1865 */
1866
1867/* KW: Deprecated to say the least:
1868 */
Eric Anholtc153f452007-09-03 12:06:45 +10001869int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001870{
1871 return 0;
1872}
1873
Linus Torvalds1da177e2005-04-16 15:20:36 -07001874/* ================================================================
1875 * Freelist management
1876 */
1877
1878/* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1879 * bufs until freelist code is used. Note this hides a problem with
1880 * the scratch register * (used to keep track of last buffer
1881 * completed) being written to before * the last buffer has actually
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001882 * completed rendering.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001883 *
1884 * KW: It's also a good way to find free buffers quickly.
1885 *
1886 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1887 * sleep. However, bugs in older versions of radeon_accel.c mean that
1888 * we essentially have to do this, else old clients will break.
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001889 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07001890 * However, it does leave open a potential deadlock where all the
1891 * buffers are held by other clients, which can't release them because
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001892 * they can't get the lock.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001893 */
1894
Dave Airlie056219e2007-07-11 16:17:42 +10001895struct drm_buf *radeon_freelist_get(struct drm_device * dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001896{
Dave Airliecdd55a22007-07-11 16:32:08 +10001897 struct drm_device_dma *dma = dev->dma;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001898 drm_radeon_private_t *dev_priv = dev->dev_private;
1899 drm_radeon_buf_priv_t *buf_priv;
Dave Airlie056219e2007-07-11 16:17:42 +10001900 struct drm_buf *buf;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001901 int i, t;
1902 int start;
1903
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001904 if (++dev_priv->last_buf >= dma->buf_count)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001905 dev_priv->last_buf = 0;
1906
1907 start = dev_priv->last_buf;
1908
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001909 for (t = 0; t < dev_priv->usec_timeout; t++) {
David Millerb07fa022009-02-12 02:15:37 -08001910 u32 done_age = GET_SCRATCH(dev_priv, 1);
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001911 DRM_DEBUG("done_age = %d\n", done_age);
1912 for (i = start; i < dma->buf_count; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001913 buf = dma->buflist[i];
1914 buf_priv = buf->dev_private;
Eric Anholt6c340ea2007-08-25 20:23:09 +10001915 if (buf->file_priv == NULL || (buf->pending &&
1916 buf_priv->age <=
1917 done_age)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001918 dev_priv->stats.requested_bufs++;
1919 buf->pending = 0;
1920 return buf;
1921 }
1922 start = 0;
1923 }
1924
1925 if (t) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001926 DRM_UDELAY(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001927 dev_priv->stats.freelist_loops++;
1928 }
1929 }
1930
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001931 DRM_DEBUG("returning NULL!\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001932 return NULL;
1933}
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001934
Linus Torvalds1da177e2005-04-16 15:20:36 -07001935#if 0
Dave Airlie056219e2007-07-11 16:17:42 +10001936struct drm_buf *radeon_freelist_get(struct drm_device * dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001937{
Dave Airliecdd55a22007-07-11 16:32:08 +10001938 struct drm_device_dma *dma = dev->dma;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001939 drm_radeon_private_t *dev_priv = dev->dev_private;
1940 drm_radeon_buf_priv_t *buf_priv;
Dave Airlie056219e2007-07-11 16:17:42 +10001941 struct drm_buf *buf;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001942 int i, t;
1943 int start;
David Millerb07fa022009-02-12 02:15:37 -08001944 u32 done_age;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001945
David Millerb07fa022009-02-12 02:15:37 -08001946 done_age = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001947 if (++dev_priv->last_buf >= dma->buf_count)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001948 dev_priv->last_buf = 0;
1949
1950 start = dev_priv->last_buf;
1951 dev_priv->stats.freelist_loops++;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001952
1953 for (t = 0; t < 2; t++) {
1954 for (i = start; i < dma->buf_count; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001955 buf = dma->buflist[i];
1956 buf_priv = buf->dev_private;
Eric Anholt6c340ea2007-08-25 20:23:09 +10001957 if (buf->file_priv == 0 || (buf->pending &&
1958 buf_priv->age <=
1959 done_age)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001960 dev_priv->stats.requested_bufs++;
1961 buf->pending = 0;
1962 return buf;
1963 }
1964 }
1965 start = 0;
1966 }
1967
1968 return NULL;
1969}
1970#endif
1971
Dave Airlie84b1fd12007-07-11 15:53:27 +10001972void radeon_freelist_reset(struct drm_device * dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001973{
Dave Airliecdd55a22007-07-11 16:32:08 +10001974 struct drm_device_dma *dma = dev->dma;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001975 drm_radeon_private_t *dev_priv = dev->dev_private;
1976 int i;
1977
1978 dev_priv->last_buf = 0;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001979 for (i = 0; i < dma->buf_count; i++) {
Dave Airlie056219e2007-07-11 16:17:42 +10001980 struct drm_buf *buf = dma->buflist[i];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001981 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1982 buf_priv->age = 0;
1983 }
1984}
1985
Linus Torvalds1da177e2005-04-16 15:20:36 -07001986/* ================================================================
1987 * CP command submission
1988 */
1989
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001990int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001991{
1992 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1993 int i;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001994 u32 last_head = GET_RING_HEAD(dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001995
Dave Airlieb5e89ed2005-09-25 14:28:13 +10001996 for (i = 0; i < dev_priv->usec_timeout; i++) {
1997 u32 head = GET_RING_HEAD(dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001998
1999 ring->space = (head - ring->tail) * sizeof(u32);
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002000 if (ring->space <= 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002001 ring->space += ring->size;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002002 if (ring->space > n)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002003 return 0;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002004
Linus Torvalds1da177e2005-04-16 15:20:36 -07002005 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
2006
2007 if (head != last_head)
2008 i = 0;
2009 last_head = head;
2010
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002011 DRM_UDELAY(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002012 }
2013
2014 /* FIXME: This return value is ignored in the BEGIN_RING macro! */
2015#if RADEON_FIFO_DEBUG
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002016 radeon_status(dev_priv);
2017 DRM_ERROR("failed!\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002018#endif
Eric Anholt20caafa2007-08-25 19:22:43 +10002019 return -EBUSY;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002020}
2021
Eric Anholt6c340ea2007-08-25 20:23:09 +10002022static int radeon_cp_get_buffers(struct drm_device *dev,
2023 struct drm_file *file_priv,
Dave Airliec60ce622007-07-11 15:27:12 +10002024 struct drm_dma * d)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002025{
2026 int i;
Dave Airlie056219e2007-07-11 16:17:42 +10002027 struct drm_buf *buf;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002028
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002029 for (i = d->granted_count; i < d->request_count; i++) {
2030 buf = radeon_freelist_get(dev);
2031 if (!buf)
Eric Anholt20caafa2007-08-25 19:22:43 +10002032 return -EBUSY; /* NOTE: broken client */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002033
Eric Anholt6c340ea2007-08-25 20:23:09 +10002034 buf->file_priv = file_priv;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002035
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002036 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
2037 sizeof(buf->idx)))
Eric Anholt20caafa2007-08-25 19:22:43 +10002038 return -EFAULT;
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002039 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
2040 sizeof(buf->total)))
Eric Anholt20caafa2007-08-25 19:22:43 +10002041 return -EFAULT;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002042
2043 d->granted_count++;
2044 }
2045 return 0;
2046}
2047
Eric Anholtc153f452007-09-03 12:06:45 +10002048int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002049{
Dave Airliecdd55a22007-07-11 16:32:08 +10002050 struct drm_device_dma *dma = dev->dma;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002051 int ret = 0;
Eric Anholtc153f452007-09-03 12:06:45 +10002052 struct drm_dma *d = data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002053
Eric Anholt6c340ea2007-08-25 20:23:09 +10002054 LOCK_TEST_WITH_RETURN(dev, file_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002055
Linus Torvalds1da177e2005-04-16 15:20:36 -07002056 /* Please don't send us buffers.
2057 */
Eric Anholtc153f452007-09-03 12:06:45 +10002058 if (d->send_count != 0) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002059 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
Eric Anholtc153f452007-09-03 12:06:45 +10002060 DRM_CURRENTPID, d->send_count);
Eric Anholt20caafa2007-08-25 19:22:43 +10002061 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002062 }
2063
2064 /* We'll send you buffers.
2065 */
Eric Anholtc153f452007-09-03 12:06:45 +10002066 if (d->request_count < 0 || d->request_count > dma->buf_count) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002067 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
Eric Anholtc153f452007-09-03 12:06:45 +10002068 DRM_CURRENTPID, d->request_count, dma->buf_count);
Eric Anholt20caafa2007-08-25 19:22:43 +10002069 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002070 }
2071
Eric Anholtc153f452007-09-03 12:06:45 +10002072 d->granted_count = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002073
Eric Anholtc153f452007-09-03 12:06:45 +10002074 if (d->request_count) {
2075 ret = radeon_cp_get_buffers(dev, file_priv, d);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002076 }
2077
Linus Torvalds1da177e2005-04-16 15:20:36 -07002078 return ret;
2079}
2080
Dave Airlie22eae942005-11-10 22:16:34 +11002081int radeon_driver_load(struct drm_device *dev, unsigned long flags)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002082{
2083 drm_radeon_private_t *dev_priv;
2084 int ret = 0;
2085
Eric Anholt9a298b22009-03-24 12:23:04 -07002086 dev_priv = kzalloc(sizeof(drm_radeon_private_t), GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002087 if (dev_priv == NULL)
Eric Anholt20caafa2007-08-25 19:22:43 +10002088 return -ENOMEM;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002089
Linus Torvalds1da177e2005-04-16 15:20:36 -07002090 dev->dev_private = (void *)dev_priv;
2091 dev_priv->flags = flags;
2092
Dave Airlie54a56ac2006-09-22 04:25:09 +10002093 switch (flags & RADEON_FAMILY_MASK) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002094 case CHIP_R100:
2095 case CHIP_RV200:
2096 case CHIP_R200:
2097 case CHIP_R300:
Dave Airlieb15ec362006-08-19 17:43:52 +10002098 case CHIP_R350:
Dave Airlie414ed532005-08-16 20:43:16 +10002099 case CHIP_R420:
Alex Deucheredc6f382008-10-17 09:21:45 +10002100 case CHIP_R423:
Dave Airlieb15ec362006-08-19 17:43:52 +10002101 case CHIP_RV410:
Dave Airlie3d5e2c12008-02-07 15:01:05 +10002102 case CHIP_RV515:
2103 case CHIP_R520:
2104 case CHIP_RV570:
2105 case CHIP_R580:
Dave Airlie54a56ac2006-09-22 04:25:09 +10002106 dev_priv->flags |= RADEON_HAS_HIERZ;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002107 break;
2108 default:
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002109 /* all other chips have no hierarchical z buffer */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002110 break;
2111 }
Dave Airlie414ed532005-08-16 20:43:16 +10002112
2113 if (drm_device_is_agp(dev))
Dave Airlie54a56ac2006-09-22 04:25:09 +10002114 dev_priv->flags |= RADEON_IS_AGP;
Dave Airlieb15ec362006-08-19 17:43:52 +10002115 else if (drm_device_is_pcie(dev))
Dave Airlie54a56ac2006-09-22 04:25:09 +10002116 dev_priv->flags |= RADEON_IS_PCIE;
Dave Airlieb15ec362006-08-19 17:43:52 +10002117 else
Dave Airlie54a56ac2006-09-22 04:25:09 +10002118 dev_priv->flags |= RADEON_IS_PCI;
Dave Airlieea98a922005-09-11 20:28:11 +10002119
Dave Airlie78538bf2008-11-11 17:56:16 +10002120 ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
2121 drm_get_resource_len(dev, 2), _DRM_REGISTERS,
2122 _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio);
2123 if (ret != 0)
2124 return ret;
2125
Keith Packard52440212008-11-18 09:30:25 -08002126 ret = drm_vblank_init(dev, 2);
2127 if (ret) {
2128 radeon_driver_unload(dev);
2129 return ret;
2130 }
2131
Dave Airlie414ed532005-08-16 20:43:16 +10002132 DRM_DEBUG("%s card detected\n",
Dave Airlie54a56ac2006-09-22 04:25:09 +10002133 ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
Linus Torvalds1da177e2005-04-16 15:20:36 -07002134 return ret;
2135}
2136
Dave Airlie7c1c2872008-11-28 14:22:24 +10002137int radeon_master_create(struct drm_device *dev, struct drm_master *master)
2138{
2139 struct drm_radeon_master_private *master_priv;
2140 unsigned long sareapage;
2141 int ret;
2142
Eric Anholt9a298b22009-03-24 12:23:04 -07002143 master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
Dave Airlie7c1c2872008-11-28 14:22:24 +10002144 if (!master_priv)
2145 return -ENOMEM;
2146
2147 /* prebuild the SAREA */
Dave Airliebdf539a2008-12-18 16:56:11 +10002148 sareapage = max_t(unsigned long, SAREA_MAX, PAGE_SIZE);
Dave Airliedf4f7fe2009-06-11 16:16:10 +10002149 ret = drm_addmap(dev, 0, sareapage, _DRM_SHM, _DRM_CONTAINS_LOCK,
Dave Airlie7c1c2872008-11-28 14:22:24 +10002150 &master_priv->sarea);
2151 if (ret) {
2152 DRM_ERROR("SAREA setup failed\n");
2153 return ret;
2154 }
2155 master_priv->sarea_priv = master_priv->sarea->handle + sizeof(struct drm_sarea);
2156 master_priv->sarea_priv->pfCurrentPage = 0;
2157
2158 master->driver_priv = master_priv;
2159 return 0;
2160}
2161
2162void radeon_master_destroy(struct drm_device *dev, struct drm_master *master)
2163{
2164 struct drm_radeon_master_private *master_priv = master->driver_priv;
2165
2166 if (!master_priv)
2167 return;
2168
2169 if (master_priv->sarea_priv &&
2170 master_priv->sarea_priv->pfCurrentPage != 0)
2171 radeon_cp_dispatch_flip(dev, master);
2172
2173 master_priv->sarea_priv = NULL;
2174 if (master_priv->sarea)
Dave Airlie4e74f362008-12-19 10:23:14 +11002175 drm_rmmap_locked(dev, master_priv->sarea);
Dave Airlie7c1c2872008-11-28 14:22:24 +10002176
Eric Anholt9a298b22009-03-24 12:23:04 -07002177 kfree(master_priv);
Dave Airlie7c1c2872008-11-28 14:22:24 +10002178
2179 master->driver_priv = NULL;
2180}
2181
Dave Airlie22eae942005-11-10 22:16:34 +11002182/* Create mappings for registers and framebuffer so userland doesn't necessarily
2183 * have to find them.
2184 */
2185int radeon_driver_firstopen(struct drm_device *dev)
Dave Airlie836cf042005-07-10 19:27:04 +10002186{
2187 int ret;
2188 drm_local_map_t *map;
2189 drm_radeon_private_t *dev_priv = dev->dev_private;
2190
Dave Airlief2b04cd2007-05-08 15:19:23 +10002191 dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
2192
Dave Airlie7fc86862007-11-05 10:45:27 +10002193 dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
2194 ret = drm_addmap(dev, dev_priv->fb_aper_offset,
Dave Airlie836cf042005-07-10 19:27:04 +10002195 drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
2196 _DRM_WRITE_COMBINING, &map);
2197 if (ret != 0)
2198 return ret;
2199
2200 return 0;
2201}
2202
Dave Airlie22eae942005-11-10 22:16:34 +11002203int radeon_driver_unload(struct drm_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002204{
2205 drm_radeon_private_t *dev_priv = dev->dev_private;
2206
2207 DRM_DEBUG("\n");
Dave Airlie78538bf2008-11-11 17:56:16 +10002208
2209 drm_rmmap(dev, dev_priv->mmio);
2210
Eric Anholt9a298b22009-03-24 12:23:04 -07002211 kfree(dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002212
2213 dev->dev_private = NULL;
2214 return 0;
2215}
Dave Airlie4247ca92009-02-20 13:28:34 +10002216
2217void radeon_commit_ring(drm_radeon_private_t *dev_priv)
2218{
2219 int i;
2220 u32 *ring;
2221 int tail_aligned;
2222
2223 /* check if the ring is padded out to 16-dword alignment */
2224
Dave Airlie98638712009-06-04 07:08:13 +10002225 tail_aligned = dev_priv->ring.tail & (RADEON_RING_ALIGN-1);
Dave Airlie4247ca92009-02-20 13:28:34 +10002226 if (tail_aligned) {
Dave Airlie98638712009-06-04 07:08:13 +10002227 int num_p2 = RADEON_RING_ALIGN - tail_aligned;
Dave Airlie4247ca92009-02-20 13:28:34 +10002228
2229 ring = dev_priv->ring.start;
2230 /* pad with some CP_PACKET2 */
2231 for (i = 0; i < num_p2; i++)
2232 ring[dev_priv->ring.tail + i] = CP_PACKET2();
2233
2234 dev_priv->ring.tail += i;
2235
2236 dev_priv->ring.space -= num_p2 * sizeof(u32);
2237 }
2238
2239 dev_priv->ring.tail &= dev_priv->ring.tail_mask;
2240
2241 DRM_MEMORYBARRIER();
2242 GET_RING_HEAD( dev_priv );
2243
Alex Deucherc05ce082009-02-24 16:22:29 -05002244 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
2245 RADEON_WRITE(R600_CP_RB_WPTR, dev_priv->ring.tail);
2246 /* read from PCI bus to ensure correct posting */
2247 RADEON_READ(R600_CP_RB_RPTR);
2248 } else {
2249 RADEON_WRITE(RADEON_CP_RB_WPTR, dev_priv->ring.tail);
2250 /* read from PCI bus to ensure correct posting */
2251 RADEON_READ(RADEON_CP_RB_RPTR);
2252 }
Dave Airlie4247ca92009-02-20 13:28:34 +10002253}