blob: e32a2b55b54f7da7ce8238c578953e1c2f912270 [file] [log] [blame]
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/ktime.h>
Stephen Rothwell568d7c72016-03-17 15:30:49 +110029#include <linux/pagemap.h>
Alex Deucherd38ceaf2015-04-20 16:55:21 -040030#include <drm/drmP.h>
31#include <drm/amdgpu_drm.h>
32#include "amdgpu.h"
33
34void amdgpu_gem_object_free(struct drm_gem_object *gobj)
35{
36 struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj);
37
38 if (robj) {
39 if (robj->gem_base.import_attach)
40 drm_prime_gem_destroy(&robj->gem_base, robj->tbo.sg);
Christian König9298e522015-06-03 21:31:20 +020041 amdgpu_mn_unregister(robj);
Alex Deucherd38ceaf2015-04-20 16:55:21 -040042 amdgpu_bo_unref(&robj);
43 }
44}
45
46int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
47 int alignment, u32 initial_domain,
48 u64 flags, bool kernel,
49 struct drm_gem_object **obj)
50{
51 struct amdgpu_bo *robj;
Alex Deucherd38ceaf2015-04-20 16:55:21 -040052 int r;
53
54 *obj = NULL;
55 /* At least align on page size */
56 if (alignment < PAGE_SIZE) {
57 alignment = PAGE_SIZE;
58 }
59
Alex Deucherd38ceaf2015-04-20 16:55:21 -040060retry:
Christian König72d76682015-09-03 17:34:59 +020061 r = amdgpu_bo_create(adev, size, alignment, kernel, initial_domain,
Yong Zhao2046d462017-07-20 18:49:09 -040062 flags, NULL, NULL, 0, &robj);
Alex Deucherd38ceaf2015-04-20 16:55:21 -040063 if (r) {
64 if (r != -ERESTARTSYS) {
65 if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
66 initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
67 goto retry;
68 }
69 DRM_ERROR("Failed to allocate GEM object (%ld, %d, %u, %d)\n",
70 size, initial_domain, alignment, r);
71 }
72 return r;
73 }
74 *obj = &robj->gem_base;
Alex Deucherd38ceaf2015-04-20 16:55:21 -040075
Alex Deucherd38ceaf2015-04-20 16:55:21 -040076 return 0;
77}
78
Christian König418aa0c2016-02-15 16:59:57 +010079void amdgpu_gem_force_release(struct amdgpu_device *adev)
Alex Deucherd38ceaf2015-04-20 16:55:21 -040080{
Christian König418aa0c2016-02-15 16:59:57 +010081 struct drm_device *ddev = adev->ddev;
82 struct drm_file *file;
Alex Deucherd38ceaf2015-04-20 16:55:21 -040083
Daniel Vetter1d2ac402016-04-26 19:29:41 +020084 mutex_lock(&ddev->filelist_mutex);
Christian König418aa0c2016-02-15 16:59:57 +010085
86 list_for_each_entry(file, &ddev->filelist, lhead) {
87 struct drm_gem_object *gobj;
88 int handle;
89
90 WARN_ONCE(1, "Still active user space clients!\n");
91 spin_lock(&file->table_lock);
92 idr_for_each_entry(&file->object_idr, gobj, handle) {
93 WARN_ONCE(1, "And also active allocations!\n");
Cihangir Akturkf62facc2017-08-03 14:58:16 +030094 drm_gem_object_put_unlocked(gobj);
Christian König418aa0c2016-02-15 16:59:57 +010095 }
96 idr_destroy(&file->object_idr);
97 spin_unlock(&file->table_lock);
98 }
99
Daniel Vetter1d2ac402016-04-26 19:29:41 +0200100 mutex_unlock(&ddev->filelist_mutex);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400101}
102
103/*
104 * Call from drm_gem_handle_create which appear in both new and open ioctl
105 * case.
106 */
Christian Königa7d64de2016-09-15 14:58:48 +0200107int amdgpu_gem_object_open(struct drm_gem_object *obj,
108 struct drm_file *file_priv)
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400109{
Christian König765e7fb2016-09-15 15:06:50 +0200110 struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj);
Christian Königa7d64de2016-09-15 14:58:48 +0200111 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400112 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
113 struct amdgpu_vm *vm = &fpriv->vm;
114 struct amdgpu_bo_va *bo_va;
Christian König4f5839c2017-08-29 16:07:31 +0200115 struct mm_struct *mm;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400116 int r;
Christian König4f5839c2017-08-29 16:07:31 +0200117
118 mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm);
119 if (mm && mm != current->mm)
120 return -EPERM;
121
Christian König765e7fb2016-09-15 15:06:50 +0200122 r = amdgpu_bo_reserve(abo, false);
Chunming Zhoue98c1b02015-11-13 15:22:04 +0800123 if (r)
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400124 return r;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400125
Christian König765e7fb2016-09-15 15:06:50 +0200126 bo_va = amdgpu_vm_bo_find(vm, abo);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400127 if (!bo_va) {
Christian König765e7fb2016-09-15 15:06:50 +0200128 bo_va = amdgpu_vm_bo_add(adev, vm, abo);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400129 } else {
130 ++bo_va->ref_count;
131 }
Christian König765e7fb2016-09-15 15:06:50 +0200132 amdgpu_bo_unreserve(abo);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400133 return 0;
134}
135
136void amdgpu_gem_object_close(struct drm_gem_object *obj,
137 struct drm_file *file_priv)
138{
Christian Königb5a5ec52016-03-08 17:47:46 +0100139 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
Christian Königa7d64de2016-09-15 14:58:48 +0200140 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400141 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
142 struct amdgpu_vm *vm = &fpriv->vm;
Christian Königb5a5ec52016-03-08 17:47:46 +0100143
144 struct amdgpu_bo_list_entry vm_pd;
Christian König5a0f3b52017-04-21 10:05:56 +0200145 struct list_head list;
Christian Königb5a5ec52016-03-08 17:47:46 +0100146 struct ttm_validate_buffer tv;
147 struct ww_acquire_ctx ticket;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400148 struct amdgpu_bo_va *bo_va;
149 int r;
Christian Königb5a5ec52016-03-08 17:47:46 +0100150
151 INIT_LIST_HEAD(&list);
Christian Königb5a5ec52016-03-08 17:47:46 +0100152
153 tv.bo = &bo->tbo;
154 tv.shared = true;
155 list_add(&tv.head, &list);
156
157 amdgpu_vm_get_pd_bo(vm, &list, &vm_pd);
158
Christian König5a0f3b52017-04-21 10:05:56 +0200159 r = ttm_eu_reserve_buffers(&ticket, &list, false, NULL);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400160 if (r) {
161 dev_err(adev->dev, "leaking bo va because "
162 "we fail to reserve bo (%d)\n", r);
163 return;
164 }
Christian Königb5a5ec52016-03-08 17:47:46 +0100165 bo_va = amdgpu_vm_bo_find(vm, bo);
Christian König5a0f3b52017-04-21 10:05:56 +0200166 if (bo_va && --bo_va->ref_count == 0) {
167 amdgpu_vm_bo_rmv(adev, bo_va);
168
Christian König3f3333f2017-08-03 14:02:13 +0200169 if (amdgpu_vm_ready(vm)) {
Christian König5a0f3b52017-04-21 10:05:56 +0200170 struct dma_fence *fence = NULL;
Nicolai Hähnle23e05632017-03-23 19:34:11 +0100171
172 r = amdgpu_vm_clear_freed(adev, vm, &fence);
173 if (unlikely(r)) {
174 dev_err(adev->dev, "failed to clear page "
175 "tables on GEM object close (%d)\n", r);
176 }
177
178 if (fence) {
179 amdgpu_bo_fence(bo, fence, true);
180 dma_fence_put(fence);
181 }
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400182 }
183 }
Christian Königb5a5ec52016-03-08 17:47:46 +0100184 ttm_eu_backoff_reservation(&ticket, &list);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400185}
186
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400187/*
188 * GEM ioctls.
189 */
190int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
191 struct drm_file *filp)
192{
193 struct amdgpu_device *adev = dev->dev_private;
194 union drm_amdgpu_gem_create *args = data;
Christian König6ac7def2017-08-23 20:11:25 +0200195 uint64_t flags = args->in.domain_flags;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400196 uint64_t size = args->in.bo_size;
197 struct drm_gem_object *gobj;
198 uint32_t handle;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400199 int r;
200
Alex Deucher834e0f82017-03-08 17:40:17 -0500201 /* reject invalid gem flags */
Christian König6ac7def2017-08-23 20:11:25 +0200202 if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
203 AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
204 AMDGPU_GEM_CREATE_CPU_GTT_USWC |
205 AMDGPU_GEM_CREATE_VRAM_CLEARED))
Christian Königa022c542017-05-08 15:14:54 +0200206 return -EINVAL;
207
Alex Deucher834e0f82017-03-08 17:40:17 -0500208 /* reject invalid gem domains */
209 if (args->in.domains & ~(AMDGPU_GEM_DOMAIN_CPU |
210 AMDGPU_GEM_DOMAIN_GTT |
211 AMDGPU_GEM_DOMAIN_VRAM |
212 AMDGPU_GEM_DOMAIN_GDS |
213 AMDGPU_GEM_DOMAIN_GWS |
Christian Königa022c542017-05-08 15:14:54 +0200214 AMDGPU_GEM_DOMAIN_OA))
215 return -EINVAL;
Alex Deucher834e0f82017-03-08 17:40:17 -0500216
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400217 /* create a gem object to contain this object in */
218 if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
219 AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
Christian König6ac7def2017-08-23 20:11:25 +0200220 flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400221 if (args->in.domains == AMDGPU_GEM_DOMAIN_GDS)
222 size = size << AMDGPU_GDS_SHIFT;
223 else if (args->in.domains == AMDGPU_GEM_DOMAIN_GWS)
224 size = size << AMDGPU_GWS_SHIFT;
225 else if (args->in.domains == AMDGPU_GEM_DOMAIN_OA)
226 size = size << AMDGPU_OA_SHIFT;
Christian Königa022c542017-05-08 15:14:54 +0200227 else
228 return -EINVAL;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400229 }
230 size = roundup(size, PAGE_SIZE);
231
232 r = amdgpu_gem_object_create(adev, size, args->in.alignment,
233 (u32)(0xffffffff & args->in.domains),
Christian König6ac7def2017-08-23 20:11:25 +0200234 flags, false, &gobj);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400235 if (r)
Christian Königa022c542017-05-08 15:14:54 +0200236 return r;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400237
238 r = drm_gem_handle_create(filp, gobj, &handle);
239 /* drop reference from allocate - handle holds it now */
Cihangir Akturkf62facc2017-08-03 14:58:16 +0300240 drm_gem_object_put_unlocked(gobj);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400241 if (r)
Christian Königa022c542017-05-08 15:14:54 +0200242 return r;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400243
244 memset(args, 0, sizeof(*args));
245 args->out.handle = handle;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400246 return 0;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400247}
248
249int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
250 struct drm_file *filp)
251{
252 struct amdgpu_device *adev = dev->dev_private;
253 struct drm_amdgpu_gem_userptr *args = data;
254 struct drm_gem_object *gobj;
255 struct amdgpu_bo *bo;
256 uint32_t handle;
257 int r;
258
259 if (offset_in_page(args->addr | args->size))
260 return -EINVAL;
261
262 /* reject unknown flag values */
263 if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY |
264 AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE |
265 AMDGPU_GEM_USERPTR_REGISTER))
266 return -EINVAL;
267
Christian König358c2582016-03-11 15:29:27 +0100268 if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) &&
269 !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) {
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400270
Christian König358c2582016-03-11 15:29:27 +0100271 /* if we want to write to it we must install a MMU notifier */
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400272 return -EACCES;
273 }
274
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400275 /* create a gem object to contain this object in */
276 r = amdgpu_gem_object_create(adev, args->size, 0,
277 AMDGPU_GEM_DOMAIN_CPU, 0,
278 0, &gobj);
279 if (r)
Christian Königa022c542017-05-08 15:14:54 +0200280 return r;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400281
282 bo = gem_to_amdgpu_bo(gobj);
Kent Russell6d7d9c52017-08-08 07:58:01 -0400283 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
Christian König1ea863f2015-12-18 22:13:12 +0100284 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400285 r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags);
286 if (r)
287 goto release_object;
288
289 if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) {
290 r = amdgpu_mn_register(bo, args->addr);
291 if (r)
292 goto release_object;
293 }
294
295 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {
296 down_read(&current->mm->mmap_sem);
Christian König2f568db2016-02-23 12:36:59 +0100297
298 r = amdgpu_ttm_tt_get_user_pages(bo->tbo.ttm,
299 bo->tbo.ttm->pages);
300 if (r)
301 goto unlock_mmap_sem;
302
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400303 r = amdgpu_bo_reserve(bo, true);
Christian König2f568db2016-02-23 12:36:59 +0100304 if (r)
305 goto free_pages;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400306
307 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
308 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
309 amdgpu_bo_unreserve(bo);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400310 if (r)
Christian König2f568db2016-02-23 12:36:59 +0100311 goto free_pages;
312
313 up_read(&current->mm->mmap_sem);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400314 }
315
316 r = drm_gem_handle_create(filp, gobj, &handle);
317 /* drop reference from allocate - handle holds it now */
Cihangir Akturkf62facc2017-08-03 14:58:16 +0300318 drm_gem_object_put_unlocked(gobj);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400319 if (r)
Christian Königa022c542017-05-08 15:14:54 +0200320 return r;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400321
322 args->handle = handle;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400323 return 0;
324
Christian König2f568db2016-02-23 12:36:59 +0100325free_pages:
326 release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages, false);
327
328unlock_mmap_sem:
329 up_read(&current->mm->mmap_sem);
330
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400331release_object:
Cihangir Akturkf62facc2017-08-03 14:58:16 +0300332 drm_gem_object_put_unlocked(gobj);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400333
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400334 return r;
335}
336
337int amdgpu_mode_dumb_mmap(struct drm_file *filp,
338 struct drm_device *dev,
339 uint32_t handle, uint64_t *offset_p)
340{
341 struct drm_gem_object *gobj;
342 struct amdgpu_bo *robj;
343
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100344 gobj = drm_gem_object_lookup(filp, handle);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400345 if (gobj == NULL) {
346 return -ENOENT;
347 }
348 robj = gem_to_amdgpu_bo(gobj);
Christian Königcc325d12016-02-08 11:08:35 +0100349 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) ||
Christian König271c8122015-05-13 14:30:53 +0200350 (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
Cihangir Akturkf62facc2017-08-03 14:58:16 +0300351 drm_gem_object_put_unlocked(gobj);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400352 return -EPERM;
353 }
354 *offset_p = amdgpu_bo_mmap_offset(robj);
Cihangir Akturkf62facc2017-08-03 14:58:16 +0300355 drm_gem_object_put_unlocked(gobj);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400356 return 0;
357}
358
359int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
360 struct drm_file *filp)
361{
362 union drm_amdgpu_gem_mmap *args = data;
363 uint32_t handle = args->in.handle;
364 memset(args, 0, sizeof(*args));
365 return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr);
366}
367
368/**
369 * amdgpu_gem_timeout - calculate jiffies timeout from absolute value
370 *
371 * @timeout_ns: timeout in ns
372 *
373 * Calculate the timeout in jiffies from an absolute timeout in ns.
374 */
375unsigned long amdgpu_gem_timeout(uint64_t timeout_ns)
376{
377 unsigned long timeout_jiffies;
378 ktime_t timeout;
379
380 /* clamp timeout if it's to large */
381 if (((int64_t)timeout_ns) < 0)
382 return MAX_SCHEDULE_TIMEOUT;
383
Christian König0f117702015-07-08 16:58:48 +0200384 timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get());
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400385 if (ktime_to_ns(timeout) < 0)
386 return 0;
387
388 timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout));
389 /* clamp timeout to avoid unsigned-> signed overflow */
390 if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT )
391 return MAX_SCHEDULE_TIMEOUT - 1;
392
393 return timeout_jiffies;
394}
395
396int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
397 struct drm_file *filp)
398{
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400399 union drm_amdgpu_gem_wait_idle *args = data;
400 struct drm_gem_object *gobj;
401 struct amdgpu_bo *robj;
402 uint32_t handle = args->in.handle;
403 unsigned long timeout = amdgpu_gem_timeout(args->in.timeout);
404 int r = 0;
405 long ret;
406
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100407 gobj = drm_gem_object_lookup(filp, handle);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400408 if (gobj == NULL) {
409 return -ENOENT;
410 }
411 robj = gem_to_amdgpu_bo(gobj);
Chris Wilson0fea2ed2016-08-29 08:08:24 +0100412 ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true,
413 timeout);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400414
415 /* ret == 0 means not signaled,
416 * ret > 0 means signaled
417 * ret < 0 means interrupted before timeout
418 */
419 if (ret >= 0) {
420 memset(args, 0, sizeof(*args));
421 args->out.status = (ret == 0);
422 } else
423 r = ret;
424
Cihangir Akturkf62facc2017-08-03 14:58:16 +0300425 drm_gem_object_put_unlocked(gobj);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400426 return r;
427}
428
429int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
430 struct drm_file *filp)
431{
432 struct drm_amdgpu_gem_metadata *args = data;
433 struct drm_gem_object *gobj;
434 struct amdgpu_bo *robj;
435 int r = -1;
436
437 DRM_DEBUG("%d \n", args->handle);
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100438 gobj = drm_gem_object_lookup(filp, args->handle);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400439 if (gobj == NULL)
440 return -ENOENT;
441 robj = gem_to_amdgpu_bo(gobj);
442
443 r = amdgpu_bo_reserve(robj, false);
444 if (unlikely(r != 0))
445 goto out;
446
447 if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) {
448 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info);
449 r = amdgpu_bo_get_metadata(robj, args->data.data,
450 sizeof(args->data.data),
451 &args->data.data_size_bytes,
452 &args->data.flags);
453 } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) {
Dan Carpenter0913eab2015-09-23 14:00:35 +0300454 if (args->data.data_size_bytes > sizeof(args->data.data)) {
455 r = -EINVAL;
456 goto unreserve;
457 }
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400458 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info);
459 if (!r)
460 r = amdgpu_bo_set_metadata(robj, args->data.data,
461 args->data.data_size_bytes,
462 args->data.flags);
463 }
464
Dan Carpenter0913eab2015-09-23 14:00:35 +0300465unreserve:
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400466 amdgpu_bo_unreserve(robj);
467out:
Cihangir Akturkf62facc2017-08-03 14:58:16 +0300468 drm_gem_object_put_unlocked(gobj);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400469 return r;
470}
471
472/**
473 * amdgpu_gem_va_update_vm -update the bo_va in its VM
474 *
475 * @adev: amdgpu_device pointer
Christian Königdc54d3d2017-03-13 10:13:38 +0100476 * @vm: vm to update
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400477 * @bo_va: bo_va to update
Christian König2ffdaaf2017-01-27 15:58:43 +0100478 * @list: validation list
Christian Königdc54d3d2017-03-13 10:13:38 +0100479 * @operation: map, unmap or clear
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400480 *
Christian König2ffdaaf2017-01-27 15:58:43 +0100481 * Update the bo_va directly after setting its address. Errors are not
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400482 * vital here, so they are not reported back to userspace.
483 */
484static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
Christian Königdc54d3d2017-03-13 10:13:38 +0100485 struct amdgpu_vm *vm,
Christian Königf7da30d2016-09-28 12:03:04 +0200486 struct amdgpu_bo_va *bo_va,
Christian König2ffdaaf2017-01-27 15:58:43 +0100487 struct list_head *list,
Christian Königf7da30d2016-09-28 12:03:04 +0200488 uint32_t operation)
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400489{
Christian König3f3333f2017-08-03 14:02:13 +0200490 int r;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400491
Christian König3f3333f2017-08-03 14:02:13 +0200492 if (!amdgpu_vm_ready(vm))
493 return;
Chunming Zhoue410b5c2015-12-07 15:02:52 +0800494
Christian König194d2162016-10-12 15:13:52 +0200495 r = amdgpu_vm_update_directories(adev, vm);
Chunming Zhou43c27fb2015-11-12 15:33:09 +0800496 if (r)
Christian König2ffdaaf2017-01-27 15:58:43 +0100497 goto error;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400498
Nicolai Hähnlef3467812017-03-23 19:36:31 +0100499 r = amdgpu_vm_clear_freed(adev, vm, NULL);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400500 if (r)
Christian König2ffdaaf2017-01-27 15:58:43 +0100501 goto error;
monk.liu194a3362015-07-22 13:29:28 +0800502
Christian König80f95c52017-03-13 10:13:39 +0100503 if (operation == AMDGPU_VA_OP_MAP ||
504 operation == AMDGPU_VA_OP_REPLACE)
Flora Cui05dcb5c2016-09-22 11:34:47 +0800505 r = amdgpu_vm_bo_update(adev, bo_va, false);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400506
Christian König2ffdaaf2017-01-27 15:58:43 +0100507error:
Christian König68fdd3d2015-06-16 14:50:02 +0200508 if (r && r != -ERESTARTSYS)
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400509 DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
510}
511
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400512int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
513 struct drm_file *filp)
514{
Junwei Zhangb85891b2017-01-16 13:59:01 +0800515 const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE |
516 AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE |
Alex Xie66e02bc2017-02-14 12:04:52 -0500517 AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK;
Junwei Zhangb85891b2017-01-16 13:59:01 +0800518 const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE |
519 AMDGPU_VM_PAGE_PRT;
520
Christian König34b5f6a2015-06-08 15:03:00 +0200521 struct drm_amdgpu_gem_va *args = data;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400522 struct drm_gem_object *gobj;
523 struct amdgpu_device *adev = dev->dev_private;
524 struct amdgpu_fpriv *fpriv = filp->driver_priv;
Christian König765e7fb2016-09-15 15:06:50 +0200525 struct amdgpu_bo *abo;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400526 struct amdgpu_bo_va *bo_va;
Christian Königb88c8792016-09-28 16:33:01 +0200527 struct amdgpu_bo_list_entry vm_pd;
528 struct ttm_validate_buffer tv;
Chunming Zhou49b02b12015-11-13 14:18:38 +0800529 struct ww_acquire_ctx ticket;
Christian Königd7d29552017-01-30 10:24:13 +0100530 struct list_head list;
Alex Xie54635452017-02-14 12:22:57 -0500531 uint64_t va_flags;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400532 int r = 0;
533
Christian König34b5f6a2015-06-08 15:03:00 +0200534 if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400535 dev_err(&dev->pdev->dev,
536 "va_address 0x%lX is in reserved area 0x%X\n",
Christian König34b5f6a2015-06-08 15:03:00 +0200537 (unsigned long)args->va_address,
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400538 AMDGPU_VA_RESERVED_SIZE);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400539 return -EINVAL;
540 }
541
Junwei Zhangb85891b2017-01-16 13:59:01 +0800542 if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {
543 dev_err(&dev->pdev->dev, "invalid flags combination 0x%08X\n",
544 args->flags);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400545 return -EINVAL;
546 }
547
Christian König34b5f6a2015-06-08 15:03:00 +0200548 switch (args->operation) {
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400549 case AMDGPU_VA_OP_MAP:
550 case AMDGPU_VA_OP_UNMAP:
Christian Königdc54d3d2017-03-13 10:13:38 +0100551 case AMDGPU_VA_OP_CLEAR:
Christian König80f95c52017-03-13 10:13:39 +0100552 case AMDGPU_VA_OP_REPLACE:
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400553 break;
554 default:
555 dev_err(&dev->pdev->dev, "unsupported operation %d\n",
Christian König34b5f6a2015-06-08 15:03:00 +0200556 args->operation);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400557 return -EINVAL;
558 }
Chunming Zhouf1892132017-05-15 16:48:27 +0800559 if ((args->operation == AMDGPU_VA_OP_MAP) ||
560 (args->operation == AMDGPU_VA_OP_REPLACE)) {
561 if (amdgpu_kms_vram_lost(adev, fpriv))
562 return -ENODEV;
563 }
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400564
Chunming Zhou49b02b12015-11-13 14:18:38 +0800565 INIT_LIST_HEAD(&list);
Christian Königdc54d3d2017-03-13 10:13:38 +0100566 if ((args->operation != AMDGPU_VA_OP_CLEAR) &&
567 !(args->flags & AMDGPU_VM_PAGE_PRT)) {
Junwei Zhangb85891b2017-01-16 13:59:01 +0800568 gobj = drm_gem_object_lookup(filp, args->handle);
569 if (gobj == NULL)
570 return -ENOENT;
571 abo = gem_to_amdgpu_bo(gobj);
572 tv.bo = &abo->tbo;
573 tv.shared = false;
574 list_add(&tv.head, &list);
575 } else {
576 gobj = NULL;
577 abo = NULL;
578 }
Chunming Zhou49b02b12015-11-13 14:18:38 +0800579
Christian Königb88c8792016-09-28 16:33:01 +0200580 amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd);
Christian Königb5a5ec52016-03-08 17:47:46 +0100581
Christian Königd7d29552017-01-30 10:24:13 +0100582 r = ttm_eu_reserve_buffers(&ticket, &list, true, NULL);
Junwei Zhangb85891b2017-01-16 13:59:01 +0800583 if (r)
584 goto error_unref;
Christian König34b5f6a2015-06-08 15:03:00 +0200585
Junwei Zhangb85891b2017-01-16 13:59:01 +0800586 if (abo) {
587 bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo);
588 if (!bo_va) {
589 r = -ENOENT;
590 goto error_backoff;
591 }
Christian Königdc54d3d2017-03-13 10:13:38 +0100592 } else if (args->operation != AMDGPU_VA_OP_CLEAR) {
Junwei Zhangb85891b2017-01-16 13:59:01 +0800593 bo_va = fpriv->prt_va;
Christian Königdc54d3d2017-03-13 10:13:38 +0100594 } else {
595 bo_va = NULL;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400596 }
597
Christian König34b5f6a2015-06-08 15:03:00 +0200598 switch (args->operation) {
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400599 case AMDGPU_VA_OP_MAP:
Christian Königec681542017-08-01 10:51:43 +0200600 r = amdgpu_vm_alloc_pts(adev, bo_va->base.vm, args->va_address,
Christian König663e4572017-03-13 10:13:37 +0100601 args->map_size);
602 if (r)
603 goto error_backoff;
Alex Xie54635452017-02-14 12:22:57 -0500604
Christian König663e4572017-03-13 10:13:37 +0100605 va_flags = amdgpu_vm_get_pte_flags(adev, args->flags);
Christian König34b5f6a2015-06-08 15:03:00 +0200606 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address,
607 args->offset_in_bo, args->map_size,
Christian König9f7eb532015-05-18 16:05:57 +0200608 va_flags);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400609 break;
610 case AMDGPU_VA_OP_UNMAP:
Christian König34b5f6a2015-06-08 15:03:00 +0200611 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400612 break;
Christian Königdc54d3d2017-03-13 10:13:38 +0100613
614 case AMDGPU_VA_OP_CLEAR:
615 r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm,
616 args->va_address,
617 args->map_size);
618 break;
Christian König80f95c52017-03-13 10:13:39 +0100619 case AMDGPU_VA_OP_REPLACE:
Christian Königec681542017-08-01 10:51:43 +0200620 r = amdgpu_vm_alloc_pts(adev, bo_va->base.vm, args->va_address,
Christian König80f95c52017-03-13 10:13:39 +0100621 args->map_size);
622 if (r)
623 goto error_backoff;
624
625 va_flags = amdgpu_vm_get_pte_flags(adev, args->flags);
626 r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address,
627 args->offset_in_bo, args->map_size,
628 va_flags);
629 break;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400630 default:
631 break;
632 }
Junwei Zhangb85891b2017-01-16 13:59:01 +0800633 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !amdgpu_vm_debug)
Christian Königdc54d3d2017-03-13 10:13:38 +0100634 amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va, &list,
635 args->operation);
Junwei Zhangb85891b2017-01-16 13:59:01 +0800636
637error_backoff:
Christian König2ffdaaf2017-01-27 15:58:43 +0100638 ttm_eu_backoff_reservation(&ticket, &list);
Chunming Zhoue98c1b02015-11-13 15:22:04 +0800639
Junwei Zhangb85891b2017-01-16 13:59:01 +0800640error_unref:
Cihangir Akturkf62facc2017-08-03 14:58:16 +0300641 drm_gem_object_put_unlocked(gobj);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400642 return r;
643}
644
645int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
646 struct drm_file *filp)
647{
648 struct drm_amdgpu_gem_op *args = data;
649 struct drm_gem_object *gobj;
650 struct amdgpu_bo *robj;
651 int r;
652
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100653 gobj = drm_gem_object_lookup(filp, args->handle);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400654 if (gobj == NULL) {
655 return -ENOENT;
656 }
657 robj = gem_to_amdgpu_bo(gobj);
658
659 r = amdgpu_bo_reserve(robj, false);
660 if (unlikely(r))
661 goto out;
662
663 switch (args->op) {
664 case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: {
665 struct drm_amdgpu_gem_create_in info;
Christian König7ecc2452017-07-26 17:02:52 +0200666 void __user *out = u64_to_user_ptr(args->value);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400667
668 info.bo_size = robj->gem_base.size;
669 info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT;
Kent Russell6d7d9c52017-08-08 07:58:01 -0400670 info.domains = robj->preferred_domains;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400671 info.domain_flags = robj->flags;
Christian König4c28fb02015-08-28 17:27:54 +0200672 amdgpu_bo_unreserve(robj);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400673 if (copy_to_user(out, &info, sizeof(info)))
674 r = -EFAULT;
675 break;
676 }
Marek Olšákd8f65a22015-05-27 14:30:38 +0200677 case AMDGPU_GEM_OP_SET_PLACEMENT:
Christopher James Halse Rogers803d89a2017-04-03 13:31:22 +1000678 if (robj->prime_shared_count && (args->value & AMDGPU_GEM_DOMAIN_VRAM)) {
679 r = -EINVAL;
680 amdgpu_bo_unreserve(robj);
681 break;
682 }
Christian Königcc325d12016-02-08 11:08:35 +0100683 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) {
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400684 r = -EPERM;
Christian König4c28fb02015-08-28 17:27:54 +0200685 amdgpu_bo_unreserve(robj);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400686 break;
687 }
Kent Russell6d7d9c52017-08-08 07:58:01 -0400688 robj->preferred_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM |
Christian König1ea863f2015-12-18 22:13:12 +0100689 AMDGPU_GEM_DOMAIN_GTT |
690 AMDGPU_GEM_DOMAIN_CPU);
Kent Russell6d7d9c52017-08-08 07:58:01 -0400691 robj->allowed_domains = robj->preferred_domains;
Christian König1ea863f2015-12-18 22:13:12 +0100692 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
693 robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
694
Christian König4c28fb02015-08-28 17:27:54 +0200695 amdgpu_bo_unreserve(robj);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400696 break;
697 default:
Christian König4c28fb02015-08-28 17:27:54 +0200698 amdgpu_bo_unreserve(robj);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400699 r = -EINVAL;
700 }
701
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400702out:
Cihangir Akturkf62facc2017-08-03 14:58:16 +0300703 drm_gem_object_put_unlocked(gobj);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400704 return r;
705}
706
707int amdgpu_mode_dumb_create(struct drm_file *file_priv,
708 struct drm_device *dev,
709 struct drm_mode_create_dumb *args)
710{
711 struct amdgpu_device *adev = dev->dev_private;
712 struct drm_gem_object *gobj;
713 uint32_t handle;
714 int r;
715
Laurent Pinchart8e911ab2016-10-18 01:41:17 +0300716 args->pitch = amdgpu_align_pitch(adev, args->width,
717 DIV_ROUND_UP(args->bpp, 8), 0);
Dan Carpenter54ef0b52015-09-23 14:00:59 +0300718 args->size = (u64)args->pitch * args->height;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400719 args->size = ALIGN(args->size, PAGE_SIZE);
720
721 r = amdgpu_gem_object_create(adev, args->size, 0,
722 AMDGPU_GEM_DOMAIN_VRAM,
Alex Deucher857d9132015-08-27 00:14:16 -0400723 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
724 ttm_bo_type_device,
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400725 &gobj);
726 if (r)
727 return -ENOMEM;
728
729 r = drm_gem_handle_create(file_priv, gobj, &handle);
730 /* drop reference from allocate - handle holds it now */
Cihangir Akturkf62facc2017-08-03 14:58:16 +0300731 drm_gem_object_put_unlocked(gobj);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400732 if (r) {
733 return r;
734 }
735 args->handle = handle;
736 return 0;
737}
738
739#if defined(CONFIG_DEBUG_FS)
Christian König7ea23562016-02-15 15:23:00 +0100740static int amdgpu_debugfs_gem_bo_info(int id, void *ptr, void *data)
741{
742 struct drm_gem_object *gobj = ptr;
743 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
744 struct seq_file *m = data;
745
746 unsigned domain;
747 const char *placement;
748 unsigned pin_count;
Christian Königb8e0e6e2017-06-26 15:19:30 +0200749 uint64_t offset;
Christian König7ea23562016-02-15 15:23:00 +0100750
751 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
752 switch (domain) {
753 case AMDGPU_GEM_DOMAIN_VRAM:
754 placement = "VRAM";
755 break;
756 case AMDGPU_GEM_DOMAIN_GTT:
757 placement = " GTT";
758 break;
759 case AMDGPU_GEM_DOMAIN_CPU:
760 default:
761 placement = " CPU";
762 break;
763 }
Christian Königb8e0e6e2017-06-26 15:19:30 +0200764 seq_printf(m, "\t0x%08x: %12ld byte %s",
765 id, amdgpu_bo_size(bo), placement);
766
767 offset = ACCESS_ONCE(bo->tbo.mem.start);
768 if (offset != AMDGPU_BO_INVALID_OFFSET)
769 seq_printf(m, " @ 0x%010Lx", offset);
Christian König7ea23562016-02-15 15:23:00 +0100770
771 pin_count = ACCESS_ONCE(bo->pin_count);
772 if (pin_count)
773 seq_printf(m, " pin count %d", pin_count);
774 seq_printf(m, "\n");
775
776 return 0;
777}
778
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400779static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data)
780{
781 struct drm_info_node *node = (struct drm_info_node *)m->private;
782 struct drm_device *dev = node->minor->dev;
Christian König7ea23562016-02-15 15:23:00 +0100783 struct drm_file *file;
784 int r;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400785
Daniel Vetter1d2ac402016-04-26 19:29:41 +0200786 r = mutex_lock_interruptible(&dev->filelist_mutex);
Christian König7ea23562016-02-15 15:23:00 +0100787 if (r)
788 return r;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400789
Christian König7ea23562016-02-15 15:23:00 +0100790 list_for_each_entry(file, &dev->filelist, lhead) {
791 struct task_struct *task;
Christian Königb22e3ce2016-02-15 12:41:37 +0100792
Christian König7ea23562016-02-15 15:23:00 +0100793 /*
794 * Although we have a valid reference on file->pid, that does
795 * not guarantee that the task_struct who called get_pid() is
796 * still alive (e.g. get_pid(current) => fork() => exit()).
797 * Therefore, we need to protect this ->comm access using RCU.
798 */
799 rcu_read_lock();
800 task = pid_task(file->pid, PIDTYPE_PID);
801 seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid),
802 task ? task->comm : "<unknown>");
803 rcu_read_unlock();
804
805 spin_lock(&file->table_lock);
806 idr_for_each(&file->object_idr, amdgpu_debugfs_gem_bo_info, m);
807 spin_unlock(&file->table_lock);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400808 }
Christian König7ea23562016-02-15 15:23:00 +0100809
Daniel Vetter1d2ac402016-04-26 19:29:41 +0200810 mutex_unlock(&dev->filelist_mutex);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400811 return 0;
812}
813
Nils Wallménius06ab6832016-05-02 12:46:15 -0400814static const struct drm_info_list amdgpu_debugfs_gem_list[] = {
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400815 {"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL},
816};
817#endif
818
819int amdgpu_gem_debugfs_init(struct amdgpu_device *adev)
820{
821#if defined(CONFIG_DEBUG_FS)
822 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1);
823#endif
824 return 0;
825}