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Kumar Gala10b35d92005-09-23 14:08:58 -05001#ifndef __ASM_POWERPC_CPUTABLE_H
2#define __ASM_POWERPC_CPUTABLE_H
3
Adrian Bunkd1cdcf22008-06-24 03:48:21 +10004
5#include <asm/asm-compat.h>
Michael Ellermanc5157e52008-06-24 11:32:39 +10006#include <asm/feature-fixups.h>
David Howellsc3617f72012-10-09 09:47:26 +01007#include <uapi/asm/cputable.h>
Adrian Bunkd1cdcf22008-06-24 03:48:21 +10008
Kumar Gala10b35d92005-09-23 14:08:58 -05009#ifndef __ASSEMBLY__
10
11/* This structure can grow, it's real size is used by head.S code
12 * via the mkdefs mechanism.
13 */
14struct cpu_spec;
Kumar Gala10b35d92005-09-23 14:08:58 -050015
Kumar Gala10b35d92005-09-23 14:08:58 -050016typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
Olof Johanssonf39b7a52006-08-11 00:07:08 -050017typedef void (*cpu_restore_t)(void);
Kumar Gala10b35d92005-09-23 14:08:58 -050018
Anton Blanchard32a33992006-01-09 15:41:31 +110019enum powerpc_oprofile_type {
Andy Whitcroft7a45fb12006-01-13 12:35:49 +000020 PPC_OPROFILE_INVALID = 0,
21 PPC_OPROFILE_RS64 = 1,
22 PPC_OPROFILE_POWER4 = 2,
23 PPC_OPROFILE_G4 = 3,
Andy Fleming39aef682008-02-04 18:27:55 -060024 PPC_OPROFILE_FSL_EMB = 4,
Maynard Johnson18f21902006-11-20 18:45:16 +010025 PPC_OPROFILE_CELL = 5,
Olof Johansson25fc5302007-04-18 16:38:21 +100026 PPC_OPROFILE_PA6T = 6,
Anton Blanchard32a33992006-01-09 15:41:31 +110027};
28
Olof Johansson1bd2e5a2007-01-28 21:23:54 -060029enum powerpc_pmc_type {
30 PPC_PMC_DEFAULT = 0,
31 PPC_PMC_IBM = 1,
32 PPC_PMC_PA6T = 2,
Benjamin Herrenschmidtb950bdd2008-08-18 14:23:51 +100033 PPC_PMC_G4 = 3,
Olof Johansson1bd2e5a2007-01-28 21:23:54 -060034};
35
Benjamin Herrenschmidt47c0bd12007-12-21 15:39:21 +110036struct pt_regs;
37
38extern int machine_check_generic(struct pt_regs *regs);
39extern int machine_check_4xx(struct pt_regs *regs);
40extern int machine_check_440A(struct pt_regs *regs);
Scott Woodfe04b112010-04-08 00:38:22 -050041extern int machine_check_e500mc(struct pt_regs *regs);
Benjamin Herrenschmidt47c0bd12007-12-21 15:39:21 +110042extern int machine_check_e500(struct pt_regs *regs);
43extern int machine_check_e200(struct pt_regs *regs);
Dave Kleikampfc5e7092010-03-05 03:43:18 +000044extern int machine_check_47x(struct pt_regs *regs);
Benjamin Herrenschmidt47c0bd12007-12-21 15:39:21 +110045
Paul Mackerras87a72f92007-10-04 14:18:01 +100046/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
Kumar Gala10b35d92005-09-23 14:08:58 -050047struct cpu_spec {
48 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
49 unsigned int pvr_mask;
50 unsigned int pvr_value;
51
52 char *cpu_name;
53 unsigned long cpu_features; /* Kernel features */
54 unsigned int cpu_user_features; /* Userland features */
Michael Neuling21713642013-04-17 17:33:11 +000055 unsigned int cpu_user_features2; /* Userland features v2 */
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +000056 unsigned int mmu_features; /* MMU features */
Kumar Gala10b35d92005-09-23 14:08:58 -050057
58 /* cache line sizes */
59 unsigned int icache_bsize;
60 unsigned int dcache_bsize;
61
62 /* number of performance monitor counters */
63 unsigned int num_pmcs;
Olof Johansson1bd2e5a2007-01-28 21:23:54 -060064 enum powerpc_pmc_type pmc_type;
Kumar Gala10b35d92005-09-23 14:08:58 -050065
66 /* this is called to initialize various CPU bits like L1 cache,
67 * BHT, SPD, etc... from head.S before branching to identify_machine
68 */
69 cpu_setup_t cpu_setup;
Olof Johanssonf39b7a52006-08-11 00:07:08 -050070 /* Used to restore cpu setup on secondary processors and at resume */
71 cpu_restore_t cpu_restore;
Kumar Gala10b35d92005-09-23 14:08:58 -050072
73 /* Used by oprofile userspace to select the right counters */
74 char *oprofile_cpu_type;
75
76 /* Processor specific oprofile operations */
Anton Blanchard32a33992006-01-09 15:41:31 +110077 enum powerpc_oprofile_type oprofile_type;
Paul Mackerras80f15dc2006-01-14 10:11:39 +110078
Michael Neulinge78dbc82006-06-08 14:42:34 +100079 /* Bit locations inside the mmcra change */
80 unsigned long oprofile_mmcra_sihv;
81 unsigned long oprofile_mmcra_sipr;
82
83 /* Bits to clear during an oprofile exception */
84 unsigned long oprofile_mmcra_clear;
85
Paul Mackerras80f15dc2006-01-14 10:11:39 +110086 /* Name of processor class, for the ELF AT_PLATFORM entry */
87 char *platform;
Benjamin Herrenschmidt47c0bd12007-12-21 15:39:21 +110088
89 /* Processor specific machine check handling. Return negative
90 * if the error is fatal, 1 if it was fully recovered and 0 to
91 * pass up (not CPU originated) */
92 int (*machine_check)(struct pt_regs *regs);
Kumar Gala10b35d92005-09-23 14:08:58 -050093};
94
Kumar Gala10b35d92005-09-23 14:08:58 -050095extern struct cpu_spec *cur_cpu_spec;
Kumar Gala10b35d92005-09-23 14:08:58 -050096
Benjamin Herrenschmidt42c4aaa2006-10-24 16:42:40 +100097extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
98
Paul Mackerras974a76f2006-11-10 20:38:53 +110099extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
Benjamin Herrenschmidt0909c8c2006-10-20 11:47:18 +1000100extern void do_feature_fixups(unsigned long value, void *fixup_start,
101 void *fixup_end);
Paul Mackerras9b6b5632005-10-06 12:06:20 +1000102
Nathan Lynch9115d132008-07-16 09:58:51 +1000103extern const char *powerpc_base_platform;
104
Kumar Gala10b35d92005-09-23 14:08:58 -0500105#endif /* __ASSEMBLY__ */
106
107/* CPU kernel features */
108
109/* Retain the 32b definitions all use bottom half of word */
Michael Neulingcde4d492012-12-20 14:06:39 +0000110#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x00000001)
111#define CPU_FTR_L2CR ASM_CONST(0x00000002)
112#define CPU_FTR_SPEC7450 ASM_CONST(0x00000004)
113#define CPU_FTR_ALTIVEC ASM_CONST(0x00000008)
114#define CPU_FTR_TAU ASM_CONST(0x00000010)
115#define CPU_FTR_CAN_DOZE ASM_CONST(0x00000020)
116#define CPU_FTR_USE_TB ASM_CONST(0x00000040)
117#define CPU_FTR_L2CSR ASM_CONST(0x00000080)
118#define CPU_FTR_601 ASM_CONST(0x00000100)
119#define CPU_FTR_DBELL ASM_CONST(0x00000200)
120#define CPU_FTR_CAN_NAP ASM_CONST(0x00000400)
121#define CPU_FTR_L3CR ASM_CONST(0x00000800)
122#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x00001000)
123#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x00002000)
124#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x00004000)
125#define CPU_FTR_NO_DPM ASM_CONST(0x00008000)
126#define CPU_FTR_476_DD2 ASM_CONST(0x00010000)
127#define CPU_FTR_NEED_COHERENT ASM_CONST(0x00020000)
128#define CPU_FTR_NO_BTIC ASM_CONST(0x00040000)
129#define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x00080000)
130#define CPU_FTR_NODSISRALIGN ASM_CONST(0x00100000)
131#define CPU_FTR_PPC_LE ASM_CONST(0x00200000)
132#define CPU_FTR_REAL_LE ASM_CONST(0x00400000)
133#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x00800000)
134#define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x01000000)
135#define CPU_FTR_SPE ASM_CONST(0x02000000)
136#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x04000000)
137#define CPU_FTR_LWSYNC ASM_CONST(0x08000000)
138#define CPU_FTR_NOEXECUTE ASM_CONST(0x10000000)
139#define CPU_FTR_INDEXED_DCR ASM_CONST(0x20000000)
140#define CPU_FTR_EMB_HV ASM_CONST(0x40000000)
Kumar Gala10b35d92005-09-23 14:08:58 -0500141
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000142/*
143 * Add the 64-bit processor unique features in the top half of the word;
144 * on 32-bit, make the names available but defined to be 0.
145 */
Kumar Gala10b35d92005-09-23 14:08:58 -0500146#ifdef __powerpc64__
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000147#define LONG_ASM_CONST(x) ASM_CONST(x)
Kumar Gala10b35d92005-09-23 14:08:58 -0500148#else
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000149#define LONG_ASM_CONST(x) 0
Kumar Gala10b35d92005-09-23 14:08:58 -0500150#endif
151
Michael Neuling1580b3b2012-12-20 14:06:40 +0000152#define CPU_FTR_HVMODE LONG_ASM_CONST(0x0000000100000000)
153#define CPU_FTR_ARCH_201 LONG_ASM_CONST(0x0000000200000000)
154#define CPU_FTR_ARCH_206 LONG_ASM_CONST(0x0000000400000000)
Michael Ellerman1de2bd42013-04-30 20:17:02 +0000155#define CPU_FTR_ARCH_207S LONG_ASM_CONST(0x0000000800000000)
Michael Neuling1580b3b2012-12-20 14:06:40 +0000156#define CPU_FTR_IABR LONG_ASM_CONST(0x0000001000000000)
157#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000002000000000)
158#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000004000000000)
159#define CPU_FTR_SMT LONG_ASM_CONST(0x0000008000000000)
160#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000010000000000)
161#define CPU_FTR_PURR LONG_ASM_CONST(0x0000020000000000)
162#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000040000000000)
163#define CPU_FTR_SPURR LONG_ASM_CONST(0x0000080000000000)
164#define CPU_FTR_DSCR LONG_ASM_CONST(0x0000100000000000)
165#define CPU_FTR_VSX LONG_ASM_CONST(0x0000200000000000)
166#define CPU_FTR_SAO LONG_ASM_CONST(0x0000400000000000)
167#define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0000800000000000)
168#define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0001000000000000)
169#define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0002000000000000)
170#define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0004000000000000)
171#define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0008000000000000)
172#define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0010000000000000)
173#define CPU_FTR_ICSWX LONG_ASM_CONST(0x0020000000000000)
174#define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x0040000000000000)
175#define CPU_FTR_TM LONG_ASM_CONST(0x0080000000000000)
Michael Ellerman1de2bd42013-04-30 20:17:02 +0000176#define CPU_FTR_CFAR LONG_ASM_CONST(0x0100000000000000)
Michael Neuling1580b3b2012-12-20 14:06:40 +0000177#define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0200000000000000)
Michael Neuling79879c12012-12-20 14:06:42 +0000178#define CPU_FTR_DAWR LONG_ASM_CONST(0x0400000000000000)
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000179
Kumar Gala10b35d92005-09-23 14:08:58 -0500180#ifndef __ASSEMBLY__
181
Matt Evans44ae3ab2011-04-06 19:48:50 +0000182#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
183
184#define MMU_FTR_PPCAS_ARCH_V2 (MMU_FTR_SLB | MMU_FTR_TLBIEL | \
185 MMU_FTR_16M_PAGE)
Kumar Gala10b35d92005-09-23 14:08:58 -0500186
187/* We only set the altivec features if the kernel was compiled with altivec
188 * support
189 */
190#ifdef CONFIG_ALTIVEC
191#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
192#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
193#else
194#define CPU_FTR_ALTIVEC_COMP 0
195#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
196#endif
197
Michael Neulingb962ce92008-06-25 14:07:18 +1000198/* We only set the VSX features if the kernel was compiled with VSX
199 * support
200 */
201#ifdef CONFIG_VSX
202#define CPU_FTR_VSX_COMP CPU_FTR_VSX
203#define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
204#else
205#define CPU_FTR_VSX_COMP 0
206#define PPC_FEATURE_HAS_VSX_COMP 0
207#endif
208
Kumar Gala5e14d212007-09-13 01:44:20 -0500209/* We only set the spe features if the kernel was compiled with spe
210 * support
211 */
212#ifdef CONFIG_SPE
213#define CPU_FTR_SPE_COMP CPU_FTR_SPE
214#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
215#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
216#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
217#else
218#define CPU_FTR_SPE_COMP 0
219#define PPC_FEATURE_HAS_SPE_COMP 0
220#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
221#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
222#endif
223
Michael Neuling6a6d5412013-02-13 16:21:29 +0000224/* We only set the TM feature if the kernel was compiled with TM supprt */
225#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
226#define CPU_FTR_TM_COMP CPU_FTR_TM
Nishanth Aravamudancbbc6f12013-05-03 14:47:56 +0000227#define PPC_FEATURE2_HTM_COMP PPC_FEATURE2_HTM
Michael Neuling6a6d5412013-02-13 16:21:29 +0000228#else
229#define CPU_FTR_TM_COMP 0
Nishanth Aravamudancbbc6f12013-05-03 14:47:56 +0000230#define PPC_FEATURE2_HTM_COMP 0
Michael Neuling6a6d5412013-02-13 16:21:29 +0000231#endif
232
Scott Wood11af1192007-09-14 15:32:14 -0500233/* We need to mark all pages as being coherent if we're SMP or we have a
234 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
235 * require it for PCI "streaming/prefetch" to work properly.
Piotr Ziecikc9310922009-03-17 09:17:50 -0600236 * This is also required by 52xx family.
Kumar Gala10b35d92005-09-23 14:08:58 -0500237 */
Kumar Gala1775dbb2006-02-22 09:46:02 -0600238#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
Piotr Ziecikc9310922009-03-17 09:17:50 -0600239 || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \
240 || defined(CONFIG_PPC_MPC52xx)
Kumar Gala10b35d92005-09-23 14:08:58 -0500241#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
242#else
243#define CPU_FTR_COMMON 0
244#endif
245
246/* The powersave features NAP & DOZE seems to confuse BDI when
247 debugging. So if a BDI is used, disable theses
248 */
249#ifndef CONFIG_BDI_SWITCH
250#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
251#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
252#else
253#define CPU_FTR_MAYBE_CAN_DOZE 0
254#define CPU_FTR_MAYBE_CAN_NAP 0
255#endif
256
257#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
258 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
259 !defined(CONFIG_BOOKE))
260
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000261#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | \
David Gibson4508dc22007-06-13 14:52:57 +1000262 CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
263#define CPU_FTRS_603 (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100264 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000265 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
David Gibson4508dc22007-06-13 14:52:57 +1000266#define CPU_FTRS_604 (CPU_FTR_COMMON | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000267 CPU_FTR_USE_TB | CPU_FTR_PPC_LE)
David Gibson4508dc22007-06-13 14:52:57 +1000268#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100269 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000270 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
David Gibson4508dc22007-06-13 14:52:57 +1000271#define CPU_FTRS_740 (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100272 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000273 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000274 CPU_FTR_PPC_LE)
David Gibson4508dc22007-06-13 14:52:57 +1000275#define CPU_FTRS_750 (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100276 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000277 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000278 CPU_FTR_PPC_LE)
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000279#define CPU_FTRS_750CL (CPU_FTRS_750)
Josh Boyerb6f41cc2007-07-03 02:06:53 +1000280#define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
281#define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000282#define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX)
Josh Boyerb6f41cc2007-07-03 02:06:53 +1000283#define CPU_FTRS_750GX (CPU_FTRS_750FX)
David Gibson4508dc22007-06-13 14:52:57 +1000284#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100285 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000286 CPU_FTR_ALTIVEC_COMP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000287 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
David Gibson4508dc22007-06-13 14:52:57 +1000288#define CPU_FTRS_7400 (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100289 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000290 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000291 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
David Gibson4508dc22007-06-13 14:52:57 +1000292#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100293 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000294 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
Becky Bruceb64f87c2007-11-10 09:17:49 +1100295 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
David Gibson4508dc22007-06-13 14:52:57 +1000296#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100297 CPU_FTR_USE_TB | \
298 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000299 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100300 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
Becky Bruceb64f87c2007-11-10 09:17:49 +1100301 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
David Gibson4508dc22007-06-13 14:52:57 +1000302#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \
Becky Bruceb64f87c2007-11-10 09:17:49 +1100303 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100304 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000305 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000306 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
David Gibson4508dc22007-06-13 14:52:57 +1000307#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
Becky Bruceb64f87c2007-11-10 09:17:49 +1100308 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100309 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000310 CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
David Gibson4508dc22007-06-13 14:52:57 +1000311#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \
Becky Bruceb64f87c2007-11-10 09:17:49 +1100312 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100313 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000314 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100315 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000316 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
David Gibson4508dc22007-06-13 14:52:57 +1000317#define CPU_FTRS_7455 (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100318 CPU_FTR_USE_TB | \
319 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000320 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
Becky Bruceb64f87c2007-11-10 09:17:49 +1100321 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
David Gibson4508dc22007-06-13 14:52:57 +1000322#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100323 CPU_FTR_USE_TB | \
324 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000325 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
Becky Bruceb64f87c2007-11-10 09:17:49 +1100326 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
327 CPU_FTR_NEED_PAIRED_STWCX)
David Gibson4508dc22007-06-13 14:52:57 +1000328#define CPU_FTRS_7447 (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100329 CPU_FTR_USE_TB | \
330 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000331 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
Becky Bruceb64f87c2007-11-10 09:17:49 +1100332 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
David Gibson4508dc22007-06-13 14:52:57 +1000333#define CPU_FTRS_7447A (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100334 CPU_FTR_USE_TB | \
335 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000336 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
Becky Bruceb64f87c2007-11-10 09:17:49 +1100337 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
David Gibson4508dc22007-06-13 14:52:57 +1000338#define CPU_FTRS_7448 (CPU_FTR_COMMON | \
James.Yang3d372542007-05-02 16:34:43 -0500339 CPU_FTR_USE_TB | \
340 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000341 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
Becky Bruceb64f87c2007-11-10 09:17:49 +1100342 CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
David Gibson4508dc22007-06-13 14:52:57 +1000343#define CPU_FTRS_82XX (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100344 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
Scott Wood11af1192007-09-14 15:32:14 -0500345#define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000346 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP)
David Gibson4508dc22007-06-13 14:52:57 +1000347#define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000348 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100349 CPU_FTR_COMMON)
David Gibson4508dc22007-06-13 14:52:57 +1000350#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000351 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
Kim Phillipsaa42c692006-12-08 02:43:30 -0600352 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000353#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_USE_TB)
David Gibson4508dc22007-06-13 14:52:57 +1000354#define CPU_FTRS_8XX (CPU_FTR_USE_TB)
Benjamin Herrenschmidt8309ce722008-12-12 17:33:25 +1100355#define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
356#define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
Benjamin Herrenschmidt6d2170b2008-12-18 19:13:22 +0000357#define CPU_FTRS_440x6 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \
358 CPU_FTR_INDEXED_DCR)
Dave Kleikampe7f75ad2010-03-05 10:43:12 +0000359#define CPU_FTRS_47X (CPU_FTRS_440x6)
Kumar Gala5e14d212007-09-13 01:44:20 -0500360#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
361 CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
Scott Wood52b066f2011-12-20 15:34:12 +0000362 CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE | \
363 CPU_FTR_DEBUG_LVL_EXC)
Kumar Galafc4033b2008-06-18 16:26:52 -0500364#define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
Benjamin Herrenschmidt8309ce722008-12-12 17:33:25 +1100365 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
366 CPU_FTR_NOEXECUTE)
Kumar Galafc4033b2008-06-18 16:26:52 -0500367#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000368 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
Benjamin Herrenschmidt8309ce722008-12-12 17:33:25 +1100369 CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
Scott Woodd51ad912010-05-27 17:35:12 -0500370#define CPU_FTRS_E500MC (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
Kumar Gala620165f2009-02-12 13:54:53 +0000371 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
Scott Wood73196cd32011-12-20 15:34:47 +0000372 CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
Kumar Gala11ed0db2011-04-06 00:11:06 -0500373#define CPU_FTRS_E5500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
374 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
Kumar Galad36b4c42011-04-06 00:18:48 -0500375 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
Scott Wood73196cd32011-12-20 15:34:47 +0000376 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
Kumar Gala10241842011-11-06 11:51:07 -0600377#define CPU_FTRS_E6500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
378 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
379 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
Kumar Galacd66cc22012-09-07 15:57:17 -0500380 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100381#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
Michael Ellerman0b8e2e12006-11-23 00:46:46 +0100382
383/* 64-bit CPUs */
Anton Blanchard5a0e9b52010-02-10 01:10:25 +0000384#define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000385 CPU_FTR_IABR | CPU_FTR_PPC_LE)
Anton Blanchard5a0e9b52010-02-10 01:10:25 +0000386#define CPU_FTRS_RS64 (CPU_FTR_USE_TB | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000387 CPU_FTR_IABR | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100388 CPU_FTR_MMCRA | CPU_FTR_CTRL)
Kumar Gala2d1b2022008-07-02 01:16:40 +1000389#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000390 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
Anton Blanchardf89451f2010-08-11 01:40:27 +0000391 CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ | \
392 CPU_FTR_STCX_CHECKS_ADDRESS)
Kumar Gala2d1b2022008-07-02 01:16:40 +1000393#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
Paul Mackerras969391c2011-06-29 00:26:11 +0000394 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_201 | \
Mark Nelson2a929432008-08-22 14:36:19 +1000395 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
Paul Mackerras969391c2011-06-29 00:26:11 +0000396 CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \
397 CPU_FTR_HVMODE)
Kumar Gala2d1b2022008-07-02 01:16:40 +1000398#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000399 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100400 CPU_FTR_MMCRA | CPU_FTR_SMT | \
Matt Evans44ae3ab2011-04-06 19:48:50 +0000401 CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
402 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB)
Kumar Gala2d1b2022008-07-02 01:16:40 +1000403#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000404 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
Anton Blanchard03054d52006-04-29 09:51:06 +1000405 CPU_FTR_MMCRA | CPU_FTR_SMT | \
Matt Evans44ae3ab2011-04-06 19:48:50 +0000406 CPU_FTR_COHERENT_ICACHE | \
Anton Blanchard4c1985572006-12-08 17:46:58 +1100407 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
Anton Blanchardf89451f2010-08-11 01:40:27 +0000408 CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
Paul Mackerras48404f22011-05-01 19:48:20 +0000409 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR)
Kumar Gala2d1b2022008-07-02 01:16:40 +1000410#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
Paul Mackerras969391c2011-06-29 00:26:11 +0000411 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
Michael Neulinge952e6c2008-06-18 10:47:26 +1000412 CPU_FTR_MMCRA | CPU_FTR_SMT | \
Matt Evans44ae3ab2011-04-06 19:48:50 +0000413 CPU_FTR_COHERENT_ICACHE | \
Michael Neulinge952e6c2008-06-18 10:47:26 +1000414 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
Anton Blanchardf89451f2010-08-11 01:40:27 +0000415 CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \
Tseng-Hui (Frank) Lin851d2e22011-05-02 20:43:04 +0000416 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
Haren Mynenid26138682012-12-06 21:47:42 +0000417 CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | \
418 CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR)
Michael Neuling71e18492012-10-30 19:34:15 +0000419#define CPU_FTRS_POWER8 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
420 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
421 CPU_FTR_MMCRA | CPU_FTR_SMT | \
422 CPU_FTR_COHERENT_ICACHE | \
423 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
424 CPU_FTR_DSCR | CPU_FTR_SAO | \
425 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
Ian Munsiee5e84f02012-11-14 18:49:50 +0000426 CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
Michael Ellerman1de2bd42013-04-30 20:17:02 +0000427 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \
428 CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP)
Kumar Gala2d1b2022008-07-02 01:16:40 +1000429#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000430 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100431 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
Matt Evans44ae3ab2011-04-06 19:48:50 +0000432 CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
Mark Nelson4ec577a2008-10-27 00:43:02 +0000433 CPU_FTR_UNALIGNED_LD_STD)
Kumar Gala2d1b2022008-07-02 01:16:40 +1000434#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
Matt Evans44ae3ab2011-04-06 19:48:50 +0000435 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
436 CPU_FTR_PURR | CPU_FTR_REAL_LE)
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000437#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
Kumar Gala10b35d92005-09-23 14:08:58 -0500438
Benjamin Herrenschmidt76b4eda2011-04-14 22:32:01 +0000439#define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \
Jimi Xenidisfac26ad2011-09-29 10:55:13 +0000440 CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN | CPU_FTR_ICSWX)
Benjamin Herrenschmidt76b4eda2011-04-14 22:32:01 +0000441
Anton Blanchard2406f602005-12-13 07:45:33 +1100442#ifdef __powerpc64__
Kumar Gala11ed0db2011-04-06 00:11:06 -0500443#ifdef CONFIG_PPC_BOOK3E
Kumar Gala10241842011-11-06 11:51:07 -0600444#define CPU_FTRS_POSSIBLE (CPU_FTRS_E6500 | CPU_FTRS_E5500 | CPU_FTRS_A2)
Kumar Gala11ed0db2011-04-06 00:11:06 -0500445#else
Stephen Rothwell7c929432006-03-23 17:36:59 +1100446#define CPU_FTRS_POSSIBLE \
447 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \
Anton Blanchard03054d52006-04-29 09:51:06 +1000448 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \
Michael Neuling71e18492012-10-30 19:34:15 +0000449 CPU_FTRS_POWER7 | CPU_FTRS_POWER8 | CPU_FTRS_CELL | \
450 CPU_FTRS_PA6T | CPU_FTR_VSX)
Kumar Gala11ed0db2011-04-06 00:11:06 -0500451#endif
Anton Blanchard2406f602005-12-13 07:45:33 +1100452#else
Stephen Rothwell7c929432006-03-23 17:36:59 +1100453enum {
454 CPU_FTRS_POSSIBLE =
Kumar Gala10b35d92005-09-23 14:08:58 -0500455#if CLASSIC_PPC
456 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
457 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
458 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
459 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
460 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
461 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
462 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
Kim Phillipsaa42c692006-12-08 02:43:30 -0600463 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
464 CPU_FTRS_CLASSIC32 |
Kumar Gala10b35d92005-09-23 14:08:58 -0500465#else
466 CPU_FTRS_GENERIC_32 |
467#endif
Kumar Gala10b35d92005-09-23 14:08:58 -0500468#ifdef CONFIG_8xx
469 CPU_FTRS_8XX |
470#endif
471#ifdef CONFIG_40x
472 CPU_FTRS_40X |
473#endif
474#ifdef CONFIG_44x
Benjamin Herrenschmidt6d2170b2008-12-18 19:13:22 +0000475 CPU_FTRS_44X | CPU_FTRS_440x6 |
Kumar Gala10b35d92005-09-23 14:08:58 -0500476#endif
Dave Kleikampe7f75ad2010-03-05 10:43:12 +0000477#ifdef CONFIG_PPC_47x
Dave Kleikampc48d0db2011-01-26 06:17:58 +0000478 CPU_FTRS_47X | CPU_FTR_476_DD2 |
Dave Kleikampe7f75ad2010-03-05 10:43:12 +0000479#endif
Kumar Gala10b35d92005-09-23 14:08:58 -0500480#ifdef CONFIG_E200
481 CPU_FTRS_E200 |
482#endif
483#ifdef CONFIG_E500
Scott Wood06aae862011-12-20 15:34:14 +0000484 CPU_FTRS_E500 | CPU_FTRS_E500_2 |
485#endif
486#ifdef CONFIG_PPC_E500MC
487 CPU_FTRS_E500MC | CPU_FTRS_E5500 | CPU_FTRS_E6500 |
Kumar Gala10b35d92005-09-23 14:08:58 -0500488#endif
Kumar Gala10b35d92005-09-23 14:08:58 -0500489 0,
Stephen Rothwell7c929432006-03-23 17:36:59 +1100490};
491#endif /* __powerpc64__ */
Kumar Gala10b35d92005-09-23 14:08:58 -0500492
Anton Blanchard2406f602005-12-13 07:45:33 +1100493#ifdef __powerpc64__
Kumar Gala11ed0db2011-04-06 00:11:06 -0500494#ifdef CONFIG_PPC_BOOK3E
Kumar Gala10241842011-11-06 11:51:07 -0600495#define CPU_FTRS_ALWAYS (CPU_FTRS_E6500 & CPU_FTRS_E5500 & CPU_FTRS_A2)
Kumar Gala11ed0db2011-04-06 00:11:06 -0500496#else
Stephen Rothwell7c929432006-03-23 17:36:59 +1100497#define CPU_FTRS_ALWAYS \
498 (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \
Anton Blanchard03054d52006-04-29 09:51:06 +1000499 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \
Michael Neulinge952e6c2008-06-18 10:47:26 +1000500 CPU_FTRS_POWER7 & CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
Kumar Gala11ed0db2011-04-06 00:11:06 -0500501#endif
Anton Blanchard2406f602005-12-13 07:45:33 +1100502#else
Stephen Rothwell7c929432006-03-23 17:36:59 +1100503enum {
504 CPU_FTRS_ALWAYS =
Kumar Gala10b35d92005-09-23 14:08:58 -0500505#if CLASSIC_PPC
506 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
507 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
508 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
509 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
510 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
511 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
512 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
Kim Phillipsaa42c692006-12-08 02:43:30 -0600513 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
514 CPU_FTRS_CLASSIC32 &
Kumar Gala10b35d92005-09-23 14:08:58 -0500515#else
516 CPU_FTRS_GENERIC_32 &
517#endif
Kumar Gala10b35d92005-09-23 14:08:58 -0500518#ifdef CONFIG_8xx
519 CPU_FTRS_8XX &
520#endif
521#ifdef CONFIG_40x
522 CPU_FTRS_40X &
523#endif
524#ifdef CONFIG_44x
Benjamin Herrenschmidt6d2170b2008-12-18 19:13:22 +0000525 CPU_FTRS_44X & CPU_FTRS_440x6 &
Kumar Gala10b35d92005-09-23 14:08:58 -0500526#endif
527#ifdef CONFIG_E200
528 CPU_FTRS_E200 &
529#endif
530#ifdef CONFIG_E500
Scott Wood06aae862011-12-20 15:34:14 +0000531 CPU_FTRS_E500 & CPU_FTRS_E500_2 &
532#endif
533#ifdef CONFIG_PPC_E500MC
534 CPU_FTRS_E500MC & CPU_FTRS_E5500 & CPU_FTRS_E6500 &
Kumar Gala10b35d92005-09-23 14:08:58 -0500535#endif
Scott Wood73196cd32011-12-20 15:34:47 +0000536 ~CPU_FTR_EMB_HV & /* can be removed at runtime */
Kumar Gala10b35d92005-09-23 14:08:58 -0500537 CPU_FTRS_POSSIBLE,
538};
Stephen Rothwell7c929432006-03-23 17:36:59 +1100539#endif /* __powerpc64__ */
Kumar Gala10b35d92005-09-23 14:08:58 -0500540
541static inline int cpu_has_feature(unsigned long feature)
542{
543 return (CPU_FTRS_ALWAYS & feature) ||
544 (CPU_FTRS_POSSIBLE
Kumar Gala10b35d92005-09-23 14:08:58 -0500545 & cur_cpu_spec->cpu_features
Kumar Gala10b35d92005-09-23 14:08:58 -0500546 & feature);
547}
548
K.Prasad5aae8a52010-06-15 11:35:19 +0530549#define HBP_NUM 1
K.Prasad5aae8a52010-06-15 11:35:19 +0530550
Kumar Gala10b35d92005-09-23 14:08:58 -0500551#endif /* !__ASSEMBLY__ */
552
Kumar Gala10b35d92005-09-23 14:08:58 -0500553#endif /* __ASM_POWERPC_CPUTABLE_H */