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gerrit-public.fairphone.software / kernel / msm-5.4 / cd66cc2ee52bca82f1b06e2fbc1ce63f33700190 / . / arch / powerpc / include / asm / cputable.h
blob: f3264445d09fd73c8c8cea9c4938b1ec92905e5c [file] [log] [blame]
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]1#ifndef __ASM_POWERPC_CPUTABLE_H
2#define __ASM_POWERPC_CPUTABLE_H
3
Adrian Bunkd1cdcf22008-06-24 03:48:21 +1000[diff] [blame]4
5#include <asm/asm-compat.h>
Michael Ellermanc5157e52008-06-24 11:32:39 +1000[diff] [blame]6#include <asm/feature-fixups.h>
David Howellsc3617f72012-10-09 09:47:26 +0100[diff] [blame]7#include <uapi/asm/cputable.h>
Adrian Bunkd1cdcf22008-06-24 03:48:21 +1000[diff] [blame]8
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]9#ifndef __ASSEMBLY__
10
11/* This structure can grow, it's real size is used by head.S code
12 * via the mkdefs mechanism.
13 */
14struct cpu_spec;
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]15
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]16typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
Olof Johanssonf39b7a52006-08-11 00:07:08 -0500[diff] [blame]17typedef void (*cpu_restore_t)(void);
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]18
Anton Blanchard32a33992006-01-09 15:41:31 +1100[diff] [blame]19enum powerpc_oprofile_type {
Andy Whitcroft7a45fb12006-01-13 12:35:49 +0000[diff] [blame]20 PPC_OPROFILE_INVALID = 0,
21 PPC_OPROFILE_RS64 = 1,
22 PPC_OPROFILE_POWER4 = 2,
23 PPC_OPROFILE_G4 = 3,
Andy Fleming39aef682008-02-04 18:27:55 -0600[diff] [blame]24 PPC_OPROFILE_FSL_EMB = 4,
Maynard Johnson18f21902006-11-20 18:45:16 +0100[diff] [blame]25 PPC_OPROFILE_CELL = 5,
Olof Johansson25fc5302007-04-18 16:38:21 +1000[diff] [blame]26 PPC_OPROFILE_PA6T = 6,
Anton Blanchard32a33992006-01-09 15:41:31 +1100[diff] [blame]27};
28
Olof Johansson1bd2e5a2007-01-28 21:23:54 -0600[diff] [blame]29enum powerpc_pmc_type {
30 PPC_PMC_DEFAULT = 0,
31 PPC_PMC_IBM = 1,
32 PPC_PMC_PA6T = 2,
Benjamin Herrenschmidtb950bdd2008-08-18 14:23:51 +1000[diff] [blame]33 PPC_PMC_G4 = 3,
Olof Johansson1bd2e5a2007-01-28 21:23:54 -0600[diff] [blame]34};
35
Benjamin Herrenschmidt47c0bd12007-12-21 15:39:21 +1100[diff] [blame]36struct pt_regs;
37
38extern int machine_check_generic(struct pt_regs *regs);
39extern int machine_check_4xx(struct pt_regs *regs);
40extern int machine_check_440A(struct pt_regs *regs);
Scott Woodfe04b112010-04-08 00:38:22 -0500[diff] [blame]41extern int machine_check_e500mc(struct pt_regs *regs);
Benjamin Herrenschmidt47c0bd12007-12-21 15:39:21 +1100[diff] [blame]42extern int machine_check_e500(struct pt_regs *regs);
43extern int machine_check_e200(struct pt_regs *regs);
Dave Kleikampfc5e7092010-03-05 03:43:18 +0000[diff] [blame]44extern int machine_check_47x(struct pt_regs *regs);
Benjamin Herrenschmidt47c0bd12007-12-21 15:39:21 +1100[diff] [blame]45
Paul Mackerras87a72f92007-10-04 14:18:01 +1000[diff] [blame]46/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]47struct cpu_spec {
48 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
49 unsigned int pvr_mask;
50 unsigned int pvr_value;
51
52 char *cpu_name;
53 unsigned long cpu_features; /* Kernel features */
54 unsigned int cpu_user_features; /* Userland features */
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]55 unsigned int mmu_features; /* MMU features */
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]56
57 /* cache line sizes */
58 unsigned int icache_bsize;
59 unsigned int dcache_bsize;
60
61 /* number of performance monitor counters */
62 unsigned int num_pmcs;
Olof Johansson1bd2e5a2007-01-28 21:23:54 -0600[diff] [blame]63 enum powerpc_pmc_type pmc_type;
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]64
65 /* this is called to initialize various CPU bits like L1 cache,
66 * BHT, SPD, etc... from head.S before branching to identify_machine
67 */
68 cpu_setup_t cpu_setup;
Olof Johanssonf39b7a52006-08-11 00:07:08 -0500[diff] [blame]69 /* Used to restore cpu setup on secondary processors and at resume */
70 cpu_restore_t cpu_restore;
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]71
72 /* Used by oprofile userspace to select the right counters */
73 char *oprofile_cpu_type;
74
75 /* Processor specific oprofile operations */
Anton Blanchard32a33992006-01-09 15:41:31 +1100[diff] [blame]76 enum powerpc_oprofile_type oprofile_type;
Paul Mackerras80f15dc2006-01-14 10:11:39 +1100[diff] [blame]77
Michael Neulinge78dbc82006-06-08 14:42:34 +1000[diff] [blame]78 /* Bit locations inside the mmcra change */
79 unsigned long oprofile_mmcra_sihv;
80 unsigned long oprofile_mmcra_sipr;
81
82 /* Bits to clear during an oprofile exception */
83 unsigned long oprofile_mmcra_clear;
84
Paul Mackerras80f15dc2006-01-14 10:11:39 +1100[diff] [blame]85 /* Name of processor class, for the ELF AT_PLATFORM entry */
86 char *platform;
Benjamin Herrenschmidt47c0bd12007-12-21 15:39:21 +1100[diff] [blame]87
88 /* Processor specific machine check handling. Return negative
89 * if the error is fatal, 1 if it was fully recovered and 0 to
90 * pass up (not CPU originated) */
91 int (*machine_check)(struct pt_regs *regs);
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]92};
93
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]94extern struct cpu_spec *cur_cpu_spec;
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]95
Benjamin Herrenschmidt42c4aaa2006-10-24 16:42:40 +1000[diff] [blame]96extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
97
Paul Mackerras974a76f2006-11-10 20:38:53 +1100[diff] [blame]98extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
Benjamin Herrenschmidt0909c8c2006-10-20 11:47:18 +1000[diff] [blame]99extern void do_feature_fixups(unsigned long value, void *fixup_start,
100 void *fixup_end);
Paul Mackerras9b6b5632005-10-06 12:06:20 +1000[diff] [blame]101
Nathan Lynch9115d132008-07-16 09:58:51 +1000[diff] [blame]102extern const char *powerpc_base_platform;
103
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]104#endif /* __ASSEMBLY__ */
105
106/* CPU kernel features */
107
108/* Retain the 32b definitions all use bottom half of word */
Michael Neulingcde4d492012-12-20 14:06:39 +0000[diff] [blame]109#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x00000001)
110#define CPU_FTR_L2CR ASM_CONST(0x00000002)
111#define CPU_FTR_SPEC7450 ASM_CONST(0x00000004)
112#define CPU_FTR_ALTIVEC ASM_CONST(0x00000008)
113#define CPU_FTR_TAU ASM_CONST(0x00000010)
114#define CPU_FTR_CAN_DOZE ASM_CONST(0x00000020)
115#define CPU_FTR_USE_TB ASM_CONST(0x00000040)
116#define CPU_FTR_L2CSR ASM_CONST(0x00000080)
117#define CPU_FTR_601 ASM_CONST(0x00000100)
118#define CPU_FTR_DBELL ASM_CONST(0x00000200)
119#define CPU_FTR_CAN_NAP ASM_CONST(0x00000400)
120#define CPU_FTR_L3CR ASM_CONST(0x00000800)
121#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x00001000)
122#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x00002000)
123#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x00004000)
124#define CPU_FTR_NO_DPM ASM_CONST(0x00008000)
125#define CPU_FTR_476_DD2 ASM_CONST(0x00010000)
126#define CPU_FTR_NEED_COHERENT ASM_CONST(0x00020000)
127#define CPU_FTR_NO_BTIC ASM_CONST(0x00040000)
128#define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x00080000)
129#define CPU_FTR_NODSISRALIGN ASM_CONST(0x00100000)
130#define CPU_FTR_PPC_LE ASM_CONST(0x00200000)
131#define CPU_FTR_REAL_LE ASM_CONST(0x00400000)
132#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x00800000)
133#define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x01000000)
134#define CPU_FTR_SPE ASM_CONST(0x02000000)
135#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x04000000)
136#define CPU_FTR_LWSYNC ASM_CONST(0x08000000)
137#define CPU_FTR_NOEXECUTE ASM_CONST(0x10000000)
138#define CPU_FTR_INDEXED_DCR ASM_CONST(0x20000000)
139#define CPU_FTR_EMB_HV ASM_CONST(0x40000000)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]140
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000[diff] [blame]141/*
142 * Add the 64-bit processor unique features in the top half of the word;
143 * on 32-bit, make the names available but defined to be 0.
144 */
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]145#ifdef __powerpc64__
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000[diff] [blame]146#define LONG_ASM_CONST(x) ASM_CONST(x)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]147#else
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000[diff] [blame]148#define LONG_ASM_CONST(x) 0
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]149#endif
150
Michael Neuling1580b3b2012-12-20 14:06:40 +0000[diff] [blame]151#define CPU_FTR_HVMODE LONG_ASM_CONST(0x0000000100000000)
152#define CPU_FTR_ARCH_201 LONG_ASM_CONST(0x0000000200000000)
153#define CPU_FTR_ARCH_206 LONG_ASM_CONST(0x0000000400000000)
154#define CPU_FTR_CFAR LONG_ASM_CONST(0x0000000800000000)
155#define CPU_FTR_IABR LONG_ASM_CONST(0x0000001000000000)
156#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000002000000000)
157#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000004000000000)
158#define CPU_FTR_SMT LONG_ASM_CONST(0x0000008000000000)
159#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000010000000000)
160#define CPU_FTR_PURR LONG_ASM_CONST(0x0000020000000000)
161#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000040000000000)
162#define CPU_FTR_SPURR LONG_ASM_CONST(0x0000080000000000)
163#define CPU_FTR_DSCR LONG_ASM_CONST(0x0000100000000000)
164#define CPU_FTR_VSX LONG_ASM_CONST(0x0000200000000000)
165#define CPU_FTR_SAO LONG_ASM_CONST(0x0000400000000000)
166#define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0000800000000000)
167#define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0001000000000000)
168#define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0002000000000000)
169#define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0004000000000000)
170#define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0008000000000000)
171#define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0010000000000000)
172#define CPU_FTR_ICSWX LONG_ASM_CONST(0x0020000000000000)
173#define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x0040000000000000)
174#define CPU_FTR_TM LONG_ASM_CONST(0x0080000000000000)
175#define CPU_FTR_BCTAR LONG_ASM_CONST(0x0100000000000000)
176#define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0200000000000000)
Michael Neuling79879c12012-12-20 14:06:42 +0000[diff] [blame]177#define CPU_FTR_DAWR LONG_ASM_CONST(0x0400000000000000)
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000[diff] [blame]178
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]179#ifndef __ASSEMBLY__
180
Matt Evans44ae3ab2011-04-06 19:48:50 +0000[diff] [blame]181#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
182
183#define MMU_FTR_PPCAS_ARCH_V2 (MMU_FTR_SLB | MMU_FTR_TLBIEL | \
184 MMU_FTR_16M_PAGE)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]185
186/* We only set the altivec features if the kernel was compiled with altivec
187 * support
188 */
189#ifdef CONFIG_ALTIVEC
190#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
191#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
192#else
193#define CPU_FTR_ALTIVEC_COMP 0
194#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
195#endif
196
Michael Neulingb962ce92008-06-25 14:07:18 +1000[diff] [blame]197/* We only set the VSX features if the kernel was compiled with VSX
198 * support
199 */
200#ifdef CONFIG_VSX
201#define CPU_FTR_VSX_COMP CPU_FTR_VSX
202#define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
203#else
204#define CPU_FTR_VSX_COMP 0
205#define PPC_FEATURE_HAS_VSX_COMP 0
206#endif
207
Kumar Gala5e14d212007-09-13 01:44:20 -0500[diff] [blame]208/* We only set the spe features if the kernel was compiled with spe
209 * support
210 */
211#ifdef CONFIG_SPE
212#define CPU_FTR_SPE_COMP CPU_FTR_SPE
213#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
214#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
215#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
216#else
217#define CPU_FTR_SPE_COMP 0
218#define PPC_FEATURE_HAS_SPE_COMP 0
219#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
220#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
221#endif
222
Michael Neuling6a6d5412013-02-13 16:21:29 +0000[diff] [blame]223/* We only set the TM feature if the kernel was compiled with TM supprt */
224#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
225#define CPU_FTR_TM_COMP CPU_FTR_TM
226#else
227#define CPU_FTR_TM_COMP 0
228#endif
229
Scott Wood11af1192007-09-14 15:32:14 -0500[diff] [blame]230/* We need to mark all pages as being coherent if we're SMP or we have a
231 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
232 * require it for PCI "streaming/prefetch" to work properly.
Piotr Ziecikc9310922009-03-17 09:17:50 -0600[diff] [blame]233 * This is also required by 52xx family.
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]234 */
Kumar Gala1775dbb2006-02-22 09:46:02 -0600[diff] [blame]235#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
Piotr Ziecikc9310922009-03-17 09:17:50 -0600[diff] [blame]236 || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \
237 || defined(CONFIG_PPC_MPC52xx)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]238#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
239#else
240#define CPU_FTR_COMMON 0
241#endif
242
243/* The powersave features NAP & DOZE seems to confuse BDI when
244 debugging. So if a BDI is used, disable theses
245 */
246#ifndef CONFIG_BDI_SWITCH
247#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
248#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
249#else
250#define CPU_FTR_MAYBE_CAN_DOZE 0
251#define CPU_FTR_MAYBE_CAN_NAP 0
252#endif
253
254#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
255 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
256 !defined(CONFIG_BOOKE))
257
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]258#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | \
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]259 CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
260#define CPU_FTRS_603 (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]261 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]262 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]263#define CPU_FTRS_604 (CPU_FTR_COMMON | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]264 CPU_FTR_USE_TB | CPU_FTR_PPC_LE)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]265#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]266 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]267 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]268#define CPU_FTRS_740 (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]269 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]270 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]271 CPU_FTR_PPC_LE)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]272#define CPU_FTRS_750 (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]273 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]274 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]275 CPU_FTR_PPC_LE)
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]276#define CPU_FTRS_750CL (CPU_FTRS_750)
Josh Boyerb6f41cc2007-07-03 02:06:53 +1000[diff] [blame]277#define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
278#define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]279#define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX)
Josh Boyerb6f41cc2007-07-03 02:06:53 +1000[diff] [blame]280#define CPU_FTRS_750GX (CPU_FTRS_750FX)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]281#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]282 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]283 CPU_FTR_ALTIVEC_COMP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]284 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]285#define CPU_FTRS_7400 (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]286 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]287 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]288 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]289#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]290 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]291 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
Becky Bruceb64f87c2007-11-10 09:17:49 +1100[diff] [blame]292 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]293#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]294 CPU_FTR_USE_TB | \
295 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]296 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]297 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
Becky Bruceb64f87c2007-11-10 09:17:49 +1100[diff] [blame]298 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]299#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \
Becky Bruceb64f87c2007-11-10 09:17:49 +1100[diff] [blame]300 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]301 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]302 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]303 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]304#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
Becky Bruceb64f87c2007-11-10 09:17:49 +1100[diff] [blame]305 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]306 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]307 CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]308#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \
Becky Bruceb64f87c2007-11-10 09:17:49 +1100[diff] [blame]309 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]310 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]311 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]312 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]313 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]314#define CPU_FTRS_7455 (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]315 CPU_FTR_USE_TB | \
316 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]317 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
Becky Bruceb64f87c2007-11-10 09:17:49 +1100[diff] [blame]318 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]319#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]320 CPU_FTR_USE_TB | \
321 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]322 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
Becky Bruceb64f87c2007-11-10 09:17:49 +1100[diff] [blame]323 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
324 CPU_FTR_NEED_PAIRED_STWCX)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]325#define CPU_FTRS_7447 (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]326 CPU_FTR_USE_TB | \
327 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]328 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
Becky Bruceb64f87c2007-11-10 09:17:49 +1100[diff] [blame]329 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]330#define CPU_FTRS_7447A (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]331 CPU_FTR_USE_TB | \
332 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]333 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
Becky Bruceb64f87c2007-11-10 09:17:49 +1100[diff] [blame]334 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]335#define CPU_FTRS_7448 (CPU_FTR_COMMON | \
James.Yang3d372542007-05-02 16:34:43 -0500[diff] [blame]336 CPU_FTR_USE_TB | \
337 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]338 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
Becky Bruceb64f87c2007-11-10 09:17:49 +1100[diff] [blame]339 CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]340#define CPU_FTRS_82XX (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]341 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
Scott Wood11af1192007-09-14 15:32:14 -0500[diff] [blame]342#define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]343 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]344#define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]345 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]346 CPU_FTR_COMMON)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]347#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]348 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
Kim Phillipsaa42c692006-12-08 02:43:30 -0600[diff] [blame]349 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]350#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_USE_TB)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]351#define CPU_FTRS_8XX (CPU_FTR_USE_TB)
Benjamin Herrenschmidt8309ce722008-12-12 17:33:25 +1100[diff] [blame]352#define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
353#define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
Benjamin Herrenschmidt6d2170b2008-12-18 19:13:22 +0000[diff] [blame]354#define CPU_FTRS_440x6 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \
355 CPU_FTR_INDEXED_DCR)
Dave Kleikampe7f75ad2010-03-05 10:43:12 +0000[diff] [blame]356#define CPU_FTRS_47X (CPU_FTRS_440x6)
Kumar Gala5e14d212007-09-13 01:44:20 -0500[diff] [blame]357#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
358 CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
Scott Wood52b066f2011-12-20 15:34:12 +0000[diff] [blame]359 CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE | \
360 CPU_FTR_DEBUG_LVL_EXC)
Kumar Galafc4033b2008-06-18 16:26:52 -0500[diff] [blame]361#define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
Benjamin Herrenschmidt8309ce722008-12-12 17:33:25 +1100[diff] [blame]362 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
363 CPU_FTR_NOEXECUTE)
Kumar Galafc4033b2008-06-18 16:26:52 -0500[diff] [blame]364#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]365 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
Benjamin Herrenschmidt8309ce722008-12-12 17:33:25 +1100[diff] [blame]366 CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
Scott Woodd51ad912010-05-27 17:35:12 -0500[diff] [blame]367#define CPU_FTRS_E500MC (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
Kumar Gala620165f2009-02-12 13:54:53 +0000[diff] [blame]368 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
Scott Wood73196cd32011-12-20 15:34:47 +0000[diff] [blame]369 CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
Kumar Gala11ed0db2011-04-06 00:11:06 -0500[diff] [blame]370#define CPU_FTRS_E5500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
371 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
Kumar Galad36b4c42011-04-06 00:18:48 -0500[diff] [blame]372 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
Scott Wood73196cd32011-12-20 15:34:47 +0000[diff] [blame]373 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
Kumar Gala10241842011-11-06 11:51:07 -0600[diff] [blame]374#define CPU_FTRS_E6500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
375 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
376 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
Kumar Galacd66cc22012-09-07 15:57:17 -0500[diff] [blame^]377 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]378#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
Michael Ellerman0b8e2e12006-11-23 00:46:46 +0100[diff] [blame]379
380/* 64-bit CPUs */
Anton Blanchard5a0e9b52010-02-10 01:10:25 +0000[diff] [blame]381#define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]382 CPU_FTR_IABR | CPU_FTR_PPC_LE)
Anton Blanchard5a0e9b52010-02-10 01:10:25 +0000[diff] [blame]383#define CPU_FTRS_RS64 (CPU_FTR_USE_TB | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]384 CPU_FTR_IABR | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]385 CPU_FTR_MMCRA | CPU_FTR_CTRL)
Kumar Gala2d1b2022008-07-02 01:16:40 +1000[diff] [blame]386#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]387 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
Anton Blanchardf89451f2010-08-11 01:40:27 +0000[diff] [blame]388 CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ | \
389 CPU_FTR_STCX_CHECKS_ADDRESS)
Kumar Gala2d1b2022008-07-02 01:16:40 +1000[diff] [blame]390#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
Paul Mackerras969391c2011-06-29 00:26:11 +0000[diff] [blame]391 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_201 | \
Mark Nelson2a929432008-08-22 14:36:19 +1000[diff] [blame]392 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
Paul Mackerras969391c2011-06-29 00:26:11 +0000[diff] [blame]393 CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \
394 CPU_FTR_HVMODE)
Kumar Gala2d1b2022008-07-02 01:16:40 +1000[diff] [blame]395#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]396 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]397 CPU_FTR_MMCRA | CPU_FTR_SMT | \
Matt Evans44ae3ab2011-04-06 19:48:50 +0000[diff] [blame]398 CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
399 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB)
Kumar Gala2d1b2022008-07-02 01:16:40 +1000[diff] [blame]400#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]401 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
Anton Blanchard03054d52006-04-29 09:51:06 +1000[diff] [blame]402 CPU_FTR_MMCRA | CPU_FTR_SMT | \
Matt Evans44ae3ab2011-04-06 19:48:50 +0000[diff] [blame]403 CPU_FTR_COHERENT_ICACHE | \
Anton Blanchard4c1985572006-12-08 17:46:58 +1100[diff] [blame]404 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
Anton Blanchardf89451f2010-08-11 01:40:27 +0000[diff] [blame]405 CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
Paul Mackerras48404f22011-05-01 19:48:20 +0000[diff] [blame]406 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR)
Kumar Gala2d1b2022008-07-02 01:16:40 +1000[diff] [blame]407#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
Paul Mackerras969391c2011-06-29 00:26:11 +0000[diff] [blame]408 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
Michael Neulinge952e6c2008-06-18 10:47:26 +1000[diff] [blame]409 CPU_FTR_MMCRA | CPU_FTR_SMT | \
Matt Evans44ae3ab2011-04-06 19:48:50 +0000[diff] [blame]410 CPU_FTR_COHERENT_ICACHE | \
Michael Neulinge952e6c2008-06-18 10:47:26 +1000[diff] [blame]411 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
Anton Blanchardf89451f2010-08-11 01:40:27 +0000[diff] [blame]412 CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \
Tseng-Hui (Frank) Lin851d2e22011-05-02 20:43:04 +0000[diff] [blame]413 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
Haren Mynenid26138682012-12-06 21:47:42 +0000[diff] [blame]414 CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | \
415 CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR)
Michael Neuling71e18492012-10-30 19:34:15 +0000[diff] [blame]416#define CPU_FTRS_POWER8 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
417 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
418 CPU_FTR_MMCRA | CPU_FTR_SMT | \
419 CPU_FTR_COHERENT_ICACHE | \
420 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
421 CPU_FTR_DSCR | CPU_FTR_SAO | \
422 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
Ian Munsiee5e84f02012-11-14 18:49:50 +0000[diff] [blame]423 CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
Michael Neulingb9eaee52013-02-13 16:21:42 +0000[diff] [blame]424 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | CPU_FTR_BCTAR | \
425 CPU_FTR_TM_COMP)
Kumar Gala2d1b2022008-07-02 01:16:40 +1000[diff] [blame]426#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]427 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]428 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
Matt Evans44ae3ab2011-04-06 19:48:50 +0000[diff] [blame]429 CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
Mark Nelson4ec577a2008-10-27 00:43:02 +0000[diff] [blame]430 CPU_FTR_UNALIGNED_LD_STD)
Kumar Gala2d1b2022008-07-02 01:16:40 +1000[diff] [blame]431#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
Matt Evans44ae3ab2011-04-06 19:48:50 +0000[diff] [blame]432 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
433 CPU_FTR_PURR | CPU_FTR_REAL_LE)
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]434#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]435
Benjamin Herrenschmidt76b4eda2011-04-14 22:32:01 +0000[diff] [blame]436#define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \
Jimi Xenidisfac26ad2011-09-29 10:55:13 +0000[diff] [blame]437 CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN | CPU_FTR_ICSWX)
Benjamin Herrenschmidt76b4eda2011-04-14 22:32:01 +0000[diff] [blame]438
Anton Blanchard2406f602005-12-13 07:45:33 +1100[diff] [blame]439#ifdef __powerpc64__
Kumar Gala11ed0db2011-04-06 00:11:06 -0500[diff] [blame]440#ifdef CONFIG_PPC_BOOK3E
Kumar Gala10241842011-11-06 11:51:07 -0600[diff] [blame]441#define CPU_FTRS_POSSIBLE (CPU_FTRS_E6500 | CPU_FTRS_E5500 | CPU_FTRS_A2)
Kumar Gala11ed0db2011-04-06 00:11:06 -0500[diff] [blame]442#else
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]443#define CPU_FTRS_POSSIBLE \
444 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \
Anton Blanchard03054d52006-04-29 09:51:06 +1000[diff] [blame]445 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \
Michael Neuling71e18492012-10-30 19:34:15 +0000[diff] [blame]446 CPU_FTRS_POWER7 | CPU_FTRS_POWER8 | CPU_FTRS_CELL | \
447 CPU_FTRS_PA6T | CPU_FTR_VSX)
Kumar Gala11ed0db2011-04-06 00:11:06 -0500[diff] [blame]448#endif
Anton Blanchard2406f602005-12-13 07:45:33 +1100[diff] [blame]449#else
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]450enum {
451 CPU_FTRS_POSSIBLE =
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]452#if CLASSIC_PPC
453 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
454 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
455 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
456 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
457 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
458 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
459 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
Kim Phillipsaa42c692006-12-08 02:43:30 -0600[diff] [blame]460 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
461 CPU_FTRS_CLASSIC32 |
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]462#else
463 CPU_FTRS_GENERIC_32 |
464#endif
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]465#ifdef CONFIG_8xx
466 CPU_FTRS_8XX |
467#endif
468#ifdef CONFIG_40x
469 CPU_FTRS_40X |
470#endif
471#ifdef CONFIG_44x
Benjamin Herrenschmidt6d2170b2008-12-18 19:13:22 +0000[diff] [blame]472 CPU_FTRS_44X | CPU_FTRS_440x6 |
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]473#endif
Dave Kleikampe7f75ad2010-03-05 10:43:12 +0000[diff] [blame]474#ifdef CONFIG_PPC_47x
Dave Kleikampc48d0db2011-01-26 06:17:58 +0000[diff] [blame]475 CPU_FTRS_47X | CPU_FTR_476_DD2 |
Dave Kleikampe7f75ad2010-03-05 10:43:12 +0000[diff] [blame]476#endif
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]477#ifdef CONFIG_E200
478 CPU_FTRS_E200 |
479#endif
480#ifdef CONFIG_E500
Scott Wood06aae862011-12-20 15:34:14 +0000[diff] [blame]481 CPU_FTRS_E500 | CPU_FTRS_E500_2 |
482#endif
483#ifdef CONFIG_PPC_E500MC
484 CPU_FTRS_E500MC | CPU_FTRS_E5500 | CPU_FTRS_E6500 |
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]485#endif
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]486 0,
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]487};
488#endif /* __powerpc64__ */
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]489
Anton Blanchard2406f602005-12-13 07:45:33 +1100[diff] [blame]490#ifdef __powerpc64__
Kumar Gala11ed0db2011-04-06 00:11:06 -0500[diff] [blame]491#ifdef CONFIG_PPC_BOOK3E
Kumar Gala10241842011-11-06 11:51:07 -0600[diff] [blame]492#define CPU_FTRS_ALWAYS (CPU_FTRS_E6500 & CPU_FTRS_E5500 & CPU_FTRS_A2)
Kumar Gala11ed0db2011-04-06 00:11:06 -0500[diff] [blame]493#else
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]494#define CPU_FTRS_ALWAYS \
495 (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \
Anton Blanchard03054d52006-04-29 09:51:06 +1000[diff] [blame]496 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \
Michael Neulinge952e6c2008-06-18 10:47:26 +1000[diff] [blame]497 CPU_FTRS_POWER7 & CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
Kumar Gala11ed0db2011-04-06 00:11:06 -0500[diff] [blame]498#endif
Anton Blanchard2406f602005-12-13 07:45:33 +1100[diff] [blame]499#else
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]500enum {
501 CPU_FTRS_ALWAYS =
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]502#if CLASSIC_PPC
503 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
504 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
505 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
506 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
507 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
508 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
509 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
Kim Phillipsaa42c692006-12-08 02:43:30 -0600[diff] [blame]510 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
511 CPU_FTRS_CLASSIC32 &
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]512#else
513 CPU_FTRS_GENERIC_32 &
514#endif
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]515#ifdef CONFIG_8xx
516 CPU_FTRS_8XX &
517#endif
518#ifdef CONFIG_40x
519 CPU_FTRS_40X &
520#endif
521#ifdef CONFIG_44x
Benjamin Herrenschmidt6d2170b2008-12-18 19:13:22 +0000[diff] [blame]522 CPU_FTRS_44X & CPU_FTRS_440x6 &
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]523#endif
524#ifdef CONFIG_E200
525 CPU_FTRS_E200 &
526#endif
527#ifdef CONFIG_E500
Scott Wood06aae862011-12-20 15:34:14 +0000[diff] [blame]528 CPU_FTRS_E500 & CPU_FTRS_E500_2 &
529#endif
530#ifdef CONFIG_PPC_E500MC
531 CPU_FTRS_E500MC & CPU_FTRS_E5500 & CPU_FTRS_E6500 &
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]532#endif
Scott Wood73196cd32011-12-20 15:34:47 +0000[diff] [blame]533 ~CPU_FTR_EMB_HV & /* can be removed at runtime */
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]534 CPU_FTRS_POSSIBLE,
535};
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]536#endif /* __powerpc64__ */
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]537
538static inline int cpu_has_feature(unsigned long feature)
539{
540 return (CPU_FTRS_ALWAYS & feature) ||
541 (CPU_FTRS_POSSIBLE
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]542 & cur_cpu_spec->cpu_features
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]543 & feature);
544}
545
K.Prasad5aae8a52010-06-15 11:35:19 +0530[diff] [blame]546#define HBP_NUM 1
K.Prasad5aae8a52010-06-15 11:35:19 +0530[diff] [blame]547
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]548#endif /* !__ASSEMBLY__ */
549
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]550#endif /* __ASM_POWERPC_CPUTABLE_H */