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Bjorn Helgaas8cfab3c2018-01-26 12:50:27 -06001/* SPDX-License-Identifier: GPL-2.0 */
Jingoo Han4b1ced82013-07-31 17:14:10 +09002/*
Bjorn Helgaas96291d52017-09-01 16:35:50 -05003 * Synopsys DesignWare PCIe host controller driver
Jingoo Han4b1ced82013-07-31 17:14:10 +09004 *
5 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
7 *
8 * Author: Jingoo Han <jg1.han@samsung.com>
Jingoo Han4b1ced82013-07-31 17:14:10 +09009 */
10
Seungwon Jeon18edf452013-10-09 09:12:21 -060011#ifndef _PCIE_DESIGNWARE_H
12#define _PCIE_DESIGNWARE_H
13
Kishon Vijay Abraham Ifeb85d92017-02-15 18:48:17 +053014#include <linux/irq.h>
15#include <linux/msi.h>
16#include <linux/pci.h>
17
Kishon Vijay Abraham If8aed6e2017-03-27 15:15:05 +053018#include <linux/pci-epc.h>
19#include <linux/pci-epf.h>
20
Kishon Vijay Abraham Ib90dc392017-02-15 18:48:10 +053021/* Parameters for the waiting for link up routine */
22#define LINK_WAIT_MAX_RETRIES 10
23#define LINK_WAIT_USLEEP_MIN 90000
24#define LINK_WAIT_USLEEP_MAX 100000
25
26/* Parameters for the waiting for iATU enabled routine */
27#define LINK_WAIT_MAX_IATU_RETRIES 5
28#define LINK_WAIT_IATU_MIN 9000
29#define LINK_WAIT_IATU_MAX 10000
30
31/* Synopsys-specific PCIe configuration registers */
32#define PCIE_PORT_LINK_CONTROL 0x710
33#define PORT_LINK_MODE_MASK (0x3f << 16)
34#define PORT_LINK_MODE_1_LANES (0x1 << 16)
35#define PORT_LINK_MODE_2_LANES (0x3 << 16)
36#define PORT_LINK_MODE_4_LANES (0x7 << 16)
37#define PORT_LINK_MODE_8_LANES (0xf << 16)
38
39#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
40#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
41#define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8)
42#define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
43#define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
44#define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
45#define PORT_LOGIC_LINK_WIDTH_8_LANES (0x8 << 8)
46
47#define PCIE_MSI_ADDR_LO 0x820
48#define PCIE_MSI_ADDR_HI 0x824
49#define PCIE_MSI_INTR0_ENABLE 0x828
50#define PCIE_MSI_INTR0_MASK 0x82C
51#define PCIE_MSI_INTR0_STATUS 0x830
52
53#define PCIE_ATU_VIEWPORT 0x900
54#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
55#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
56#define PCIE_ATU_REGION_INDEX2 (0x2 << 0)
57#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
58#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
59#define PCIE_ATU_CR1 0x904
60#define PCIE_ATU_TYPE_MEM (0x0 << 0)
61#define PCIE_ATU_TYPE_IO (0x2 << 0)
62#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
63#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
64#define PCIE_ATU_CR2 0x908
65#define PCIE_ATU_ENABLE (0x1 << 31)
66#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
67#define PCIE_ATU_LOWER_BASE 0x90C
68#define PCIE_ATU_UPPER_BASE 0x910
69#define PCIE_ATU_LIMIT 0x914
70#define PCIE_ATU_LOWER_TARGET 0x918
71#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
72#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
73#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
74#define PCIE_ATU_UPPER_TARGET 0x91C
75
Hou Zhiqiange44abfe2017-08-28 18:52:59 +080076#define PCIE_MISC_CONTROL_1_OFF 0x8BC
77#define PCIE_DBI_RO_WR_EN (0x1 << 0)
78
Kishon Vijay Abraham Ib90dc392017-02-15 18:48:10 +053079/*
80 * iATU Unroll-specific register definitions
81 * From 4.80 core version the address translation will be made by unroll
82 */
83#define PCIE_ATU_UNR_REGION_CTRL1 0x00
84#define PCIE_ATU_UNR_REGION_CTRL2 0x04
85#define PCIE_ATU_UNR_LOWER_BASE 0x08
86#define PCIE_ATU_UNR_UPPER_BASE 0x0C
87#define PCIE_ATU_UNR_LIMIT 0x10
88#define PCIE_ATU_UNR_LOWER_TARGET 0x14
89#define PCIE_ATU_UNR_UPPER_TARGET 0x18
90
91/* Register address builder */
92#define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) \
93 ((0x3 << 20) | ((region) << 9))
94
Kishon Vijay Abraham If8aed6e2017-03-27 15:15:05 +053095#define PCIE_GET_ATU_INB_UNR_REG_OFFSET(region) \
96 ((0x3 << 20) | ((region) << 9) | (0x1 << 8))
97
98#define MSI_MESSAGE_CONTROL 0x52
99#define MSI_CAP_MMC_SHIFT 1
100#define MSI_CAP_MME_SHIFT 4
101#define MSI_CAP_MME_MASK (7 << MSI_CAP_MME_SHIFT)
102#define MSI_MESSAGE_ADDR_L32 0x54
103#define MSI_MESSAGE_ADDR_U32 0x58
104
Jingoo Hanf342d942013-09-06 15:54:59 +0900105/*
106 * Maximum number of MSI IRQs can be 256 per controller. But keep
107 * it 32 as of now. Probably we will never need more than 32. If needed,
108 * then increment it in multiple of 32.
109 */
110#define MAX_MSI_IRQS 32
111#define MAX_MSI_CTRLS (MAX_MSI_IRQS / 32)
112
Kishon Vijay Abraham I442ec4c2017-02-15 18:48:14 +0530113struct pcie_port;
114struct dw_pcie;
Kishon Vijay Abraham If8aed6e2017-03-27 15:15:05 +0530115struct dw_pcie_ep;
116
117enum dw_pcie_region_type {
118 DW_PCIE_REGION_UNKNOWN,
119 DW_PCIE_REGION_INBOUND,
120 DW_PCIE_REGION_OUTBOUND,
121};
Kishon Vijay Abraham I442ec4c2017-02-15 18:48:14 +0530122
Kishon Vijay Abraham I608793e2017-03-27 15:15:08 +0530123enum dw_pcie_device_mode {
124 DW_PCIE_UNKNOWN_TYPE,
125 DW_PCIE_EP_TYPE,
126 DW_PCIE_LEG_EP_TYPE,
127 DW_PCIE_RC_TYPE,
128};
129
Kishon Vijay Abraham I442ec4c2017-02-15 18:48:14 +0530130struct dw_pcie_host_ops {
131 int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val);
132 int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32 val);
133 int (*rd_other_conf)(struct pcie_port *pp, struct pci_bus *bus,
134 unsigned int devfn, int where, int size, u32 *val);
135 int (*wr_other_conf)(struct pcie_port *pp, struct pci_bus *bus,
136 unsigned int devfn, int where, int size, u32 val);
Bjorn Andersson4a301762017-07-15 23:39:45 -0700137 int (*host_init)(struct pcie_port *pp);
Kishon Vijay Abraham I442ec4c2017-02-15 18:48:14 +0530138 void (*msi_set_irq)(struct pcie_port *pp, int irq);
139 void (*msi_clear_irq)(struct pcie_port *pp, int irq);
140 phys_addr_t (*get_msi_addr)(struct pcie_port *pp);
141 u32 (*get_msi_data)(struct pcie_port *pp, int pos);
142 void (*scan_bus)(struct pcie_port *pp);
143 int (*msi_host_init)(struct pcie_port *pp, struct msi_controller *chip);
144};
145
Jingoo Han4b1ced82013-07-31 17:14:10 +0900146struct pcie_port {
Jingoo Han4b1ced82013-07-31 17:14:10 +0900147 u8 root_bus_nr;
Jingoo Han4b1ced82013-07-31 17:14:10 +0900148 u64 cfg0_base;
149 void __iomem *va_cfg0_base;
Pratyush Anandadf70fc2014-09-05 17:48:54 -0600150 u32 cfg0_size;
Jingoo Han4b1ced82013-07-31 17:14:10 +0900151 u64 cfg1_base;
152 void __iomem *va_cfg1_base;
Pratyush Anandadf70fc2014-09-05 17:48:54 -0600153 u32 cfg1_size;
Zhou Wang0021d222015-10-29 19:57:06 -0500154 resource_size_t io_base;
Pratyush Anandadf70fc2014-09-05 17:48:54 -0600155 phys_addr_t io_bus_addr;
156 u32 io_size;
Jingoo Han4b1ced82013-07-31 17:14:10 +0900157 u64 mem_base;
Pratyush Anandadf70fc2014-09-05 17:48:54 -0600158 phys_addr_t mem_bus_addr;
159 u32 mem_size;
Zhou Wang0021d222015-10-29 19:57:06 -0500160 struct resource *cfg;
161 struct resource *io;
162 struct resource *mem;
163 struct resource *busn;
Jingoo Han4b1ced82013-07-31 17:14:10 +0900164 int irq;
Jisheng Zhang4ab2e7c2017-06-05 16:53:46 +0800165 const struct dw_pcie_host_ops *ops;
Jingoo Hanf342d942013-09-06 15:54:59 +0900166 int msi_irq;
Pratyush Anand904d0e72013-10-09 21:32:12 +0900167 struct irq_domain *irq_domain;
Jingoo Hanf342d942013-09-06 15:54:59 +0900168 unsigned long msi_data;
169 DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
Jingoo Han4b1ced82013-07-31 17:14:10 +0900170};
171
Kishon Vijay Abraham If8aed6e2017-03-27 15:15:05 +0530172enum dw_pcie_as_type {
173 DW_PCIE_AS_UNKNOWN,
174 DW_PCIE_AS_MEM,
175 DW_PCIE_AS_IO,
176};
177
178struct dw_pcie_ep_ops {
179 void (*ep_init)(struct dw_pcie_ep *ep);
180 int (*raise_irq)(struct dw_pcie_ep *ep, enum pci_epc_irq_type type,
181 u8 interrupt_num);
182};
183
184struct dw_pcie_ep {
185 struct pci_epc *epc;
186 struct dw_pcie_ep_ops *ops;
187 phys_addr_t phys_base;
188 size_t addr_size;
Kishon Vijay Abraham Ia937fe02017-08-18 20:28:02 +0530189 size_t page_size;
Kishon Vijay Abraham If8aed6e2017-03-27 15:15:05 +0530190 u8 bar_to_atu[6];
191 phys_addr_t *outbound_addr;
192 unsigned long ib_window_map;
193 unsigned long ob_window_map;
194 u32 num_ib_windows;
195 u32 num_ob_windows;
196};
197
Kishon Vijay Abraham I442ec4c2017-02-15 18:48:14 +0530198struct dw_pcie_ops {
Kishon Vijay Abraham Ia6600832017-03-13 19:13:22 +0530199 u64 (*cpu_addr_fixup)(u64 cpu_addr);
Kishon Vijay Abraham Ia509d7d2017-03-13 19:13:26 +0530200 u32 (*read_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
201 size_t size);
202 void (*write_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
203 size_t size, u32 val);
Kishon Vijay Abraham I442ec4c2017-02-15 18:48:14 +0530204 int (*link_up)(struct dw_pcie *pcie);
Kishon Vijay Abraham If8aed6e2017-03-27 15:15:05 +0530205 int (*start_link)(struct dw_pcie *pcie);
206 void (*stop_link)(struct dw_pcie *pcie);
Jingoo Han4b1ced82013-07-31 17:14:10 +0900207};
208
Kishon Vijay Abraham I442ec4c2017-02-15 18:48:14 +0530209struct dw_pcie {
210 struct device *dev;
211 void __iomem *dbi_base;
Kishon Vijay Abraham If8aed6e2017-03-27 15:15:05 +0530212 void __iomem *dbi_base2;
Kishon Vijay Abraham I442ec4c2017-02-15 18:48:14 +0530213 u32 num_viewport;
214 u8 iatu_unroll_enabled;
215 struct pcie_port pp;
Kishon Vijay Abraham If8aed6e2017-03-27 15:15:05 +0530216 struct dw_pcie_ep ep;
Kishon Vijay Abraham I442ec4c2017-02-15 18:48:14 +0530217 const struct dw_pcie_ops *ops;
218};
219
220#define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp)
221
Kishon Vijay Abraham If8aed6e2017-03-27 15:15:05 +0530222#define to_dw_pcie_from_ep(endpoint) \
223 container_of((endpoint), struct dw_pcie, ep)
224
Kishon Vijay Abraham I19ce01cc2017-02-15 18:48:12 +0530225int dw_pcie_read(void __iomem *addr, int size, u32 *val);
226int dw_pcie_write(void __iomem *addr, int size, u32 val);
Seungwon Jeon18edf452013-10-09 09:12:21 -0600227
Kishon Vijay Abraham Ia509d7d2017-03-13 19:13:26 +0530228u32 __dw_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
229 size_t size);
230void __dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
231 size_t size, u32 val);
Kishon Vijay Abraham I442ec4c2017-02-15 18:48:14 +0530232int dw_pcie_link_up(struct dw_pcie *pci);
233int dw_pcie_wait_for_link(struct dw_pcie *pci);
Kishon Vijay Abraham Ifeb85d92017-02-15 18:48:17 +0530234void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index,
235 int type, u64 cpu_addr, u64 pci_addr,
236 u32 size);
Kishon Vijay Abraham If8aed6e2017-03-27 15:15:05 +0530237int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int bar,
238 u64 cpu_addr, enum dw_pcie_as_type as_type);
239void dw_pcie_disable_atu(struct dw_pcie *pci, int index,
240 enum dw_pcie_region_type type);
Kishon Vijay Abraham Ifeb85d92017-02-15 18:48:17 +0530241void dw_pcie_setup(struct dw_pcie *pci);
Kishon Vijay Abraham Ia0560202017-02-15 18:48:18 +0530242
Kishon Vijay Abraham Ib50b2db2017-03-13 19:13:25 +0530243static inline void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val)
244{
Kishon Vijay Abraham Ia509d7d2017-03-13 19:13:26 +0530245 __dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x4, val);
Kishon Vijay Abraham Ib50b2db2017-03-13 19:13:25 +0530246}
247
248static inline u32 dw_pcie_readl_dbi(struct dw_pcie *pci, u32 reg)
249{
Kishon Vijay Abraham Ia509d7d2017-03-13 19:13:26 +0530250 return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x4);
Kishon Vijay Abraham Ib50b2db2017-03-13 19:13:25 +0530251}
252
Kishon Vijay Abraham If8aed6e2017-03-27 15:15:05 +0530253static inline void dw_pcie_writew_dbi(struct dw_pcie *pci, u32 reg, u16 val)
254{
255 __dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x2, val);
256}
257
258static inline u16 dw_pcie_readw_dbi(struct dw_pcie *pci, u32 reg)
259{
260 return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x2);
261}
262
263static inline void dw_pcie_writeb_dbi(struct dw_pcie *pci, u32 reg, u8 val)
264{
265 __dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x1, val);
266}
267
268static inline u8 dw_pcie_readb_dbi(struct dw_pcie *pci, u32 reg)
269{
270 return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x1);
271}
272
273static inline void dw_pcie_writel_dbi2(struct dw_pcie *pci, u32 reg, u32 val)
274{
275 __dw_pcie_write_dbi(pci, pci->dbi_base2, reg, 0x4, val);
276}
277
278static inline u32 dw_pcie_readl_dbi2(struct dw_pcie *pci, u32 reg)
279{
280 return __dw_pcie_read_dbi(pci, pci->dbi_base2, reg, 0x4);
281}
282
Hou Zhiqiange44abfe2017-08-28 18:52:59 +0800283static inline void dw_pcie_dbi_ro_wr_en(struct dw_pcie *pci)
284{
285 u32 reg;
286 u32 val;
287
288 reg = PCIE_MISC_CONTROL_1_OFF;
289 val = dw_pcie_readl_dbi(pci, reg);
290 val |= PCIE_DBI_RO_WR_EN;
291 dw_pcie_writel_dbi(pci, reg, val);
292}
293
294static inline void dw_pcie_dbi_ro_wr_dis(struct dw_pcie *pci)
295{
296 u32 reg;
297 u32 val;
298
299 reg = PCIE_MISC_CONTROL_1_OFF;
300 val = dw_pcie_readl_dbi(pci, reg);
301 val &= ~PCIE_DBI_RO_WR_EN;
302 dw_pcie_writel_dbi(pci, reg, val);
303}
304
Kishon Vijay Abraham Ia0560202017-02-15 18:48:18 +0530305#ifdef CONFIG_PCIE_DW_HOST
306irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
307void dw_pcie_msi_init(struct pcie_port *pp);
308void dw_pcie_setup_rc(struct pcie_port *pp);
309int dw_pcie_host_init(struct pcie_port *pp);
310#else
311static inline irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
312{
313 return IRQ_NONE;
314}
315
316static inline void dw_pcie_msi_init(struct pcie_port *pp)
317{
318}
319
320static inline void dw_pcie_setup_rc(struct pcie_port *pp)
321{
322}
323
324static inline int dw_pcie_host_init(struct pcie_port *pp)
325{
326 return 0;
327}
328#endif
Kishon Vijay Abraham If8aed6e2017-03-27 15:15:05 +0530329
330#ifdef CONFIG_PCIE_DW_EP
331void dw_pcie_ep_linkup(struct dw_pcie_ep *ep);
332int dw_pcie_ep_init(struct dw_pcie_ep *ep);
333void dw_pcie_ep_exit(struct dw_pcie_ep *ep);
334#else
335static inline void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
336{
337}
338
339static inline int dw_pcie_ep_init(struct dw_pcie_ep *ep)
340{
341 return 0;
342}
343
344static inline void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
345{
346}
347#endif
Seungwon Jeon18edf452013-10-09 09:12:21 -0600348#endif /* _PCIE_DESIGNWARE_H */