blob: 78d1df9112ba3932fe993c5f9700f00bb830a786 [file] [log] [blame]
Geert Uytterhoeven80978a42017-04-24 16:54:14 +02001config CLK_RENESAS
2 bool "Renesas SoC clock support" if COMPILE_TEST && !ARCH_RENESAS
3 default y if ARCH_RENESAS
4 select CLK_EMEV2 if ARCH_EMEV2
5 select CLK_RZA1 if ARCH_R7S72100
6 select CLK_R8A73A4 if ARCH_R8A73A4
7 select CLK_R8A7740 if ARCH_R8A7740
8 select CLK_R8A7743 if ARCH_R8A7743
9 select CLK_R8A7745 if ARCH_R8A7745
10 select CLK_R8A7778 if ARCH_R8A7778
11 select CLK_R8A7779 if ARCH_R8A7779
12 select CLK_R8A7790 if ARCH_R8A7790
13 select CLK_R8A7791 if ARCH_R8A7791 || ARCH_R8A7793
14 select CLK_R8A7792 if ARCH_R8A7792
15 select CLK_R8A7794 if ARCH_R8A7794
16 select CLK_R8A7795 if ARCH_R8A7795
17 select CLK_R8A7796 if ARCH_R8A7796
18 select CLK_SH73A0 if ARCH_SH73A0
19
20if CLK_RENESAS
21
Geert Uytterhoevend4e59f12017-03-19 18:05:42 +010022config CLK_RENESAS_LEGACY
23 bool "Legacy DT clock support"
Geert Uytterhoeven2d755882017-03-19 18:12:51 +010024 depends on CLK_R8A7790 || CLK_R8A7791 || CLK_R8A7792 || CLK_R8A7794
Geert Uytterhoevend4e59f12017-03-19 18:05:42 +010025 default y
26 help
27 Enable backward compatibility with old device trees describing a
28 hierarchical representation of the various CPG and MSTP clocks.
29
30 Say Y if you want your kernel to work with old DTBs.
31
Geert Uytterhoeven80978a42017-04-24 16:54:14 +020032# SoC
33config CLK_EMEV2
34 bool "Emma Mobile EV2 clock support" if COMPILE_TEST
35
36config CLK_RZA1
37 bool
38 select CLK_RENESAS_CPG_MSTP
39
40config CLK_R8A73A4
41 bool
42 select CLK_RENESAS_CPG_MSTP
43 select CLK_RENESAS_DIV6
44
45config CLK_R8A7740
46 bool
47 select CLK_RENESAS_CPG_MSTP
48 select CLK_RENESAS_DIV6
49
50config CLK_R8A7743
51 bool
52 select CLK_RCAR_GEN2_CPG
53
54config CLK_R8A7745
55 bool
56 select CLK_RCAR_GEN2_CPG
57
58config CLK_R8A7778
59 bool
60 select CLK_RENESAS_CPG_MSTP
61
62config CLK_R8A7779
63 bool
64 select CLK_RENESAS_CPG_MSTP
65
66config CLK_R8A7790
67 bool
Geert Uytterhoevend4e59f12017-03-19 18:05:42 +010068 select CLK_RCAR_GEN2 if CLK_RENESAS_LEGACY
69 select CLK_RCAR_GEN2_CPG
Geert Uytterhoeven80978a42017-04-24 16:54:14 +020070 select CLK_RENESAS_DIV6
71
72config CLK_R8A7791
73 bool
Geert Uytterhoeven6449ab82015-10-16 11:41:19 +020074 select CLK_RCAR_GEN2 if CLK_RENESAS_LEGACY
75 select CLK_RCAR_GEN2_CPG
Geert Uytterhoeven80978a42017-04-24 16:54:14 +020076 select CLK_RENESAS_DIV6
77
78config CLK_R8A7792
79 bool
Geert Uytterhoevenfd3c2f32017-03-19 18:08:59 +010080 select CLK_RCAR_GEN2 if CLK_RENESAS_LEGACY
81 select CLK_RCAR_GEN2_CPG
Geert Uytterhoeven80978a42017-04-24 16:54:14 +020082
83config CLK_R8A7794
84 bool
Geert Uytterhoeven2d755882017-03-19 18:12:51 +010085 select CLK_RCAR_GEN2 if CLK_RENESAS_LEGACY
86 select CLK_RCAR_GEN2_CPG
Geert Uytterhoeven80978a42017-04-24 16:54:14 +020087 select CLK_RENESAS_DIV6
88
89config CLK_R8A7795
90 bool
91 select CLK_RCAR_GEN3_CPG
92
93config CLK_R8A7796
94 bool
95 select CLK_RCAR_GEN3_CPG
96
97config CLK_SH73A0
98 bool
99 select CLK_RENESAS_CPG_MSTP
100 select CLK_RENESAS_DIV6
101
102
103# Family
104config CLK_RCAR_GEN2
105 bool
106 select CLK_RENESAS_CPG_MSTP
107 select CLK_RENESAS_DIV6
108
109config CLK_RCAR_GEN2_CPG
110 bool
111 select CLK_RENESAS_CPG_MSSR
112
113config CLK_RCAR_GEN3_CPG
114 bool
115 select CLK_RENESAS_CPG_MSSR
116
117
118# Generic
Geert Uytterhoevena5bd7f72016-04-13 11:08:42 +0200119config CLK_RENESAS_CPG_MSSR
120 bool
Geert Uytterhoeven80978a42017-04-24 16:54:14 +0200121 select CLK_RENESAS_DIV6
Geert Uytterhoevena5bd7f72016-04-13 11:08:42 +0200122
123config CLK_RENESAS_CPG_MSTP
124 bool
Geert Uytterhoeven80978a42017-04-24 16:54:14 +0200125
126config CLK_RENESAS_DIV6
127 bool "DIV6 clock support" if COMPILE_TEST
128
129endif # CLK_RENESAS