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gerrit-public.fairphone.software / kernel / msm-5.4 / 966ed8785f15064a55915ffae723354dd7467653 / . / arch / arm / boot / dts / stm32mp157c.dtsi
blob: 509347cb5ba548cea4cb6ebeb314ae9f2f44a3fb [file] [log] [blame]
Ludovic Barre8471a202018-02-26 16:35:40 +0100[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5 */
6#include <dt-bindings/interrupt-controller/arm-gic.h>
Gabriel Fernandez3599a8a2018-03-15 08:18:00 +0100[diff] [blame]7#include <dt-bindings/clock/stm32mp1-clks.h>
Ludovic Barre8471a202018-02-26 16:35:40 +0100[diff] [blame]8
9/ {
10 #address-cells = <1>;
11 #size-cells = <1>;
12
13 cpus {
14 #address-cells = <1>;
15 #size-cells = <0>;
16
17 cpu0: cpu@0 {
18 compatible = "arm,cortex-a7";
19 device_type = "cpu";
20 reg = <0>;
21 };
22
23 cpu1: cpu@1 {
24 compatible = "arm,cortex-a7";
25 device_type = "cpu";
26 reg = <1>;
27 };
28 };
29
30 psci {
31 compatible = "arm,psci";
32 method = "smc";
33 cpu_off = <0x84000002>;
34 cpu_on = <0x84000003>;
35 };
36
37 aliases {
38 gpio0 = &gpioa;
39 gpio1 = &gpiob;
40 gpio2 = &gpioc;
41 gpio3 = &gpiod;
42 gpio4 = &gpioe;
43 gpio5 = &gpiof;
44 gpio6 = &gpiog;
45 gpio7 = &gpioh;
46 gpio8 = &gpioi;
47 gpio9 = &gpioj;
48 gpio10 = &gpiok;
49 };
50
51 intc: interrupt-controller@a0021000 {
52 compatible = "arm,cortex-a7-gic";
53 #interrupt-cells = <3>;
54 interrupt-controller;
55 reg = <0xa0021000 0x1000>,
56 <0xa0022000 0x2000>;
57 };
58
59 timer {
60 compatible = "arm,armv7-timer";
61 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
62 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
63 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
64 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
65 interrupt-parent = <&intc>;
66 };
67
68 clocks {
69 clk_hse: clk-hse {
70 #clock-cells = <0>;
71 compatible = "fixed-clock";
72 clock-frequency = <24000000>;
73 };
74
Ludovic Barre8471a202018-02-26 16:35:40 +0100[diff] [blame]75 clk_hsi: clk-hsi {
76 #clock-cells = <0>;
77 compatible = "fixed-clock";
78 clock-frequency = <64000000>;
79 };
80
81 clk_lse: clk-lse {
82 #clock-cells = <0>;
83 compatible = "fixed-clock";
84 clock-frequency = <32768>;
85 };
86
87 clk_lsi: clk-lsi {
88 #clock-cells = <0>;
89 compatible = "fixed-clock";
90 clock-frequency = <32000>;
91 };
92
93 clk_csi: clk-csi {
94 #clock-cells = <0>;
95 compatible = "fixed-clock";
96 clock-frequency = <4000000>;
97 };
Ludovic Barre8471a202018-02-26 16:35:40 +0100[diff] [blame]98 };
99
100 soc {
101 compatible = "simple-bus";
102 #address-cells = <1>;
103 #size-cells = <1>;
104 interrupt-parent = <&intc>;
105 ranges;
106
Fabrice Gasnier61fc2112018-04-17 15:45:00 +0200[diff] [blame]107 timers2: timer@40000000 {
108 #address-cells = <1>;
109 #size-cells = <0>;
110 compatible = "st,stm32-timers";
111 reg = <0x40000000 0x400>;
112 clocks = <&rcc TIM2_K>;
113 clock-names = "int";
114 status = "disabled";
115
116 pwm {
117 compatible = "st,stm32-pwm";
118 status = "disabled";
119 };
120
121 timer@1 {
122 compatible = "st,stm32h7-timer-trigger";
123 reg = <1>;
124 status = "disabled";
125 };
126 };
127
128 timers3: timer@40001000 {
129 #address-cells = <1>;
130 #size-cells = <0>;
131 compatible = "st,stm32-timers";
132 reg = <0x40001000 0x400>;
133 clocks = <&rcc TIM3_K>;
134 clock-names = "int";
135 status = "disabled";
136
137 pwm {
138 compatible = "st,stm32-pwm";
139 status = "disabled";
140 };
141
142 timer@2 {
143 compatible = "st,stm32h7-timer-trigger";
144 reg = <2>;
145 status = "disabled";
146 };
147 };
148
149 timers4: timer@40002000 {
150 #address-cells = <1>;
151 #size-cells = <0>;
152 compatible = "st,stm32-timers";
153 reg = <0x40002000 0x400>;
154 clocks = <&rcc TIM4_K>;
155 clock-names = "int";
156 status = "disabled";
157
158 pwm {
159 compatible = "st,stm32-pwm";
160 status = "disabled";
161 };
162
163 timer@3 {
164 compatible = "st,stm32h7-timer-trigger";
165 reg = <3>;
166 status = "disabled";
167 };
168 };
169
170 timers5: timer@40003000 {
171 #address-cells = <1>;
172 #size-cells = <0>;
173 compatible = "st,stm32-timers";
174 reg = <0x40003000 0x400>;
175 clocks = <&rcc TIM5_K>;
176 clock-names = "int";
177 status = "disabled";
178
179 pwm {
180 compatible = "st,stm32-pwm";
181 status = "disabled";
182 };
183
184 timer@4 {
185 compatible = "st,stm32h7-timer-trigger";
186 reg = <4>;
187 status = "disabled";
188 };
189 };
190
191 timers6: timer@40004000 {
192 #address-cells = <1>;
193 #size-cells = <0>;
194 compatible = "st,stm32-timers";
195 reg = <0x40004000 0x400>;
196 clocks = <&rcc TIM6_K>;
197 clock-names = "int";
198 status = "disabled";
199
200 timer@5 {
201 compatible = "st,stm32h7-timer-trigger";
202 reg = <5>;
203 status = "disabled";
204 };
205 };
206
207 timers7: timer@40005000 {
208 #address-cells = <1>;
209 #size-cells = <0>;
210 compatible = "st,stm32-timers";
211 reg = <0x40005000 0x400>;
212 clocks = <&rcc TIM7_K>;
213 clock-names = "int";
214 status = "disabled";
215
216 timer@6 {
217 compatible = "st,stm32h7-timer-trigger";
218 reg = <6>;
219 status = "disabled";
220 };
221 };
222
223 timers12: timer@40006000 {
224 #address-cells = <1>;
225 #size-cells = <0>;
226 compatible = "st,stm32-timers";
227 reg = <0x40006000 0x400>;
228 clocks = <&rcc TIM12_K>;
229 clock-names = "int";
230 status = "disabled";
231
232 pwm {
233 compatible = "st,stm32-pwm";
234 status = "disabled";
235 };
236
237 timer@11 {
238 compatible = "st,stm32h7-timer-trigger";
239 reg = <11>;
240 status = "disabled";
241 };
242 };
243
244 timers13: timer@40007000 {
245 #address-cells = <1>;
246 #size-cells = <0>;
247 compatible = "st,stm32-timers";
248 reg = <0x40007000 0x400>;
249 clocks = <&rcc TIM13_K>;
250 clock-names = "int";
251 status = "disabled";
252
253 pwm {
254 compatible = "st,stm32-pwm";
255 status = "disabled";
256 };
257
258 timer@12 {
259 compatible = "st,stm32h7-timer-trigger";
260 reg = <12>;
261 status = "disabled";
262 };
263 };
264
265 timers14: timer@40008000 {
266 #address-cells = <1>;
267 #size-cells = <0>;
268 compatible = "st,stm32-timers";
269 reg = <0x40008000 0x400>;
270 clocks = <&rcc TIM14_K>;
271 clock-names = "int";
272 status = "disabled";
273
274 pwm {
275 compatible = "st,stm32-pwm";
276 status = "disabled";
277 };
278
279 timer@13 {
280 compatible = "st,stm32h7-timer-trigger";
281 reg = <13>;
282 status = "disabled";
283 };
284 };
285
Fabrice Gasnier966ed872018-05-02 13:53:38 +0200[diff] [blame^]286 lptimer1: timer@40009000 {
287 #address-cells = <1>;
288 #size-cells = <0>;
289 compatible = "st,stm32-lptimer";
290 reg = <0x40009000 0x400>;
291 clocks = <&rcc LPTIM1_K>;
292 clock-names = "mux";
293 status = "disabled";
294
295 pwm {
296 compatible = "st,stm32-pwm-lp";
297 #pwm-cells = <3>;
298 status = "disabled";
299 };
300
301 trigger@0 {
302 compatible = "st,stm32-lptimer-trigger";
303 reg = <0>;
304 status = "disabled";
305 };
306
307 counter {
308 compatible = "st,stm32-lptimer-counter";
309 status = "disabled";
310 };
311 };
312
Ludovic Barre8471a202018-02-26 16:35:40 +0100[diff] [blame]313 usart2: serial@4000e000 {
314 compatible = "st,stm32h7-uart";
315 reg = <0x4000e000 0x400>;
316 interrupts = <GIC_SPI 38 IRQ_TYPE_NONE>;
Gabriel Fernandez3599a8a2018-03-15 08:18:00 +0100[diff] [blame]317 clocks = <&rcc USART2_K>;
Ludovic Barre8471a202018-02-26 16:35:40 +0100[diff] [blame]318 status = "disabled";
319 };
320
321 usart3: serial@4000f000 {
322 compatible = "st,stm32h7-uart";
323 reg = <0x4000f000 0x400>;
324 interrupts = <GIC_SPI 39 IRQ_TYPE_NONE>;
Gabriel Fernandez3599a8a2018-03-15 08:18:00 +0100[diff] [blame]325 clocks = <&rcc USART3_K>;
Ludovic Barre8471a202018-02-26 16:35:40 +0100[diff] [blame]326 status = "disabled";
327 };
328
329 uart4: serial@40010000 {
330 compatible = "st,stm32h7-uart";
331 reg = <0x40010000 0x400>;
332 interrupts = <GIC_SPI 52 IRQ_TYPE_NONE>;
Gabriel Fernandez3599a8a2018-03-15 08:18:00 +0100[diff] [blame]333 clocks = <&rcc UART4_K>;
Ludovic Barre8471a202018-02-26 16:35:40 +0100[diff] [blame]334 status = "disabled";
335 };
336
337 uart5: serial@40011000 {
338 compatible = "st,stm32h7-uart";
339 reg = <0x40011000 0x400>;
340 interrupts = <GIC_SPI 53 IRQ_TYPE_NONE>;
Gabriel Fernandez3599a8a2018-03-15 08:18:00 +0100[diff] [blame]341 clocks = <&rcc UART5_K>;
Ludovic Barre8471a202018-02-26 16:35:40 +0100[diff] [blame]342 status = "disabled";
343 };
344
345 uart7: serial@40018000 {
346 compatible = "st,stm32h7-uart";
347 reg = <0x40018000 0x400>;
348 interrupts = <GIC_SPI 82 IRQ_TYPE_NONE>;
Gabriel Fernandez3599a8a2018-03-15 08:18:00 +0100[diff] [blame]349 clocks = <&rcc UART7_K>;
Ludovic Barre8471a202018-02-26 16:35:40 +0100[diff] [blame]350 status = "disabled";
351 };
352
353 uart8: serial@40019000 {
354 compatible = "st,stm32h7-uart";
355 reg = <0x40019000 0x400>;
356 interrupts = <GIC_SPI 83 IRQ_TYPE_NONE>;
Gabriel Fernandez3599a8a2018-03-15 08:18:00 +0100[diff] [blame]357 clocks = <&rcc UART8_K>;
Ludovic Barre8471a202018-02-26 16:35:40 +0100[diff] [blame]358 status = "disabled";
359 };
360
Fabrice Gasnier61fc2112018-04-17 15:45:00 +0200[diff] [blame]361 timers1: timer@44000000 {
362 #address-cells = <1>;
363 #size-cells = <0>;
364 compatible = "st,stm32-timers";
365 reg = <0x44000000 0x400>;
366 clocks = <&rcc TIM1_K>;
367 clock-names = "int";
368 status = "disabled";
369
370 pwm {
371 compatible = "st,stm32-pwm";
372 status = "disabled";
373 };
374
375 timer@0 {
376 compatible = "st,stm32h7-timer-trigger";
377 reg = <0>;
378 status = "disabled";
379 };
380 };
381
382 timers8: timer@44001000 {
383 #address-cells = <1>;
384 #size-cells = <0>;
385 compatible = "st,stm32-timers";
386 reg = <0x44001000 0x400>;
387 clocks = <&rcc TIM8_K>;
388 clock-names = "int";
389 status = "disabled";
390
391 pwm {
392 compatible = "st,stm32-pwm";
393 status = "disabled";
394 };
395
396 timer@7 {
397 compatible = "st,stm32h7-timer-trigger";
398 reg = <7>;
399 status = "disabled";
400 };
401 };
402
Ludovic Barre8471a202018-02-26 16:35:40 +0100[diff] [blame]403 usart6: serial@44003000 {
404 compatible = "st,stm32h7-uart";
405 reg = <0x44003000 0x400>;
406 interrupts = <GIC_SPI 71 IRQ_TYPE_NONE>;
Gabriel Fernandez3599a8a2018-03-15 08:18:00 +0100[diff] [blame]407 clocks = <&rcc USART6_K>;
Ludovic Barre8471a202018-02-26 16:35:40 +0100[diff] [blame]408 status = "disabled";
409 };
410
Fabrice Gasnier61fc2112018-04-17 15:45:00 +0200[diff] [blame]411 timers15: timer@44006000 {
412 #address-cells = <1>;
413 #size-cells = <0>;
414 compatible = "st,stm32-timers";
415 reg = <0x44006000 0x400>;
416 clocks = <&rcc TIM15_K>;
417 clock-names = "int";
418 status = "disabled";
419
420 pwm {
421 compatible = "st,stm32-pwm";
422 status = "disabled";
423 };
424
425 timer@14 {
426 compatible = "st,stm32h7-timer-trigger";
427 reg = <14>;
428 status = "disabled";
429 };
430 };
431
432 timers16: timer@44007000 {
433 #address-cells = <1>;
434 #size-cells = <0>;
435 compatible = "st,stm32-timers";
436 reg = <0x44007000 0x400>;
437 clocks = <&rcc TIM16_K>;
438 clock-names = "int";
439 status = "disabled";
440
441 pwm {
442 compatible = "st,stm32-pwm";
443 status = "disabled";
444 };
445 timer@15 {
446 compatible = "st,stm32h7-timer-trigger";
447 reg = <15>;
448 status = "disabled";
449 };
450 };
451
452 timers17: timer@44008000 {
453 #address-cells = <1>;
454 #size-cells = <0>;
455 compatible = "st,stm32-timers";
456 reg = <0x44008000 0x400>;
457 clocks = <&rcc TIM17_K>;
458 clock-names = "int";
459 status = "disabled";
460
461 pwm {
462 compatible = "st,stm32-pwm";
463 status = "disabled";
464 };
465
466 timer@16 {
467 compatible = "st,stm32h7-timer-trigger";
468 reg = <16>;
469 status = "disabled";
470 };
471 };
472
Gabriel Fernandez3599a8a2018-03-15 08:18:00 +0100[diff] [blame]473 rcc: rcc@50000000 {
474 compatible = "st,stm32mp1-rcc", "syscon";
475 reg = <0x50000000 0x1000>;
476 #clock-cells = <1>;
477 #reset-cells = <1>;
478 };
479
Fabrice Gasnier966ed872018-05-02 13:53:38 +0200[diff] [blame^]480 lptimer2: timer@50021000 {
481 #address-cells = <1>;
482 #size-cells = <0>;
483 compatible = "st,stm32-lptimer";
484 reg = <0x50021000 0x400>;
485 clocks = <&rcc LPTIM2_K>;
486 clock-names = "mux";
487 status = "disabled";
488
489 pwm {
490 compatible = "st,stm32-pwm-lp";
491 #pwm-cells = <3>;
492 status = "disabled";
493 };
494
495 trigger@1 {
496 compatible = "st,stm32-lptimer-trigger";
497 reg = <1>;
498 status = "disabled";
499 };
500
501 counter {
502 compatible = "st,stm32-lptimer-counter";
503 status = "disabled";
504 };
505 };
506
507 lptimer3: timer@50022000 {
508 #address-cells = <1>;
509 #size-cells = <0>;
510 compatible = "st,stm32-lptimer";
511 reg = <0x50022000 0x400>;
512 clocks = <&rcc LPTIM3_K>;
513 clock-names = "mux";
514 status = "disabled";
515
516 pwm {
517 compatible = "st,stm32-pwm-lp";
518 #pwm-cells = <3>;
519 status = "disabled";
520 };
521
522 trigger@2 {
523 compatible = "st,stm32-lptimer-trigger";
524 reg = <2>;
525 status = "disabled";
526 };
527 };
528
529 lptimer4: timer@50023000 {
530 compatible = "st,stm32-lptimer";
531 reg = <0x50023000 0x400>;
532 clocks = <&rcc LPTIM4_K>;
533 clock-names = "mux";
534 status = "disabled";
535
536 pwm {
537 compatible = "st,stm32-pwm-lp";
538 #pwm-cells = <3>;
539 status = "disabled";
540 };
541 };
542
543 lptimer5: timer@50024000 {
544 compatible = "st,stm32-lptimer";
545 reg = <0x50024000 0x400>;
546 clocks = <&rcc LPTIM5_K>;
547 clock-names = "mux";
548 status = "disabled";
549
550 pwm {
551 compatible = "st,stm32-pwm-lp";
552 #pwm-cells = <3>;
553 status = "disabled";
554 };
555 };
556
Fabrice Gasnier9f790af2018-04-18 09:47:00 +0200[diff] [blame]557 vrefbuf: vrefbuf@50025000 {
558 compatible = "st,stm32-vrefbuf";
559 reg = <0x50025000 0x8>;
560 regulator-min-microvolt = <1500000>;
561 regulator-max-microvolt = <2500000>;
562 clocks = <&rcc VREF>;
563 status = "disabled";
564 };
565
Ludovic Barre8471a202018-02-26 16:35:40 +0100[diff] [blame]566 usart1: serial@5c000000 {
567 compatible = "st,stm32h7-uart";
568 reg = <0x5c000000 0x400>;
569 interrupts = <GIC_SPI 37 IRQ_TYPE_NONE>;
Gabriel Fernandez3599a8a2018-03-15 08:18:00 +0100[diff] [blame]570 clocks = <&rcc USART1_K>;
Ludovic Barre8471a202018-02-26 16:35:40 +0100[diff] [blame]571 status = "disabled";
572 };
573 };
574};