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Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001/* QLogic qed NIC Driver
Mintz, Yuvale8f1cb52017-01-01 13:57:00 +02002 * Copyright (c) 2015-2017 QLogic Corporation
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02003 *
Mintz, Yuvale8f1cb52017-01-01 13:57:00 +02004 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020031 */
32
33#include <linux/types.h>
34#include <asm/byteorder.h>
35#include <linux/io.h>
36#include <linux/delay.h>
37#include <linux/dma-mapping.h>
38#include <linux/errno.h>
39#include <linux/kernel.h>
40#include <linux/mutex.h>
41#include <linux/pci.h>
42#include <linux/slab.h>
43#include <linux/string.h>
Yuval Mintza91eb522016-06-03 14:35:32 +030044#include <linux/vmalloc.h>
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020045#include <linux/etherdevice.h>
46#include <linux/qed/qed_chain.h>
47#include <linux/qed/qed_if.h>
48#include "qed.h"
49#include "qed_cxt.h"
Sudarsana Reddy Kalluru39651ab2016-05-17 06:44:26 -040050#include "qed_dcbx.h"
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020051#include "qed_dev_api.h"
Arun Easi1e128c82017-02-15 06:28:22 -080052#include "qed_fcoe.h"
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020053#include "qed_hsi.h"
54#include "qed_hw.h"
55#include "qed_init_ops.h"
56#include "qed_int.h"
Yuval Mintzfc831822016-12-01 00:21:06 -080057#include "qed_iscsi.h"
Yuval Mintz0a7fb112016-10-01 21:59:55 +030058#include "qed_ll2.h"
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020059#include "qed_mcp.h"
Yuval Mintz1d6cff42016-12-01 00:21:07 -080060#include "qed_ooo.h"
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020061#include "qed_reg_addr.h"
62#include "qed_sp.h"
Yuval Mintz32a47e72016-05-11 16:36:12 +030063#include "qed_sriov.h"
Yuval Mintz0b55e272016-05-11 16:36:15 +030064#include "qed_vf.h"
Ram Amrani51ff1722016-10-01 21:59:57 +030065#include "qed_roce.h"
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020066
Wei Yongjun0caf5b22016-08-02 13:49:00 +000067static DEFINE_SPINLOCK(qm_lock);
Sudarsana Reddy Kalluru39651ab2016-05-17 06:44:26 -040068
Ram Amrani51ff1722016-10-01 21:59:57 +030069#define QED_MIN_DPIS (4)
70#define QED_MIN_PWM_REGION (QED_WID_SIZE * QED_MIN_DPIS)
71
Yuval Mintzfe56b9e2015-10-26 11:02:25 +020072/* API common to all protocols */
Ram Amranic2035ee2016-03-02 20:26:00 +020073enum BAR_ID {
74 BAR_ID_0, /* used for GRC */
75 BAR_ID_1 /* Used for doorbells */
76};
77
Yuval Mintz1a635e42016-08-15 10:42:43 +030078static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn, enum BAR_ID bar_id)
Ram Amranic2035ee2016-03-02 20:26:00 +020079{
Yuval Mintz1408cc1f2016-05-11 16:36:14 +030080 u32 bar_reg = (bar_id == BAR_ID_0 ?
81 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
82 u32 val;
Ram Amranic2035ee2016-03-02 20:26:00 +020083
Yuval Mintz1408cc1f2016-05-11 16:36:14 +030084 if (IS_VF(p_hwfn->cdev))
85 return 1 << 17;
86
87 val = qed_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg);
Ram Amranic2035ee2016-03-02 20:26:00 +020088 if (val)
89 return 1 << (val + 15);
90
91 /* Old MFW initialized above registered only conditionally */
92 if (p_hwfn->cdev->num_hwfns > 1) {
93 DP_INFO(p_hwfn,
94 "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
95 return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
96 } else {
97 DP_INFO(p_hwfn,
98 "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
99 return 512 * 1024;
100 }
101}
102
Yuval Mintz1a635e42016-08-15 10:42:43 +0300103void qed_init_dp(struct qed_dev *cdev, u32 dp_module, u8 dp_level)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200104{
105 u32 i;
106
107 cdev->dp_level = dp_level;
108 cdev->dp_module = dp_module;
109 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
110 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
111
112 p_hwfn->dp_level = dp_level;
113 p_hwfn->dp_module = dp_module;
114 }
115}
116
117void qed_init_struct(struct qed_dev *cdev)
118{
119 u8 i;
120
121 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
122 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
123
124 p_hwfn->cdev = cdev;
125 p_hwfn->my_id = i;
126 p_hwfn->b_active = false;
127
128 mutex_init(&p_hwfn->dmae_info.mutex);
129 }
130
131 /* hwfn 0 is always active */
132 cdev->hwfns[0].b_active = true;
133
134 /* set the default cache alignment to 128 */
135 cdev->cache_shift = 7;
136}
137
138static void qed_qm_info_free(struct qed_hwfn *p_hwfn)
139{
140 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
141
142 kfree(qm_info->qm_pq_params);
143 qm_info->qm_pq_params = NULL;
144 kfree(qm_info->qm_vport_params);
145 qm_info->qm_vport_params = NULL;
146 kfree(qm_info->qm_port_params);
147 qm_info->qm_port_params = NULL;
Manish Choprabcd197c2016-04-26 10:56:08 -0400148 kfree(qm_info->wfq_data);
149 qm_info->wfq_data = NULL;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200150}
151
152void qed_resc_free(struct qed_dev *cdev)
153{
154 int i;
155
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300156 if (IS_VF(cdev))
157 return;
158
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200159 kfree(cdev->fw_data);
160 cdev->fw_data = NULL;
161
162 kfree(cdev->reset_stats);
163
164 for_each_hwfn(cdev, i) {
165 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
166
167 qed_cxt_mngr_free(p_hwfn);
168 qed_qm_info_free(p_hwfn);
169 qed_spq_free(p_hwfn);
170 qed_eq_free(p_hwfn, p_hwfn->p_eq);
171 qed_consq_free(p_hwfn, p_hwfn->p_consq);
172 qed_int_free(p_hwfn);
Yuval Mintz0a7fb112016-10-01 21:59:55 +0300173#ifdef CONFIG_QED_LL2
174 qed_ll2_free(p_hwfn, p_hwfn->p_ll2_info);
175#endif
Arun Easi1e128c82017-02-15 06:28:22 -0800176 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
177 qed_fcoe_free(p_hwfn, p_hwfn->p_fcoe_info);
178
Yuval Mintz1d6cff42016-12-01 00:21:07 -0800179 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
Yuval Mintzfc831822016-12-01 00:21:06 -0800180 qed_iscsi_free(p_hwfn, p_hwfn->p_iscsi_info);
Yuval Mintz1d6cff42016-12-01 00:21:07 -0800181 qed_ooo_free(p_hwfn, p_hwfn->p_ooo_info);
182 }
Yuval Mintz32a47e72016-05-11 16:36:12 +0300183 qed_iov_free(p_hwfn);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200184 qed_dmae_info_free(p_hwfn);
Sudarsana Reddy Kalluru39651ab2016-05-17 06:44:26 -0400185 qed_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200186 }
187}
188
Sudarsana Reddy Kalluru79529292016-05-26 11:01:20 +0300189static int qed_init_qm_info(struct qed_hwfn *p_hwfn, bool b_sleepable)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200190{
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300191 u8 num_vports, vf_offset = 0, i, vport_id, num_ports, curr_queue = 0;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200192 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
193 struct init_qm_port_params *p_qm_port;
Yuval Mintzdbb799c2016-06-03 14:35:35 +0300194 bool init_rdma_offload_pq = false;
195 bool init_pure_ack_pq = false;
196 bool init_ooo_pq = false;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200197 u16 num_pqs, multi_cos_tcs = 1;
Yuval Mintzcc3d5eb2016-05-26 11:01:21 +0300198 u8 pf_wfq = qm_info->pf_wfq;
199 u32 pf_rl = qm_info->pf_rl;
Yuval Mintzdbb799c2016-06-03 14:35:35 +0300200 u16 num_pf_rls = 0;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300201 u16 num_vfs = 0;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200202
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300203#ifdef CONFIG_QED_SRIOV
204 if (p_hwfn->cdev->p_iov_info)
205 num_vfs = p_hwfn->cdev->p_iov_info->total_vfs;
206#endif
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200207 memset(qm_info, 0, sizeof(*qm_info));
208
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300209 num_pqs = multi_cos_tcs + num_vfs + 1; /* The '1' is for pure-LB */
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200210 num_vports = (u8)RESC_NUM(p_hwfn, QED_VPORT);
211
Yuval Mintzdbb799c2016-06-03 14:35:35 +0300212 if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) {
213 num_pqs++; /* for RoCE queue */
214 init_rdma_offload_pq = true;
215 /* we subtract num_vfs because each require a rate limiter,
216 * and one default rate limiter
217 */
218 if (p_hwfn->pf_params.rdma_pf_params.enable_dcqcn)
219 num_pf_rls = RESC_NUM(p_hwfn, QED_RL) - num_vfs - 1;
220
221 num_pqs += num_pf_rls;
222 qm_info->num_pf_rls = (u8) num_pf_rls;
223 }
224
225 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
226 num_pqs += 2; /* for iSCSI pure-ACK / OOO queue */
227 init_pure_ack_pq = true;
228 init_ooo_pq = true;
229 }
230
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200231 /* Sanity checking that setup requires legal number of resources */
232 if (num_pqs > RESC_NUM(p_hwfn, QED_PQ)) {
233 DP_ERR(p_hwfn,
234 "Need too many Physical queues - 0x%04x when only %04x are available\n",
235 num_pqs, RESC_NUM(p_hwfn, QED_PQ));
236 return -EINVAL;
237 }
238
239 /* PQs will be arranged as follows: First per-TC PQ then pure-LB quete.
240 */
Sudarsana Reddy Kalluru79529292016-05-26 11:01:20 +0300241 qm_info->qm_pq_params = kcalloc(num_pqs,
242 sizeof(struct init_qm_pq_params),
243 b_sleepable ? GFP_KERNEL : GFP_ATOMIC);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200244 if (!qm_info->qm_pq_params)
245 goto alloc_err;
246
Sudarsana Reddy Kalluru79529292016-05-26 11:01:20 +0300247 qm_info->qm_vport_params = kcalloc(num_vports,
248 sizeof(struct init_qm_vport_params),
249 b_sleepable ? GFP_KERNEL
250 : GFP_ATOMIC);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200251 if (!qm_info->qm_vport_params)
252 goto alloc_err;
253
Sudarsana Reddy Kalluru79529292016-05-26 11:01:20 +0300254 qm_info->qm_port_params = kcalloc(MAX_NUM_PORTS,
255 sizeof(struct init_qm_port_params),
256 b_sleepable ? GFP_KERNEL
257 : GFP_ATOMIC);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200258 if (!qm_info->qm_port_params)
259 goto alloc_err;
260
Sudarsana Reddy Kalluru79529292016-05-26 11:01:20 +0300261 qm_info->wfq_data = kcalloc(num_vports, sizeof(struct qed_wfq_data),
262 b_sleepable ? GFP_KERNEL : GFP_ATOMIC);
Manish Choprabcd197c2016-04-26 10:56:08 -0400263 if (!qm_info->wfq_data)
264 goto alloc_err;
265
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200266 vport_id = (u8)RESC_START(p_hwfn, QED_VPORT);
267
Yuval Mintzdbb799c2016-06-03 14:35:35 +0300268 /* First init rate limited queues */
269 for (curr_queue = 0; curr_queue < num_pf_rls; curr_queue++) {
270 qm_info->qm_pq_params[curr_queue].vport_id = vport_id++;
271 qm_info->qm_pq_params[curr_queue].tc_id =
272 p_hwfn->hw_info.non_offload_tc;
273 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
274 qm_info->qm_pq_params[curr_queue].rl_valid = 1;
275 }
276
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200277 /* First init per-TC PQs */
Sudarsana Reddy Kalluru39651ab2016-05-17 06:44:26 -0400278 for (i = 0; i < multi_cos_tcs; i++) {
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300279 struct init_qm_pq_params *params =
Sudarsana Reddy Kalluru39651ab2016-05-17 06:44:26 -0400280 &qm_info->qm_pq_params[curr_queue++];
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200281
Yuval Mintzdbb799c2016-06-03 14:35:35 +0300282 if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE ||
283 p_hwfn->hw_info.personality == QED_PCI_ETH) {
Sudarsana Reddy Kalluru39651ab2016-05-17 06:44:26 -0400284 params->vport_id = vport_id;
285 params->tc_id = p_hwfn->hw_info.non_offload_tc;
286 params->wrr_group = 1;
287 } else {
288 params->vport_id = vport_id;
289 params->tc_id = p_hwfn->hw_info.offload_tc;
290 params->wrr_group = 1;
291 }
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200292 }
293
294 /* Then init pure-LB PQ */
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300295 qm_info->pure_lb_pq = curr_queue;
296 qm_info->qm_pq_params[curr_queue].vport_id =
297 (u8) RESC_START(p_hwfn, QED_VPORT);
298 qm_info->qm_pq_params[curr_queue].tc_id = PURE_LB_TC;
299 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
300 curr_queue++;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200301
302 qm_info->offload_pq = 0;
Yuval Mintzdbb799c2016-06-03 14:35:35 +0300303 if (init_rdma_offload_pq) {
304 qm_info->offload_pq = curr_queue;
305 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
306 qm_info->qm_pq_params[curr_queue].tc_id =
307 p_hwfn->hw_info.offload_tc;
308 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
309 curr_queue++;
310 }
311
312 if (init_pure_ack_pq) {
313 qm_info->pure_ack_pq = curr_queue;
314 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
315 qm_info->qm_pq_params[curr_queue].tc_id =
316 p_hwfn->hw_info.offload_tc;
317 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
318 curr_queue++;
319 }
320
321 if (init_ooo_pq) {
322 qm_info->ooo_pq = curr_queue;
323 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
324 qm_info->qm_pq_params[curr_queue].tc_id = DCBX_ISCSI_OOO_TC;
325 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
326 curr_queue++;
327 }
328
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300329 /* Then init per-VF PQs */
330 vf_offset = curr_queue;
331 for (i = 0; i < num_vfs; i++) {
332 /* First vport is used by the PF */
333 qm_info->qm_pq_params[curr_queue].vport_id = vport_id + i + 1;
334 qm_info->qm_pq_params[curr_queue].tc_id =
335 p_hwfn->hw_info.non_offload_tc;
336 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300337 qm_info->qm_pq_params[curr_queue].rl_valid = 1;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300338 curr_queue++;
339 }
340
341 qm_info->vf_queues_offset = vf_offset;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200342 qm_info->num_pqs = num_pqs;
343 qm_info->num_vports = num_vports;
344
345 /* Initialize qm port parameters */
346 num_ports = p_hwfn->cdev->num_ports_in_engines;
347 for (i = 0; i < num_ports; i++) {
348 p_qm_port = &qm_info->qm_port_params[i];
349 p_qm_port->active = 1;
Yuval Mintz351a4ded2016-06-02 10:23:29 +0300350 if (num_ports == 4)
351 p_qm_port->active_phys_tcs = 0x7;
352 else
353 p_qm_port->active_phys_tcs = 0x9f;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200354 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
355 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
356 }
357
358 qm_info->max_phys_tcs_per_port = NUM_OF_PHYS_TCS;
359
360 qm_info->start_pq = (u16)RESC_START(p_hwfn, QED_PQ);
361
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300362 qm_info->num_vf_pqs = num_vfs;
363 qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200364
Manish Chopraa64b02d2016-04-26 10:56:10 -0400365 for (i = 0; i < qm_info->num_vports; i++)
366 qm_info->qm_vport_params[i].vport_wfq = 1;
367
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200368 qm_info->vport_rl_en = 1;
Manish Chopraa64b02d2016-04-26 10:56:10 -0400369 qm_info->vport_wfq_en = 1;
Yuval Mintzcc3d5eb2016-05-26 11:01:21 +0300370 qm_info->pf_rl = pf_rl;
371 qm_info->pf_wfq = pf_wfq;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200372
373 return 0;
374
375alloc_err:
Manish Choprabcd197c2016-04-26 10:56:08 -0400376 qed_qm_info_free(p_hwfn);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200377 return -ENOMEM;
378}
379
Sudarsana Reddy Kalluru39651ab2016-05-17 06:44:26 -0400380/* This function reconfigures the QM pf on the fly.
381 * For this purpose we:
382 * 1. reconfigure the QM database
383 * 2. set new values to runtime arrat
384 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
385 * 4. activate init tool in QM_PF stage
386 * 5. send an sdm_qm_cmd through rbc interface to release the QM
387 */
388int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
389{
390 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
391 bool b_rc;
392 int rc;
393
394 /* qm_info is allocated in qed_init_qm_info() which is already called
395 * from qed_resc_alloc() or previous call of qed_qm_reconf().
396 * The allocated size may change each init, so we free it before next
397 * allocation.
398 */
399 qed_qm_info_free(p_hwfn);
400
401 /* initialize qed's qm data structure */
Sudarsana Reddy Kalluru79529292016-05-26 11:01:20 +0300402 rc = qed_init_qm_info(p_hwfn, false);
Sudarsana Reddy Kalluru39651ab2016-05-17 06:44:26 -0400403 if (rc)
404 return rc;
405
406 /* stop PF's qm queues */
407 spin_lock_bh(&qm_lock);
408 b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
409 qm_info->start_pq, qm_info->num_pqs);
410 spin_unlock_bh(&qm_lock);
411 if (!b_rc)
412 return -EINVAL;
413
414 /* clear the QM_PF runtime phase leftovers from previous init */
415 qed_init_clear_rt_data(p_hwfn);
416
417 /* prepare QM portion of runtime array */
418 qed_qm_init_pf(p_hwfn);
419
420 /* activate init tool on runtime array */
421 rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
422 p_hwfn->hw_info.hw_mode);
423 if (rc)
424 return rc;
425
426 /* start PF's qm queues */
427 spin_lock_bh(&qm_lock);
428 b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
429 qm_info->start_pq, qm_info->num_pqs);
430 spin_unlock_bh(&qm_lock);
431 if (!b_rc)
432 return -EINVAL;
433
434 return 0;
435}
436
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200437int qed_resc_alloc(struct qed_dev *cdev)
438{
Yuval Mintzfc831822016-12-01 00:21:06 -0800439 struct qed_iscsi_info *p_iscsi_info;
Arun Easi1e128c82017-02-15 06:28:22 -0800440 struct qed_fcoe_info *p_fcoe_info;
Yuval Mintz1d6cff42016-12-01 00:21:07 -0800441 struct qed_ooo_info *p_ooo_info;
Yuval Mintz0a7fb112016-10-01 21:59:55 +0300442#ifdef CONFIG_QED_LL2
443 struct qed_ll2_info *p_ll2_info;
444#endif
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200445 struct qed_consq *p_consq;
446 struct qed_eq *p_eq;
447 int i, rc = 0;
448
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300449 if (IS_VF(cdev))
450 return rc;
451
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200452 cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL);
453 if (!cdev->fw_data)
454 return -ENOMEM;
455
456 for_each_hwfn(cdev, i) {
457 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
Yuval Mintzdbb799c2016-06-03 14:35:35 +0300458 u32 n_eqes, num_cons;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200459
460 /* First allocate the context manager structure */
461 rc = qed_cxt_mngr_alloc(p_hwfn);
462 if (rc)
463 goto alloc_err;
464
465 /* Set the HW cid/tid numbers (in the contest manager)
466 * Must be done prior to any further computations.
467 */
468 rc = qed_cxt_set_pf_params(p_hwfn);
469 if (rc)
470 goto alloc_err;
471
472 /* Prepare and process QM requirements */
Sudarsana Reddy Kalluru79529292016-05-26 11:01:20 +0300473 rc = qed_init_qm_info(p_hwfn, true);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200474 if (rc)
475 goto alloc_err;
476
477 /* Compute the ILT client partition */
478 rc = qed_cxt_cfg_ilt_compute(p_hwfn);
479 if (rc)
480 goto alloc_err;
481
482 /* CID map / ILT shadow table / T2
483 * The talbes sizes are determined by the computations above
484 */
485 rc = qed_cxt_tables_alloc(p_hwfn);
486 if (rc)
487 goto alloc_err;
488
489 /* SPQ, must follow ILT because initializes SPQ context */
490 rc = qed_spq_alloc(p_hwfn);
491 if (rc)
492 goto alloc_err;
493
494 /* SP status block allocation */
495 p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn,
496 RESERVED_PTT_DPC);
497
498 rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
499 if (rc)
500 goto alloc_err;
501
Yuval Mintz32a47e72016-05-11 16:36:12 +0300502 rc = qed_iov_alloc(p_hwfn);
503 if (rc)
504 goto alloc_err;
505
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200506 /* EQ */
Yuval Mintzdbb799c2016-06-03 14:35:35 +0300507 n_eqes = qed_chain_get_capacity(&p_hwfn->p_spq->chain);
508 if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) {
509 num_cons = qed_cxt_get_proto_cid_count(p_hwfn,
510 PROTOCOLID_ROCE,
Yuval Mintz8c93bea2016-10-13 22:57:03 +0300511 NULL) * 2;
Yuval Mintzdbb799c2016-06-03 14:35:35 +0300512 n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
513 } else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
514 num_cons =
515 qed_cxt_get_proto_cid_count(p_hwfn,
Yuval Mintz8c93bea2016-10-13 22:57:03 +0300516 PROTOCOLID_ISCSI,
517 NULL);
Yuval Mintzdbb799c2016-06-03 14:35:35 +0300518 n_eqes += 2 * num_cons;
519 }
520
521 if (n_eqes > 0xFFFF) {
522 DP_ERR(p_hwfn,
523 "Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n",
524 n_eqes, 0xFFFF);
Wei Yongjun1b4985b2016-08-02 00:55:34 +0000525 rc = -EINVAL;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200526 goto alloc_err;
Dan Carpenter9b15acb2015-11-05 11:41:28 +0300527 }
Yuval Mintzdbb799c2016-06-03 14:35:35 +0300528
529 p_eq = qed_eq_alloc(p_hwfn, (u16) n_eqes);
530 if (!p_eq)
531 goto alloc_no_mem;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200532 p_hwfn->p_eq = p_eq;
533
534 p_consq = qed_consq_alloc(p_hwfn);
Yuval Mintzdbb799c2016-06-03 14:35:35 +0300535 if (!p_consq)
536 goto alloc_no_mem;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200537 p_hwfn->p_consq = p_consq;
538
Yuval Mintz0a7fb112016-10-01 21:59:55 +0300539#ifdef CONFIG_QED_LL2
540 if (p_hwfn->using_ll2) {
541 p_ll2_info = qed_ll2_alloc(p_hwfn);
542 if (!p_ll2_info)
543 goto alloc_no_mem;
544 p_hwfn->p_ll2_info = p_ll2_info;
545 }
546#endif
Arun Easi1e128c82017-02-15 06:28:22 -0800547
548 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
549 p_fcoe_info = qed_fcoe_alloc(p_hwfn);
550 if (!p_fcoe_info)
551 goto alloc_no_mem;
552 p_hwfn->p_fcoe_info = p_fcoe_info;
553 }
554
Yuval Mintzfc831822016-12-01 00:21:06 -0800555 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
556 p_iscsi_info = qed_iscsi_alloc(p_hwfn);
557 if (!p_iscsi_info)
558 goto alloc_no_mem;
559 p_hwfn->p_iscsi_info = p_iscsi_info;
Yuval Mintz1d6cff42016-12-01 00:21:07 -0800560 p_ooo_info = qed_ooo_alloc(p_hwfn);
561 if (!p_ooo_info)
562 goto alloc_no_mem;
563 p_hwfn->p_ooo_info = p_ooo_info;
Yuval Mintzfc831822016-12-01 00:21:06 -0800564 }
Yuval Mintz0a7fb112016-10-01 21:59:55 +0300565
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200566 /* DMA info initialization */
567 rc = qed_dmae_info_alloc(p_hwfn);
Joe Perches2591c282016-09-04 14:24:03 -0700568 if (rc)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200569 goto alloc_err;
Sudarsana Reddy Kalluru39651ab2016-05-17 06:44:26 -0400570
571 /* DCBX initialization */
572 rc = qed_dcbx_info_alloc(p_hwfn);
Joe Perches2591c282016-09-04 14:24:03 -0700573 if (rc)
Sudarsana Reddy Kalluru39651ab2016-05-17 06:44:26 -0400574 goto alloc_err;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200575 }
576
577 cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL);
Joe Perches2591c282016-09-04 14:24:03 -0700578 if (!cdev->reset_stats)
Yuval Mintz83aeb932016-08-15 10:42:44 +0300579 goto alloc_no_mem;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200580
581 return 0;
582
Yuval Mintzdbb799c2016-06-03 14:35:35 +0300583alloc_no_mem:
584 rc = -ENOMEM;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200585alloc_err:
586 qed_resc_free(cdev);
587 return rc;
588}
589
590void qed_resc_setup(struct qed_dev *cdev)
591{
592 int i;
593
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300594 if (IS_VF(cdev))
595 return;
596
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200597 for_each_hwfn(cdev, i) {
598 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
599
600 qed_cxt_mngr_setup(p_hwfn);
601 qed_spq_setup(p_hwfn);
602 qed_eq_setup(p_hwfn, p_hwfn->p_eq);
603 qed_consq_setup(p_hwfn, p_hwfn->p_consq);
604
605 /* Read shadow of current MFW mailbox */
606 qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
607 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
608 p_hwfn->mcp_info->mfw_mb_cur,
609 p_hwfn->mcp_info->mfw_mb_length);
610
611 qed_int_setup(p_hwfn, p_hwfn->p_main_ptt);
Yuval Mintz32a47e72016-05-11 16:36:12 +0300612
613 qed_iov_setup(p_hwfn, p_hwfn->p_main_ptt);
Yuval Mintz0a7fb112016-10-01 21:59:55 +0300614#ifdef CONFIG_QED_LL2
615 if (p_hwfn->using_ll2)
616 qed_ll2_setup(p_hwfn, p_hwfn->p_ll2_info);
617#endif
Arun Easi1e128c82017-02-15 06:28:22 -0800618 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
619 qed_fcoe_setup(p_hwfn, p_hwfn->p_fcoe_info);
620
Yuval Mintz1d6cff42016-12-01 00:21:07 -0800621 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
Yuval Mintzfc831822016-12-01 00:21:06 -0800622 qed_iscsi_setup(p_hwfn, p_hwfn->p_iscsi_info);
Yuval Mintz1d6cff42016-12-01 00:21:07 -0800623 qed_ooo_setup(p_hwfn, p_hwfn->p_ooo_info);
624 }
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200625 }
626}
627
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200628#define FINAL_CLEANUP_POLL_CNT (100)
629#define FINAL_CLEANUP_POLL_TIME (10)
630int qed_final_cleanup(struct qed_hwfn *p_hwfn,
Yuval Mintz0b55e272016-05-11 16:36:15 +0300631 struct qed_ptt *p_ptt, u16 id, bool is_vf)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200632{
633 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
634 int rc = -EBUSY;
635
Yuval Mintzfc48b7a2016-02-15 13:22:35 -0500636 addr = GTT_BAR0_MAP_REG_USDM_RAM +
637 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200638
Yuval Mintz0b55e272016-05-11 16:36:15 +0300639 if (is_vf)
640 id += 0x10;
641
Yuval Mintzfc48b7a2016-02-15 13:22:35 -0500642 command |= X_FINAL_CLEANUP_AGG_INT <<
643 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
644 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
645 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
646 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200647
648 /* Make sure notification is not set before initiating final cleanup */
649 if (REG_RD(p_hwfn, addr)) {
Yuval Mintz1a635e42016-08-15 10:42:43 +0300650 DP_NOTICE(p_hwfn,
651 "Unexpected; Found final cleanup notification before initiating final cleanup\n");
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200652 REG_WR(p_hwfn, addr, 0);
653 }
654
655 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
656 "Sending final cleanup for PFVF[%d] [Command %08x\n]",
657 id, command);
658
659 qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
660
661 /* Poll until completion */
662 while (!REG_RD(p_hwfn, addr) && count--)
663 msleep(FINAL_CLEANUP_POLL_TIME);
664
665 if (REG_RD(p_hwfn, addr))
666 rc = 0;
667 else
668 DP_NOTICE(p_hwfn,
669 "Failed to receive FW final cleanup notification\n");
670
671 /* Cleanup afterwards */
672 REG_WR(p_hwfn, addr, 0);
673
674 return rc;
675}
676
Mintz, Yuval9c79dda2017-03-14 16:23:54 +0200677static int qed_calc_hw_mode(struct qed_hwfn *p_hwfn)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200678{
679 int hw_mode = 0;
680
Mintz, Yuval9c79dda2017-03-14 16:23:54 +0200681 if (QED_IS_BB_B0(p_hwfn->cdev)) {
682 hw_mode |= 1 << MODE_BB;
683 } else if (QED_IS_AH(p_hwfn->cdev)) {
684 hw_mode |= 1 << MODE_K2;
685 } else {
686 DP_NOTICE(p_hwfn, "Unknown chip type %#x\n",
687 p_hwfn->cdev->type);
688 return -EINVAL;
689 }
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200690
691 switch (p_hwfn->cdev->num_ports_in_engines) {
692 case 1:
693 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
694 break;
695 case 2:
696 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
697 break;
698 case 4:
699 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
700 break;
701 default:
702 DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n",
703 p_hwfn->cdev->num_ports_in_engines);
Mintz, Yuval9c79dda2017-03-14 16:23:54 +0200704 return -EINVAL;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200705 }
706
707 switch (p_hwfn->cdev->mf_mode) {
Yuval Mintzfc48b7a2016-02-15 13:22:35 -0500708 case QED_MF_DEFAULT:
709 case QED_MF_NPAR:
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200710 hw_mode |= 1 << MODE_MF_SI;
711 break;
Yuval Mintzfc48b7a2016-02-15 13:22:35 -0500712 case QED_MF_OVLAN:
713 hw_mode |= 1 << MODE_MF_SD;
714 break;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200715 default:
Yuval Mintzfc48b7a2016-02-15 13:22:35 -0500716 DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n");
717 hw_mode |= 1 << MODE_MF_SI;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200718 }
719
720 hw_mode |= 1 << MODE_ASIC;
721
Yuval Mintz1af9dcf2016-05-26 11:01:22 +0300722 if (p_hwfn->cdev->num_hwfns > 1)
723 hw_mode |= 1 << MODE_100G;
724
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200725 p_hwfn->hw_info.hw_mode = hw_mode;
Yuval Mintz1af9dcf2016-05-26 11:01:22 +0300726
727 DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP),
728 "Configuring function for hw_mode: 0x%08x\n",
729 p_hwfn->hw_info.hw_mode);
Mintz, Yuval9c79dda2017-03-14 16:23:54 +0200730
731 return 0;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200732}
733
734/* Init run time data for all PFs on an engine. */
735static void qed_init_cau_rt_data(struct qed_dev *cdev)
736{
737 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
738 int i, sb_id;
739
740 for_each_hwfn(cdev, i) {
741 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
742 struct qed_igu_info *p_igu_info;
743 struct qed_igu_block *p_block;
744 struct cau_sb_entry sb_entry;
745
746 p_igu_info = p_hwfn->hw_info.p_igu_info;
747
748 for (sb_id = 0; sb_id < QED_MAPPING_MEMORY_SIZE(cdev);
749 sb_id++) {
750 p_block = &p_igu_info->igu_map.igu_blocks[sb_id];
751 if (!p_block->is_pf)
752 continue;
753
754 qed_init_cau_sb_entry(p_hwfn, &sb_entry,
Yuval Mintz1a635e42016-08-15 10:42:43 +0300755 p_block->function_id, 0, 0);
756 STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, sb_entry);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200757 }
758 }
759}
760
761static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
Yuval Mintz1a635e42016-08-15 10:42:43 +0300762 struct qed_ptt *p_ptt, int hw_mode)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200763{
764 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
765 struct qed_qm_common_rt_init_params params;
766 struct qed_dev *cdev = p_hwfn->cdev;
Mintz, Yuval9c79dda2017-03-14 16:23:54 +0200767 u8 vf_id, max_num_vfs;
Yuval Mintzdbb799c2016-06-03 14:35:35 +0300768 u16 num_pfs, pf_id;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300769 u32 concrete_fid;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200770 int rc = 0;
771
772 qed_init_cau_rt_data(cdev);
773
774 /* Program GTT windows */
775 qed_gtt_init(p_hwfn);
776
777 if (p_hwfn->mcp_info) {
778 if (p_hwfn->mcp_info->func_info.bandwidth_max)
779 qm_info->pf_rl_en = 1;
780 if (p_hwfn->mcp_info->func_info.bandwidth_min)
781 qm_info->pf_wfq_en = 1;
782 }
783
784 memset(&params, 0, sizeof(params));
785 params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engines;
786 params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port;
787 params.pf_rl_en = qm_info->pf_rl_en;
788 params.pf_wfq_en = qm_info->pf_wfq_en;
789 params.vport_rl_en = qm_info->vport_rl_en;
790 params.vport_wfq_en = qm_info->vport_wfq_en;
791 params.port_params = qm_info->qm_port_params;
792
793 qed_qm_common_rt_init(p_hwfn, &params);
794
795 qed_cxt_hw_init_common(p_hwfn);
796
797 /* Close gate from NIG to BRB/Storm; By default they are open, but
798 * we close them to prevent NIG from passing data to reset blocks.
799 * Should have been done in the ENGINE phase, but init-tool lacks
800 * proper port-pretend capabilities.
801 */
802 qed_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
803 qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
804 qed_port_pretend(p_hwfn, p_ptt, p_hwfn->port_id ^ 1);
805 qed_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
806 qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
807 qed_port_unpretend(p_hwfn, p_ptt);
808
809 rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
Yuval Mintz1a635e42016-08-15 10:42:43 +0300810 if (rc)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200811 return rc;
812
813 qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
814 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
815
Yuval Mintzdbb799c2016-06-03 14:35:35 +0300816 if (QED_IS_BB(p_hwfn->cdev)) {
817 num_pfs = NUM_OF_ENG_PFS(p_hwfn->cdev);
818 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
819 qed_fid_pretend(p_hwfn, p_ptt, pf_id);
820 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
821 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
822 }
823 /* pretend to original PF */
824 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
825 }
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200826
Mintz, Yuval9c79dda2017-03-14 16:23:54 +0200827 max_num_vfs = QED_IS_AH(cdev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
828 for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300829 concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id);
830 qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid);
831 qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
Yuval Mintz05fafbf2016-08-19 09:33:31 +0300832 qed_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
833 qed_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
834 qed_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300835 }
836 /* pretend to original PF */
837 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
838
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200839 return rc;
840}
841
Ram Amrani51ff1722016-10-01 21:59:57 +0300842static int
843qed_hw_init_dpi_size(struct qed_hwfn *p_hwfn,
844 struct qed_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
845{
846 u32 dpi_page_size_1, dpi_page_size_2, dpi_page_size;
847 u32 dpi_bit_shift, dpi_count;
848 u32 min_dpis;
849
850 /* Calculate DPI size */
851 dpi_page_size_1 = QED_WID_SIZE * n_cpus;
852 dpi_page_size_2 = max_t(u32, QED_WID_SIZE, PAGE_SIZE);
853 dpi_page_size = max_t(u32, dpi_page_size_1, dpi_page_size_2);
854 dpi_page_size = roundup_pow_of_two(dpi_page_size);
855 dpi_bit_shift = ilog2(dpi_page_size / 4096);
856
857 dpi_count = pwm_region_size / dpi_page_size;
858
859 min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
860 min_dpis = max_t(u32, QED_MIN_DPIS, min_dpis);
861
862 p_hwfn->dpi_size = dpi_page_size;
863 p_hwfn->dpi_count = dpi_count;
864
865 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
866
867 if (dpi_count < min_dpis)
868 return -EINVAL;
869
870 return 0;
871}
872
873enum QED_ROCE_EDPM_MODE {
874 QED_ROCE_EDPM_MODE_ENABLE = 0,
875 QED_ROCE_EDPM_MODE_FORCE_ON = 1,
876 QED_ROCE_EDPM_MODE_DISABLE = 2,
877};
878
879static int
880qed_hw_init_pf_doorbell_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
881{
882 u32 pwm_regsize, norm_regsize;
883 u32 non_pwm_conn, min_addr_reg1;
884 u32 db_bar_size, n_cpus;
885 u32 roce_edpm_mode;
886 u32 pf_dems_shift;
887 int rc = 0;
888 u8 cond;
889
890 db_bar_size = qed_hw_bar_size(p_hwfn, BAR_ID_1);
891 if (p_hwfn->cdev->num_hwfns > 1)
892 db_bar_size /= 2;
893
894 /* Calculate doorbell regions */
895 non_pwm_conn = qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
896 qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
897 NULL) +
898 qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
899 NULL);
900 norm_regsize = roundup(QED_PF_DEMS_SIZE * non_pwm_conn, 4096);
901 min_addr_reg1 = norm_regsize / 4096;
902 pwm_regsize = db_bar_size - norm_regsize;
903
904 /* Check that the normal and PWM sizes are valid */
905 if (db_bar_size < norm_regsize) {
906 DP_ERR(p_hwfn->cdev,
907 "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
908 db_bar_size, norm_regsize);
909 return -EINVAL;
910 }
911
912 if (pwm_regsize < QED_MIN_PWM_REGION) {
913 DP_ERR(p_hwfn->cdev,
914 "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
915 pwm_regsize,
916 QED_MIN_PWM_REGION, db_bar_size, norm_regsize);
917 return -EINVAL;
918 }
919
920 /* Calculate number of DPIs */
921 roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
922 if ((roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE) ||
923 ((roce_edpm_mode == QED_ROCE_EDPM_MODE_FORCE_ON))) {
924 /* Either EDPM is mandatory, or we are attempting to allocate a
925 * WID per CPU.
926 */
Ram Amranic2dedf82017-02-20 22:43:33 +0200927 n_cpus = num_present_cpus();
Ram Amrani51ff1722016-10-01 21:59:57 +0300928 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
929 }
930
931 cond = (rc && (roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE)) ||
932 (roce_edpm_mode == QED_ROCE_EDPM_MODE_DISABLE);
933 if (cond || p_hwfn->dcbx_no_edpm) {
934 /* Either EDPM is disabled from user configuration, or it is
935 * disabled via DCBx, or it is not mandatory and we failed to
936 * allocated a WID per CPU.
937 */
938 n_cpus = 1;
939 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
940
941 if (cond)
942 qed_rdma_dpm_bar(p_hwfn, p_ptt);
943 }
944
945 DP_INFO(p_hwfn,
946 "doorbell bar: normal_region_size=%d, pwm_region_size=%d, dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
947 norm_regsize,
948 pwm_regsize,
949 p_hwfn->dpi_size,
950 p_hwfn->dpi_count,
951 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
952 "disabled" : "enabled");
953
954 if (rc) {
955 DP_ERR(p_hwfn,
956 "Failed to allocate enough DPIs. Allocated %d but the current minimum is %d.\n",
957 p_hwfn->dpi_count,
958 p_hwfn->pf_params.rdma_pf_params.min_dpis);
959 return -EINVAL;
960 }
961
962 p_hwfn->dpi_start_offset = norm_regsize;
963
964 /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
965 pf_dems_shift = ilog2(QED_PF_DEMS_SIZE / 4);
966 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
967 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
968
969 return 0;
970}
971
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200972static int qed_hw_init_port(struct qed_hwfn *p_hwfn,
Yuval Mintz1a635e42016-08-15 10:42:43 +0300973 struct qed_ptt *p_ptt, int hw_mode)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200974{
Yuval Mintz05fafbf2016-08-19 09:33:31 +0300975 return qed_init_run(p_hwfn, p_ptt, PHASE_PORT,
976 p_hwfn->port_id, hw_mode);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200977}
978
979static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
980 struct qed_ptt *p_ptt,
Manish Chopra464f6642016-04-14 01:38:29 -0400981 struct qed_tunn_start_params *p_tunn,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200982 int hw_mode,
983 bool b_hw_start,
984 enum qed_int_mode int_mode,
985 bool allow_npar_tx_switch)
986{
987 u8 rel_pf_id = p_hwfn->rel_pf_id;
988 int rc = 0;
989
990 if (p_hwfn->mcp_info) {
991 struct qed_mcp_function_info *p_info;
992
993 p_info = &p_hwfn->mcp_info->func_info;
994 if (p_info->bandwidth_min)
995 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
996
997 /* Update rate limit once we'll actually have a link */
Manish Chopra4b01e512016-04-26 10:56:09 -0400998 p_hwfn->qm_info.pf_rl = 100000;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +0200999 }
1000
1001 qed_cxt_hw_init_pf(p_hwfn);
1002
1003 qed_int_igu_init_rt(p_hwfn);
1004
1005 /* Set VLAN in NIG if needed */
Yuval Mintz1a635e42016-08-15 10:42:43 +03001006 if (hw_mode & BIT(MODE_MF_SD)) {
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001007 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1008 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1009 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1010 p_hwfn->hw_info.ovlan);
1011 }
1012
1013 /* Enable classification by MAC if needed */
Yuval Mintz1a635e42016-08-15 10:42:43 +03001014 if (hw_mode & BIT(MODE_MF_SI)) {
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001015 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
1016 "Configuring TAGMAC_CLS_TYPE\n");
1017 STORE_RT_REG(p_hwfn,
1018 NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1);
1019 }
1020
1021 /* Protocl Configuration */
Yuval Mintzdbb799c2016-06-03 14:35:35 +03001022 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
1023 (p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0);
Arun Easi1e128c82017-02-15 06:28:22 -08001024 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
1025 (p_hwfn->hw_info.personality == QED_PCI_FCOE) ? 1 : 0);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001026 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
1027
1028 /* Cleanup chip from previous driver if such remains exist */
Yuval Mintz0b55e272016-05-11 16:36:15 +03001029 rc = qed_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
Yuval Mintz1a635e42016-08-15 10:42:43 +03001030 if (rc)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001031 return rc;
1032
1033 /* PF Init sequence */
1034 rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1035 if (rc)
1036 return rc;
1037
1038 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1039 rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1040 if (rc)
1041 return rc;
1042
1043 /* Pure runtime initializations - directly to the HW */
1044 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1045
Ram Amrani51ff1722016-10-01 21:59:57 +03001046 rc = qed_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1047 if (rc)
1048 return rc;
1049
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001050 if (b_hw_start) {
1051 /* enable interrupts */
1052 qed_int_igu_enable(p_hwfn, p_ptt, int_mode);
1053
1054 /* send function start command */
Yuval Mintz831bfb0e2016-05-11 16:36:25 +03001055 rc = qed_sp_pf_start(p_hwfn, p_tunn, p_hwfn->cdev->mf_mode,
1056 allow_npar_tx_switch);
Arun Easi1e128c82017-02-15 06:28:22 -08001057 if (rc) {
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001058 DP_NOTICE(p_hwfn, "Function start ramrod failed\n");
Arun Easi1e128c82017-02-15 06:28:22 -08001059 return rc;
1060 }
1061 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
1062 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1, BIT(2));
1063 qed_wr(p_hwfn, p_ptt,
1064 PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
1065 0x100);
1066 }
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001067 }
1068 return rc;
1069}
1070
1071static int qed_change_pci_hwfn(struct qed_hwfn *p_hwfn,
1072 struct qed_ptt *p_ptt,
1073 u8 enable)
1074{
1075 u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
1076
1077 /* Change PF in PXP */
1078 qed_wr(p_hwfn, p_ptt,
1079 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1080
1081 /* wait until value is set - try for 1 second every 50us */
1082 for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1083 val = qed_rd(p_hwfn, p_ptt,
1084 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1085 if (val == set_val)
1086 break;
1087
1088 usleep_range(50, 60);
1089 }
1090
1091 if (val != set_val) {
1092 DP_NOTICE(p_hwfn,
1093 "PFID_ENABLE_MASTER wasn't changed after a second\n");
1094 return -EAGAIN;
1095 }
1096
1097 return 0;
1098}
1099
1100static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn,
1101 struct qed_ptt *p_main_ptt)
1102{
1103 /* Read shadow of current MFW mailbox */
1104 qed_mcp_read_mb(p_hwfn, p_main_ptt);
1105 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
Yuval Mintz1a635e42016-08-15 10:42:43 +03001106 p_hwfn->mcp_info->mfw_mb_cur, p_hwfn->mcp_info->mfw_mb_length);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001107}
1108
Tomer Tayar5d24bcf2017-03-28 15:12:52 +03001109static void
1110qed_fill_load_req_params(struct qed_load_req_params *p_load_req,
1111 struct qed_drv_load_params *p_drv_load)
1112{
1113 memset(p_load_req, 0, sizeof(*p_load_req));
1114
1115 p_load_req->drv_role = p_drv_load->is_crash_kernel ?
1116 QED_DRV_ROLE_KDUMP : QED_DRV_ROLE_OS;
1117 p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
1118 p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
1119 p_load_req->override_force_load = p_drv_load->override_force_load;
1120}
1121
Mintz, Yuvalc0c2d0b2017-03-28 15:12:51 +03001122int qed_hw_init(struct qed_dev *cdev, struct qed_hw_init_params *p_params)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001123{
Tomer Tayar5d24bcf2017-03-28 15:12:52 +03001124 struct qed_load_req_params load_req_params;
Sudarsana Kalluru0fefbfb2016-10-31 07:14:21 +02001125 u32 load_code, param, drv_mb_param;
1126 bool b_default_mtu = true;
1127 struct qed_hwfn *p_hwfn;
1128 int rc = 0, mfw_rc, i;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001129
Mintz, Yuvalc0c2d0b2017-03-28 15:12:51 +03001130 if ((p_params->int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) {
Sudarsana Reddy Kallurubb13ace2016-05-26 11:01:23 +03001131 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n");
1132 return -EINVAL;
1133 }
1134
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001135 if (IS_PF(cdev)) {
Mintz, Yuvalc0c2d0b2017-03-28 15:12:51 +03001136 rc = qed_init_fw_data(cdev, p_params->bin_fw_data);
Yuval Mintz1a635e42016-08-15 10:42:43 +03001137 if (rc)
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001138 return rc;
1139 }
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001140
1141 for_each_hwfn(cdev, i) {
1142 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1143
Sudarsana Kalluru0fefbfb2016-10-31 07:14:21 +02001144 /* If management didn't provide a default, set one of our own */
1145 if (!p_hwfn->hw_info.mtu) {
1146 p_hwfn->hw_info.mtu = 1500;
1147 b_default_mtu = false;
1148 }
1149
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001150 if (IS_VF(cdev)) {
1151 p_hwfn->b_int_enabled = 1;
1152 continue;
1153 }
1154
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001155 /* Enable DMAE in PXP */
1156 rc = qed_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
1157
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02001158 rc = qed_calc_hw_mode(p_hwfn);
1159 if (rc)
1160 return rc;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001161
Tomer Tayar5d24bcf2017-03-28 15:12:52 +03001162 qed_fill_load_req_params(&load_req_params,
1163 p_params->p_drv_load_params);
1164 rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
1165 &load_req_params);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001166 if (rc) {
Tomer Tayar5d24bcf2017-03-28 15:12:52 +03001167 DP_NOTICE(p_hwfn, "Failed sending a LOAD_REQ command\n");
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001168 return rc;
1169 }
1170
Tomer Tayar5d24bcf2017-03-28 15:12:52 +03001171 load_code = load_req_params.load_code;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001172 DP_VERBOSE(p_hwfn, QED_MSG_SP,
Tomer Tayar5d24bcf2017-03-28 15:12:52 +03001173 "Load request was sent. Load code: 0x%x\n",
1174 load_code);
1175
1176 qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001177
1178 p_hwfn->first_on_engine = (load_code ==
1179 FW_MSG_CODE_DRV_LOAD_ENGINE);
1180
1181 switch (load_code) {
1182 case FW_MSG_CODE_DRV_LOAD_ENGINE:
1183 rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
1184 p_hwfn->hw_info.hw_mode);
1185 if (rc)
1186 break;
1187 /* Fall into */
1188 case FW_MSG_CODE_DRV_LOAD_PORT:
1189 rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
1190 p_hwfn->hw_info.hw_mode);
1191 if (rc)
1192 break;
1193
1194 /* Fall into */
1195 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1196 rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
Mintz, Yuvalc0c2d0b2017-03-28 15:12:51 +03001197 p_params->p_tunn,
1198 p_hwfn->hw_info.hw_mode,
1199 p_params->b_hw_start,
1200 p_params->int_mode,
1201 p_params->allow_npar_tx_switch);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001202 break;
1203 default:
Mintz, Yuvalc0c2d0b2017-03-28 15:12:51 +03001204 DP_NOTICE(p_hwfn,
1205 "Unexpected load code [0x%08x]", load_code);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001206 rc = -EINVAL;
1207 break;
1208 }
1209
1210 if (rc)
1211 DP_NOTICE(p_hwfn,
1212 "init phase failed for loadcode 0x%x (rc %d)\n",
1213 load_code, rc);
1214
1215 /* ACK mfw regardless of success or failure of initialization */
1216 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1217 DRV_MSG_CODE_LOAD_DONE,
1218 0, &load_code, &param);
1219 if (rc)
1220 return rc;
1221 if (mfw_rc) {
1222 DP_NOTICE(p_hwfn, "Failed sending LOAD_DONE command\n");
1223 return mfw_rc;
1224 }
1225
Sudarsana Reddy Kalluru39651ab2016-05-17 06:44:26 -04001226 /* send DCBX attention request command */
1227 DP_VERBOSE(p_hwfn,
1228 QED_MSG_DCB,
1229 "sending phony dcbx set command to trigger DCBx attention handling\n");
1230 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1231 DRV_MSG_CODE_SET_DCBX,
1232 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
1233 &load_code, &param);
1234 if (mfw_rc) {
1235 DP_NOTICE(p_hwfn,
1236 "Failed to send DCBX attention request\n");
1237 return mfw_rc;
1238 }
1239
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001240 p_hwfn->hw_init_done = true;
1241 }
1242
Sudarsana Kalluru0fefbfb2016-10-31 07:14:21 +02001243 if (IS_PF(cdev)) {
1244 p_hwfn = QED_LEADING_HWFN(cdev);
Tomer Tayar5d24bcf2017-03-28 15:12:52 +03001245 drv_mb_param = STORM_FW_VERSION;
Sudarsana Kalluru0fefbfb2016-10-31 07:14:21 +02001246 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1247 DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
1248 drv_mb_param, &load_code, &param);
1249 if (rc)
1250 DP_INFO(p_hwfn, "Failed to update firmware version\n");
1251
1252 if (!b_default_mtu) {
1253 rc = qed_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
1254 p_hwfn->hw_info.mtu);
1255 if (rc)
1256 DP_INFO(p_hwfn,
1257 "Failed to update default mtu\n");
1258 }
1259
1260 rc = qed_mcp_ov_update_driver_state(p_hwfn,
1261 p_hwfn->p_main_ptt,
1262 QED_OV_DRIVER_STATE_DISABLED);
1263 if (rc)
1264 DP_INFO(p_hwfn, "Failed to update driver state\n");
1265
1266 rc = qed_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt,
1267 QED_OV_ESWITCH_VEB);
1268 if (rc)
1269 DP_INFO(p_hwfn, "Failed to update eswitch mode\n");
1270 }
1271
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001272 return 0;
1273}
1274
1275#define QED_HW_STOP_RETRY_LIMIT (10)
Yuval Mintz1a635e42016-08-15 10:42:43 +03001276static void qed_hw_timers_stop(struct qed_dev *cdev,
1277 struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
Yuval Mintz8c925c42016-03-02 20:26:03 +02001278{
1279 int i;
1280
1281 /* close timers */
1282 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
1283 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
1284
1285 for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) {
1286 if ((!qed_rd(p_hwfn, p_ptt,
1287 TM_REG_PF_SCAN_ACTIVE_CONN)) &&
Yuval Mintz1a635e42016-08-15 10:42:43 +03001288 (!qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
Yuval Mintz8c925c42016-03-02 20:26:03 +02001289 break;
1290
1291 /* Dependent on number of connection/tasks, possibly
1292 * 1ms sleep is required between polls
1293 */
1294 usleep_range(1000, 2000);
1295 }
1296
1297 if (i < QED_HW_STOP_RETRY_LIMIT)
1298 return;
1299
1300 DP_NOTICE(p_hwfn,
1301 "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
1302 (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
1303 (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
1304}
1305
1306void qed_hw_timers_stop_all(struct qed_dev *cdev)
1307{
1308 int j;
1309
1310 for_each_hwfn(cdev, j) {
1311 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
1312 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
1313
1314 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
1315 }
1316}
1317
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001318int qed_hw_stop(struct qed_dev *cdev)
1319{
Tomer Tayar12263372017-03-28 15:12:50 +03001320 struct qed_hwfn *p_hwfn;
1321 struct qed_ptt *p_ptt;
1322 int rc, rc2 = 0;
Yuval Mintz8c925c42016-03-02 20:26:03 +02001323 int j;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001324
1325 for_each_hwfn(cdev, j) {
Tomer Tayar12263372017-03-28 15:12:50 +03001326 p_hwfn = &cdev->hwfns[j];
1327 p_ptt = p_hwfn->p_main_ptt;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001328
1329 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n");
1330
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001331 if (IS_VF(cdev)) {
Yuval Mintz0b55e272016-05-11 16:36:15 +03001332 qed_vf_pf_int_cleanup(p_hwfn);
Tomer Tayar12263372017-03-28 15:12:50 +03001333 rc = qed_vf_pf_reset(p_hwfn);
1334 if (rc) {
1335 DP_NOTICE(p_hwfn,
1336 "qed_vf_pf_reset failed. rc = %d.\n",
1337 rc);
1338 rc2 = -EINVAL;
1339 }
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001340 continue;
1341 }
1342
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001343 /* mark the hw as uninitialized... */
1344 p_hwfn->hw_init_done = false;
1345
Tomer Tayar12263372017-03-28 15:12:50 +03001346 /* Send unload command to MCP */
1347 rc = qed_mcp_unload_req(p_hwfn, p_ptt);
1348 if (rc) {
Yuval Mintz8c925c42016-03-02 20:26:03 +02001349 DP_NOTICE(p_hwfn,
Tomer Tayar12263372017-03-28 15:12:50 +03001350 "Failed sending a UNLOAD_REQ command. rc = %d.\n",
1351 rc);
1352 rc2 = -EINVAL;
1353 }
1354
1355 qed_slowpath_irq_sync(p_hwfn);
1356
1357 /* After this point no MFW attentions are expected, e.g. prevent
1358 * race between pf stop and dcbx pf update.
1359 */
1360 rc = qed_sp_pf_stop(p_hwfn);
1361 if (rc) {
1362 DP_NOTICE(p_hwfn,
1363 "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
1364 rc);
1365 rc2 = -EINVAL;
1366 }
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001367
1368 qed_wr(p_hwfn, p_ptt,
1369 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1370
1371 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1372 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1373 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1374 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1375 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1376
Yuval Mintz8c925c42016-03-02 20:26:03 +02001377 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001378
1379 /* Disable Attention Generation */
1380 qed_int_igu_disable_int(p_hwfn, p_ptt);
1381
1382 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
1383 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
1384
1385 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
1386
1387 /* Need to wait 1ms to guarantee SBs are cleared */
1388 usleep_range(1000, 2000);
Tomer Tayar12263372017-03-28 15:12:50 +03001389
1390 /* Disable PF in HW blocks */
1391 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
1392 qed_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
1393
1394 qed_mcp_unload_done(p_hwfn, p_ptt);
1395 if (rc) {
1396 DP_NOTICE(p_hwfn,
1397 "Failed sending a UNLOAD_DONE command. rc = %d.\n",
1398 rc);
1399 rc2 = -EINVAL;
1400 }
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001401 }
1402
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001403 if (IS_PF(cdev)) {
Tomer Tayar12263372017-03-28 15:12:50 +03001404 p_hwfn = QED_LEADING_HWFN(cdev);
1405 p_ptt = QED_LEADING_HWFN(cdev)->p_main_ptt;
1406
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001407 /* Disable DMAE in PXP - in CMT, this should only be done for
1408 * first hw-function, and only after all transactions have
1409 * stopped for all active hw-functions.
1410 */
Tomer Tayar12263372017-03-28 15:12:50 +03001411 rc = qed_change_pci_hwfn(p_hwfn, p_ptt, false);
1412 if (rc) {
1413 DP_NOTICE(p_hwfn,
1414 "qed_change_pci_hwfn failed. rc = %d.\n", rc);
1415 rc2 = -EINVAL;
1416 }
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001417 }
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001418
Tomer Tayar12263372017-03-28 15:12:50 +03001419 return rc2;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001420}
1421
Manish Chopracee4d262015-10-26 11:02:28 +02001422void qed_hw_stop_fastpath(struct qed_dev *cdev)
1423{
Yuval Mintz8c925c42016-03-02 20:26:03 +02001424 int j;
Manish Chopracee4d262015-10-26 11:02:28 +02001425
1426 for_each_hwfn(cdev, j) {
1427 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001428 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
1429
1430 if (IS_VF(cdev)) {
1431 qed_vf_pf_int_cleanup(p_hwfn);
1432 continue;
1433 }
Manish Chopracee4d262015-10-26 11:02:28 +02001434
1435 DP_VERBOSE(p_hwfn,
Yuval Mintz1a635e42016-08-15 10:42:43 +03001436 NETIF_MSG_IFDOWN, "Shutting down the fastpath\n");
Manish Chopracee4d262015-10-26 11:02:28 +02001437
1438 qed_wr(p_hwfn, p_ptt,
1439 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1440
1441 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1442 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1443 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1444 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1445 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1446
Manish Chopracee4d262015-10-26 11:02:28 +02001447 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
1448
1449 /* Need to wait 1ms to guarantee SBs are cleared */
1450 usleep_range(1000, 2000);
1451 }
1452}
1453
1454void qed_hw_start_fastpath(struct qed_hwfn *p_hwfn)
1455{
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001456 if (IS_VF(p_hwfn->cdev))
1457 return;
1458
Manish Chopracee4d262015-10-26 11:02:28 +02001459 /* Re-open incoming traffic */
1460 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1461 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
1462}
1463
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001464/* Free hwfn memory and resources acquired in hw_hwfn_prepare */
1465static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn)
1466{
1467 qed_ptt_pool_free(p_hwfn);
1468 kfree(p_hwfn->hw_info.p_igu_info);
1469}
1470
1471/* Setup bar access */
Yuval Mintz12e09c62016-03-02 20:26:01 +02001472static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001473{
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001474 /* clear indirect access */
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02001475 if (QED_IS_AH(p_hwfn->cdev)) {
1476 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1477 PGLUE_B_REG_PGL_ADDR_E8_F0_K2, 0);
1478 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1479 PGLUE_B_REG_PGL_ADDR_EC_F0_K2, 0);
1480 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1481 PGLUE_B_REG_PGL_ADDR_F0_F0_K2, 0);
1482 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1483 PGLUE_B_REG_PGL_ADDR_F4_F0_K2, 0);
1484 } else {
1485 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1486 PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
1487 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1488 PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
1489 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1490 PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
1491 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1492 PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
1493 }
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001494
1495 /* Clean Previous errors if such exist */
1496 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
Yuval Mintz1a635e42016-08-15 10:42:43 +03001497 PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001498
1499 /* enable internal target-read */
1500 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1501 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001502}
1503
1504static void get_function_id(struct qed_hwfn *p_hwfn)
1505{
1506 /* ME Register */
Yuval Mintz1a635e42016-08-15 10:42:43 +03001507 p_hwfn->hw_info.opaque_fid = (u16) REG_RD(p_hwfn,
1508 PXP_PF_ME_OPAQUE_ADDR);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001509
1510 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
1511
1512 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
1513 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
1514 PXP_CONCRETE_FID_PFID);
1515 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
1516 PXP_CONCRETE_FID_PORT);
Yuval Mintz525ef5c2016-08-15 10:42:45 +03001517
1518 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
1519 "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
1520 p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001521}
1522
Yuval Mintz25c089d2015-10-26 11:02:26 +02001523static void qed_hw_set_feat(struct qed_hwfn *p_hwfn)
1524{
1525 u32 *feat_num = p_hwfn->hw_info.feat_num;
Mintz, Yuval5a1f9652016-10-31 07:14:26 +02001526 struct qed_sb_cnt_info sb_cnt_info;
Mintz, Yuval810bb1f2017-03-23 15:50:19 +02001527 u32 non_l2_sbs = 0;
Yuval Mintz25c089d2015-10-26 11:02:26 +02001528
Yuval Mintz0189efb2016-10-13 22:57:02 +03001529 if (IS_ENABLED(CONFIG_QED_RDMA) &&
1530 p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) {
1531 /* Roce CNQ each requires: 1 status block + 1 CNQ. We divide
1532 * the status blocks equally between L2 / RoCE but with
1533 * consideration as to how many l2 queues / cnqs we have.
1534 */
Ram Amrani51ff1722016-10-01 21:59:57 +03001535 feat_num[QED_RDMA_CNQ] =
Mintz, Yuval810bb1f2017-03-23 15:50:19 +02001536 min_t(u32, RESC_NUM(p_hwfn, QED_SB) / 2,
Ram Amrani51ff1722016-10-01 21:59:57 +03001537 RESC_NUM(p_hwfn, QED_RDMA_CNQ_RAM));
Mintz, Yuval810bb1f2017-03-23 15:50:19 +02001538
1539 non_l2_sbs = feat_num[QED_RDMA_CNQ];
Ram Amrani51ff1722016-10-01 21:59:57 +03001540 }
Yuval Mintz0189efb2016-10-13 22:57:02 +03001541
Mintz, Yuvaldec26532017-03-23 15:50:20 +02001542 if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE ||
1543 p_hwfn->hw_info.personality == QED_PCI_ETH) {
1544 /* Start by allocating VF queues, then PF's */
1545 memset(&sb_cnt_info, 0, sizeof(sb_cnt_info));
1546 qed_int_get_num_sbs(p_hwfn, &sb_cnt_info);
1547 feat_num[QED_VF_L2_QUE] = min_t(u32,
1548 RESC_NUM(p_hwfn, QED_L2_QUEUE),
1549 sb_cnt_info.sb_iov_cnt);
1550 feat_num[QED_PF_L2_QUE] = min_t(u32,
1551 RESC_NUM(p_hwfn, QED_SB) -
1552 non_l2_sbs,
1553 RESC_NUM(p_hwfn,
1554 QED_L2_QUEUE) -
1555 FEAT_NUM(p_hwfn,
1556 QED_VF_L2_QUE));
1557 }
Mintz, Yuval5a1f9652016-10-31 07:14:26 +02001558
1559 DP_VERBOSE(p_hwfn,
1560 NETIF_MSG_PROBE,
Mintz, Yuval810bb1f2017-03-23 15:50:19 +02001561 "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #SBS=%d\n",
Mintz, Yuval5a1f9652016-10-31 07:14:26 +02001562 (int)FEAT_NUM(p_hwfn, QED_PF_L2_QUE),
1563 (int)FEAT_NUM(p_hwfn, QED_VF_L2_QUE),
1564 (int)FEAT_NUM(p_hwfn, QED_RDMA_CNQ),
Mintz, Yuval810bb1f2017-03-23 15:50:19 +02001565 RESC_NUM(p_hwfn, QED_SB));
Yuval Mintz25c089d2015-10-26 11:02:26 +02001566}
1567
Tomer Tayar2edbff82016-10-31 07:14:27 +02001568static enum resource_id_enum qed_hw_get_mfw_res_id(enum qed_resources res_id)
1569{
1570 enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID;
1571
1572 switch (res_id) {
1573 case QED_SB:
1574 mfw_res_id = RESOURCE_NUM_SB_E;
1575 break;
1576 case QED_L2_QUEUE:
1577 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E;
1578 break;
1579 case QED_VPORT:
1580 mfw_res_id = RESOURCE_NUM_VPORT_E;
1581 break;
1582 case QED_RSS_ENG:
1583 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E;
1584 break;
1585 case QED_PQ:
1586 mfw_res_id = RESOURCE_NUM_PQ_E;
1587 break;
1588 case QED_RL:
1589 mfw_res_id = RESOURCE_NUM_RL_E;
1590 break;
1591 case QED_MAC:
1592 case QED_VLAN:
1593 /* Each VFC resource can accommodate both a MAC and a VLAN */
1594 mfw_res_id = RESOURCE_VFC_FILTER_E;
1595 break;
1596 case QED_ILT:
1597 mfw_res_id = RESOURCE_ILT_E;
1598 break;
1599 case QED_LL2_QUEUE:
1600 mfw_res_id = RESOURCE_LL2_QUEUE_E;
1601 break;
1602 case QED_RDMA_CNQ_RAM:
1603 case QED_CMDQS_CQS:
1604 /* CNQ/CMDQS are the same resource */
1605 mfw_res_id = RESOURCE_CQS_E;
1606 break;
1607 case QED_RDMA_STATS_QUEUE:
1608 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E;
1609 break;
1610 default:
1611 break;
1612 }
1613
1614 return mfw_res_id;
1615}
1616
1617static u32 qed_hw_get_dflt_resc_num(struct qed_hwfn *p_hwfn,
1618 enum qed_resources res_id)
1619{
1620 u8 num_funcs = p_hwfn->num_funcs_on_engine;
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02001621 bool b_ah = QED_IS_AH(p_hwfn->cdev);
Tomer Tayar2edbff82016-10-31 07:14:27 +02001622 struct qed_sb_cnt_info sb_cnt_info;
1623 u32 dflt_resc_num = 0;
1624
1625 switch (res_id) {
1626 case QED_SB:
1627 memset(&sb_cnt_info, 0, sizeof(sb_cnt_info));
1628 qed_int_get_num_sbs(p_hwfn, &sb_cnt_info);
1629 dflt_resc_num = sb_cnt_info.sb_cnt;
1630 break;
1631 case QED_L2_QUEUE:
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02001632 dflt_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2
1633 : MAX_NUM_L2_QUEUES_BB) / num_funcs;
Tomer Tayar2edbff82016-10-31 07:14:27 +02001634 break;
1635 case QED_VPORT:
1636 dflt_resc_num = MAX_NUM_VPORTS_BB / num_funcs;
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02001637 dflt_resc_num = (b_ah ? MAX_NUM_VPORTS_K2
1638 : MAX_NUM_VPORTS_BB) / num_funcs;
Tomer Tayar2edbff82016-10-31 07:14:27 +02001639 break;
1640 case QED_RSS_ENG:
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02001641 dflt_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2
1642 : ETH_RSS_ENGINE_NUM_BB) / num_funcs;
Tomer Tayar2edbff82016-10-31 07:14:27 +02001643 break;
1644 case QED_PQ:
1645 /* The granularity of the PQs is 8 */
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02001646 dflt_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2
1647 : MAX_QM_TX_QUEUES_BB) / num_funcs;
Tomer Tayar2edbff82016-10-31 07:14:27 +02001648 dflt_resc_num &= ~0x7;
1649 break;
1650 case QED_RL:
1651 dflt_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
1652 break;
1653 case QED_MAC:
1654 case QED_VLAN:
1655 /* Each VFC resource can accommodate both a MAC and a VLAN */
1656 dflt_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
1657 break;
1658 case QED_ILT:
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02001659 dflt_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2
1660 : PXP_NUM_ILT_RECORDS_BB) / num_funcs;
Tomer Tayar2edbff82016-10-31 07:14:27 +02001661 break;
1662 case QED_LL2_QUEUE:
1663 dflt_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
1664 break;
1665 case QED_RDMA_CNQ_RAM:
1666 case QED_CMDQS_CQS:
1667 /* CNQ/CMDQS are the same resource */
1668 dflt_resc_num = NUM_OF_CMDQS_CQS / num_funcs;
1669 break;
1670 case QED_RDMA_STATS_QUEUE:
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02001671 dflt_resc_num = (b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2
1672 : RDMA_NUM_STATISTIC_COUNTERS_BB) /
1673 num_funcs;
1674
Tomer Tayar2edbff82016-10-31 07:14:27 +02001675 break;
1676 default:
1677 break;
1678 }
1679
1680 return dflt_resc_num;
1681}
1682
1683static const char *qed_hw_get_resc_name(enum qed_resources res_id)
1684{
1685 switch (res_id) {
1686 case QED_SB:
1687 return "SB";
1688 case QED_L2_QUEUE:
1689 return "L2_QUEUE";
1690 case QED_VPORT:
1691 return "VPORT";
1692 case QED_RSS_ENG:
1693 return "RSS_ENG";
1694 case QED_PQ:
1695 return "PQ";
1696 case QED_RL:
1697 return "RL";
1698 case QED_MAC:
1699 return "MAC";
1700 case QED_VLAN:
1701 return "VLAN";
1702 case QED_RDMA_CNQ_RAM:
1703 return "RDMA_CNQ_RAM";
1704 case QED_ILT:
1705 return "ILT";
1706 case QED_LL2_QUEUE:
1707 return "LL2_QUEUE";
1708 case QED_CMDQS_CQS:
1709 return "CMDQS_CQS";
1710 case QED_RDMA_STATS_QUEUE:
1711 return "RDMA_STATS_QUEUE";
1712 default:
1713 return "UNKNOWN_RESOURCE";
1714 }
1715}
1716
1717static int qed_hw_set_resc_info(struct qed_hwfn *p_hwfn,
1718 enum qed_resources res_id)
1719{
1720 u32 dflt_resc_num = 0, dflt_resc_start = 0, mcp_resp, mcp_param;
1721 u32 *p_resc_num, *p_resc_start;
1722 struct resource_info resc_info;
1723 int rc;
1724
1725 p_resc_num = &RESC_NUM(p_hwfn, res_id);
1726 p_resc_start = &RESC_START(p_hwfn, res_id);
1727
1728 /* Default values assumes that each function received equal share */
1729 dflt_resc_num = qed_hw_get_dflt_resc_num(p_hwfn, res_id);
1730 if (!dflt_resc_num) {
1731 DP_ERR(p_hwfn,
1732 "Failed to get default amount for resource %d [%s]\n",
1733 res_id, qed_hw_get_resc_name(res_id));
1734 return -EINVAL;
1735 }
1736 dflt_resc_start = dflt_resc_num * p_hwfn->enabled_func_idx;
1737
1738 memset(&resc_info, 0, sizeof(resc_info));
1739 resc_info.res_id = qed_hw_get_mfw_res_id(res_id);
1740 if (resc_info.res_id == RESOURCE_NUM_INVALID) {
1741 DP_ERR(p_hwfn,
1742 "Failed to match resource %d [%s] with the MFW resources\n",
1743 res_id, qed_hw_get_resc_name(res_id));
1744 return -EINVAL;
1745 }
1746
1747 rc = qed_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, &resc_info,
1748 &mcp_resp, &mcp_param);
1749 if (rc) {
1750 DP_NOTICE(p_hwfn,
1751 "MFW response failure for an allocation request for resource %d [%s]\n",
1752 res_id, qed_hw_get_resc_name(res_id));
1753 return rc;
1754 }
1755
1756 /* Default driver values are applied in the following cases:
1757 * - The resource allocation MB command is not supported by the MFW
1758 * - There is an internal error in the MFW while processing the request
1759 * - The resource ID is unknown to the MFW
1760 */
1761 if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK &&
1762 mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED) {
1763 DP_NOTICE(p_hwfn,
1764 "Resource %d [%s]: No allocation info was received [mcp_resp 0x%x]. Applying default values [num %d, start %d].\n",
1765 res_id,
1766 qed_hw_get_resc_name(res_id),
1767 mcp_resp, dflt_resc_num, dflt_resc_start);
1768 *p_resc_num = dflt_resc_num;
1769 *p_resc_start = dflt_resc_start;
1770 goto out;
1771 }
1772
1773 /* Special handling for status blocks; Would be revised in future */
1774 if (res_id == QED_SB) {
1775 resc_info.size -= 1;
1776 resc_info.offset -= p_hwfn->enabled_func_idx;
1777 }
1778
1779 *p_resc_num = resc_info.size;
1780 *p_resc_start = resc_info.offset;
1781
1782out:
1783 /* PQs have to divide by 8 [that's the HW granularity].
1784 * Reduce number so it would fit.
1785 */
1786 if ((res_id == QED_PQ) && ((*p_resc_num % 8) || (*p_resc_start % 8))) {
1787 DP_INFO(p_hwfn,
1788 "PQs need to align by 8; Number %08x --> %08x, Start %08x --> %08x\n",
1789 *p_resc_num,
1790 (*p_resc_num) & ~0x7,
1791 *p_resc_start, (*p_resc_start) & ~0x7);
1792 *p_resc_num &= ~0x7;
1793 *p_resc_start &= ~0x7;
1794 }
1795
1796 return 0;
1797}
1798
Yuval Mintzdbb799c2016-06-03 14:35:35 +03001799static int qed_hw_get_resc(struct qed_hwfn *p_hwfn)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001800{
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02001801 bool b_ah = QED_IS_AH(p_hwfn->cdev);
Tomer Tayar2edbff82016-10-31 07:14:27 +02001802 u8 res_id;
1803 int rc;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001804
Tomer Tayar2edbff82016-10-31 07:14:27 +02001805 for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
1806 rc = qed_hw_set_resc_info(p_hwfn, res_id);
1807 if (rc)
1808 return rc;
1809 }
Yuval Mintzdbb799c2016-06-03 14:35:35 +03001810
1811 /* Sanity for ILT */
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02001812 if ((b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
1813 (!b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
Yuval Mintzdbb799c2016-06-03 14:35:35 +03001814 DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n",
1815 RESC_START(p_hwfn, QED_ILT),
1816 RESC_END(p_hwfn, QED_ILT) - 1);
1817 return -EINVAL;
1818 }
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001819
Yuval Mintz25c089d2015-10-26 11:02:26 +02001820 qed_hw_set_feat(p_hwfn);
1821
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001822 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
Tomer Tayar2edbff82016-10-31 07:14:27 +02001823 "The numbers for each resource are:\n");
1824 for (res_id = 0; res_id < QED_MAX_RESC; res_id++)
1825 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, "%s = %d start = %d\n",
1826 qed_hw_get_resc_name(res_id),
1827 RESC_NUM(p_hwfn, res_id),
1828 RESC_START(p_hwfn, res_id));
Yuval Mintzdbb799c2016-06-03 14:35:35 +03001829
1830 return 0;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001831}
1832
Yuval Mintz1a635e42016-08-15 10:42:43 +03001833static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001834{
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001835 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
Arun Easi1e128c82017-02-15 06:28:22 -08001836 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
Yuval Mintzcc875c22015-10-26 11:02:31 +02001837 struct qed_mcp_link_params *link;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001838
1839 /* Read global nvm_cfg address */
1840 nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
1841
1842 /* Verify MCP has initialized it */
1843 if (!nvm_cfg_addr) {
1844 DP_NOTICE(p_hwfn, "Shared memory not initialized\n");
1845 return -EINVAL;
1846 }
1847
1848 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */
1849 nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
1850
Yuval Mintzcc875c22015-10-26 11:02:31 +02001851 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1852 offsetof(struct nvm_cfg1, glob) +
1853 offsetof(struct nvm_cfg1_glob, core_cfg);
1854
1855 core_cfg = qed_rd(p_hwfn, p_ptt, addr);
1856
1857 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
1858 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001859 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
Yuval Mintzcc875c22015-10-26 11:02:31 +02001860 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G;
1861 break;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001862 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
Yuval Mintzcc875c22015-10-26 11:02:31 +02001863 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G;
1864 break;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001865 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
Yuval Mintzcc875c22015-10-26 11:02:31 +02001866 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G;
1867 break;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001868 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
Yuval Mintzcc875c22015-10-26 11:02:31 +02001869 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F;
1870 break;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001871 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
Yuval Mintzcc875c22015-10-26 11:02:31 +02001872 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E;
1873 break;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001874 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
Yuval Mintzcc875c22015-10-26 11:02:31 +02001875 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G;
1876 break;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001877 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
Yuval Mintzcc875c22015-10-26 11:02:31 +02001878 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G;
1879 break;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001880 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
Yuval Mintzcc875c22015-10-26 11:02:31 +02001881 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G;
1882 break;
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02001883 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
1884 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X10G;
1885 break;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001886 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
Yuval Mintzcc875c22015-10-26 11:02:31 +02001887 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G;
1888 break;
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02001889 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
1890 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X25G;
1891 break;
Yuval Mintzcc875c22015-10-26 11:02:31 +02001892 default:
Yuval Mintz1a635e42016-08-15 10:42:43 +03001893 DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", core_cfg);
Yuval Mintzcc875c22015-10-26 11:02:31 +02001894 break;
1895 }
1896
Yuval Mintzcc875c22015-10-26 11:02:31 +02001897 /* Read default link configuration */
1898 link = &p_hwfn->mcp_info->link_input;
1899 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1900 offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
1901 link_temp = qed_rd(p_hwfn, p_ptt,
1902 port_cfg_addr +
1903 offsetof(struct nvm_cfg1_port, speed_cap_mask));
Yuval Mintz83aeb932016-08-15 10:42:44 +03001904 link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
1905 link->speed.advertised_speeds = link_temp;
Yuval Mintzcc875c22015-10-26 11:02:31 +02001906
Yuval Mintz83aeb932016-08-15 10:42:44 +03001907 link_temp = link->speed.advertised_speeds;
1908 p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
Yuval Mintzcc875c22015-10-26 11:02:31 +02001909
1910 link_temp = qed_rd(p_hwfn, p_ptt,
1911 port_cfg_addr +
1912 offsetof(struct nvm_cfg1_port, link_settings));
1913 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
1914 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
1915 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
1916 link->speed.autoneg = true;
1917 break;
1918 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
1919 link->speed.forced_speed = 1000;
1920 break;
1921 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
1922 link->speed.forced_speed = 10000;
1923 break;
1924 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
1925 link->speed.forced_speed = 25000;
1926 break;
1927 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
1928 link->speed.forced_speed = 40000;
1929 break;
1930 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
1931 link->speed.forced_speed = 50000;
1932 break;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001933 case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
Yuval Mintzcc875c22015-10-26 11:02:31 +02001934 link->speed.forced_speed = 100000;
1935 break;
1936 default:
Yuval Mintz1a635e42016-08-15 10:42:43 +03001937 DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", link_temp);
Yuval Mintzcc875c22015-10-26 11:02:31 +02001938 }
1939
1940 link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
1941 link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
1942 link->pause.autoneg = !!(link_temp &
1943 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
1944 link->pause.forced_rx = !!(link_temp &
1945 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
1946 link->pause.forced_tx = !!(link_temp &
1947 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
1948 link->loopback_mode = 0;
1949
1950 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1951 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n",
1952 link->speed.forced_speed, link->speed.advertised_speeds,
1953 link->speed.autoneg, link->pause.autoneg);
1954
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001955 /* Read Multi-function information from shmem */
1956 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1957 offsetof(struct nvm_cfg1, glob) +
1958 offsetof(struct nvm_cfg1_glob, generic_cont0);
1959
1960 generic_cont0 = qed_rd(p_hwfn, p_ptt, addr);
1961
1962 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
1963 NVM_CFG1_GLOB_MF_MODE_OFFSET;
1964
1965 switch (mf_mode) {
1966 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001967 p_hwfn->cdev->mf_mode = QED_MF_OVLAN;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001968 break;
1969 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001970 p_hwfn->cdev->mf_mode = QED_MF_NPAR;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001971 break;
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001972 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
1973 p_hwfn->cdev->mf_mode = QED_MF_DEFAULT;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001974 break;
1975 }
1976 DP_INFO(p_hwfn, "Multi function mode is %08x\n",
1977 p_hwfn->cdev->mf_mode);
1978
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001979 /* Read Multi-function information from shmem */
1980 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1981 offsetof(struct nvm_cfg1, glob) +
1982 offsetof(struct nvm_cfg1_glob, device_capabilities);
1983
1984 device_capabilities = qed_rd(p_hwfn, p_ptt, addr);
1985 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
1986 __set_bit(QED_DEV_CAP_ETH,
1987 &p_hwfn->hw_info.device_capabilities);
Arun Easi1e128c82017-02-15 06:28:22 -08001988 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
1989 __set_bit(QED_DEV_CAP_FCOE,
1990 &p_hwfn->hw_info.device_capabilities);
Yuval Mintzc5ac9312016-06-03 14:35:34 +03001991 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
1992 __set_bit(QED_DEV_CAP_ISCSI,
1993 &p_hwfn->hw_info.device_capabilities);
1994 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
1995 __set_bit(QED_DEV_CAP_ROCE,
1996 &p_hwfn->hw_info.device_capabilities);
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05001997
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02001998 return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
1999}
2000
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03002001static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2002{
Yuval Mintzdbb799c2016-06-03 14:35:35 +03002003 u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
2004 u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02002005 struct qed_dev *cdev = p_hwfn->cdev;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03002006
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02002007 num_funcs = QED_IS_AH(cdev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03002008
2009 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
2010 * in the other bits are selected.
2011 * Bits 1-15 are for functions 1-15, respectively, and their value is
2012 * '0' only for enabled functions (function 0 always exists and
2013 * enabled).
2014 * In case of CMT, only the "even" functions are enabled, and thus the
2015 * number of functions for both hwfns is learnt from the same bits.
2016 */
2017 reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
2018
2019 if (reg_function_hide & 0x1) {
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02002020 if (QED_IS_BB(cdev)) {
2021 if (QED_PATH_ID(p_hwfn) && cdev->num_hwfns == 1) {
2022 num_funcs = 0;
2023 eng_mask = 0xaaaa;
2024 } else {
2025 num_funcs = 1;
2026 eng_mask = 0x5554;
2027 }
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03002028 } else {
2029 num_funcs = 1;
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02002030 eng_mask = 0xfffe;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03002031 }
2032
2033 /* Get the number of the enabled functions on the engine */
2034 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
2035 while (tmp) {
2036 if (tmp & 0x1)
2037 num_funcs++;
2038 tmp >>= 0x1;
2039 }
Yuval Mintzdbb799c2016-06-03 14:35:35 +03002040
2041 /* Get the PF index within the enabled functions */
2042 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
2043 tmp = reg_function_hide & eng_mask & low_pfs_mask;
2044 while (tmp) {
2045 if (tmp & 0x1)
2046 enabled_func_idx--;
2047 tmp >>= 0x1;
2048 }
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03002049 }
2050
2051 p_hwfn->num_funcs_on_engine = num_funcs;
Yuval Mintzdbb799c2016-06-03 14:35:35 +03002052 p_hwfn->enabled_func_idx = enabled_func_idx;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03002053
2054 DP_VERBOSE(p_hwfn,
2055 NETIF_MSG_PROBE,
Yuval Mintz525ef5c2016-08-15 10:42:45 +03002056 "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03002057 p_hwfn->rel_pf_id,
2058 p_hwfn->abs_pf_id,
Yuval Mintz525ef5c2016-08-15 10:42:45 +03002059 p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03002060}
2061
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02002062static void qed_hw_info_port_num_bb(struct qed_hwfn *p_hwfn,
2063 struct qed_ptt *p_ptt)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002064{
2065 u32 port_mode;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002066
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02002067 port_mode = qed_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB_B0);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002068
2069 if (port_mode < 3) {
2070 p_hwfn->cdev->num_ports_in_engines = 1;
2071 } else if (port_mode <= 5) {
2072 p_hwfn->cdev->num_ports_in_engines = 2;
2073 } else {
2074 DP_NOTICE(p_hwfn, "PORT MODE: %d not supported\n",
2075 p_hwfn->cdev->num_ports_in_engines);
2076
2077 /* Default num_ports_in_engines to something */
2078 p_hwfn->cdev->num_ports_in_engines = 1;
2079 }
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02002080}
2081
2082static void qed_hw_info_port_num_ah(struct qed_hwfn *p_hwfn,
2083 struct qed_ptt *p_ptt)
2084{
2085 u32 port;
2086 int i;
2087
2088 p_hwfn->cdev->num_ports_in_engines = 0;
2089
2090 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
2091 port = qed_rd(p_hwfn, p_ptt,
2092 CNIG_REG_NIG_PORT0_CONF_K2 + (i * 4));
2093 if (port & 1)
2094 p_hwfn->cdev->num_ports_in_engines++;
2095 }
2096
2097 if (!p_hwfn->cdev->num_ports_in_engines) {
2098 DP_NOTICE(p_hwfn, "All NIG ports are inactive\n");
2099
2100 /* Default num_ports_in_engine to something */
2101 p_hwfn->cdev->num_ports_in_engines = 1;
2102 }
2103}
2104
2105static void qed_hw_info_port_num(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2106{
2107 if (QED_IS_BB(p_hwfn->cdev))
2108 qed_hw_info_port_num_bb(p_hwfn, p_ptt);
2109 else
2110 qed_hw_info_port_num_ah(p_hwfn, p_ptt);
2111}
2112
2113static int
2114qed_get_hw_info(struct qed_hwfn *p_hwfn,
2115 struct qed_ptt *p_ptt,
2116 enum qed_pci_personality personality)
2117{
2118 int rc;
2119
2120 /* Since all information is common, only first hwfns should do this */
2121 if (IS_LEAD_HWFN(p_hwfn)) {
2122 rc = qed_iov_hw_info(p_hwfn);
2123 if (rc)
2124 return rc;
2125 }
2126
2127 qed_hw_info_port_num(p_hwfn, p_ptt);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002128
2129 qed_hw_get_nvm_info(p_hwfn, p_ptt);
2130
2131 rc = qed_int_igu_read_cam(p_hwfn, p_ptt);
2132 if (rc)
2133 return rc;
2134
2135 if (qed_mcp_is_init(p_hwfn))
2136 ether_addr_copy(p_hwfn->hw_info.hw_mac_addr,
2137 p_hwfn->mcp_info->func_info.mac);
2138 else
2139 eth_random_addr(p_hwfn->hw_info.hw_mac_addr);
2140
2141 if (qed_mcp_is_init(p_hwfn)) {
2142 if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET)
2143 p_hwfn->hw_info.ovlan =
2144 p_hwfn->mcp_info->func_info.ovlan;
2145
2146 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
2147 }
2148
2149 if (qed_mcp_is_init(p_hwfn)) {
2150 enum qed_pci_personality protocol;
2151
2152 protocol = p_hwfn->mcp_info->func_info.protocol;
2153 p_hwfn->hw_info.personality = protocol;
2154 }
2155
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03002156 qed_get_num_funcs(p_hwfn, p_ptt);
2157
Sudarsana Kalluru0fefbfb2016-10-31 07:14:21 +02002158 if (qed_mcp_is_init(p_hwfn))
2159 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
2160
Yuval Mintzdbb799c2016-06-03 14:35:35 +03002161 return qed_hw_get_resc(p_hwfn);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002162}
2163
Yuval Mintz12e09c62016-03-02 20:26:01 +02002164static int qed_get_dev_info(struct qed_dev *cdev)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002165{
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002166 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02002167 u16 device_id_mask;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002168 u32 tmp;
2169
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002170 /* Read Vendor Id / Device Id */
Yuval Mintz1a635e42016-08-15 10:42:43 +03002171 pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, &cdev->vendor_id);
2172 pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, &cdev->device_id);
2173
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02002174 /* Determine type */
2175 device_id_mask = cdev->device_id & QED_DEV_ID_MASK;
2176 switch (device_id_mask) {
2177 case QED_DEV_ID_MASK_BB:
2178 cdev->type = QED_DEV_TYPE_BB;
2179 break;
2180 case QED_DEV_ID_MASK_AH:
2181 cdev->type = QED_DEV_TYPE_AH;
2182 break;
2183 default:
2184 DP_NOTICE(p_hwfn, "Unknown device id 0x%x\n", cdev->device_id);
2185 return -EBUSY;
2186 }
2187
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002188 cdev->chip_num = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002189 MISCS_REG_CHIP_NUM);
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002190 cdev->chip_rev = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002191 MISCS_REG_CHIP_REV);
2192 MASK_FIELD(CHIP_REV, cdev->chip_rev);
2193
2194 /* Learn number of HW-functions */
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002195 tmp = qed_rd(p_hwfn, p_hwfn->p_main_ptt,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002196 MISCS_REG_CMT_ENABLED_FOR_PAIR);
2197
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002198 if (tmp & (1 << p_hwfn->rel_pf_id)) {
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002199 DP_NOTICE(cdev->hwfns, "device in CMT mode\n");
2200 cdev->num_hwfns = 2;
2201 } else {
2202 cdev->num_hwfns = 1;
2203 }
2204
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002205 cdev->chip_bond_id = qed_rd(p_hwfn, p_hwfn->p_main_ptt,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002206 MISCS_REG_CHIP_TEST_REG) >> 4;
2207 MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id);
Yuval Mintzfc48b7a2016-02-15 13:22:35 -05002208 cdev->chip_metal = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002209 MISCS_REG_CHIP_METAL);
2210 MASK_FIELD(CHIP_METAL, cdev->chip_metal);
2211
2212 DP_INFO(cdev->hwfns,
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02002213 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
2214 QED_IS_BB(cdev) ? "BB" : "AH",
2215 'A' + cdev->chip_rev,
2216 (int)cdev->chip_metal,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002217 cdev->chip_num, cdev->chip_rev,
2218 cdev->chip_bond_id, cdev->chip_metal);
Yuval Mintz12e09c62016-03-02 20:26:01 +02002219
2220 if (QED_IS_BB(cdev) && CHIP_REV_IS_A0(cdev)) {
2221 DP_NOTICE(cdev->hwfns,
2222 "The chip type/rev (BB A0) is not supported!\n");
2223 return -EINVAL;
2224 }
2225
2226 return 0;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002227}
2228
2229static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn,
2230 void __iomem *p_regview,
2231 void __iomem *p_doorbells,
2232 enum qed_pci_personality personality)
2233{
2234 int rc = 0;
2235
2236 /* Split PCI bars evenly between hwfns */
2237 p_hwfn->regview = p_regview;
2238 p_hwfn->doorbells = p_doorbells;
2239
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03002240 if (IS_VF(p_hwfn->cdev))
2241 return qed_vf_hw_prepare(p_hwfn);
2242
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002243 /* Validate that chip access is feasible */
2244 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
2245 DP_ERR(p_hwfn,
2246 "Reading the ME register returns all Fs; Preventing further chip access\n");
2247 return -EINVAL;
2248 }
2249
2250 get_function_id(p_hwfn);
2251
Yuval Mintz12e09c62016-03-02 20:26:01 +02002252 /* Allocate PTT pool */
2253 rc = qed_ptt_pool_alloc(p_hwfn);
Joe Perches2591c282016-09-04 14:24:03 -07002254 if (rc)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002255 goto err0;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002256
Yuval Mintz12e09c62016-03-02 20:26:01 +02002257 /* Allocate the main PTT */
2258 p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
2259
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002260 /* First hwfn learns basic information, e.g., number of hwfns */
Yuval Mintz12e09c62016-03-02 20:26:01 +02002261 if (!p_hwfn->my_id) {
2262 rc = qed_get_dev_info(p_hwfn->cdev);
Yuval Mintz1a635e42016-08-15 10:42:43 +03002263 if (rc)
Yuval Mintz12e09c62016-03-02 20:26:01 +02002264 goto err1;
2265 }
2266
2267 qed_hw_hwfn_prepare(p_hwfn);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002268
2269 /* Initialize MCP structure */
2270 rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
2271 if (rc) {
2272 DP_NOTICE(p_hwfn, "Failed initializing mcp command\n");
2273 goto err1;
2274 }
2275
2276 /* Read the device configuration information from the HW and SHMEM */
2277 rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality);
2278 if (rc) {
2279 DP_NOTICE(p_hwfn, "Failed to get HW information\n");
2280 goto err2;
2281 }
2282
Mintz, Yuval18a69e32017-03-28 15:12:53 +03002283 /* Sending a mailbox to the MFW should be done after qed_get_hw_info()
2284 * is called as it sets the ports number in an engine.
2285 */
2286 if (IS_LEAD_HWFN(p_hwfn)) {
2287 rc = qed_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
2288 if (rc)
2289 DP_NOTICE(p_hwfn, "Failed to initiate PF FLR\n");
2290 }
2291
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002292 /* Allocate the init RT array and initialize the init-ops engine */
2293 rc = qed_init_alloc(p_hwfn);
Joe Perches2591c282016-09-04 14:24:03 -07002294 if (rc)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002295 goto err2;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002296
2297 return rc;
2298err2:
Yuval Mintz32a47e72016-05-11 16:36:12 +03002299 if (IS_LEAD_HWFN(p_hwfn))
2300 qed_iov_free_hw_info(p_hwfn->cdev);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002301 qed_mcp_free(p_hwfn);
2302err1:
2303 qed_hw_hwfn_free(p_hwfn);
2304err0:
2305 return rc;
2306}
2307
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002308int qed_hw_prepare(struct qed_dev *cdev,
2309 int personality)
2310{
Ariel Eliorc78df142015-12-07 06:25:58 -05002311 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2312 int rc;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002313
2314 /* Store the precompiled init data ptrs */
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03002315 if (IS_PF(cdev))
2316 qed_init_iro_array(cdev);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002317
2318 /* Initialize the first hwfn - will learn number of hwfns */
Ariel Eliorc78df142015-12-07 06:25:58 -05002319 rc = qed_hw_prepare_single(p_hwfn,
2320 cdev->regview,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002321 cdev->doorbells, personality);
2322 if (rc)
2323 return rc;
2324
Ariel Eliorc78df142015-12-07 06:25:58 -05002325 personality = p_hwfn->hw_info.personality;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002326
2327 /* Initialize the rest of the hwfns */
Ariel Eliorc78df142015-12-07 06:25:58 -05002328 if (cdev->num_hwfns > 1) {
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002329 void __iomem *p_regview, *p_doorbell;
Ariel Eliorc78df142015-12-07 06:25:58 -05002330 u8 __iomem *addr;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002331
Ariel Eliorc78df142015-12-07 06:25:58 -05002332 /* adjust bar offset for second engine */
Ram Amranic2035ee2016-03-02 20:26:00 +02002333 addr = cdev->regview + qed_hw_bar_size(p_hwfn, BAR_ID_0) / 2;
Ariel Eliorc78df142015-12-07 06:25:58 -05002334 p_regview = addr;
2335
2336 /* adjust doorbell bar offset for second engine */
Ram Amranic2035ee2016-03-02 20:26:00 +02002337 addr = cdev->doorbells + qed_hw_bar_size(p_hwfn, BAR_ID_1) / 2;
Ariel Eliorc78df142015-12-07 06:25:58 -05002338 p_doorbell = addr;
2339
2340 /* prepare second hw function */
2341 rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview,
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002342 p_doorbell, personality);
Ariel Eliorc78df142015-12-07 06:25:58 -05002343
2344 /* in case of error, need to free the previously
2345 * initiliazed hwfn 0.
2346 */
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002347 if (rc) {
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03002348 if (IS_PF(cdev)) {
2349 qed_init_free(p_hwfn);
2350 qed_mcp_free(p_hwfn);
2351 qed_hw_hwfn_free(p_hwfn);
2352 }
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002353 }
2354 }
2355
Ariel Eliorc78df142015-12-07 06:25:58 -05002356 return rc;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002357}
2358
2359void qed_hw_remove(struct qed_dev *cdev)
2360{
Sudarsana Kalluru0fefbfb2016-10-31 07:14:21 +02002361 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002362 int i;
2363
Sudarsana Kalluru0fefbfb2016-10-31 07:14:21 +02002364 if (IS_PF(cdev))
2365 qed_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
2366 QED_OV_DRIVER_STATE_NOT_LOADED);
2367
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002368 for_each_hwfn(cdev, i) {
2369 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2370
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03002371 if (IS_VF(cdev)) {
Yuval Mintz0b55e272016-05-11 16:36:15 +03002372 qed_vf_pf_release(p_hwfn);
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03002373 continue;
2374 }
2375
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002376 qed_init_free(p_hwfn);
2377 qed_hw_hwfn_free(p_hwfn);
2378 qed_mcp_free(p_hwfn);
2379 }
Yuval Mintz32a47e72016-05-11 16:36:12 +03002380
2381 qed_iov_free_hw_info(cdev);
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002382}
2383
Yuval Mintza91eb522016-06-03 14:35:32 +03002384static void qed_chain_free_next_ptr(struct qed_dev *cdev,
2385 struct qed_chain *p_chain)
2386{
2387 void *p_virt = p_chain->p_virt_addr, *p_virt_next = NULL;
2388 dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
2389 struct qed_chain_next *p_next;
2390 u32 size, i;
2391
2392 if (!p_virt)
2393 return;
2394
2395 size = p_chain->elem_size * p_chain->usable_per_page;
2396
2397 for (i = 0; i < p_chain->page_cnt; i++) {
2398 if (!p_virt)
2399 break;
2400
2401 p_next = (struct qed_chain_next *)((u8 *)p_virt + size);
2402 p_virt_next = p_next->next_virt;
2403 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
2404
2405 dma_free_coherent(&cdev->pdev->dev,
2406 QED_CHAIN_PAGE_SIZE, p_virt, p_phys);
2407
2408 p_virt = p_virt_next;
2409 p_phys = p_phys_next;
2410 }
2411}
2412
2413static void qed_chain_free_single(struct qed_dev *cdev,
2414 struct qed_chain *p_chain)
2415{
2416 if (!p_chain->p_virt_addr)
2417 return;
2418
2419 dma_free_coherent(&cdev->pdev->dev,
2420 QED_CHAIN_PAGE_SIZE,
2421 p_chain->p_virt_addr, p_chain->p_phys_addr);
2422}
2423
2424static void qed_chain_free_pbl(struct qed_dev *cdev, struct qed_chain *p_chain)
2425{
2426 void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
2427 u32 page_cnt = p_chain->page_cnt, i, pbl_size;
Mintz, Yuval6d937ac2016-11-29 16:47:01 +02002428 u8 *p_pbl_virt = p_chain->pbl_sp.p_virt_table;
Yuval Mintza91eb522016-06-03 14:35:32 +03002429
2430 if (!pp_virt_addr_tbl)
2431 return;
2432
Mintz, Yuval6d937ac2016-11-29 16:47:01 +02002433 if (!p_pbl_virt)
Yuval Mintza91eb522016-06-03 14:35:32 +03002434 goto out;
2435
2436 for (i = 0; i < page_cnt; i++) {
2437 if (!pp_virt_addr_tbl[i])
2438 break;
2439
2440 dma_free_coherent(&cdev->pdev->dev,
2441 QED_CHAIN_PAGE_SIZE,
2442 pp_virt_addr_tbl[i],
2443 *(dma_addr_t *)p_pbl_virt);
2444
2445 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
2446 }
2447
2448 pbl_size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
2449 dma_free_coherent(&cdev->pdev->dev,
2450 pbl_size,
Mintz, Yuval6d937ac2016-11-29 16:47:01 +02002451 p_chain->pbl_sp.p_virt_table,
2452 p_chain->pbl_sp.p_phys_table);
Yuval Mintza91eb522016-06-03 14:35:32 +03002453out:
2454 vfree(p_chain->pbl.pp_virt_addr_tbl);
2455}
2456
2457void qed_chain_free(struct qed_dev *cdev, struct qed_chain *p_chain)
2458{
2459 switch (p_chain->mode) {
2460 case QED_CHAIN_MODE_NEXT_PTR:
2461 qed_chain_free_next_ptr(cdev, p_chain);
2462 break;
2463 case QED_CHAIN_MODE_SINGLE:
2464 qed_chain_free_single(cdev, p_chain);
2465 break;
2466 case QED_CHAIN_MODE_PBL:
2467 qed_chain_free_pbl(cdev, p_chain);
2468 break;
2469 }
2470}
2471
2472static int
2473qed_chain_alloc_sanity_check(struct qed_dev *cdev,
2474 enum qed_chain_cnt_type cnt_type,
2475 size_t elem_size, u32 page_cnt)
2476{
2477 u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
2478
2479 /* The actual chain size can be larger than the maximal possible value
2480 * after rounding up the requested elements number to pages, and after
2481 * taking into acount the unusuable elements (next-ptr elements).
2482 * The size of a "u16" chain can be (U16_MAX + 1) since the chain
2483 * size/capacity fields are of a u32 type.
2484 */
2485 if ((cnt_type == QED_CHAIN_CNT_TYPE_U16 &&
Tomer Tayar3ef310a2017-03-14 15:25:59 +02002486 chain_size > ((u32)U16_MAX + 1)) ||
2487 (cnt_type == QED_CHAIN_CNT_TYPE_U32 && chain_size > U32_MAX)) {
Yuval Mintza91eb522016-06-03 14:35:32 +03002488 DP_NOTICE(cdev,
2489 "The actual chain size (0x%llx) is larger than the maximal possible value\n",
2490 chain_size);
2491 return -EINVAL;
2492 }
2493
2494 return 0;
2495}
2496
2497static int
2498qed_chain_alloc_next_ptr(struct qed_dev *cdev, struct qed_chain *p_chain)
2499{
2500 void *p_virt = NULL, *p_virt_prev = NULL;
2501 dma_addr_t p_phys = 0;
2502 u32 i;
2503
2504 for (i = 0; i < p_chain->page_cnt; i++) {
2505 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
2506 QED_CHAIN_PAGE_SIZE,
2507 &p_phys, GFP_KERNEL);
Joe Perches2591c282016-09-04 14:24:03 -07002508 if (!p_virt)
Yuval Mintza91eb522016-06-03 14:35:32 +03002509 return -ENOMEM;
Yuval Mintza91eb522016-06-03 14:35:32 +03002510
2511 if (i == 0) {
2512 qed_chain_init_mem(p_chain, p_virt, p_phys);
2513 qed_chain_reset(p_chain);
2514 } else {
2515 qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
2516 p_virt, p_phys);
2517 }
2518
2519 p_virt_prev = p_virt;
2520 }
2521 /* Last page's next element should point to the beginning of the
2522 * chain.
2523 */
2524 qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
2525 p_chain->p_virt_addr,
2526 p_chain->p_phys_addr);
2527
2528 return 0;
2529}
2530
2531static int
2532qed_chain_alloc_single(struct qed_dev *cdev, struct qed_chain *p_chain)
2533{
2534 dma_addr_t p_phys = 0;
2535 void *p_virt = NULL;
2536
2537 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
2538 QED_CHAIN_PAGE_SIZE, &p_phys, GFP_KERNEL);
Joe Perches2591c282016-09-04 14:24:03 -07002539 if (!p_virt)
Yuval Mintza91eb522016-06-03 14:35:32 +03002540 return -ENOMEM;
Yuval Mintza91eb522016-06-03 14:35:32 +03002541
2542 qed_chain_init_mem(p_chain, p_virt, p_phys);
2543 qed_chain_reset(p_chain);
2544
2545 return 0;
2546}
2547
2548static int qed_chain_alloc_pbl(struct qed_dev *cdev, struct qed_chain *p_chain)
2549{
2550 u32 page_cnt = p_chain->page_cnt, size, i;
2551 dma_addr_t p_phys = 0, p_pbl_phys = 0;
2552 void **pp_virt_addr_tbl = NULL;
2553 u8 *p_pbl_virt = NULL;
2554 void *p_virt = NULL;
2555
2556 size = page_cnt * sizeof(*pp_virt_addr_tbl);
Joe Perches2591c282016-09-04 14:24:03 -07002557 pp_virt_addr_tbl = vzalloc(size);
2558 if (!pp_virt_addr_tbl)
Yuval Mintza91eb522016-06-03 14:35:32 +03002559 return -ENOMEM;
Yuval Mintza91eb522016-06-03 14:35:32 +03002560
2561 /* The allocation of the PBL table is done with its full size, since it
2562 * is expected to be successive.
2563 * qed_chain_init_pbl_mem() is called even in a case of an allocation
2564 * failure, since pp_virt_addr_tbl was previously allocated, and it
2565 * should be saved to allow its freeing during the error flow.
2566 */
2567 size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
2568 p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev,
2569 size, &p_pbl_phys, GFP_KERNEL);
2570 qed_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
2571 pp_virt_addr_tbl);
Joe Perches2591c282016-09-04 14:24:03 -07002572 if (!p_pbl_virt)
Yuval Mintza91eb522016-06-03 14:35:32 +03002573 return -ENOMEM;
Yuval Mintza91eb522016-06-03 14:35:32 +03002574
2575 for (i = 0; i < page_cnt; i++) {
2576 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
2577 QED_CHAIN_PAGE_SIZE,
2578 &p_phys, GFP_KERNEL);
Joe Perches2591c282016-09-04 14:24:03 -07002579 if (!p_virt)
Yuval Mintza91eb522016-06-03 14:35:32 +03002580 return -ENOMEM;
Yuval Mintza91eb522016-06-03 14:35:32 +03002581
2582 if (i == 0) {
2583 qed_chain_init_mem(p_chain, p_virt, p_phys);
2584 qed_chain_reset(p_chain);
2585 }
2586
2587 /* Fill the PBL table with the physical address of the page */
2588 *(dma_addr_t *)p_pbl_virt = p_phys;
2589 /* Keep the virtual address of the page */
2590 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
2591
2592 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
2593 }
2594
2595 return 0;
2596}
2597
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002598int qed_chain_alloc(struct qed_dev *cdev,
2599 enum qed_chain_use_mode intended_use,
2600 enum qed_chain_mode mode,
Yuval Mintza91eb522016-06-03 14:35:32 +03002601 enum qed_chain_cnt_type cnt_type,
2602 u32 num_elems, size_t elem_size, struct qed_chain *p_chain)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002603{
Yuval Mintza91eb522016-06-03 14:35:32 +03002604 u32 page_cnt;
2605 int rc = 0;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002606
2607 if (mode == QED_CHAIN_MODE_SINGLE)
2608 page_cnt = 1;
2609 else
2610 page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
2611
Yuval Mintza91eb522016-06-03 14:35:32 +03002612 rc = qed_chain_alloc_sanity_check(cdev, cnt_type, elem_size, page_cnt);
2613 if (rc) {
2614 DP_NOTICE(cdev,
Joe Perches2591c282016-09-04 14:24:03 -07002615 "Cannot allocate a chain with the given arguments:\n");
2616 DP_NOTICE(cdev,
Yuval Mintza91eb522016-06-03 14:35:32 +03002617 "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
2618 intended_use, mode, cnt_type, num_elems, elem_size);
2619 return rc;
2620 }
2621
2622 qed_chain_init_params(p_chain, page_cnt, (u8) elem_size, intended_use,
2623 mode, cnt_type);
2624
2625 switch (mode) {
2626 case QED_CHAIN_MODE_NEXT_PTR:
2627 rc = qed_chain_alloc_next_ptr(cdev, p_chain);
2628 break;
2629 case QED_CHAIN_MODE_SINGLE:
2630 rc = qed_chain_alloc_single(cdev, p_chain);
2631 break;
2632 case QED_CHAIN_MODE_PBL:
2633 rc = qed_chain_alloc_pbl(cdev, p_chain);
2634 break;
2635 }
2636 if (rc)
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002637 goto nomem;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002638
2639 return 0;
2640
2641nomem:
Yuval Mintza91eb522016-06-03 14:35:32 +03002642 qed_chain_free(cdev, p_chain);
2643 return rc;
Yuval Mintzfe56b9e2015-10-26 11:02:25 +02002644}
2645
Yuval Mintza91eb522016-06-03 14:35:32 +03002646int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id)
Manish Chopracee4d262015-10-26 11:02:28 +02002647{
2648 if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) {
2649 u16 min, max;
2650
Yuval Mintza91eb522016-06-03 14:35:32 +03002651 min = (u16) RESC_START(p_hwfn, QED_L2_QUEUE);
Manish Chopracee4d262015-10-26 11:02:28 +02002652 max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE);
2653 DP_NOTICE(p_hwfn,
2654 "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
2655 src_id, min, max);
2656
2657 return -EINVAL;
2658 }
2659
2660 *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id;
2661
2662 return 0;
2663}
2664
Yuval Mintz1a635e42016-08-15 10:42:43 +03002665int qed_fw_vport(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
Manish Chopracee4d262015-10-26 11:02:28 +02002666{
2667 if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) {
2668 u8 min, max;
2669
2670 min = (u8)RESC_START(p_hwfn, QED_VPORT);
2671 max = min + RESC_NUM(p_hwfn, QED_VPORT);
2672 DP_NOTICE(p_hwfn,
2673 "vport id [%d] is not valid, available indices [%d - %d]\n",
2674 src_id, min, max);
2675
2676 return -EINVAL;
2677 }
2678
2679 *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id;
2680
2681 return 0;
2682}
2683
Yuval Mintz1a635e42016-08-15 10:42:43 +03002684int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
Manish Chopracee4d262015-10-26 11:02:28 +02002685{
2686 if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) {
2687 u8 min, max;
2688
2689 min = (u8)RESC_START(p_hwfn, QED_RSS_ENG);
2690 max = min + RESC_NUM(p_hwfn, QED_RSS_ENG);
2691 DP_NOTICE(p_hwfn,
2692 "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
2693 src_id, min, max);
2694
2695 return -EINVAL;
2696 }
2697
2698 *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id;
2699
2700 return 0;
2701}
Manish Choprabcd197c2016-04-26 10:56:08 -04002702
Yuval Mintz0a7fb112016-10-01 21:59:55 +03002703static void qed_llh_mac_to_filter(u32 *p_high, u32 *p_low,
2704 u8 *p_filter)
2705{
2706 *p_high = p_filter[1] | (p_filter[0] << 8);
2707 *p_low = p_filter[5] | (p_filter[4] << 8) |
2708 (p_filter[3] << 16) | (p_filter[2] << 24);
2709}
2710
2711int qed_llh_add_mac_filter(struct qed_hwfn *p_hwfn,
2712 struct qed_ptt *p_ptt, u8 *p_filter)
2713{
2714 u32 high = 0, low = 0, en;
2715 int i;
2716
2717 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
2718 return 0;
2719
2720 qed_llh_mac_to_filter(&high, &low, p_filter);
2721
2722 /* Find a free entry and utilize it */
2723 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
2724 en = qed_rd(p_hwfn, p_ptt,
2725 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
2726 if (en)
2727 continue;
2728 qed_wr(p_hwfn, p_ptt,
2729 NIG_REG_LLH_FUNC_FILTER_VALUE +
2730 2 * i * sizeof(u32), low);
2731 qed_wr(p_hwfn, p_ptt,
2732 NIG_REG_LLH_FUNC_FILTER_VALUE +
2733 (2 * i + 1) * sizeof(u32), high);
2734 qed_wr(p_hwfn, p_ptt,
2735 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
2736 qed_wr(p_hwfn, p_ptt,
2737 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
2738 i * sizeof(u32), 0);
2739 qed_wr(p_hwfn, p_ptt,
2740 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
2741 break;
2742 }
2743 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
2744 DP_NOTICE(p_hwfn,
2745 "Failed to find an empty LLH filter to utilize\n");
2746 return -EINVAL;
2747 }
2748
2749 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
2750 "mac: %pM is added at %d\n",
2751 p_filter, i);
2752
2753 return 0;
2754}
2755
2756void qed_llh_remove_mac_filter(struct qed_hwfn *p_hwfn,
2757 struct qed_ptt *p_ptt, u8 *p_filter)
2758{
2759 u32 high = 0, low = 0;
2760 int i;
2761
2762 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
2763 return;
2764
2765 qed_llh_mac_to_filter(&high, &low, p_filter);
2766
2767 /* Find the entry and clean it */
2768 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
2769 if (qed_rd(p_hwfn, p_ptt,
2770 NIG_REG_LLH_FUNC_FILTER_VALUE +
2771 2 * i * sizeof(u32)) != low)
2772 continue;
2773 if (qed_rd(p_hwfn, p_ptt,
2774 NIG_REG_LLH_FUNC_FILTER_VALUE +
2775 (2 * i + 1) * sizeof(u32)) != high)
2776 continue;
2777
2778 qed_wr(p_hwfn, p_ptt,
2779 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
2780 qed_wr(p_hwfn, p_ptt,
2781 NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0);
2782 qed_wr(p_hwfn, p_ptt,
2783 NIG_REG_LLH_FUNC_FILTER_VALUE +
2784 (2 * i + 1) * sizeof(u32), 0);
2785
2786 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
2787 "mac: %pM is removed from %d\n",
2788 p_filter, i);
2789 break;
2790 }
2791 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
2792 DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n");
2793}
2794
Arun Easi1e128c82017-02-15 06:28:22 -08002795int
2796qed_llh_add_protocol_filter(struct qed_hwfn *p_hwfn,
2797 struct qed_ptt *p_ptt,
2798 u16 source_port_or_eth_type,
2799 u16 dest_port, enum qed_llh_port_filter_type_t type)
2800{
2801 u32 high = 0, low = 0, en;
2802 int i;
2803
2804 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
2805 return 0;
2806
2807 switch (type) {
2808 case QED_LLH_FILTER_ETHERTYPE:
2809 high = source_port_or_eth_type;
2810 break;
2811 case QED_LLH_FILTER_TCP_SRC_PORT:
2812 case QED_LLH_FILTER_UDP_SRC_PORT:
2813 low = source_port_or_eth_type << 16;
2814 break;
2815 case QED_LLH_FILTER_TCP_DEST_PORT:
2816 case QED_LLH_FILTER_UDP_DEST_PORT:
2817 low = dest_port;
2818 break;
2819 case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
2820 case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
2821 low = (source_port_or_eth_type << 16) | dest_port;
2822 break;
2823 default:
2824 DP_NOTICE(p_hwfn,
2825 "Non valid LLH protocol filter type %d\n", type);
2826 return -EINVAL;
2827 }
2828 /* Find a free entry and utilize it */
2829 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
2830 en = qed_rd(p_hwfn, p_ptt,
2831 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
2832 if (en)
2833 continue;
2834 qed_wr(p_hwfn, p_ptt,
2835 NIG_REG_LLH_FUNC_FILTER_VALUE +
2836 2 * i * sizeof(u32), low);
2837 qed_wr(p_hwfn, p_ptt,
2838 NIG_REG_LLH_FUNC_FILTER_VALUE +
2839 (2 * i + 1) * sizeof(u32), high);
2840 qed_wr(p_hwfn, p_ptt,
2841 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1);
2842 qed_wr(p_hwfn, p_ptt,
2843 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
2844 i * sizeof(u32), 1 << type);
2845 qed_wr(p_hwfn, p_ptt,
2846 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
2847 break;
2848 }
2849 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
2850 DP_NOTICE(p_hwfn,
2851 "Failed to find an empty LLH filter to utilize\n");
2852 return -EINVAL;
2853 }
2854 switch (type) {
2855 case QED_LLH_FILTER_ETHERTYPE:
2856 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
2857 "ETH type %x is added at %d\n",
2858 source_port_or_eth_type, i);
2859 break;
2860 case QED_LLH_FILTER_TCP_SRC_PORT:
2861 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
2862 "TCP src port %x is added at %d\n",
2863 source_port_or_eth_type, i);
2864 break;
2865 case QED_LLH_FILTER_UDP_SRC_PORT:
2866 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
2867 "UDP src port %x is added at %d\n",
2868 source_port_or_eth_type, i);
2869 break;
2870 case QED_LLH_FILTER_TCP_DEST_PORT:
2871 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
2872 "TCP dst port %x is added at %d\n", dest_port, i);
2873 break;
2874 case QED_LLH_FILTER_UDP_DEST_PORT:
2875 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
2876 "UDP dst port %x is added at %d\n", dest_port, i);
2877 break;
2878 case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
2879 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
2880 "TCP src/dst ports %x/%x are added at %d\n",
2881 source_port_or_eth_type, dest_port, i);
2882 break;
2883 case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
2884 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
2885 "UDP src/dst ports %x/%x are added at %d\n",
2886 source_port_or_eth_type, dest_port, i);
2887 break;
2888 }
2889 return 0;
2890}
2891
2892void
2893qed_llh_remove_protocol_filter(struct qed_hwfn *p_hwfn,
2894 struct qed_ptt *p_ptt,
2895 u16 source_port_or_eth_type,
2896 u16 dest_port,
2897 enum qed_llh_port_filter_type_t type)
2898{
2899 u32 high = 0, low = 0;
2900 int i;
2901
2902 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
2903 return;
2904
2905 switch (type) {
2906 case QED_LLH_FILTER_ETHERTYPE:
2907 high = source_port_or_eth_type;
2908 break;
2909 case QED_LLH_FILTER_TCP_SRC_PORT:
2910 case QED_LLH_FILTER_UDP_SRC_PORT:
2911 low = source_port_or_eth_type << 16;
2912 break;
2913 case QED_LLH_FILTER_TCP_DEST_PORT:
2914 case QED_LLH_FILTER_UDP_DEST_PORT:
2915 low = dest_port;
2916 break;
2917 case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
2918 case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
2919 low = (source_port_or_eth_type << 16) | dest_port;
2920 break;
2921 default:
2922 DP_NOTICE(p_hwfn,
2923 "Non valid LLH protocol filter type %d\n", type);
2924 return;
2925 }
2926
2927 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
2928 if (!qed_rd(p_hwfn, p_ptt,
2929 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)))
2930 continue;
2931 if (!qed_rd(p_hwfn, p_ptt,
2932 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32)))
2933 continue;
2934 if (!(qed_rd(p_hwfn, p_ptt,
2935 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
2936 i * sizeof(u32)) & BIT(type)))
2937 continue;
2938 if (qed_rd(p_hwfn, p_ptt,
2939 NIG_REG_LLH_FUNC_FILTER_VALUE +
2940 2 * i * sizeof(u32)) != low)
2941 continue;
2942 if (qed_rd(p_hwfn, p_ptt,
2943 NIG_REG_LLH_FUNC_FILTER_VALUE +
2944 (2 * i + 1) * sizeof(u32)) != high)
2945 continue;
2946
2947 qed_wr(p_hwfn, p_ptt,
2948 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
2949 qed_wr(p_hwfn, p_ptt,
2950 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
2951 qed_wr(p_hwfn, p_ptt,
2952 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
2953 i * sizeof(u32), 0);
2954 qed_wr(p_hwfn, p_ptt,
2955 NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0);
2956 qed_wr(p_hwfn, p_ptt,
2957 NIG_REG_LLH_FUNC_FILTER_VALUE +
2958 (2 * i + 1) * sizeof(u32), 0);
2959 break;
2960 }
2961
2962 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
2963 DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n");
2964}
2965
Sudarsana Reddy Kalluru722003a2016-06-21 09:36:21 -04002966static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
2967 u32 hw_addr, void *p_eth_qzone,
2968 size_t eth_qzone_size, u8 timeset)
2969{
2970 struct coalescing_timeset *p_coal_timeset;
2971
2972 if (p_hwfn->cdev->int_coalescing_mode != QED_COAL_MODE_ENABLE) {
2973 DP_NOTICE(p_hwfn, "Coalescing configuration not enabled\n");
2974 return -EINVAL;
2975 }
2976
2977 p_coal_timeset = p_eth_qzone;
2978 memset(p_coal_timeset, 0, eth_qzone_size);
2979 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
2980 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
2981 qed_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
2982
2983 return 0;
2984}
2985
2986int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
2987 u16 coalesce, u8 qid, u16 sb_id)
2988{
2989 struct ustorm_eth_queue_zone eth_qzone;
2990 u8 timeset, timer_res;
2991 u16 fw_qid = 0;
2992 u32 address;
2993 int rc;
2994
2995 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
2996 if (coalesce <= 0x7F) {
2997 timer_res = 0;
2998 } else if (coalesce <= 0xFF) {
2999 timer_res = 1;
3000 } else if (coalesce <= 0x1FF) {
3001 timer_res = 2;
3002 } else {
3003 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3004 return -EINVAL;
3005 }
3006 timeset = (u8)(coalesce >> timer_res);
3007
3008 rc = qed_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
3009 if (rc)
3010 return rc;
3011
3012 rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, false);
3013 if (rc)
3014 goto out;
3015
3016 address = BAR0_MAP_REG_USDM_RAM + USTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
3017
3018 rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
3019 sizeof(struct ustorm_eth_queue_zone), timeset);
3020 if (rc)
3021 goto out;
3022
3023 p_hwfn->cdev->rx_coalesce_usecs = coalesce;
3024out:
3025 return rc;
3026}
3027
3028int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
3029 u16 coalesce, u8 qid, u16 sb_id)
3030{
3031 struct xstorm_eth_queue_zone eth_qzone;
3032 u8 timeset, timer_res;
3033 u16 fw_qid = 0;
3034 u32 address;
3035 int rc;
3036
3037 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3038 if (coalesce <= 0x7F) {
3039 timer_res = 0;
3040 } else if (coalesce <= 0xFF) {
3041 timer_res = 1;
3042 } else if (coalesce <= 0x1FF) {
3043 timer_res = 2;
3044 } else {
3045 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3046 return -EINVAL;
3047 }
3048 timeset = (u8)(coalesce >> timer_res);
3049
3050 rc = qed_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
3051 if (rc)
3052 return rc;
3053
3054 rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, true);
3055 if (rc)
3056 goto out;
3057
3058 address = BAR0_MAP_REG_XSDM_RAM + XSTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
3059
3060 rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
3061 sizeof(struct xstorm_eth_queue_zone), timeset);
3062 if (rc)
3063 goto out;
3064
3065 p_hwfn->cdev->tx_coalesce_usecs = coalesce;
3066out:
3067 return rc;
3068}
3069
Manish Choprabcd197c2016-04-26 10:56:08 -04003070/* Calculate final WFQ values for all vports and configure them.
3071 * After this configuration each vport will have
3072 * approx min rate = min_pf_rate * (vport_wfq / QED_WFQ_UNIT)
3073 */
3074static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
3075 struct qed_ptt *p_ptt,
3076 u32 min_pf_rate)
3077{
3078 struct init_qm_vport_params *vport_params;
3079 int i;
3080
3081 vport_params = p_hwfn->qm_info.qm_vport_params;
3082
3083 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3084 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3085
3086 vport_params[i].vport_wfq = (wfq_speed * QED_WFQ_UNIT) /
3087 min_pf_rate;
3088 qed_init_vport_wfq(p_hwfn, p_ptt,
3089 vport_params[i].first_tx_pq_id,
3090 vport_params[i].vport_wfq);
3091 }
3092}
3093
3094static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn,
3095 u32 min_pf_rate)
3096
3097{
3098 int i;
3099
3100 for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
3101 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
3102}
3103
3104static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
3105 struct qed_ptt *p_ptt,
3106 u32 min_pf_rate)
3107{
3108 struct init_qm_vport_params *vport_params;
3109 int i;
3110
3111 vport_params = p_hwfn->qm_info.qm_vport_params;
3112
3113 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3114 qed_init_wfq_default_param(p_hwfn, min_pf_rate);
3115 qed_init_vport_wfq(p_hwfn, p_ptt,
3116 vport_params[i].first_tx_pq_id,
3117 vport_params[i].vport_wfq);
3118 }
3119}
3120
3121/* This function performs several validations for WFQ
3122 * configuration and required min rate for a given vport
3123 * 1. req_rate must be greater than one percent of min_pf_rate.
3124 * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
3125 * rates to get less than one percent of min_pf_rate.
3126 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
3127 */
3128static int qed_init_wfq_param(struct qed_hwfn *p_hwfn,
Yuval Mintz1a635e42016-08-15 10:42:43 +03003129 u16 vport_id, u32 req_rate, u32 min_pf_rate)
Manish Choprabcd197c2016-04-26 10:56:08 -04003130{
3131 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
3132 int non_requested_count = 0, req_count = 0, i, num_vports;
3133
3134 num_vports = p_hwfn->qm_info.num_vports;
3135
3136 /* Accounting for the vports which are configured for WFQ explicitly */
3137 for (i = 0; i < num_vports; i++) {
3138 u32 tmp_speed;
3139
3140 if ((i != vport_id) &&
3141 p_hwfn->qm_info.wfq_data[i].configured) {
3142 req_count++;
3143 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3144 total_req_min_rate += tmp_speed;
3145 }
3146 }
3147
3148 /* Include current vport data as well */
3149 req_count++;
3150 total_req_min_rate += req_rate;
3151 non_requested_count = num_vports - req_count;
3152
3153 if (req_rate < min_pf_rate / QED_WFQ_UNIT) {
3154 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3155 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
3156 vport_id, req_rate, min_pf_rate);
3157 return -EINVAL;
3158 }
3159
3160 if (num_vports > QED_WFQ_UNIT) {
3161 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3162 "Number of vports is greater than %d\n",
3163 QED_WFQ_UNIT);
3164 return -EINVAL;
3165 }
3166
3167 if (total_req_min_rate > min_pf_rate) {
3168 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3169 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
3170 total_req_min_rate, min_pf_rate);
3171 return -EINVAL;
3172 }
3173
3174 total_left_rate = min_pf_rate - total_req_min_rate;
3175
3176 left_rate_per_vp = total_left_rate / non_requested_count;
3177 if (left_rate_per_vp < min_pf_rate / QED_WFQ_UNIT) {
3178 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3179 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
3180 left_rate_per_vp, min_pf_rate);
3181 return -EINVAL;
3182 }
3183
3184 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
3185 p_hwfn->qm_info.wfq_data[vport_id].configured = true;
3186
3187 for (i = 0; i < num_vports; i++) {
3188 if (p_hwfn->qm_info.wfq_data[i].configured)
3189 continue;
3190
3191 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
3192 }
3193
3194 return 0;
3195}
3196
Yuval Mintz733def62016-05-11 16:36:22 +03003197static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn,
3198 struct qed_ptt *p_ptt, u16 vp_id, u32 rate)
3199{
3200 struct qed_mcp_link_state *p_link;
3201 int rc = 0;
3202
3203 p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output;
3204
3205 if (!p_link->min_pf_rate) {
3206 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
3207 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
3208 return rc;
3209 }
3210
3211 rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
3212
Yuval Mintz1a635e42016-08-15 10:42:43 +03003213 if (!rc)
Yuval Mintz733def62016-05-11 16:36:22 +03003214 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt,
3215 p_link->min_pf_rate);
3216 else
3217 DP_NOTICE(p_hwfn,
3218 "Validation failed while configuring min rate\n");
3219
3220 return rc;
3221}
3222
Manish Choprabcd197c2016-04-26 10:56:08 -04003223static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn,
3224 struct qed_ptt *p_ptt,
3225 u32 min_pf_rate)
3226{
3227 bool use_wfq = false;
3228 int rc = 0;
3229 u16 i;
3230
3231 /* Validate all pre configured vports for wfq */
3232 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3233 u32 rate;
3234
3235 if (!p_hwfn->qm_info.wfq_data[i].configured)
3236 continue;
3237
3238 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
3239 use_wfq = true;
3240
3241 rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
3242 if (rc) {
3243 DP_NOTICE(p_hwfn,
3244 "WFQ validation failed while configuring min rate\n");
3245 break;
3246 }
3247 }
3248
3249 if (!rc && use_wfq)
3250 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
3251 else
3252 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
3253
3254 return rc;
3255}
3256
Yuval Mintz733def62016-05-11 16:36:22 +03003257/* Main API for qed clients to configure vport min rate.
3258 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
3259 * rate - Speed in Mbps needs to be assigned to a given vport.
3260 */
3261int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate)
3262{
3263 int i, rc = -EINVAL;
3264
3265 /* Currently not supported; Might change in future */
3266 if (cdev->num_hwfns > 1) {
3267 DP_NOTICE(cdev,
3268 "WFQ configuration is not supported for this device\n");
3269 return rc;
3270 }
3271
3272 for_each_hwfn(cdev, i) {
3273 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
3274 struct qed_ptt *p_ptt;
3275
3276 p_ptt = qed_ptt_acquire(p_hwfn);
3277 if (!p_ptt)
3278 return -EBUSY;
3279
3280 rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
3281
Yuval Mintzd572c432016-07-27 14:45:23 +03003282 if (rc) {
Yuval Mintz733def62016-05-11 16:36:22 +03003283 qed_ptt_release(p_hwfn, p_ptt);
3284 return rc;
3285 }
3286
3287 qed_ptt_release(p_hwfn, p_ptt);
3288 }
3289
3290 return rc;
3291}
3292
Manish Choprabcd197c2016-04-26 10:56:08 -04003293/* API to configure WFQ from mcp link change */
Mintz, Yuval6f437d42017-02-27 11:06:33 +02003294void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev,
3295 struct qed_ptt *p_ptt, u32 min_pf_rate)
Manish Choprabcd197c2016-04-26 10:56:08 -04003296{
3297 int i;
3298
Yuval Mintz3e7cfce2016-05-26 11:01:24 +03003299 if (cdev->num_hwfns > 1) {
3300 DP_VERBOSE(cdev,
3301 NETIF_MSG_LINK,
3302 "WFQ configuration is not supported for this device\n");
3303 return;
3304 }
3305
Manish Choprabcd197c2016-04-26 10:56:08 -04003306 for_each_hwfn(cdev, i) {
3307 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
3308
Mintz, Yuval6f437d42017-02-27 11:06:33 +02003309 __qed_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
Manish Choprabcd197c2016-04-26 10:56:08 -04003310 min_pf_rate);
3311 }
3312}
Manish Chopra4b01e512016-04-26 10:56:09 -04003313
3314int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn,
3315 struct qed_ptt *p_ptt,
3316 struct qed_mcp_link_state *p_link,
3317 u8 max_bw)
3318{
3319 int rc = 0;
3320
3321 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
3322
3323 if (!p_link->line_speed && (max_bw != 100))
3324 return rc;
3325
3326 p_link->speed = (p_link->line_speed * max_bw) / 100;
3327 p_hwfn->qm_info.pf_rl = p_link->speed;
3328
3329 /* Since the limiter also affects Tx-switched traffic, we don't want it
3330 * to limit such traffic in case there's no actual limit.
3331 * In that case, set limit to imaginary high boundary.
3332 */
3333 if (max_bw == 100)
3334 p_hwfn->qm_info.pf_rl = 100000;
3335
3336 rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
3337 p_hwfn->qm_info.pf_rl);
3338
3339 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3340 "Configured MAX bandwidth to be %08x Mb/sec\n",
3341 p_link->speed);
3342
3343 return rc;
3344}
3345
3346/* Main API to configure PF max bandwidth where bw range is [1 - 100] */
3347int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw)
3348{
3349 int i, rc = -EINVAL;
3350
3351 if (max_bw < 1 || max_bw > 100) {
3352 DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n");
3353 return rc;
3354 }
3355
3356 for_each_hwfn(cdev, i) {
3357 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
3358 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
3359 struct qed_mcp_link_state *p_link;
3360 struct qed_ptt *p_ptt;
3361
3362 p_link = &p_lead->mcp_info->link_output;
3363
3364 p_ptt = qed_ptt_acquire(p_hwfn);
3365 if (!p_ptt)
3366 return -EBUSY;
3367
3368 rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt,
3369 p_link, max_bw);
3370
3371 qed_ptt_release(p_hwfn, p_ptt);
3372
3373 if (rc)
3374 break;
3375 }
3376
3377 return rc;
3378}
Manish Chopraa64b02d2016-04-26 10:56:10 -04003379
3380int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn,
3381 struct qed_ptt *p_ptt,
3382 struct qed_mcp_link_state *p_link,
3383 u8 min_bw)
3384{
3385 int rc = 0;
3386
3387 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
3388 p_hwfn->qm_info.pf_wfq = min_bw;
3389
3390 if (!p_link->line_speed)
3391 return rc;
3392
3393 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
3394
3395 rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
3396
3397 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3398 "Configured MIN bandwidth to be %d Mb/sec\n",
3399 p_link->min_pf_rate);
3400
3401 return rc;
3402}
3403
3404/* Main API to configure PF min bandwidth where bw range is [1-100] */
3405int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw)
3406{
3407 int i, rc = -EINVAL;
3408
3409 if (min_bw < 1 || min_bw > 100) {
3410 DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n");
3411 return rc;
3412 }
3413
3414 for_each_hwfn(cdev, i) {
3415 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
3416 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
3417 struct qed_mcp_link_state *p_link;
3418 struct qed_ptt *p_ptt;
3419
3420 p_link = &p_lead->mcp_info->link_output;
3421
3422 p_ptt = qed_ptt_acquire(p_hwfn);
3423 if (!p_ptt)
3424 return -EBUSY;
3425
3426 rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt,
3427 p_link, min_bw);
3428 if (rc) {
3429 qed_ptt_release(p_hwfn, p_ptt);
3430 return rc;
3431 }
3432
3433 if (p_link->min_pf_rate) {
3434 u32 min_rate = p_link->min_pf_rate;
3435
3436 rc = __qed_configure_vp_wfq_on_link_change(p_hwfn,
3437 p_ptt,
3438 min_rate);
3439 }
3440
3441 qed_ptt_release(p_hwfn, p_ptt);
3442 }
3443
3444 return rc;
3445}
Yuval Mintz733def62016-05-11 16:36:22 +03003446
3447void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3448{
3449 struct qed_mcp_link_state *p_link;
3450
3451 p_link = &p_hwfn->mcp_info->link_output;
3452
3453 if (p_link->min_pf_rate)
3454 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt,
3455 p_link->min_pf_rate);
3456
3457 memset(p_hwfn->qm_info.wfq_data, 0,
3458 sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports);
3459}
Mintz, Yuval9c79dda2017-03-14 16:23:54 +02003460
3461int qed_device_num_engines(struct qed_dev *cdev)
3462{
3463 return QED_IS_BB(cdev) ? 2 : 1;
3464}