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gerrit-public.fairphone.software / kernel / msm-5.4 / 9f639269ed1522c7d69c54cc8b80ab8ee53fcb10 / . / drivers / scsi / mpt2sas / mpi / mpi2.h
blob: a80f3220c641b8e45e9bc558dfe8596dc1dd4c8b [file] [log] [blame]
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1/*
nagalakshmi.nandigama@lsi.comf9d979c2011-10-19 15:36:05 +0530[diff] [blame]2 * Copyright (c) 2000-2011 LSI Corporation.
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]3 *
4 *
5 * Name: mpi2.h
6 * Title: MPI Message independent structures and definitions
7 * including System Interface Register Set and
8 * scatter/gather formats.
9 * Creation Date: June 21, 2006
10 *
nagalakshmi.nandigama@lsi.com609dc442012-03-20 12:03:16 +0530[diff] [blame]11 * mpi2.h Version: 02.00.23
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]12 *
13 * Version History
14 * ---------------
15 *
16 * Date Version Description
17 * -------- -------- ------------------------------------------------------
18 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
19 * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT.
20 * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT.
21 * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT.
22 * Moved ReplyPostHostIndex register to offset 0x6C of the
23 * MPI2_SYSTEM_INTERFACE_REGS and modified the define for
24 * MPI2_REPLY_POST_HOST_INDEX_OFFSET.
25 * Added union of request descriptors.
26 * Added union of reply descriptors.
27 * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT.
28 * Added define for MPI2_VERSION_02_00.
29 * Fixed the size of the FunctionDependent5 field in the
30 * MPI2_DEFAULT_REPLY structure.
31 * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT.
32 * Removed the MPI-defined Fault Codes and extended the
33 * product specific codes up to 0xEFFF.
34 * Added a sixth key value for the WriteSequence register
35 * and changed the flush value to 0x0.
36 * Added message function codes for Diagnostic Buffer Post
37 * and Diagnsotic Release.
38 * New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED
39 * Moved MPI2_VERSION_UNION from mpi2_ioc.h.
40 * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT.
41 * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT.
42 * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT.
43 * Added #defines for marking a reply descriptor as unused.
44 * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT.
45 * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT.
46 * Moved LUN field defines from mpi2_init.h.
47 * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT.
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]48 * 05-06-09 02.00.12 Bumped MPI2_HEADER_VERSION_UNIT.
49 * In all request and reply descriptors, replaced VF_ID
50 * field with MSIxIndex field.
51 * Removed DevHandle field from
52 * MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those
53 * bytes reserved.
54 * Added RAID Accelerator functionality.
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]55 * 07-30-09 02.00.13 Bumped MPI2_HEADER_VERSION_UNIT.
Kashyap, Desaif4af3c12009-12-16 18:55:54 +0530[diff] [blame]56 * 10-28-09 02.00.14 Bumped MPI2_HEADER_VERSION_UNIT.
57 * Added MSI-x index mask and shift for Reply Post Host
58 * Index register.
59 * Added function code for Host Based Discovery Action.
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]60 * 02-10-10 02.00.15 Bumped MPI2_HEADER_VERSION_UNIT.
61 * Added define for MPI2_FUNCTION_PWR_MGMT_CONTROL.
62 * Added defines for product-specific range of message
63 * function codes, 0xF0 to 0xFF.
Kashyap, Desai7d061402010-11-13 04:36:14 +0530[diff] [blame]64 * 05-12-10 02.00.16 Bumped MPI2_HEADER_VERSION_UNIT.
65 * Added alternative defines for the SGE Direction bit.
Kashyap, Desai9af05d92011-01-04 11:35:41 +0530[diff] [blame]66 * 08-11-10 02.00.17 Bumped MPI2_HEADER_VERSION_UNIT.
Kashyap, Desaice7b1812011-06-14 10:55:45 +0530[diff] [blame]67 * 11-10-10 02.00.18 Bumped MPI2_HEADER_VERSION_UNIT.
68 * Added MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR define.
nagalakshmi.nandigama@lsi.comf9d979c2011-10-19 15:36:05 +0530[diff] [blame]69 * 02-23-11 02.00.19 Bumped MPI2_HEADER_VERSION_UNIT.
70 * Added MPI2_FUNCTION_SEND_HOST_MESSAGE.
71 * 03-09-11 02.00.20 Bumped MPI2_HEADER_VERSION_UNIT.
nagalakshmi.nandigama@lsi.comc1bc0702011-12-01 07:43:37 +0530[diff] [blame]72 * 05-25-11 02.00.21 Bumped MPI2_HEADER_VERSION_UNIT.
nagalakshmi.nandigama@lsi.coma6affbd2011-12-01 07:52:49 +0530[diff] [blame]73 * 08-24-11 02.00.22 Bumped MPI2_HEADER_VERSION_UNIT.
nagalakshmi.nandigama@lsi.com609dc442012-03-20 12:03:16 +0530[diff] [blame]74 * 11-18-11 02.00.23 Bumped MPI2_HEADER_VERSION_UNIT.
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]75 * --------------------------------------------------------------------------
76 */
77
78#ifndef MPI2_H
79#define MPI2_H
80
81
82/*****************************************************************************
83*
84* MPI Version Definitions
85*
86*****************************************************************************/
87
88#define MPI2_VERSION_MAJOR (0x02)
89#define MPI2_VERSION_MINOR (0x00)
90#define MPI2_VERSION_MAJOR_MASK (0xFF00)
91#define MPI2_VERSION_MAJOR_SHIFT (8)
92#define MPI2_VERSION_MINOR_MASK (0x00FF)
93#define MPI2_VERSION_MINOR_SHIFT (0)
94#define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
95 MPI2_VERSION_MINOR)
96
97#define MPI2_VERSION_02_00 (0x0200)
98
99/* versioning for this MPI header set */
nagalakshmi.nandigama@lsi.com609dc442012-03-20 12:03:16 +0530[diff] [blame]100#define MPI2_HEADER_VERSION_UNIT (0x17)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]101#define MPI2_HEADER_VERSION_DEV (0x00)
102#define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
103#define MPI2_HEADER_VERSION_UNIT_SHIFT (8)
104#define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
105#define MPI2_HEADER_VERSION_DEV_SHIFT (0)
106#define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV)
107
108
109/*****************************************************************************
110*
111* IOC State Definitions
112*
113*****************************************************************************/
114
115#define MPI2_IOC_STATE_RESET (0x00000000)
116#define MPI2_IOC_STATE_READY (0x10000000)
117#define MPI2_IOC_STATE_OPERATIONAL (0x20000000)
118#define MPI2_IOC_STATE_FAULT (0x40000000)
119
120#define MPI2_IOC_STATE_MASK (0xF0000000)
121#define MPI2_IOC_STATE_SHIFT (28)
122
123/* Fault state range for prodcut specific codes */
124#define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000)
125#define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF)
126
127
128/*****************************************************************************
129*
130* System Interface Register Definitions
131*
132*****************************************************************************/
133
134typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS
135{
136 U32 Doorbell; /* 0x00 */
137 U32 WriteSequence; /* 0x04 */
138 U32 HostDiagnostic; /* 0x08 */
139 U32 Reserved1; /* 0x0C */
140 U32 DiagRWData; /* 0x10 */
141 U32 DiagRWAddressLow; /* 0x14 */
142 U32 DiagRWAddressHigh; /* 0x18 */
143 U32 Reserved2[5]; /* 0x1C */
144 U32 HostInterruptStatus; /* 0x30 */
145 U32 HostInterruptMask; /* 0x34 */
146 U32 DCRData; /* 0x38 */
147 U32 DCRAddress; /* 0x3C */
148 U32 Reserved3[2]; /* 0x40 */
149 U32 ReplyFreeHostIndex; /* 0x48 */
150 U32 Reserved4[8]; /* 0x4C */
151 U32 ReplyPostHostIndex; /* 0x6C */
152 U32 Reserved5; /* 0x70 */
153 U32 HCBSize; /* 0x74 */
154 U32 HCBAddressLow; /* 0x78 */
155 U32 HCBAddressHigh; /* 0x7C */
156 U32 Reserved6[16]; /* 0x80 */
157 U32 RequestDescriptorPostLow; /* 0xC0 */
158 U32 RequestDescriptorPostHigh; /* 0xC4 */
159 U32 Reserved7[14]; /* 0xC8 */
160} MPI2_SYSTEM_INTERFACE_REGS, MPI2_POINTER PTR_MPI2_SYSTEM_INTERFACE_REGS,
161 Mpi2SystemInterfaceRegs_t, MPI2_POINTER pMpi2SystemInterfaceRegs_t;
162
163/*
164 * Defines for working with the Doorbell register.
165 */
166#define MPI2_DOORBELL_OFFSET (0x00000000)
167
168/* IOC --> System values */
169#define MPI2_DOORBELL_USED (0x08000000)
170#define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000)
171#define MPI2_DOORBELL_WHO_INIT_SHIFT (24)
172#define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF)
173#define MPI2_DOORBELL_DATA_MASK (0x0000FFFF)
174
175/* System --> IOC values */
176#define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000)
177#define MPI2_DOORBELL_FUNCTION_SHIFT (24)
178#define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000)
179#define MPI2_DOORBELL_ADD_DWORDS_SHIFT (16)
180
181
182/*
183 * Defines for the WriteSequence register
184 */
185#define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
186#define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F)
187#define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
188#define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
189#define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
190#define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
191#define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
192#define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
193#define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
194
195/*
196 * Defines for the HostDiagnostic register
197 */
198#define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008)
199
200#define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800)
201#define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000)
202#define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800)
203
204#define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400)
205#define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200)
206#define MPI2_DIAG_HCB_MODE (0x00000100)
207#define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080)
208#define MPI2_DIAG_FLASH_BAD_SIG (0x00000040)
209#define MPI2_DIAG_RESET_HISTORY (0x00000020)
210#define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010)
211#define MPI2_DIAG_RESET_ADAPTER (0x00000004)
212#define MPI2_DIAG_HOLD_IOC_RESET (0x00000002)
213
214/*
215 * Offsets for DiagRWData and address
216 */
217#define MPI2_DIAG_RW_DATA_OFFSET (0x00000010)
218#define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014)
219#define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018)
220
221/*
222 * Defines for the HostInterruptStatus register
223 */
224#define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030)
225#define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000)
226#define MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS
227#define MPI2_HIS_RESET_IRQ_STATUS (0x40000000)
228#define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008)
229#define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001)
230#define MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS
231
232/*
233 * Defines for the HostInterruptMask register
234 */
235#define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034)
236#define MPI2_HIM_RESET_IRQ_MASK (0x40000000)
237#define MPI2_HIM_REPLY_INT_MASK (0x00000008)
238#define MPI2_HIM_RIM MPI2_HIM_REPLY_INT_MASK
239#define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001)
240#define MPI2_HIM_DIM MPI2_HIM_IOC2SYS_DB_MASK
241
242/*
243 * Offsets for DCRData and address
244 */
245#define MPI2_DCR_DATA_OFFSET (0x00000038)
246#define MPI2_DCR_ADDRESS_OFFSET (0x0000003C)
247
248/*
249 * Offset for the Reply Free Queue
250 */
251#define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048)
252
253/*
Kashyap, Desaif4af3c12009-12-16 18:55:54 +0530[diff] [blame]254 * Defines for the Reply Descriptor Post Queue
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]255 */
256#define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C)
Kashyap, Desaif4af3c12009-12-16 18:55:54 +0530[diff] [blame]257#define MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF)
258#define MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000)
259#define MPI2_RPHI_MSIX_INDEX_SHIFT (24)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]260
261/*
262 * Defines for the HCBSize and address
263 */
264#define MPI2_HCB_SIZE_OFFSET (0x00000074)
265#define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000)
266#define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001)
267
268#define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078)
269#define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C)
270
271/*
272 * Offsets for the Request Queue
273 */
274#define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0)
275#define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4)
276
277
278/*****************************************************************************
279*
280* Message Descriptors
281*
282*****************************************************************************/
283
284/* Request Descriptors */
285
286/* Default Request Descriptor */
287typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR
288{
289 U8 RequestFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]290 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]291 U16 SMID; /* 0x02 */
292 U16 LMID; /* 0x04 */
293 U16 DescriptorTypeDependent; /* 0x06 */
294} MPI2_DEFAULT_REQUEST_DESCRIPTOR,
295 MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR,
296 Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t;
297
298/* defines for the RequestFlags field */
299#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E)
300#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
301#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02)
302#define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06)
303#define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08)
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]304#define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]305
306#define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01)
307
308
309/* High Priority Request Descriptor */
310typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR
311{
312 U8 RequestFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]313 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]314 U16 SMID; /* 0x02 */
315 U16 LMID; /* 0x04 */
316 U16 Reserved1; /* 0x06 */
317} MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
318 MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
319 Mpi2HighPriorityRequestDescriptor_t,
320 MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t;
321
322
323/* SCSI IO Request Descriptor */
324typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR
325{
326 U8 RequestFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]327 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]328 U16 SMID; /* 0x02 */
329 U16 LMID; /* 0x04 */
330 U16 DevHandle; /* 0x06 */
331} MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
332 MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
333 Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t;
334
335
336/* SCSI Target Request Descriptor */
337typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR
338{
339 U8 RequestFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]340 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]341 U16 SMID; /* 0x02 */
342 U16 LMID; /* 0x04 */
343 U16 IoIndex; /* 0x06 */
344} MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
345 MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
346 Mpi2SCSITargetRequestDescriptor_t,
347 MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t;
348
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]349
350/* RAID Accelerator Request Descriptor */
351typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR {
352 U8 RequestFlags; /* 0x00 */
353 U8 MSIxIndex; /* 0x01 */
354 U16 SMID; /* 0x02 */
355 U16 LMID; /* 0x04 */
356 U16 Reserved; /* 0x06 */
357} MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
358 MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
359 Mpi2RAIDAcceleratorRequestDescriptor_t,
360 MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t;
361
362
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]363/* union of Request Descriptors */
364typedef union _MPI2_REQUEST_DESCRIPTOR_UNION
365{
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]366 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
367 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
368 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
369 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
370 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
371 U64 Words;
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]372} MPI2_REQUEST_DESCRIPTOR_UNION, MPI2_POINTER PTR_MPI2_REQUEST_DESCRIPTOR_UNION,
373 Mpi2RequestDescriptorUnion_t, MPI2_POINTER pMpi2RequestDescriptorUnion_t;
374
375
376/* Reply Descriptors */
377
378/* Default Reply Descriptor */
379typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR
380{
381 U8 ReplyFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]382 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]383 U16 DescriptorTypeDependent1; /* 0x02 */
384 U32 DescriptorTypeDependent2; /* 0x04 */
385} MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR,
386 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t;
387
388/* defines for the ReplyFlags field */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]389#define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
390#define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
391#define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01)
392#define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02)
393#define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03)
394#define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05)
395#define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]396
397/* values for marking a reply descriptor as unused */
398#define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF)
399#define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF)
400
401/* Address Reply Descriptor */
402typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR
403{
404 U8 ReplyFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]405 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]406 U16 SMID; /* 0x02 */
407 U32 ReplyFrameAddress; /* 0x04 */
408} MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR,
409 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t;
410
411#define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00)
412
413
414/* SCSI IO Success Reply Descriptor */
415typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR
416{
417 U8 ReplyFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]418 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]419 U16 SMID; /* 0x02 */
420 U16 TaskTag; /* 0x04 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]421 U16 Reserved1; /* 0x06 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]422} MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
423 MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
424 Mpi2SCSIIOSuccessReplyDescriptor_t,
425 MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t;
426
427
428/* TargetAssist Success Reply Descriptor */
429typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR
430{
431 U8 ReplyFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]432 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]433 U16 SMID; /* 0x02 */
434 U8 SequenceNumber; /* 0x04 */
435 U8 Reserved1; /* 0x05 */
436 U16 IoIndex; /* 0x06 */
437} MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
438 MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
439 Mpi2TargetAssistSuccessReplyDescriptor_t,
440 MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t;
441
442
443/* Target Command Buffer Reply Descriptor */
444typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR
445{
446 U8 ReplyFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]447 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]448 U8 VP_ID; /* 0x02 */
449 U8 Flags; /* 0x03 */
450 U16 InitiatorDevHandle; /* 0x04 */
451 U16 IoIndex; /* 0x06 */
452} MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
453 MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
454 Mpi2TargetCommandBufferReplyDescriptor_t,
455 MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t;
456
457/* defines for Flags field */
458#define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F)
459
460
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]461/* RAID Accelerator Success Reply Descriptor */
462typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR {
463 U8 ReplyFlags; /* 0x00 */
464 U8 MSIxIndex; /* 0x01 */
465 U16 SMID; /* 0x02 */
466 U32 Reserved; /* 0x04 */
467} MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
468 MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
469 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t,
470 MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t;
471
472
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]473/* union of Reply Descriptors */
474typedef union _MPI2_REPLY_DESCRIPTORS_UNION
475{
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]476 MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
477 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
478 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
479 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
480 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
481 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess;
482 U64 Words;
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]483} MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION,
nagalakshmi.nandigama@lsi.com609dc442012-03-20 12:03:16 +0530[diff] [blame]484Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t;
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]485
486
487
488/*****************************************************************************
489*
490* Message Functions
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]491*
492*****************************************************************************/
493
494#define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */
495#define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */
496#define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */
497#define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */
498#define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */
499#define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */
500#define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */
501#define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */
502#define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */
503#define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */
504#define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */
505#define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */
506#define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */
507#define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */
508#define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */
509#define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */
510#define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */
511#define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */
512#define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */
513#define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */
514#define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */
515#define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */
516#define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */
517#define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */
518#define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]519#define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator*/
Kashyap, Desaif4af3c12009-12-16 18:55:54 +0530[diff] [blame]520/* Host Based Discovery Action */
521#define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F)
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]522/* Power Management Control */
523#define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30)
nagalakshmi.nandigama@lsi.comf9d979c2011-10-19 15:36:05 +0530[diff] [blame]524/* Send Host Message */
525#define MPI2_FUNCTION_SEND_HOST_MESSAGE (0x31)
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]526/* beginning of product-specific range */
527#define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0)
528/* end of product-specific range */
529#define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF)
530
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]531
532
533
534/* Doorbell functions */
535#define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]536#define MPI2_FUNCTION_HANDSHAKE (0x42)
537
538
539/*****************************************************************************
540*
541* IOC Status Values
542*
543*****************************************************************************/
544
545/* mask for IOCStatus status value */
546#define MPI2_IOCSTATUS_MASK (0x7FFF)
547
548/****************************************************************************
549* Common IOCStatus values for all replies
550****************************************************************************/
551
552#define MPI2_IOCSTATUS_SUCCESS (0x0000)
553#define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001)
554#define MPI2_IOCSTATUS_BUSY (0x0002)
555#define MPI2_IOCSTATUS_INVALID_SGL (0x0003)
556#define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004)
557#define MPI2_IOCSTATUS_INVALID_VPID (0x0005)
558#define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006)
559#define MPI2_IOCSTATUS_INVALID_FIELD (0x0007)
560#define MPI2_IOCSTATUS_INVALID_STATE (0x0008)
561#define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009)
562
563/****************************************************************************
564* Config IOCStatus values
565****************************************************************************/
566
567#define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020)
568#define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021)
569#define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022)
570#define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023)
571#define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024)
572#define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025)
573
574/****************************************************************************
575* SCSI IO Reply
576****************************************************************************/
577
578#define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040)
579#define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042)
580#define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043)
581#define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044)
582#define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045)
583#define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046)
584#define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047)
585#define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048)
586#define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049)
587#define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A)
588#define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B)
589#define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C)
590
591/****************************************************************************
592* For use by SCSI Initiator and SCSI Target end-to-end data protection
593****************************************************************************/
594
595#define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D)
596#define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E)
597#define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F)
598
599/****************************************************************************
600* SCSI Target values
601****************************************************************************/
602
603#define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062)
604#define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063)
605#define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064)
606#define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065)
607#define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A)
608#define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D)
609#define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E)
610#define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F)
611#define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070)
612#define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071)
613
614/****************************************************************************
615* Serial Attached SCSI values
616****************************************************************************/
617
618#define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090)
619#define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091)
620
621/****************************************************************************
622* Diagnostic Buffer Post / Diagnostic Release values
623****************************************************************************/
624
625#define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0)
626
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]627/****************************************************************************
628* RAID Accelerator values
629****************************************************************************/
630
631#define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]632
633/****************************************************************************
634* IOCStatus flag to indicate that log info is available
635****************************************************************************/
636
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]637#define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]638
639/****************************************************************************
640* IOCLogInfo Types
641****************************************************************************/
642
643#define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000)
644#define MPI2_IOCLOGINFO_TYPE_SHIFT (28)
645#define MPI2_IOCLOGINFO_TYPE_NONE (0x0)
646#define MPI2_IOCLOGINFO_TYPE_SCSI (0x1)
647#define MPI2_IOCLOGINFO_TYPE_FC (0x2)
648#define MPI2_IOCLOGINFO_TYPE_SAS (0x3)
649#define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4)
650#define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF)
651
652
653/*****************************************************************************
654*
655* Standard Message Structures
656*
657*****************************************************************************/
658
659/****************************************************************************
660* Request Message Header for all request messages
661****************************************************************************/
662
663typedef struct _MPI2_REQUEST_HEADER
664{
665 U16 FunctionDependent1; /* 0x00 */
666 U8 ChainOffset; /* 0x02 */
667 U8 Function; /* 0x03 */
668 U16 FunctionDependent2; /* 0x04 */
669 U8 FunctionDependent3; /* 0x06 */
670 U8 MsgFlags; /* 0x07 */
671 U8 VP_ID; /* 0x08 */
672 U8 VF_ID; /* 0x09 */
673 U16 Reserved1; /* 0x0A */
674} MPI2_REQUEST_HEADER, MPI2_POINTER PTR_MPI2_REQUEST_HEADER,
675 MPI2RequestHeader_t, MPI2_POINTER pMPI2RequestHeader_t;
676
677
678/****************************************************************************
679* Default Reply
680****************************************************************************/
681
682typedef struct _MPI2_DEFAULT_REPLY
683{
684 U16 FunctionDependent1; /* 0x00 */
685 U8 MsgLength; /* 0x02 */
686 U8 Function; /* 0x03 */
687 U16 FunctionDependent2; /* 0x04 */
688 U8 FunctionDependent3; /* 0x06 */
689 U8 MsgFlags; /* 0x07 */
690 U8 VP_ID; /* 0x08 */
691 U8 VF_ID; /* 0x09 */
692 U16 Reserved1; /* 0x0A */
693 U16 FunctionDependent5; /* 0x0C */
694 U16 IOCStatus; /* 0x0E */
695 U32 IOCLogInfo; /* 0x10 */
696} MPI2_DEFAULT_REPLY, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY,
697 MPI2DefaultReply_t, MPI2_POINTER pMPI2DefaultReply_t;
698
699
700/* common version structure/union used in messages and configuration pages */
701
702typedef struct _MPI2_VERSION_STRUCT
703{
704 U8 Dev; /* 0x00 */
705 U8 Unit; /* 0x01 */
706 U8 Minor; /* 0x02 */
707 U8 Major; /* 0x03 */
708} MPI2_VERSION_STRUCT;
709
710typedef union _MPI2_VERSION_UNION
711{
712 MPI2_VERSION_STRUCT Struct;
713 U32 Word;
714} MPI2_VERSION_UNION;
715
716
717/* LUN field defines, common to many structures */
718#define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF)
719#define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000)
720#define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF)
721#define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000)
722#define MPI2_LUN_LEVEL_1_WORD (0xFF00)
723#define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00)
724
725
726/*****************************************************************************
727*
728* Fusion-MPT MPI Scatter Gather Elements
729*
730*****************************************************************************/
731
732/****************************************************************************
733* MPI Simple Element structures
734****************************************************************************/
735
736typedef struct _MPI2_SGE_SIMPLE32
737{
738 U32 FlagsLength;
739 U32 Address;
740} MPI2_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_SGE_SIMPLE32,
741 Mpi2SGESimple32_t, MPI2_POINTER pMpi2SGESimple32_t;
742
743typedef struct _MPI2_SGE_SIMPLE64
744{
745 U32 FlagsLength;
746 U64 Address;
747} MPI2_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_SGE_SIMPLE64,
748 Mpi2SGESimple64_t, MPI2_POINTER pMpi2SGESimple64_t;
749
750typedef struct _MPI2_SGE_SIMPLE_UNION
751{
752 U32 FlagsLength;
753 union
754 {
755 U32 Address32;
756 U64 Address64;
757 } u;
758} MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION,
759 Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t;
760
761
762/****************************************************************************
763* MPI Chain Element structures
764****************************************************************************/
765
766typedef struct _MPI2_SGE_CHAIN32
767{
768 U16 Length;
769 U8 NextChainOffset;
770 U8 Flags;
771 U32 Address;
772} MPI2_SGE_CHAIN32, MPI2_POINTER PTR_MPI2_SGE_CHAIN32,
773 Mpi2SGEChain32_t, MPI2_POINTER pMpi2SGEChain32_t;
774
775typedef struct _MPI2_SGE_CHAIN64
776{
777 U16 Length;
778 U8 NextChainOffset;
779 U8 Flags;
780 U64 Address;
781} MPI2_SGE_CHAIN64, MPI2_POINTER PTR_MPI2_SGE_CHAIN64,
782 Mpi2SGEChain64_t, MPI2_POINTER pMpi2SGEChain64_t;
783
784typedef struct _MPI2_SGE_CHAIN_UNION
785{
786 U16 Length;
787 U8 NextChainOffset;
788 U8 Flags;
789 union
790 {
791 U32 Address32;
792 U64 Address64;
793 } u;
794} MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION,
795 Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t;
796
797
798/****************************************************************************
799* MPI Transaction Context Element structures
800****************************************************************************/
801
802typedef struct _MPI2_SGE_TRANSACTION32
803{
804 U8 Reserved;
805 U8 ContextSize;
806 U8 DetailsLength;
807 U8 Flags;
808 U32 TransactionContext[1];
809 U32 TransactionDetails[1];
810} MPI2_SGE_TRANSACTION32, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION32,
811 Mpi2SGETransaction32_t, MPI2_POINTER pMpi2SGETransaction32_t;
812
813typedef struct _MPI2_SGE_TRANSACTION64
814{
815 U8 Reserved;
816 U8 ContextSize;
817 U8 DetailsLength;
818 U8 Flags;
819 U32 TransactionContext[2];
820 U32 TransactionDetails[1];
821} MPI2_SGE_TRANSACTION64, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION64,
822 Mpi2SGETransaction64_t, MPI2_POINTER pMpi2SGETransaction64_t;
823
824typedef struct _MPI2_SGE_TRANSACTION96
825{
826 U8 Reserved;
827 U8 ContextSize;
828 U8 DetailsLength;
829 U8 Flags;
830 U32 TransactionContext[3];
831 U32 TransactionDetails[1];
832} MPI2_SGE_TRANSACTION96, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION96,
833 Mpi2SGETransaction96_t, MPI2_POINTER pMpi2SGETransaction96_t;
834
835typedef struct _MPI2_SGE_TRANSACTION128
836{
837 U8 Reserved;
838 U8 ContextSize;
839 U8 DetailsLength;
840 U8 Flags;
841 U32 TransactionContext[4];
842 U32 TransactionDetails[1];
843} MPI2_SGE_TRANSACTION128, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION128,
844 Mpi2SGETransaction_t128, MPI2_POINTER pMpi2SGETransaction_t128;
845
846typedef struct _MPI2_SGE_TRANSACTION_UNION
847{
848 U8 Reserved;
849 U8 ContextSize;
850 U8 DetailsLength;
851 U8 Flags;
852 union
853 {
854 U32 TransactionContext32[1];
855 U32 TransactionContext64[2];
856 U32 TransactionContext96[3];
857 U32 TransactionContext128[4];
858 } u;
859 U32 TransactionDetails[1];
860} MPI2_SGE_TRANSACTION_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION_UNION,
861 Mpi2SGETransactionUnion_t, MPI2_POINTER pMpi2SGETransactionUnion_t;
862
863
864/****************************************************************************
865* MPI SGE union for IO SGL's
866****************************************************************************/
867
868typedef struct _MPI2_MPI_SGE_IO_UNION
869{
870 union
871 {
872 MPI2_SGE_SIMPLE_UNION Simple;
873 MPI2_SGE_CHAIN_UNION Chain;
874 } u;
875} MPI2_MPI_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_IO_UNION,
876 Mpi2MpiSGEIOUnion_t, MPI2_POINTER pMpi2MpiSGEIOUnion_t;
877
878
879/****************************************************************************
880* MPI SGE union for SGL's with Simple and Transaction elements
881****************************************************************************/
882
883typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION
884{
885 union
886 {
887 MPI2_SGE_SIMPLE_UNION Simple;
888 MPI2_SGE_TRANSACTION_UNION Transaction;
889 } u;
890} MPI2_SGE_TRANS_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANS_SIMPLE_UNION,
891 Mpi2SGETransSimpleUnion_t, MPI2_POINTER pMpi2SGETransSimpleUnion_t;
892
893
894/****************************************************************************
895* All MPI SGE types union
896****************************************************************************/
897
898typedef struct _MPI2_MPI_SGE_UNION
899{
900 union
901 {
902 MPI2_SGE_SIMPLE_UNION Simple;
903 MPI2_SGE_CHAIN_UNION Chain;
904 MPI2_SGE_TRANSACTION_UNION Transaction;
905 } u;
906} MPI2_MPI_SGE_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_UNION,
907 Mpi2MpiSgeUnion_t, MPI2_POINTER pMpi2MpiSgeUnion_t;
908
909
910/****************************************************************************
911* MPI SGE field definition and masks
912****************************************************************************/
913
914/* Flags field bit definitions */
915
916#define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80)
917#define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40)
918#define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30)
919#define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08)
920#define MPI2_SGE_FLAGS_DIRECTION (0x04)
921#define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02)
922#define MPI2_SGE_FLAGS_END_OF_LIST (0x01)
923
924#define MPI2_SGE_FLAGS_SHIFT (24)
925
926#define MPI2_SGE_LENGTH_MASK (0x00FFFFFF)
927#define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF)
928
929/* Element Type */
930
931#define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00)
932#define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10)
933#define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30)
934#define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30)
935
936/* Address location */
937
938#define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00)
939
940/* Direction */
941
942#define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00)
943#define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04)
944
Kashyap, Desai7d061402010-11-13 04:36:14 +0530[diff] [blame]945#define MPI2_SGE_FLAGS_DEST (MPI2_SGE_FLAGS_IOC_TO_HOST)
946#define MPI2_SGE_FLAGS_SOURCE (MPI2_SGE_FLAGS_HOST_TO_IOC)
947
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]948/* Address Size */
949
950#define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00)
951#define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
952
953/* Context Size */
954
955#define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00)
956#define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02)
957#define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04)
958#define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06)
959
960#define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000)
961#define MPI2_SGE_CHAIN_OFFSET_SHIFT (16)
962
963/****************************************************************************
964* MPI SGE operation Macros
965****************************************************************************/
966
967/* SIMPLE FlagsLength manipulations... */
968#define MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT)
969#define MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> MPI2_SGE_FLAGS_SHIFT)
970#define MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK)
971#define MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK)
972
973#define MPI2_SGE_SET_FLAGS_LENGTH(f,l) (MPI2_SGE_SET_FLAGS(f) | MPI2_SGE_LENGTH(l))
974
975#define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength)
976#define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength)
977#define MPI2_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_SGE_SET_FLAGS_LENGTH(f,l)
978
979/* CAUTION - The following are READ-MODIFY-WRITE! */
980#define MPI2_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_SGE_SET_FLAGS(f)
981#define MPI2_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_SGE_LENGTH(l)
982
983#define MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> MPI2_SGE_CHAIN_OFFSET_SHIFT)
984
985
986/*****************************************************************************
987*
988* Fusion-MPT IEEE Scatter Gather Elements
989*
990*****************************************************************************/
991
992/****************************************************************************
993* IEEE Simple Element structures
994****************************************************************************/
995
996typedef struct _MPI2_IEEE_SGE_SIMPLE32
997{
998 U32 Address;
999 U32 FlagsLength;
1000} MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32,
1001 Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t;
1002
1003typedef struct _MPI2_IEEE_SGE_SIMPLE64
1004{
1005 U64 Address;
1006 U32 Length;
1007 U16 Reserved1;
1008 U8 Reserved2;
1009 U8 Flags;
1010} MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64,
1011 Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t;
1012
1013typedef union _MPI2_IEEE_SGE_SIMPLE_UNION
1014{
1015 MPI2_IEEE_SGE_SIMPLE32 Simple32;
1016 MPI2_IEEE_SGE_SIMPLE64 Simple64;
1017} MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION,
1018 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t;
1019
1020
1021/****************************************************************************
1022* IEEE Chain Element structures
1023****************************************************************************/
1024
1025typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32;
1026
1027typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64;
1028
1029typedef union _MPI2_IEEE_SGE_CHAIN_UNION
1030{
1031 MPI2_IEEE_SGE_CHAIN32 Chain32;
1032 MPI2_IEEE_SGE_CHAIN64 Chain64;
1033} MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION,
1034 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t;
1035
1036
1037/****************************************************************************
1038* All IEEE SGE types union
1039****************************************************************************/
1040
1041typedef struct _MPI2_IEEE_SGE_UNION
1042{
1043 union
1044 {
1045 MPI2_IEEE_SGE_SIMPLE_UNION Simple;
1046 MPI2_IEEE_SGE_CHAIN_UNION Chain;
1047 } u;
1048} MPI2_IEEE_SGE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_UNION,
1049 Mpi2IeeeSgeUnion_t, MPI2_POINTER pMpi2IeeeSgeUnion_t;
1050
1051
1052/****************************************************************************
1053* IEEE SGE field definitions and masks
1054****************************************************************************/
1055
1056/* Flags field bit definitions */
1057
1058#define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80)
1059
1060#define MPI2_IEEE32_SGE_FLAGS_SHIFT (24)
1061
1062#define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF)
1063
1064/* Element Type */
1065
1066#define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00)
1067#define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
1068
1069/* Data Location Address Space */
1070
1071#define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03)
1072#define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00)
Kashyap, Desaice7b1812011-06-14 10:55:45 +0530[diff] [blame]1073 /* IEEE Simple Element only */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1074#define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01)
Kashyap, Desaice7b1812011-06-14 10:55:45 +0530[diff] [blame]1075 /* IEEE Simple Element only */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1076#define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
1077#define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
Kashyap, Desaice7b1812011-06-14 10:55:45 +0530[diff] [blame]1078 /* IEEE Simple Element only */
nagalakshmi.nandigama@lsi.comc1bc0702011-12-01 07:43:37 +0530[diff] [blame]1079#define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR (0x03)
Kashyap, Desaice7b1812011-06-14 10:55:45 +0530[diff] [blame]1080 /* IEEE Chain Element only */
nagalakshmi.nandigama@lsi.comc1bc0702011-12-01 07:43:37 +0530[diff] [blame]1081#define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR \
1082 (MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR) /* typo in name */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1083
1084/****************************************************************************
1085* IEEE SGE operation Macros
1086****************************************************************************/
1087
1088/* SIMPLE FlagsLength manipulations... */
1089#define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT)
1090#define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) >> MPI2_IEEE32_SGE_FLAGS_SHIFT)
1091#define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK)
1092
1093#define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) | MPI2_IEEE32_SGE_LENGTH(l))
1094
1095#define MPI2_IEEE32_pSGE_GET_FLAGS(psg) MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength)
1096#define MPI2_IEEE32_pSGE_GET_LENGTH(psg) MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength)
1097#define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f,l)
1098
1099/* CAUTION - The following are READ-MODIFY-WRITE! */
1100#define MPI2_IEEE32_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_IEEE32_SGE_SET_FLAGS(f)
1101#define MPI2_IEEE32_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_IEEE32_SGE_LENGTH(l)
1102
1103
1104
1105
1106/*****************************************************************************
1107*
1108* Fusion-MPT MPI/IEEE Scatter Gather Unions
1109*
1110*****************************************************************************/
1111
1112typedef union _MPI2_SIMPLE_SGE_UNION
1113{
1114 MPI2_SGE_SIMPLE_UNION MpiSimple;
1115 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1116} MPI2_SIMPLE_SGE_UNION, MPI2_POINTER PTR_MPI2_SIMPLE_SGE_UNION,
1117 Mpi2SimpleSgeUntion_t, MPI2_POINTER pMpi2SimpleSgeUntion_t;
1118
1119
1120typedef union _MPI2_SGE_IO_UNION
1121{
1122 MPI2_SGE_SIMPLE_UNION MpiSimple;
1123 MPI2_SGE_CHAIN_UNION MpiChain;
1124 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1125 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
1126} MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION,
1127 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t;
1128
1129
1130/****************************************************************************
1131*
1132* Values for SGLFlags field, used in many request messages with an SGL
1133*
1134****************************************************************************/
1135
1136/* values for MPI SGL Data Location Address Space subfield */
1137#define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C)
1138#define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00)
1139#define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04)
1140#define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08)
1141#define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C)
1142/* values for SGL Type subfield */
1143#define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03)
1144#define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00)
1145#define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01)
1146#define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02)
1147
1148
1149#endif
1150